From: richardbarry Date: Tue, 2 May 2006 09:39:15 +0000 (+0000) Subject: First version under SVN is V4.0.1 X-Git-Tag: V4.0.1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=0ef7f2fd33f7f595813c31954a4896a9269691e3;p=freertos First version under SVN is V4.0.1 git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@4 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h b/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h new file mode 100644 index 000000000..e99ef0503 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h @@ -0,0 +1,707 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91R40008.h +// Object : AT91R40008 definitions +// Generated : AT91 SW Application Group 02/19/2003 (11:13:31) +// +// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002// +// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002// +// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002// +// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002// +// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002// +// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002// +// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002// +// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002// +// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002// +// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003// +// ---------------------------------------------------------------------------- + +#ifndef AT91R40008_H +#define AT91R40008_H + +/* AT91 Register type */ +typedef volatile unsigned int AT91_REG; // Hardware register definition +typedef volatile unsigned int at91_reg; + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode egister + AT91_REG AIC_SVR[32]; // Source Vector egister + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command egister + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Interface +// ***************************************************************************** +typedef struct _AT91S_WD { + AT91_REG WD_OMR; // Overflow Mode Register + AT91_REG WD_CMR; // Clock Mode Register + AT91_REG WD_CR; // Control Register + AT91_REG WD_SR; // Status Register +} AT91S_WD, *AT91PS_WD; + +// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- +#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable +#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable +#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable +#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable +#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable +// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- +#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection +#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32 +#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128 +#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024 +#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096 +#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value +#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key +// -------- WD_CR : (WD Offset: 0x8) Control Register -------- +#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key +// -------- WD_SR : (WD Offset: 0xc) Status Register -------- +#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Saving Controler +// ***************************************************************************** +typedef struct _AT91S_PS { + AT91_REG PS_CR; // Control Register + AT91_REG PS_PCER; // Peripheral Clock Enable Register + AT91_REG PS_PCDR; // Peripheral Clock Disable Register + AT91_REG PS_PCSR; // Peripheral Clock Status Register +} AT91S_PS, *AT91PS_PS; + +// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- +#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock +#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock +#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock +#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock +#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock +#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock +// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- +// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register +} AT91S_PDC, *AT91PS_PDC; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[1]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin. +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Special Function Interface +// ***************************************************************************** +typedef struct _AT91S_SF { + AT91_REG SF_CIDR; // Chip ID Register + AT91_REG SF_EXID; // Chip ID Extension Register + AT91_REG SF_RSR; // Reset Status Register + AT91_REG SF_MMR; // Memory Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SF_PMR; // Protect Mode Register +} AT91S_SF, *AT91PS_SF; + +// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- +#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip +#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0 +#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1 +#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0 +#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size +#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None +#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes +#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes +#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes +#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes +#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size +#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None +#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size +#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None +#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes +#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes +#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes +#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes +#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture +#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy +#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy +#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy +#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type +#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series +#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series +#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag +// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- +#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset +#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog +#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin +// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- +#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection +// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- +#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable +#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +typedef struct _AT91S_EBI { + AT91_REG EBI_CSR[8]; // Chip-select Register + AT91_REG EBI_RCR; // Remap Control Register + AT91_REG EBI_MCR; // Memory Control Register +} AT91S_EBI, *AT91PS_EBI; + +// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- +#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width +#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width +#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width +#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states +#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state +#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state +#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state +#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state +#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state +#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state +#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state +#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state +#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable +#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size +#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte +#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte +#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte +#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte +#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time +#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF +#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF +#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF +#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF +#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF +#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF +#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF +#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF +#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type +#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable +#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address +// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- +#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices. +// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- +#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable +#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None +#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4 +#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 +#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 +#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 +#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91R40008 +// ***************************************************************************** +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister +// ========== Register definition for WD peripheral ========== +#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register +#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register +#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register +#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register +// ========== Register definition for PS peripheral ========== +#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register +#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register +#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register +#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register +// ========== Register definition for PIO peripheral ========== +#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register +#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register +#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register +#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register +#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register +#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register +#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register +#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register +#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register +#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register +#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register +#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register +#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register +#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register +#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register +#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register +#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register +#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register +#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register +#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register +// ========== Register definition for SF peripheral ========== +#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register +#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register +#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register +#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register +#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register +#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register +#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0 +#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal +#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1 +#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A +#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10 +#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1 +#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11 +#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2 +#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12 +#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt +#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13 +#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock +#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14 +#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data +#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15 +#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data +#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16 +#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17 +#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18 +#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19 +#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2 +#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B +#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20 +#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock +#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21 +#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data +#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode +#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22 +#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data +#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23 +#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24 +#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select +#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25 +#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out +#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26 +#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2 +#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27 +#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3 +#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28 +#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20 +#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7 +#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29 +#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21 +#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6 +#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3 +#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal +#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30 +#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22 +#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5 +#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31 +#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23 +#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4 +#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4 +#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A +#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5 +#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B +#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6 +#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal +#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7 +#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A +#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8 +#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B +#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9 +#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // SWI +#define AT91C_ID_US0 ((unsigned int) 2) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 3) // USART 1 +#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2 +#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer +#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller +#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address +#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address +#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address +#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address +#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address +#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address +#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte) +#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address +#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte) + +#endif diff --git a/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg b/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg new file mode 100644 index 000000000..756339f29 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg @@ -0,0 +1,24 @@ +[SETUP] +CpuVendor=Atmel +CpuChip=AT91R40807 +FlashVendor=Atmel +FlashChip=AT49BV/F1614A +RamAddress=$00000000 +RamSupport=1 +FlashAddress=$01000000 +FlashWidth=16 +FlashChipsPerSector=1 +LittleEndian=0 +SectStart=0 +SectEnd=38 +AutoErase=0 +AutoVerify=1 +CpuEndian=LITTLE +SimCount=3 +MemoryCount=0 +ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex +UploadFile=c:\EB40_Lower.bin +Format=Intel Hex +Sim3=EBI_RCR:$00000001 +Sim2=EBI_CSR1:$02002122 +Sim1=EBI_CSR0:$01002539 diff --git a/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h b/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..46e1ab5d0 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h @@ -0,0 +1,79 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */ + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_AT91FR40008_GCC/Makefile b/Demo/ARM7_AT91FR40008_GCC/Makefile new file mode 100644 index 000000000..f18de5ba6 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/Makefile @@ -0,0 +1,99 @@ +# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + -Wcast-align $(OPTIM) + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +main.c \ +serial/serial.c \ +ParTest/ParTest.c \ +../Common/Minimal/integer.c \ +../Common/Minimal/flash.c \ +../Common/Minimal/PollQ.c \ +../Common/Minimal/comtest.c \ +../Common/Minimal/flop.c \ +../Common/Minimal/semtest.c \ +../Common/Minimal/dynamic.c \ +../Common/Minimal/BlockQ.c \ +../../Source/tasks.c \ +../../Source/queue.c \ +../../Source/list.c \ +../../Source/portable/MemMang/heap_2.c \ +../../Source/portable/GCC/ARM7_AT91FR40008/port.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \ +serial/serialISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +rtosdemo.hex : rtosdemo.elf + $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex + +rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch Makefile + diff --git a/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c b/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..583d26323 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c @@ -0,0 +1,120 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Demo app includes. */ +#include "partest.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" + +#define partstNUM_LEDS ( 8 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) ) + +static unsigned portLONG ulLEDReg; + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +static void SetLeds (unsigned int leds) +{ +unsigned portLONG ulPIOSetReg, ulPIOClearReg; + + /* LEDs are grouped in different port bits: P3-P6 and P16-P19. + A port bit set to '0' turns an LED on, '1' turns it off. */ + + ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 ); + ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078; + + AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg; + AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg; +} +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. Ensure the outputs are off to start. */ + ulLEDReg = partstALL_OUTPUTS_OFF; + + /* Enable clock to PIO... */ + AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO; + + /* Enable all 8 LEDs and the four switches to be controlled by PIO... */ + AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12; + + /* Configure all LED PIO lines for output... */ + AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19; + + /* Configure all switch PIO lines for input... */ + AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12; + + /* Set initial state of LEDs. */ + SetLeds( ulLEDReg ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* Switch an LED on or off as requested. */ + if (uxLED < partstNUM_LEDS) + { + if( xValue ) + { + ulLEDReg &= ~(1 << uxLED); + } + else + { + ulLEDReg |= (1 << uxLED); + } + + SetLeds( ulLEDReg ); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* Toggle the state of the requested LED. */ + if (uxLED < partstNUM_LEDS) + { + ulLEDReg ^= ( 1 << uxLED ); + SetLeds( ulLEDReg ); + } +} + diff --git a/Demo/ARM7_AT91FR40008_GCC/aic.h b/Demo/ARM7_AT91FR40008_GCC/aic.h new file mode 100644 index 000000000..82df09078 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/aic.h @@ -0,0 +1,81 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : aic.h +//* Object : Advanced Interrupt Controller Definition File. +//* +//* 1.0 01/04/00 JCZ : Creation +//*---------------------------------------------------------------------------- + +#ifndef aic_h +#define aic_h + +//#include "periph/stdc/std_c.h" + +/*-----------------------------------------*/ +/* AIC User Interface Structure Definition */ +/*-----------------------------------------*/ + +typedef struct +{ + at91_reg AIC_SMR[32] ; /* Source Mode Register */ + at91_reg AIC_SVR[32] ; /* Source Vector Register */ + at91_reg AIC_IVR ; /* IRQ Vector Register */ + at91_reg AIC_FVR ; /* FIQ Vector Register */ + at91_reg AIC_ISR ; /* Interrupt Status Register */ + at91_reg AIC_IPR ; /* Interrupt Pending Register */ + at91_reg AIC_IMR ; /* Interrupt Mask Register */ + at91_reg AIC_CISR ; /* Core Interrupt Status Register */ + at91_reg reserved0 ; + at91_reg reserved1 ; + at91_reg AIC_IECR ; /* Interrupt Enable Command Register */ + at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */ + at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */ + at91_reg AIC_ISCR ; /* Interrupt Set Command Register */ + at91_reg AIC_EOICR ; /* End of Interrupt Command Register */ + at91_reg AIC_SPU ; /* Spurious Vector Register */ +} StructAIC ; + +/*--------------------------------------------*/ +/* AIC_SMR[]: Interrupt Source Mode Registers */ +/*--------------------------------------------*/ + +#define AIC_PRIOR 0x07 /* Priority */ + +#define AIC_SRCTYPE 0x60 /* Source Type Definition */ + +/* Internal Interrupts */ +#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */ +#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */ + +/* External Interrupts */ +#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */ +#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */ +#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */ +#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */ + +/*------------------------------------*/ +/* AIC_ISR: Interrupt Status Register */ +/*------------------------------------*/ + +#define AIC_IRQID 0x1F /* Current source interrupt */ + +/*------------------------------------------*/ +/* AIC_CISR: Interrupt Core Status Register */ +/*------------------------------------------*/ + +#define AIC_NFIQ 0x01 /* Core FIQ Status */ +#define AIC_NIRQ 0x02 /* Core IRQ Status */ + +/*-------------------------------*/ +/* Advanced Interrupt Controller */ +/*-------------------------------*/ +#define AIC_BASE ((StructAIC *)0xFFFFF000) + +#endif /* aic_h */ diff --git a/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld b/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld new file mode 100644 index 000000000..692202661 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld @@ -0,0 +1,48 @@ +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 256K +} + +__stack_end__ = 0x00000000 + 256K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >ram + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >ram + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld b/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld new file mode 100644 index 000000000..35578fd96 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0x00000000, LENGTH = 2048K + ram : ORIGIN = 0x00300000, LENGTH = 256K +} + +__stack_end__ = 0x00300000 + 256K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/Demo/ARM7_AT91FR40008_GCC/boot.s b/Demo/ARM7_AT91FR40008_GCC/boot.s new file mode 100644 index 000000000..5947d158f --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/Demo/ARM7_AT91FR40008_GCC/ebi.h b/Demo/ARM7_AT91FR40008_GCC/ebi.h new file mode 100644 index 000000000..62c36f0ad --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/ebi.h @@ -0,0 +1,121 @@ +//*----------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*----------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : ebi.h +//* Object : External Bus Interface Definition File +//* Translator : ARM Software Development Toolkit V2.11a +//* +//* 1.0 03/11/97 JCZ : Creation +//* 2.0 21/10/98 JCZ : Clean up +//*----------------------------------------------------------------------------- + +#ifndef ebi_h +#define ebi_h + +/*----------------------------------------*/ +/* Memory Controller Interface Definition */ +/*----------------------------------------*/ + +typedef struct +{ + at91_reg EBI_CSR[8] ; /* Chip Select Register */ + at91_reg EBI_RCR ; /* Remap Control Register */ + at91_reg EBI_MCR ; /* Memory Control Register */ +} StructEBI ; + +/*-----------------------*/ +/* Chip Select Registers */ +/*-----------------------*/ + +/* Data Bus Width */ +#define DataBus16 (1<<0) +#define DataBus8 (2<<0) +#define DBW (3<<0) + +/* Number of Wait States */ +#define B_NWS 2 +#define WaitState1 (0< +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/* Hardware specific definitions. */ +#include "aic.h" +#include "ebi.h" + +/*-----------------------------------------------------------*/ + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 5 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 7 ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +#define MAX_WAIT_STATES 8 +static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] = +{ + WaitState1,/* There is no "zero wait state" value, so use one wait state */ + WaitState1, + WaitState2, + WaitState3, + WaitState4, + WaitState5, + WaitState6, + WaitState7, + WaitState8 +}; +/*-----------------------------------------------------------*/ + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Reset xCreatedTask. This is modified by the task about to be + created so we can tell if it is executing correctly or not. */ + xCreatedTask = mainNO_TASK; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* The toggle rate of the LED depends on how long this task delays for. + An error reduces the delay period and so increases the toggle rate. */ + vParTestToggleLED( mainON_BOARD_LED_BIT ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +portLONG lCount; + + #ifdef RUN_FROM_ROM + { + portFLOAT nsecsPerClockTick; + portLONG lNumWaitStates; + unsigned portLONG ulCSRWaitValue; + + /* We are compiling to run from ROM (either on-chip or off-chip flash). + Leave the RAM/flash mapped the way they are on reset + (flash @ 0x00000000, RAM @ 0x00300000), and set up the + proper flash wait states (starts out at the maximum number + of wait states on reset, so we should be able to reduce it). + Most of this code will probably get removed by the compiler + if optimization is enabled, since these calculations are + based on constants. But the compiler should still produce + a correct wait state register value. */ + nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ; + lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1; + + if( lNumWaitStates < 0 ) + { + lNumWaitStates = 0; + } + + if( lNumWaitStates > MAX_WAIT_STATES ) + { + lNumWaitStates = MAX_WAIT_STATES; + } + + ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ]; + ulCSRWaitValue = WaitState5; + + AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable + | PageSize1M | tDF_0cycle + | ByteWriteAccessType | CSEnable + | 0x00000000 /* Base Address */; + } + #else /* else we are compiling to run from on-chip RAM */ + { + /* If compiling to run from RAM, we expect the on-chip RAM to already + be mapped at 0x00000000. This is typically done with an initialization + script for the JTAG emulator you are using to download and run the + demo application. So there is nothing to do here in this case. */ + } + #endif + + /* Disable all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + + /* Set all SVR and SMR entries to default values (start with a clean slate)... */ + for( lCount = 0; lCount < 32; lCount++ ) + { + AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0; + AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED; + } + + /* Disable clocks to all peripherals initially... */ + AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF; + + /* Clear all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + + /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out + nIRQ */ + for( lCount = 0; lCount < 8; lCount++ ) + { + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + /* Initialise LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + have failed. */ + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* There has been an error so reset the counter so the check task + can tell that an error occurred. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} + diff --git a/Demo/ARM7_AT91FR40008_GCC/pio.h b/Demo/ARM7_AT91FR40008_GCC/pio.h new file mode 100644 index 000000000..a65d138fc --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/pio.h @@ -0,0 +1,149 @@ +//*--------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*--------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : pio.h +//* Object : Parallel I/O Definition File +//* Translator : ARM Software Development Toolkit V2.11a +//* +//* 1.0 20/10/97 JCZ : Creation +//* 2.0 21/10/98 JCZ : Clean up +//*--------------------------------------------------------------------------- + +#ifndef pio_h +#define pio_h + +/*---------------------------------------------*/ +/* Parallel I/O Interface Structure Definition */ +/*---------------------------------------------*/ + +typedef struct +{ + at91_reg PIO_PER ; /* PIO Enable Register */ + at91_reg PIO_PDR ; /* PIO Disable Register */ + at91_reg PIO_PSR ; /* PIO Status Register */ + at91_reg Reserved0 ; + at91_reg PIO_OER ; /* Output Enable Register */ + at91_reg PIO_ODR ; /* Output Disable Register */ + at91_reg PIO_OSR ; /* Output Status Register */ + at91_reg Reserved1 ; + at91_reg PIO_IFER ; /* Input Filter Enable Register */ + at91_reg PIO_IFDR ; /* Input Filter Disable Register */ + at91_reg PIO_IFSR ; /* Input Filter Status Register */ + at91_reg Reserved2 ; + at91_reg PIO_SODR ; /* Set Output Data Register */ + at91_reg PIO_CODR ; /* Clear Output Data Register */ + at91_reg PIO_ODSR ; /* Output Data Status Register */ + at91_reg PIO_PDSR ; /* Pin Data Status Register */ + at91_reg PIO_IER ; /* Interrupt Enable Register */ + at91_reg PIO_IDR ; /* Interrupt Disable Register */ + at91_reg PIO_IMR ; /* Interrupt Mask Register */ + at91_reg PIO_ISR ; /* Interrupt Status Register */ +} StructPIO ; + +/*-----------------------------*/ +/* PIO Handler type definition */ +/*-----------------------------*/ + +//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ; + +/*--------------------------------*/ +/* Device Dependancies Definition */ +/*--------------------------------*/ + +/* Number of PIO Controller */ +#define NB_PIO_CTRL 1 +/* Base Address */ +#define PIO_BASE ((StructPIO *) 0xFFFF0000 ) +/* Number of PIO Lines */ +#define NB_PIO 32 + +/* Parallel I/O Bits Definition */ +#define P0 (1<<0) +#define P1 (1<<1) +#define P2 (1<<2) +#define P3 (1<<3) +#define P4 (1<<4) +#define P5 (1<<5) +#define P6 (1<<6) +#define P7 (1<<7) +#define P8 (1<<8) +#define P9 (1<<9) +#define P10 (1<<10) +#define P11 (1<<11) +#define P12 (1<<12) +#define P13 (1<<13) +#define P14 (1<<14) +#define P15 (1<<15) +#define P16 (1<<16) +#define P17 (1<<17) +#define P18 (1<<18) +#define P19 (1<<19) +#define P20 (1<<20) +#define P21 (1<<21) +#define P22 (1<<22) +#define P23 (1<<23) +#define P24 (1<<24) +#define P25 (1<<25) +#define P26 (1<<26) +#define P27 (1<<27) +#define P28 (1<<28) +#define P29 (1<<29) +#define P30 (1<<30) +#define P31 (1<<31) + +/* PIO Multiplexing Definition */ + +/* There is only one PIO Controller */ +#define PIO_CTRL 0 + +#define PIO_TC0 PIO_CTRL +#define TCLK0 P0 +#define TIOA0 P1 +#define TIOB0 P2 +#define PIN_TC0 (TIOA0|TIOB0|TCLK0) + +#define PIO_TC1 PIO_CTRL +#define TCLK1 P3 +#define TIOA1 P4 +#define TIOB1 P5 +#define PIN_TC1 (TIOA1|TIOB1|TCLK1) + +#define PIO_TC2 PIO_CTRL +#define TCLK2 P6 +#define TIOA2 P7 +#define TIOB2 P8 +#define PIN_TC2 (TIOA2|TIOB2|TCLK2) + +#define PIO_EXT_IRQ PIO_CTRL +#define PIN_IRQ0 P9 +#define PIN_IRQ1 P10 +#define PIN_IRQ2 P11 +#define PIN_FIQ P12 + +#define PIO_USART0 PIO_CTRL +#define SCK0 P13 +#define TXD0 P14 +#define RXD0 P15 +#define PIN_USART0 (SCK0|TXD0|RXD0) + +#define PIO_USART1 PIO_CTRL +#define SCK1 P20 +#define TXD1 P21 +#define RXD1 P22 +#define PIN_USART1 (SCK1|TXD1|RXD1) + +#define MCKO P25 +#define CS2 P26 +#define CS3 P27 +#define CS4 P31 +#define CS5 P30 +#define CS6 P29 +#define CS7 P28 + +#endif /* pio_h */ diff --git a/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat b/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat new file mode 100644 index 000000000..355bb5ec2 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=atmel-ram.ld +make diff --git a/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat b/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat new file mode 100644 index 000000000..4d5b84593 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=atmel-ram.ld +make diff --git a/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat b/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat new file mode 100644 index 000000000..0499bdbc9 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O2 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=atmel-rom.ld +make diff --git a/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat b/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat new file mode 100644 index 000000000..9c36b6cfe --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O2 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=atmel-rom.ld +make diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serial.c b/Demo/ARM7_AT91FR40008_GCC/serial/serial.c new file mode 100644 index 000000000..b3fef853f --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/serial/serial.c @@ -0,0 +1,228 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" +#include "AT91R40008.h" +#include "usart.h" +#include "pio.h" +#include "aic.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define portUSART0_AIC_CHANNEL ( ( unsigned portLONG ) 2 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulSpeed; +unsigned portLONG ulCD; +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR )( void ); + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode. */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Enable clock to USART0... */ + AT91C_BASE_PS->PS_PCER = AT91C_PS_US0; + + /* Disable all USART0 interrupt sources to begin... */ + AT91C_BASE_US0->US_IDR = 0xFFFFFFFF; + + /* Reset various status bits (just in case)... */ + AT91C_BASE_US0->US_CR = US_RSTSTA; + + AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */ + AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS; + + /* Clear Transmit and Receive Counters */ + AT91C_BASE_US0->US_RCR = 0; + AT91C_BASE_US0->US_TCR = 0; + + /* Input clock to baud rate generator is MCK */ + ulSpeed = configCPU_CLOCK_HZ * 10; + ulSpeed = ulSpeed / 16; + ulSpeed = ulSpeed / ulWantedBaud; + + /* compute the error */ + ulCD = ulSpeed / 10; + if ((ulSpeed - (ulCD * 10)) >= 5) + ulCD++; + + /* Define the baud rate divisor register */ + AT91C_BASE_US0->US_BRGR = ulCD; + + /* Define the USART mode */ + AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL; + + /* Write the Timeguard Register */ + AT91C_BASE_US0->US_TTGR = 0; + + /* Setup the interrupt for USART0. + + Store interrupt handler function address in USART0 vector register... */ + AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR; + + /* USART0 interrupt level-sensitive, priority 1... */ + AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1; + + /* Clear some pending USART0 interrupts (just in case)... */ + AT91C_BASE_US0->US_CR = US_RSTSTA; + + /* Enable USART0 interrupt sources (but not Tx for now)... */ + AT91C_BASE_US0->US_IER = US_RXRDY; + + /* Enable USART0 interrupts in the AIC... */ + AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL ); + + /* Enable receiver and transmitter... */ + AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + AT91C_BASE_US0->US_IER = US_TXRDY; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c b/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c new file mode 100644 index 000000000..8f8b1c2b2 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c @@ -0,0 +1,144 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. + +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" +#include "AT91R40008.h" +#include "usart.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the AIC. */ +#define serCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* UART0 interrupt service routine. This can cause a context switch so MUST +be declared "naked". */ +void vUART_ISR( void ) __attribute__ ((naked)); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) +{ + /* This ISR can cause a context switch, so the first statement must be a + call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + variable declarations. */ + portENTER_SWITCHING_ISR(); + + /* Now we can declare the local variables. */ + signed portCHAR cChar; + portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; + unsigned portLONG ulStatus; + + /* What caused the interrupt? */ + ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR; + + if (ulStatus & US_TXRDY) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + AT91C_BASE_US0->US_THR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + AT91C_BASE_US0->US_IDR = US_TXRDY; + } + } + + if (ulStatus & US_RXRDY) + { + /* The interrupt was caused by the receiver getting data. */ + cChar = AT91C_BASE_US0->US_RHR; + + if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE)) + { + xTaskWokenByRx = pdTRUE; + } + } + + // Acknowledge the interrupt at AIC level... + AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT; + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/ARM7_AT91FR40008_GCC/tc.h b/Demo/ARM7_AT91FR40008_GCC/tc.h new file mode 100644 index 000000000..518220e47 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/tc.h @@ -0,0 +1,301 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : tc.h +//* Object : Timer Counter Header File +//* +//* 1.0 01/04/00 JCZ : Creation +//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT, +//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT +//*----------------------------------------------------------------------------- + +#ifndef tc_h +#define tc_h + +//#include "periph/stdc/std_c.h" +//#include "periph/pio/lib_pio.h" + +/*-------------------------------------------*/ +/* Timer User Interface Structure Definition */ +/*-------------------------------------------*/ + +typedef struct +{ + at91_reg TC_CCR ; /* Control Register */ + at91_reg TC_CMR ; /* Mode Register */ + at91_reg Reserved0 ; + at91_reg Reserved1 ; + at91_reg TC_CV ; /* Counter value */ + at91_reg TC_RA ; /* Register A */ + at91_reg TC_RB ; /* Register B */ + at91_reg TC_RC ; /* Register C */ + at91_reg TC_SR ; /* Status Register */ + at91_reg TC_IER ; /* Interrupt Enable Register */ + at91_reg TC_IDR ; /* Interrupt Disable Register */ + at91_reg TC_IMR ; /* Interrupt Mask Register */ + at91_reg Reserved2 ; + at91_reg Reserved3 ; + at91_reg Reserved4 ; + at91_reg Reserved5 ; +} StructTC ; + +#define NB_TC_CHANNEL 3 + +typedef struct +{ + StructTC TC[NB_TC_CHANNEL] ; + at91_reg TC_BCR ; /* Block Control Register */ + at91_reg TC_BMR ; /* Block Mode Register */ +} StructTCBlock ; + +/*--------------------------------------------------------*/ +/* TC_CCR: Timer Counter Control Register Bits Definition */ +/*--------------------------------------------------------*/ +#define TC_CLKEN 0x1 +#define TC_CLKDIS 0x2 +#define TC_SWTRG 0x4 + +/*---------------------------------------------------------------*/ +/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */ +/*---------------------------------------------------------------*/ + +/*-----------------*/ +/* Clock Selection */ +/*-----------------*/ +#define TC_CLKS 0x7 +#define TC_CLKS_MCK2 0x0 +#define TC_CLKS_MCK8 0x1 +#define TC_CLKS_MCK32 0x2 +#define TC_CLKS_MCK128 0x3 +#define TC_CLKS_MCK1024 0x4 + +#define TC_CLKS_SLCK 0x4 + +#define TC_CLKS_XC0 0x5 +#define TC_CLKS_XC1 0x6 +#define TC_CLKS_XC2 0x7 + + +/*-----------------*/ +/* Clock Inversion */ +/*-----------------*/ +#define TC_CLKI 0x8 + +/*------------------------*/ +/* Burst Signal Selection */ +/*------------------------*/ +#define TC_BURST 0x30 +#define TC_BURST_NONE 0x0 +#define TC_BUSRT_XC0 0x10 +#define TC_BURST_XC1 0x20 +#define TC_BURST_XC2 0x30 + +/*------------------------------------------------------*/ +/* Capture Mode : Counter Clock Stopped with RB Loading */ +/*------------------------------------------------------*/ +#define TC_LDBSTOP 0x40 + +/*-------------------------------------------------------*/ +/* Waveform Mode : Counter Clock Stopped with RC Compare */ +/*-------------------------------------------------------*/ +#define TC_CPCSTOP 0x40 + +/*-------------------------------------------------------*/ +/* Capture Mode : Counter Clock Disabled with RB Loading */ +/*--------------------------------------------------------*/ +#define TC_LDBDIS 0x80 + +/*--------------------------------------------------------*/ +/* Waveform Mode : Counter Clock Disabled with RC Compare */ +/*--------------------------------------------------------*/ +#define TC_CPCDIS 0x80 + +/*------------------------------------------------*/ +/* Capture Mode : External Trigger Edge Selection */ +/*------------------------------------------------*/ +#define TC_ETRGEDG 0x300 +#define TC_ETRGEDG_EDGE_NONE 0x0 +#define TC_ETRGEDG_RISING_EDGE 0x100 +#define TC_ETRGEDG_FALLING_EDGE 0x200 +#define TC_ETRGEDG_BOTH_EDGE 0x300 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Edge Selection */ +/*-----------------------------------------------*/ +#define TC_EEVTEDG 0x300 +#define TC_EEVTEDG_EDGE_NONE 0x0 +#define TC_EEVTEDG_RISING_EDGE 0x100 +#define TC_EEVTEDG_FALLING_EDGE 0x200 +#define TC_EEVTEDG_BOTH_EDGE 0x300 + +/*--------------------------------------------------------*/ +/* Capture Mode : TIOA or TIOB External Trigger Selection */ +/*--------------------------------------------------------*/ +#define TC_ABETRG 0x400 +#define TC_ABETRG_TIOB 0x0 +#define TC_ABETRG_TIOA 0x400 + +/*------------------------------------------*/ +/* Waveform Mode : External Event Selection */ +/*------------------------------------------*/ +#define TC_EEVT 0xC00 +#define TC_EEVT_TIOB 0x0 +#define TC_EEVT_XC0 0x400 +#define TC_EEVT_XC1 0x800 +#define TC_EEVT_XC2 0xC00 + +/*--------------------------------------------------*/ +/* Waveform Mode : Enable Trigger on External Event */ +/*--------------------------------------------------*/ +#define TC_ENETRG 0x1000 + +/*----------------------------------*/ +/* RC Compare Enable Trigger Enable */ +/*----------------------------------*/ +#define TC_CPCTRG 0x4000 + +/*----------------*/ +/* Mode Selection */ +/*----------------*/ +#define TC_WAVE 0x8000 +#define TC_CAPT 0x0 + +/*-------------------------------------*/ +/* Capture Mode : RA Loading Selection */ +/*-------------------------------------*/ +#define TC_LDRA 0x30000 +#define TC_LDRA_EDGE_NONE 0x0 +#define TC_LDRA_RISING_EDGE 0x10000 +#define TC_LDRA_FALLING_EDGE 0x20000 +#define TC_LDRA_BOTH_EDGE 0x30000 + +/*-------------------------------------------*/ +/* Waveform Mode : RA Compare Effect on TIOA */ +/*-------------------------------------------*/ +#define TC_ACPA 0x30000 +#define TC_ACPA_OUTPUT_NONE 0x0 +#define TC_ACPA_SET_OUTPUT 0x10000 +#define TC_ACPA_CLEAR_OUTPUT 0x20000 +#define TC_ACPA_TOGGLE_OUTPUT 0x30000 + +/*-------------------------------------*/ +/* Capture Mode : RB Loading Selection */ +/*-------------------------------------*/ +#define TC_LDRB 0xC0000 +#define TC_LDRB_EDGE_NONE 0x0 +#define TC_LDRB_RISING_EDGE 0x40000 +#define TC_LDRB_FALLING_EDGE 0x80000 +#define TC_LDRB_BOTH_EDGE 0xC0000 + +/*-------------------------------------------*/ +/* Waveform Mode : RC Compare Effect on TIOA */ +/*-------------------------------------------*/ +#define TC_ACPC 0xC0000 +#define TC_ACPC_OUTPUT_NONE 0x0 +#define TC_ACPC_SET_OUTPUT 0x40000 +#define TC_ACPC_CLEAR_OUTPUT 0x80000 +#define TC_ACPC_TOGGLE_OUTPUT 0xC0000 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Effect on TIOA */ +/*-----------------------------------------------*/ +#define TC_AEEVT 0x300000 +#define TC_AEEVT_OUTPUT_NONE 0x0 +#define TC_AEEVT_SET_OUTPUT 0x100000 +#define TC_AEEVT_CLEAR_OUTPUT 0x200000 +#define TC_AEEVT_TOGGLE_OUTPUT 0x300000 + +/*-------------------------------------------------*/ +/* Waveform Mode : Software Trigger Effect on TIOA */ +/*-------------------------------------------------*/ +#define TC_ASWTRG 0xC00000 +#define TC_ASWTRG_OUTPUT_NONE 0x0 +#define TC_ASWTRG_SET_OUTPUT 0x400000 +#define TC_ASWTRG_CLEAR_OUTPUT 0x800000 +#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000 + +/*-------------------------------------------*/ +/* Waveform Mode : RB Compare Effect on TIOB */ +/*-------------------------------------------*/ +#define TC_BCPB 0x1000000 +#define TC_BCPB_OUTPUT_NONE 0x0 +#define TC_BCPB_SET_OUTPUT 0x1000000 +#define TC_BCPB_CLEAR_OUTPUT 0x2000000 +#define TC_BCPB_TOGGLE_OUTPUT 0x3000000 + +/*-------------------------------------------*/ +/* Waveform Mode : RC Compare Effect on TIOB */ +/*-------------------------------------------*/ +#define TC_BCPC 0xC000000 +#define TC_BCPC_OUTPUT_NONE 0x0 +#define TC_BCPC_SET_OUTPUT 0x4000000 +#define TC_BCPC_CLEAR_OUTPUT 0x8000000 +#define TC_BCPC_TOGGLE_OUTPUT 0xC000000 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Effect on TIOB */ +/*-----------------------------------------------*/ +#define TC_BEEVT 0x30000000 //* bit 29-28 +#define TC_BEEVT_OUTPUT_NONE 0x0 +#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01 +#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10 +#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11 + +/*- -----------------------------------------------*/ +/* Waveform Mode : Software Trigger Effect on TIOB */ +/*-------------------------------------------------*/ +#define TC_BSWTRG 0xC0000000 +#define TC_BSWTRG_OUTPUT_NONE 0x0 +#define TC_BSWTRG_SET_OUTPUT 0x40000000 +#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000 +#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 + +/*------------------------------------------------------*/ +/* TC_SR: Timer Counter Status Register Bits Definition */ +/*------------------------------------------------------*/ +#define TC_COVFS 0x1 /* Counter Overflow Status */ +#define TC_LOVRS 0x2 /* Load Overrun Status */ +#define TC_CPAS 0x4 /* RA Compare Status */ +#define TC_CPBS 0x8 /* RB Compare Status */ +#define TC_CPCS 0x10 /* RC Compare Status */ +#define TC_LDRAS 0x20 /* RA Loading Status */ +#define TC_LDRBS 0x40 /* RB Loading Status */ +#define TC_ETRGS 0x80 /* External Trigger Status */ +#define TC_CLKSTA 0x10000 /* Clock Status */ +#define TC_MTIOA 0x20000 /* TIOA Mirror */ +#define TC_MTIOB 0x40000 /* TIOB Status */ + +/*--------------------------------------------------------------*/ +/* TC_BCR: Timer Counter Block Control Register Bits Definition */ +/*--------------------------------------------------------------*/ +#define TC_SYNC 0x1 /* Synchronisation Trigger */ + +/*------------------------------------------------------------*/ +/* TC_BMR: Timer Counter Block Mode Register Bits Definition */ +/*------------------------------------------------------------*/ +#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */ +#define TC_TCLK0XC0 0x0 +#define TC_NONEXC0 0x1 +#define TC_TIOA1XC0 0x2 +#define TC_TIOA2XC0 0x3 + +#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */ +#define TC_TCLK1XC1 0x0 +#define TC_NONEXC1 0x4 +#define TC_TIOA0XC1 0x8 +#define TC_TIOA2XC1 0xC + +#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */ +#define TC_TCLK2XC2 0x0 +#define TC_NONEXC2 0x10 +#define TC_TIOA0XC2 0x20 +#define TC_TIOA1XC2 0x30 + +#endif /* tc_h */ + diff --git a/Demo/ARM7_AT91FR40008_GCC/usart.h b/Demo/ARM7_AT91FR40008_GCC/usart.h new file mode 100644 index 000000000..ad36ef504 --- /dev/null +++ b/Demo/ARM7_AT91FR40008_GCC/usart.h @@ -0,0 +1,151 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : usart.h +//* Object : USART Header File. +//* +//* 1.0 01/04/00 JCZ : Creation +//*---------------------------------------------------------------------------- + +#ifndef usart_h +#define usart_h + +//#include "periph/stdc/std_c.h" +//#include "periph/pio/lib_pio.h" + +/*-------------------------------------------*/ +/* USART User Interface Structure Definition */ +/*-------------------------------------------*/ + +typedef struct +{ + at91_reg US_CR ; /* Control Register */ + at91_reg US_MR ; /* Mode Register */ + at91_reg US_IER ; /* Interrupt Enable Register */ + at91_reg US_IDR ; /* Interrupt Disable Register */ + at91_reg US_IMR ; /* Interrupt Mask Register */ + at91_reg US_CSR ; /* Channel Status Register */ + at91_reg US_RHR ; /* Receive Holding Register */ + at91_reg US_THR ; /* Transmit Holding Register */ + at91_reg US_BRGR ; /* Baud Rate Generator Register */ + at91_reg US_RTOR ; /* Receiver Timeout Register */ + at91_reg US_TTGR ; /* Transmitter Time-guard Register */ + at91_reg Reserved ; + at91_reg US_RPR ; /* Receiver Pointer Register */ + at91_reg US_RCR ; /* Receiver Counter Register */ + at91_reg US_TPR ; /* Transmitter Pointer Register */ + at91_reg US_TCR ; /* Transmitter Counter Register */ +} StructUSART ; + +/*--------------------------*/ +/* US_CR : Control Register */ +/*--------------------------*/ + +#define US_RSTRX 0x0004 /* Reset Receiver */ +#define US_RSTTX 0x0008 /* Reset Transmitter */ +#define US_RXEN 0x0010 /* Receiver Enable */ +#define US_RXDIS 0x0020 /* Receiver Disable */ +#define US_TXEN 0x0040 /* Transmitter Enable */ +#define US_TXDIS 0x0080 /* Transmitter Disable */ +#define US_RSTSTA 0x0100 /* Reset Status Bits */ +#define US_STTBRK 0x0200 /* Start Break */ +#define US_STPBRK 0x0400 /* Stop Break */ +#define US_STTTO 0x0800 /* Start Time-out */ +#define US_SENDA 0x1000 /* Send Address */ + +/*-----------------------*/ +/* US_MR : Mode Register */ +/*-----------------------*/ + +#define US_CLKS 0x0030 /* Clock Selection */ +#define US_CLKS_MCK 0x00 /* Master Clock */ +#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */ +#define US_CLKS_SCK 0x20 /* External Clock */ +#define US_CLKS_SLCK 0x30 /* Slow Clock */ + +#define US_CHRL 0x00C0 /* Byte Length */ +#define US_CHRL_5 0x00 /* 5 bits */ +#define US_CHRL_6 0x40 /* 6 bits */ +#define US_CHRL_7 0x80 /* 7 bits */ +#define US_CHRL_8 0xC0 /* 8 bits */ + +#define US_SYNC 0x0100 /* Synchronous Mode Enable */ + +#define US_PAR 0x0E00 /* Parity Mode */ +#define US_PAR_EVEN 0x00 /* Even Parity */ +#define US_PAR_ODD 0x200 /* Odd Parity */ +#define US_PAR_SPACE 0x400 /* Space Parity to 0 */ +#define US_PAR_MARK 0x600 /* Marked Parity to 1 */ +#define US_PAR_NO 0x800 /* No Parity */ +#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */ + +#define US_NBSTOP 0x3000 /* Stop Bit Number */ +#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */ +#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */ +#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */ + +#define US_CHMODE 0xC000 /* Channel Mode */ +#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */ +#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */ +#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */ +#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */ + +#define US_MODE9 0x20000 /* 9 Bit Mode */ + +#define US_CLKO 0x40000 /* Baud Rate Output Enable */ + +/* Mode Register model */ + +/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_MCK ) + +/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_SCK ) + +/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */ +#define US_SYNC_MODE ( US_SYNC + \ + US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_MCK ) + +/* SCK used Label */ +#define SCK_USED (US_CLKO | US_CLKS_SCK) + +/*---------------------------------------------------------------*/ +/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */ +/*---------------------------------------------------------------*/ + +#define US_RXRDY 0x1 /* Receiver Ready */ +#define US_TXRDY 0x2 /* Transmitter Ready */ +#define US_RXBRK 0x4 /* Receiver Break */ +#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */ +#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */ +#define US_OVRE 0x20 /* Overrun Error */ +#define US_FRAME 0x40 /* Framing Error */ +#define US_PARE 0x80 /* Parity Error */ +#define US_TIMEOUT 0x100 /* Receiver Timeout */ +#define US_TXEMPTY 0x200 /* Transmitter Empty */ + +#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY) +#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT) +#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK) + + + +#endif /* usart_h */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..7b016ae5b --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include "board.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c b/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..5c46686fc --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c @@ -0,0 +1,81 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "partest.h" +#include "board.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's. + *-----------------------------------------------------------*/ + +const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 }; + +void vParTestInitialise( void ) +{ + /* Start with all LED's off. */ + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < ( portBASE_TYPE ) NB_LED ) + { + if( xValue ) + { + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); + } + else + { + AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < ( portBASE_TYPE ) NB_LED ) + { + if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] ) + { + AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); + } + else + { + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); + } + } +} + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h new file mode 100644 index 000000000..f6da8060c --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h @@ -0,0 +1,89 @@ +/*---------------------------------------------------------------------------- +* ATMEL Microcontroller Software Support - ROUSSET - +*---------------------------------------------------------------------------- +* The software is delivered "AS IS" without warranty or condition of any +* kind, either express, implied or statutory. This includes without +* limitation any warranty or condition with respect to merchantability or +* fitness for any particular purpose, or against the infringements of +* intellectual property rights of others. +*---------------------------------------------------------------------------- +* File Name : Board.h +* Object : AT91SAM7S Evaluation Board Features Definition File. +* +* Creation : JPP 16/Jun/2004 +*---------------------------------------------------------------------------- +*/ +#ifndef Board_h +#define Board_h + +#include "AT91SAM7S64.h" +#define __inline inline +#include "lib_AT91SAM7S64.h" + +#define true -1 +#define false 0 + +/*-------------------------------*/ +/* SAM7Board Memories Definition */ +/*-------------------------------*/ +// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash + +#define INT_SARM 0x00200000 +#define INT_SARM_REMAP 0x00000000 + +#define INT_FLASH 0x00000000 +#define INT_FLASH_REMAP 0x01000000 + +#define FLASH_PAGE_NB 512 +#define FLASH_PAGE_SIZE 128 + +/*-----------------*/ +/* Leds Definition */ +/*-----------------*/ +/* PIO Flash PA PB PIN */ +#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */ +#define NB_LED 4 + +#define LED_MASK (LED1|LED2|LED3|LED4) + +/*-------------------------*/ +/* Push Buttons Definition */ +/*-------------------------*/ +/* PIO Flash PA PB PIN */ +#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */ +#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */ +#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */ +#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */ +#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) + + +#define SW1 (1<<19) // PA19 +#define SW2 (1<<20) // PA20 +#define SW3 (1<<15) // PA15 +#define SW4 (1<<14) // PA14 + +/*------------------*/ +/* USART Definition */ +/*------------------*/ +/* SUB-D 9 points J3 DBGU*/ +#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */ +#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */ +#define AT91C_DBGU_BAUD 115200 // Baud rate + +#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */ +#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */ +#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */ +#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */ + +/*--------------*/ +/* Master Clock */ +/*--------------*/ + +#define EXT_OC 18432000 // Exetrnal ocilator MAINCK +#define MCK 47923200 // MCK (PLLRC div by 2) +#define MCKKHz (MCK/1000) // + +#endif /* Board_h */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 new file mode 100644 index 000000000..966f6f243 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 @@ -0,0 +1,223 @@ +;------------------------------------------------------------------------------ +;- ATMEL Microcontroller Software Support - ROUSSET - +;------------------------------------------------------------------------------ +; The software is delivered "AS IS" without warranty or condition of any +; kind, either express, implied or statutory. This includes without +; limitation any warranty or condition with respect to merchantability or +; fitness for any particular purpose, or against the infringements of +; intellectual property rights of others. +;----------------------------------------------------------------------------- +;- File source : Cstartup.s79 +;- Object : Generic CStartup for IAR No Use REMAP +;- Compilation flag : None +;- +;- 1.0 15/Jun/04 JPP : Creation +;------------------------------------------------------------------------------ + +#include "AT91SAM7S64_inc.h" + +;------------------------------------------------------------------------------ +;- Area Definition +;------------------------------------------------------------------------------ + +;--------------------------------------------------------------- +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other +; addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;------------------------------------------------------------- + + PROGRAM ?RESET + RSEG INTRAMSTART_REMAP + RSEG INTRAMEND_REMAP + + EXTERN vPortYieldProcessor + + RSEG ICODE:CODE:ROOT(2) + CODE32 ; Always ARM mode after reset + org 0 +reset +;------------------------------------------------------------------------------ +;- Exception vectors +;-------------------- +;- These vectors can be read at address 0 or at RAM address +;- They ABSOLUTELY requires to be in relative addresssing mode in order to +;- guarantee a valid jump. For the moment, all are just looping. +;- If an exception occurs before remap, this would result in an infinite loop. +;- To ensure if a exeption occurs before start application to infinite loop. +;------------------------------------------------------------------------------ + + B InitReset ; 0x00 Reset handler +undefvec: + B undefvec ; 0x04 Undefined Instruction +swivec: + B vPortYieldProcessor ; 0x08 Software Interrupt +pabtvec: + B pabtvec ; 0x0C Prefetch Abort +dabtvec: + B dabtvec ; 0x10 Data Abort +rsvdvec: + B rsvdvec ; 0x14 reserved +irqvec: + LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC + +fiqvec: ; 0x1c FIQ + +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- Called Functions : AIC_FVR[interrupt] +;------------------------------------------------------------------------------ + +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 + +InitReset: +;------------------------------------------------------------------------------ +;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit +;------------------------------------------------------------------------------ + EXTERN AT91F_LowLevelInit + +#define __iramend SFB(INTRAMEND_REMAP) + +;- minumum C initialization +;- call AT91F_LowLevelInit( void) + + ldr r13,=__iramend ; temporary stack in internal RAM +;--Call Low level init function in ABSOLUTE through the Interworking + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 +;------------------------------------------------------------------------------ +;- Stack Sizes Definition +;------------------------ +;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using +;- the vectoring. This assume that the IRQ management. +;- The Interrupt Stack must be adjusted depending on the interrupt handlers. +;- Fast Interrupt not requires stack If in your application it required you must +;- be definehere. +;- The System stack size is not defined and is limited by the free internal +;- SRAM. +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +;- Top of Stack Definition +;------------------------- +;- Interrupt and Supervisor Stack are located at the top of internal memory in +;- order to speed the exception handling context saving and restoring. +;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. +;------------------------------------------------------------------------------ + +IRQ_STACK_SIZE EQU 300 + +ARM_MODE_FIQ EQU 0x11 +ARM_MODE_IRQ EQU 0x12 +ARM_MODE_SVC EQU 0x13 + +I_BIT EQU 0x80 +F_BIT EQU 0x40 + +;------------------------------------------------------------------------------ +;- Setup the stack for each mode +;------------------------------- + ldr r0, =__iramend + +;- Set up Fast Interrupt Mode and set FIQ Mode Stack + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT +;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + +;- Set up Interrupt Mode and set IRQ Mode Stack + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov r13, r0 ; Init stack IRQ + sub r0, r0, #IRQ_STACK_SIZE + +;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack + msr CPSR_c, #ARM_MODE_SVC + mov r13, r0 + + +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- + EXTERN __segment_init + EXTERN main +; Initialize segments. +; __segment_init is assumed to use +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + ldr r0,=__segment_init + mov lr, pc + bx r0 + + PUBLIC __main +?jump_to_main: + ldr lr,=?call_exit + ldr r0,=main +__main: + bx r0 + +;------------------------------------------------------------------------------ +;- Loop for ever +;--------------- +;- End of application. Normally, never occur. +;- Could jump on Software Reset ( B 0x0 ). +;------------------------------------------------------------------------------ +?call_exit: +End + b End + + + +;--------------------------------------------------------------- +; ?EXEPTION_VECTOR +; This module is only linked if needed for closing files. +;--------------------------------------------------------------- + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + CODE32 ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + ENDMOD + + END + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c new file mode 100644 index 000000000..90b3982b8 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c @@ -0,0 +1,84 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Cstartup_SAM7.c +//* Object : Low level initializations written in C for IAR +//* tools +//* Creation : 12/Jun/04 +//* +//*---------------------------------------------------------------------------- + + +// Include the board file description +#include "Board.h" + +// The following functions must be write in ARM mode this function called directly +// by exception vector +extern void AT91F_Spurious_handler(void); +extern void AT91F_Default_IRQ_handler(void); +extern void AT91F_Default_FIQ_handler(void); + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//* this function can be use a Stack, depending the compilation +//* optimization mode +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit( void ); +void AT91F_LowLevelInit( void) @ "ICODE" +{ + int i; + AT91PS_PMC pPMC = AT91C_BASE_PMC; + //* Set Flash Waite sate + // Single Cycle Access at Up to 30 MHz, or 40 + // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN + AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ; + + //* Watchdog Disable + AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + + //* Set MCK at 47 923 200 + // 1 Enabling the Main Oscillator: + // SCK = 1/32768 = 30.51 uSeconde + // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); + // 2 Checking the Main Oscillator Frequency (Optional) + // 3 Setting PLL and divider: + // - div by 5 Fin = 3,6864 =(18,432 / 5) + // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) + // for 96 MHz the erroe is 0.16% + // Field out NOT USED = 0 + // PLLCOUNT pll startup time esrtimate at : 0.844 ms + // PLLCOUNT 28 = 0.000844 /(1/32768) + pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (25<<16))); + + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); + // 4. Selection of Master Clock and Processor Clock + // select the PLL clock divided by 2 + pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ; + + // Enable User Reset and set its minimal assertion to 960 us + AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24); + + + // Set up the default interrupts handler vectors + AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; + for (i=1;i < 31; i++) + { + AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; + } + AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; + +} + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c new file mode 100644 index 000000000..e53e62909 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c @@ -0,0 +1,1273 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Sample interrupt driven USB device driver. This is a minimal implementation + for demonstration only. Although functional, it is not a full and compliant + implementation. + + The USB device enumerates as a simple 3 axis joystick, and once configured + transmits 3 axis of data which can be viewed from the USB host machine. + + This file implements the USB interrupt service routine, and a demo FreeRTOS + task. The interrupt service routine handles the USB hardware - taking a + snapshot of the USB status at the point of the interrupt. The task receives + the status information from the interrupt for processing at the task level. + + See the FreeRTOS.org WEB documentation for more information. +*/ + +/* + Changes from V2.5.5 + + + Descriptors that have a length that is an exact multiple of usbFIFO_LENGTH + can now be transmitted. To this end an extra parameter has been + added to the prvSendControlData() function, and the state + eSENDING_EVEN_DESCRIPTOR has been introduced. Thanks to Scott Miller for + assisting with this contribution. + + Changes from V2.6.0 + + + Replaced the duplicated RX_DATA_BK0 in the interrupt mask with the + RX_DATA_BK1. +*/ + +/* Standard includes. */ +#include + +/* Demo board includes. */ +#include "board.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + + +/* Descriptor type definitions. */ +#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 ) +#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 ) +#define usbDESCRIPTOR_TYPE_STRING ( 0x03 ) + +/* USB request type definitions. */ +#define usbGET_REPORT_REQUEST ( 0x01 ) +#define usbGET_IDLE_REQUEST ( 0x02 ) +#define usbGET_PROTOCOL_REQUEST ( 0x03 ) +#define usbSET_REPORT_REQUEST ( 0x09 ) +#define usbSET_IDLE_REQUEST ( 0x0A ) +#define usbSET_PROTOCOL_REQUEST ( 0x0B ) +#define usbGET_CONFIGURATION_REQUEST ( 0x08 ) +#define usbGET_STATUS_REQUEST ( 0x00 ) +#define usbCLEAR_FEATURE_REQUEST ( 0x01 ) +#define usbSET_FEATURE_REQUEST ( 0x03 ) +#define usbSET_ADDRESS_REQUEST ( 0x05 ) +#define usbGET_DESCRIPTOR_REQUEST ( 0x06 ) +#define usbSET_CONFIGURATION_REQUEST ( 0x09 ) +#define usbGET_INTERFACE_REQUEST ( 0x0A ) +#define usbSET_INTERFACE_REQUEST ( 0x0B ) + + +/* Misc USB definitions. */ +#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF ) +#define usbBUS_POWERED ( 0x80 ) +#define usbHID_REPORT_DESCRIPTOR ( 0x22 ) +#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) ) + +/* Index to the various string. */ +#define usbLANGUAGE_STRING ( 0 ) +#define usbMANUFACTURER_STRING ( 1 ) +#define usbPRODUCT_STRING ( 2 ) +#define usbCONFIGURATION_STRING ( 3 ) +#define usbINTERFACE_STRING ( 4 ) + +/* Data indexes for reading the request from the xISRStatus.ucFifoData[] +into xUSB_REQUEST. The data order is designed for speed - so looks a +little odd. */ +#define usbREQUEST_TYPE_INDEX ( 7 ) +#define usbREQUEST_INDEX ( 6 ) +#define usbVALUE_HIGH_BYTE ( 4 ) +#define usbVALUE_LOW_BYTE ( 5 ) +#define usbINDEX_HIGH_BYTE ( 2 ) +#define usbINDEX_LOW_BYTE ( 3 ) +#define usbLENGTH_HIGH_BYTE ( 0 ) +#define usbLENGTH_LOW_BYTE ( 1 ) + +/* Misc application definitions. */ +#define usbINTERRUPT_PRIORITY ( 3 ) +#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */ +#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 ) +#define usbEND_POINT_0 ( 0 ) +#define usbEND_POINT_1 ( 1 ) +#define usbXUP ( 1 ) +#define usbXDOWN ( 2 ) +#define usbYUP ( 3 ) +#define usbYDOWN ( 4 ) +#define usbMAX_COORD ( 120 ) +#define usbMAX_TX_MESSAGE_SIZE ( 128 ) +#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff ) +#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR +#define usbSHORTEST_DELAY ( ( portTickType ) 1 ) +#define usbINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS ) +#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f ) +#define usbDATA_INC ( ( portCHAR ) 5 ) +#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 ) + +/* Control request types. */ +#define usbSTANDARD_DEVICE_REQUEST ( 0 ) +#define usbSTANDARD_INTERFACE_REQUEST ( 1 ) +#define usbSTANDARD_END_POINT_REQUEST ( 2 ) +#define usbCLASS_INTERFACE_REQUEST ( 5 ) + +/*-----------------------------------------------------------*/ + +/* Structure used to take a snapshot of the USB status from within the ISR. */ +typedef struct X_ISR_STATUS +{ + unsigned portLONG ulISR; + unsigned portLONG ulCSR0; + unsigned portCHAR ucFifoData[ 8 ]; +} xISRStatus; + +/* Structure used to hold the received requests. */ +typedef struct +{ + unsigned portCHAR ucReqType; + unsigned portCHAR ucRequest; + unsigned portSHORT usValue; + unsigned portSHORT usIndex; + unsigned portSHORT usLength; +} xUSB_REQUEST; + +typedef enum +{ + eNOTHING, + eJUST_RESET, + eJUST_GOT_CONFIG, + eJUST_GOT_ADDRESS, + eSENDING_EVEN_DESCRIPTOR, + eREADY_TO_SEND +} eDRIVER_STATE; + +/* Structure used to control the data being sent to the host. */ +typedef struct +{ + unsigned portCHAR ucTxBuffer[ usbMAX_TX_MESSAGE_SIZE ]; + unsigned portLONG ulNextCharIndex; + unsigned portLONG ulTotalDataLength; +} xTX_MESSAGE; + +/*-----------------------------------------------------------*/ + +/* + * The USB interrupt service routine. This takes a snapshot of the USB + * device at the time of the interrupt, clears the interrupts, and posts + * the data to the USB processing task. + */ +__arm void vUSB_ISR( void ); + +/* + * Called after the bus reset interrupt - this function readies all the + * end points for communication. + */ +static void prvResetEndPoints( void ); + +/* + * Setup the USB hardware, install the interrupt service routine and + * initialise all the state variables. + */ +static void vInitUSBInterface( void ); + +/* + * Decode and act upon an interrupt generated by the control end point. + */ +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard device requests originating on the control + * end point. + */ +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard interface requests originating on the control + * end point. + */ +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard end point requests originating on the control + * end point. + */ +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle the class interface requests. + */ +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * Setup the Tx buffer to send data in response to a control request. + * + * The data to be transmitted is buffered, the state variables are updated, + * then prvSendNextSegment() is called to start the transmission off. Once + * the first segment has been sent the remaining segments are transmitted + * in response to TXCOMP interrupts until the entire buffer has been + * sent. + */ +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor ); + +/* + * Examine the Tx buffer to see if there is any more data to be transmitted. + * + * If there is data to be transmitted then send the next segment. A segment + * can have a maximum of 8 bytes (this is defined as the maximum for the end + * point by the descriptor). The final segment may be less than 8 bytes if + * the total data length was not an exact multiple of 8. + */ +static void prvSendNextSegment( void ); + +/* + * A stall condition is forced each time the host makes a request that is not + * supported by this minimal implementation. + * + * A stall is forced by setting the appropriate bit in the end points control + * and status register. + */ +static void prvSendStall( void ); + +/* + * A NULL (or zero length packet) is transmitted in acknowledge the reception + * of certain events from the host. + */ +static void prvUSBTransmitNull( void ); + +/* + * When the host requests a descriptor this function is called to determine + * which descriptor is being requested and start its transmission. + */ +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ); + +/* + * This demo USB device enumerates as a simple 3 axis joystick. Once + * configured this function is periodically called to generate some sample + * joystick data. + * + * The x and y axis are made to move in a square. The z axis is made to + * repeatedly increment up to its maximum. + */ +static void prvTransmitSampleValues( void ); + +/* + * The created task to handle the USB demo functionality. + */ +void vUSBDemoTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* + - DESCRIPTOR DEFINITIONS - +*/ + +/* String descriptors used during the enumeration process. +These take the form: + +{ + Length of descriptor, + Descriptor type, + Data +} +*/ +const portCHAR pxLanguageStringDescriptor[] = +{ + 4, + usbDESCRIPTOR_TYPE_STRING, + 0x09, 0x04 +}; + +const portCHAR pxManufacturerStringDescriptor[] = +{ + 18, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00 +}; + +const portCHAR pxProductStringDescriptor[] = +{ + 44, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00, + '.', 0x00, + 'o', 0x00, + 'r', 0x00, + 'g', 0x00, + ' ', 0x00, + 'J', 0x00, + 'o', 0x00, + 'y', 0x00, + 's', 0x00, + 't', 0x00, + 'i', 0x00, + 'c', 0x00, + 'k', 0x00 +}; + +const portCHAR pxConfigurationStringDescriptor[] = +{ + 38, + usbDESCRIPTOR_TYPE_STRING, + + 'C', 0x00, + 'o', 0x00, + 'n', 0x00, + 'f', 0x00, + 'i', 0x00, + 'g', 0x00, + 'u', 0x00, + 'r', 0x00, + 'a', 0x00, + 't', 0x00, + 'i', 0x00, + 'o', 0x00, + 'n', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +const portCHAR pxInterfaceStringDescriptor[] = +{ + 30, + usbDESCRIPTOR_TYPE_STRING, + + 'I', 0x00, + 'n', 0x00, + 't', 0x00, + 'e', 0x00, + 'r', 0x00, + 'f', 0x00, + 'a', 0x00, + 'c', 0x00, + 'e', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +/* Enumeration descriptors. */ +const portCHAR pxReportDescriptor[] = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x04, /* USAGE (Joystick) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x01, /* USAGE (Pointer) */ + 0xa1, 0x00, /* COLLECTION (Physical) */ + 0x09, 0x30, /* USAGE (X) */ + 0x09, 0x31, /* USAGE (Y) */ + 0x09, 0x32, /* USAGE (Z) */ + 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */ + 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0xc0, /* END_COLLECTION */ + 0xc0 /* END_COLLECTION */ +}; + +const char pxDeviceDescriptor[] = +{ + /* Device descriptor */ + 0x12, /* bLength */ + 0x01, /* bDescriptorType */ + 0x10, 0x01, /* bcdUSBL */ + usbDEVICE_CLASS_VENDOR_SPECIFIC, /* bDeviceClass: */ + 0x00, /* bDeviceSubclass: */ + 0x00, /* bDeviceProtocol: */ + 0x08, /* bMaxPacketSize0 */ + 0xFF, 0xFF, /* idVendorL */ + 0x01, 0x00, /* idProductL */ + 0x00, 0x01, /* bcdDeviceL */ + usbMANUFACTURER_STRING, /* iManufacturer */ + usbPRODUCT_STRING, /* iProduct */ + 0x00, /* SerialNumber */ + 0x01 /* bNumConfigs */ +}; + +const char pxConfigDescriptor[] = { + /* Configuration 1 descriptor */ + 0x09, /* CbLength */ + 0x02, /* CbDescriptorType */ + 0x22, 0x00, /* CwTotalLength 2 EP + Control */ + 0x01, /* CbNumInterfaces */ + 0x01, /* CbConfigurationValue */ + usbCONFIGURATION_STRING,/* CiConfiguration */ + usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/ + 0x32, /* CMaxPower: 100mA */ + + /* Joystick Interface Descriptor Requirement */ + 0x09, /* bLength */ + 0x04, /* bDescriptorType */ + 0x00, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID code */ + 0x00, /* bInterfaceSubclass */ + 0x00, /* bInterfaceProtocol */ + usbINTERFACE_STRING,/* iInterface */ + + /* HID Descriptor */ + 0x09, /* bLength */ + 0x21, /* bDescriptor type: HID Descriptor Type */ + 0x00, 0x01, /* bcdHID */ + 0x00, /* bCountryCode */ + 0x01, /* bNumDescriptors */ + usbHID_REPORT_DESCRIPTOR, /* bDescriptorType */ + sizeof( pxReportDescriptor ), 0x00, /* wItemLength */ + + /* Endpoint 1 descriptor */ + 0x07, /* bLength */ + 0x05, /* bDescriptorType */ + 0x81, /* bEndpointAddress, Endpoint 01 - IN */ + 0x03, /* bmAttributes INT */ + 0x03, 0x00, /* wMaxPacketSize: 3 bytes (x, y, z) */ + 0x0A /* bInterval */ +}; + +/*-----------------------------------------------------------*/ + +/* File scope state variables. */ +static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0; +static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0; +static eDRIVER_STATE eDriverState = eNOTHING; + +/* Array in which the USB interrupt status is passed between the ISR and task. */ +static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ]; + +/* Structure used to control the characters being sent to the host. */ +static xTX_MESSAGE pxCharsForTx; + +/* Queue used to pass messages between the ISR and the task. */ +static xQueueHandle xUSBInterruptQueue; + +/* ISR entry has to be written in the asm file as we want a context switch +to occur from within the ISR. See the port documentation on the FreeRTOS.org +WEB site for more information. */ +extern void vUSBISREntry( void ); + +/*-----------------------------------------------------------*/ + +/* Macros to manipulate the control and status registers. These registers +cannot be accessed using a direct read modify write operation outside of the +ISR as some bits are left unchanged by writing with a 0, and some are left +unchanged by writing with a 1. */ + +#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) + +#define usbCSR_SET_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Set whichever bit we want set. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \ +} + +#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Clear whichever bit we want clear. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \ +} + +/*-----------------------------------------------------------*/ + +__arm void vUSB_ISR( void ) +{ +portBASE_TYPE xTaskWokenByPost = pdFALSE; +static volatile unsigned portLONG ulNextMessage = 0; +xISRStatus *pxMessage; +unsigned portLONG ulTemp, ulRxBytes; + + /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must* + be all 1's, as in 0x01, 0x03, 0x07, etc. */ + pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] ); + ulNextMessage++; + + /* Take a snapshot of the current USB state for processing at the task + level. */ + pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR; + pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + + /* Clear the interrupts from the ICR register. The bus end interrupt is + cleared separately as it does not appear in the mask register. */ + AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES; + + /* If there are bytes in the FIFO then we have to retrieve them here. + Ideally this would be done at the task level. However we need to clear the + RXSETUP interrupt before leaving the ISR, and this may cause the data in + the FIFO to be overwritten. Also the DIR bit has to be changed before the + RXSETUP bit is cleared (as per the SAM7 manual). */ + ulTemp = pxMessage->ulCSR0; + + /* Are there any bytes in the FIFO? */ + ulRxBytes = ulTemp >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + /* With this minimal implementation we are only interested in receiving + setup bytes on the control end point. */ + if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) ) + { + /* Take off 1 for a zero based index. */ + while( ulRxBytes > 0 ) + { + ulRxBytes--; + pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ]; + } + + /* The direction must be changed first. */ + usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + } + + /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA + registers to clear the interrupts in the CSR register. */ + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + + /* Also clear the interrupts in the CSR1 register. */ + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + + /* The message now contains the entire state and optional data from + the USB interrupt. This can now be posted on the Rx queue ready for + processing at the task level. */ + xTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, xTaskWokenByPost ); + + /* We may want to switch to the USB task, if this message has made + it the highest priority task that is ready to execute. */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + + /* Clear the AIC ready for the next interrupt. */ + AT91C_BASE_AIC->AIC_EOICR = 0; +} +/*-----------------------------------------------------------*/ + +void vUSBDemoTask( void *pvParameters ) +{ +xISRStatus *pxMessage; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Init USB device */ + portENTER_CRITICAL(); + vInitUSBInterface(); + portEXIT_CRITICAL(); + + /* Process interrupts as they arrive. The ISR takes a snapshot of the + interrupt status then posts the information on this queue for processing + at the task level. This simple demo implementation only processes + a few interrupt sources. */ + for( ;; ) + { + if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORT_DELAY ) ) + { + if( pxMessage->ulISR & AT91C_UDP_EPINT0 ) + { + /* Process end point 0 interrupt. */ + prvProcessEndPoint0Interrupt( pxMessage ); + } + + if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES ) + { + /* Process an end of bus reset interrupt. */ + prvResetEndPoints(); + } + } + else + { + /* The ISR did not post any data for us to process on the queue, so + just generate and send some sample data. */ + if( eDriverState == eREADY_TO_SEND ) + { + prvTransmitSampleValues(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvTransmitSampleValues( void ) +{ +unsigned portLONG ulStatus; +static portLONG lState = usbXUP; + +/* Variables to hold dummy x, y and z joystick axis data. */ +static signed portCHAR x = 0, y = 0, z = 0; + + /* Generate some sample data in the x and y axis - draw a square. */ + switch( lState ) + { + case usbXUP : x += usbDATA_INC; + if( x >= usbMAX_COORD ) + { + lState = usbYUP; + } + break; + + case usbXDOWN : x -= usbDATA_INC; + if( x <= -usbMAX_COORD ) + { + lState = usbYDOWN; + } + break; + + case usbYUP : y += usbDATA_INC; + if( y >= usbMAX_COORD ) + { + lState = usbXDOWN; + } + break; + + case usbYDOWN : y -= usbDATA_INC; + if( y <= -usbMAX_COORD ) + { + lState = usbXUP; + } + break; + } + + /* Just make the z axis go up and down. */ + z += usbDATA_INC; + + /* Can we place data in the fifo? */ + if( !( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & AT91C_UDP_TXPKTRDY ) ) + { + /* Write our sample data to the fifo. */ + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = x; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = y; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = z; + + /* Send the data. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +static void prvUSBTransmitNull( void ) +{ +unsigned portLONG ulStatus; + + /* Wait until the FIFO is free - even though we are not going to use it. + THERE IS NO TIMEOUT HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + portENTER_CRITICAL(); + { + /* Set the length of data to send to equal the index of the next byte + to send. This will prevent the ACK to this NULL packet causing any + further data transmissions. */ + pxCharsForTx.ulTotalDataLength = pxCharsForTx.ulNextCharIndex; + + /* Set the TXPKTRDY bit to cause a transmission with no data. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvSendStall( void ) +{ +unsigned portLONG ulStatus; + + portENTER_CRITICAL(); + { + /* Force a stall by simply setting the FORCESTALL bit in the CSR. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvResetEndPoints( void ) +{ +unsigned portLONG ulTemp; + + eDriverState = eJUST_RESET; + + /* Reset all the end points. */ + AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK; + AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00; + + /* Enable data to be sent and received. */ + AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN; + + /* Repair the configuration end point. */ + portENTER_CRITICAL(); + { + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT0 ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ) +{ + if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 ) + { + /* We only expect to receive zero length data here as ACK's. + Set the data pointer to the end of the current Tx packet to + ensure we don't send out any more data. */ + pxCharsForTx.ulNextCharIndex = pxCharsForTx.ulTotalDataLength; + } + + if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP ) + { + /* We received a TX complete interrupt. What we do depends on + what we sent to get this interrupt. */ + + if( eDriverState == eJUST_GOT_CONFIG ) + { + /* We sent an acknowledgement of a SET_CONFIG request. We + are now at the end of the enumeration. */ + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG; + + /* Read the end point for data transfer. */ + portENTER_CRITICAL(); + { + unsigned portLONG ulTemp; + + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT1 ); + } + portEXIT_CRITICAL(); + + eDriverState = eREADY_TO_SEND; + } + else if( eDriverState == eJUST_GOT_ADDRESS ) + { + /* We sent an acknowledgement of a SET_ADDRESS request. Move + to the addressed state. */ + if( ulReceivedAddress != ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; + } + else + { + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + } + + AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); + eDriverState = eNOTHING; + } + else + { + /* The TXCOMP was not for any special type of transmission. See + if there is any more data to send. */ + prvSendNextSegment(); + } + } + + if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP ) + { + xUSB_REQUEST xRequest; + unsigned portCHAR ucRequest; + unsigned portLONG ulRxBytes; + + /* A data packet is available. */ + ulRxBytes = pxMessage->ulCSR0 >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES ) + { + /* Create an xUSB_REQUEST variable from the raw bytes array. */ + + xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ]; + xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ]; + + /* NOT PORTABLE CODE! */ + xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ]; + xRequest.usValue <<= 8; + xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ]; + + xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ]; + xRequest.usIndex <<= 8; + xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ]; + + xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ]; + xRequest.usLength <<= 8; + xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ]; + + /* Manipulate the ucRequestType and the ucRequest parameters to + generate a zero based request selection. This is just done to + break up the requests into subsections for clarity. The + alternative would be to have more huge switch statement that would + be difficult to optimise. */ + ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 ); + ucRequest |= ( xRequest.ucReqType & 0x03 ); + + switch( ucRequest ) + { + case usbSTANDARD_DEVICE_REQUEST: + /* Standard Device request */ + prvHandleStandardDeviceRequest( &xRequest ); + break; + + case usbSTANDARD_INTERFACE_REQUEST: + /* Standard Interface request */ + prvHandleStandardInterfaceRequest( &xRequest ); + break; + + case usbSTANDARD_END_POINT_REQUEST: + /* Standard Endpoint request */ + prvHandleStandardEndPointRequest( &xRequest ); + break; + + case usbCLASS_INTERFACE_REQUEST: + /* Class Interface request */ + prvHandleClassInterfaceRequest( &xRequest ); + break; + + default: /* This is not something we want to respond to. */ + prvSendStall(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest ) +{ + /* The type is in the high byte. Return whatever has been requested. */ + switch( ( pxRequest->usValue & 0xff00 ) >> 8 ) + { + case usbDESCRIPTOR_TYPE_DEVICE: + prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_CONFIGURATION: + prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_STRING: + + /* The index to the string descriptor is the lower byte. */ + switch( pxRequest->usValue & 0xff ) + { + case usbLANGUAGE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE ); + break; + + case usbMANUFACTURER_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE ); + break; + + case usbPRODUCT_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE ); + break; + + case usbCONFIGURATION_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE ); + break; + + case usbINTERFACE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE ); + break; + + default: + /* Don't know what this string is. */ + prvSendStall(); + break; + } + + break; + + default: + /* We are not responding to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Just send two byte dummy status. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + /* Send device descriptor */ + prvGetStandardDeviceDescriptor( pxRequest ); + break; + + case usbGET_CONFIGURATION_REQUEST: + /* Send selected device configuration */ + prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE ); + break; + + case usbSET_FEATURE_REQUEST: + prvUSBTransmitNull(); + break; + + case usbSET_ADDRESS_REQUEST: + + /* Acknowledge the SET_ADDRESS, but (according to the manual) we + cannot actually move to the addressed state until we get a TXCOMP + interrupt from this NULL packet. Therefore we just remember the + address and set our state so we know we have received the address. */ + prvUSBTransmitNull(); + eDriverState = eJUST_GOT_ADDRESS; + ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue; + break; + + case usbSET_CONFIGURATION_REQUEST: + + /* Acknowledge the SET_CONFIGURATION, but (according to the manual) + we cannot actually move to the configured state until we get a + TXCOMP interrupt from this NULL packet. Therefore we just remember the + config and set our state so we know we have received the go ahead. */ + ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff ); + eDriverState = eJUST_GOT_CONFIG; + prvUSBTransmitNull(); + break; + + default: + + /* We don't answer to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + case usbSET_IDLE_REQUEST: + prvUSBTransmitNull(); + break; + + /* This minimal implementation ignores these. */ + case usbGET_REPORT_REQUEST: + case usbGET_IDLE_REQUEST: + case usbGET_PROTOCOL_REQUEST: + case usbSET_REPORT_REQUEST: + case usbSET_PROTOCOL_REQUEST: + default: + + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ) +{ + switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 ) + { + case usbHID_REPORT_DESCRIPTOR: + prvSendControlData( ( unsigned portCHAR * ) pxReportDescriptor, pxRequest->usLength, sizeof( pxReportDescriptor ), pdTRUE ); + break; + + default: + + /* Don't expect to send any others. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Send dummy 2 bytes. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + prvGetStandardInterfaceDescriptor( pxRequest ); + break; + + /* This minimal implementation does not respond to these. */ + case usbGET_INTERFACE_REQUEST: + case usbSET_FEATURE_REQUEST: + case usbSET_INTERFACE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + /* This minimal implementation does not expect to respond to these. */ + case usbGET_STATUS_REQUEST: + case usbCLEAR_FEATURE_REQUEST: + case usbSET_FEATURE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void vInitUSBInterface( void ) +{ +volatile unsigned portLONG ulTemp; + + /* Create the queue used to communicate between the USB ISR and task. */ + xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) ); + + /* Initialise a few state variables. */ + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + ucUSBConfig = ( unsigned portCHAR ) 0; + eDriverState = eNOTHING; + + /* HARDWARE SETUP */ + + /* Set the PLL USB Divider */ + AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1; + + /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */ + AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP; + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP); + + /* Setup the PIO for the USB pull up resistor. */ + AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16); + + /* Start without the pullup - this will get set at the end of this + function. */ + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, AT91C_PIO_PA16 ); + + /* When using the USB debugger the peripheral registers do not always get + set to the correct default values. To make sure set the relevant registers + manually here. */ + AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + AT91C_BASE_UDP->UDP_FADDR = 0; + + /* Enable the transceiver. */ + AT91C_UDP_TRANSCEIVER_ENABLE = 0; + + /* Enable the USB interrupts - other interrupts get enabled as the + enumeration process progresses. */ + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vUSBISREntry ); + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_UDP ); + + /* Wait a short while before making our presence known. */ + vTaskDelay( usbINIT_DELAY ); + AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA16 ); +} +/*-----------------------------------------------------------*/ + +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor ) +{ + if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) ) + { + /* Cap the data length to that requested. */ + ulLengthToSend = ( unsigned portSHORT ) usRequestedLength; + } + else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor ) + { + /* We are sending a descriptor. If the descriptor is an exact + multiple of the FIFO length then it will have to be terminated + with a NULL packet. Set the state to indicate this if + necessary. */ + if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 ) + { + eDriverState = eSENDING_EVEN_DESCRIPTOR; + } + } + + /* Here we assume that the previous message has been sent. THERE IS NO + BUFFER OVERFLOW PROTECTION HERE. + + Copy the data to send into the buffer as we cannot send it all at once + (if it is greater than 8 bytes in length). */ + memcpy( pxCharsForTx.ucTxBuffer, pucData, ulLengthToSend ); + + /* Reinitialise the buffer index so we start sending from the start of + the data. */ + pxCharsForTx.ulTotalDataLength = ulLengthToSend; + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + + /* Send the first 8 bytes now. The rest will get sent in response to + TXCOMP interrupts. */ + prvSendNextSegment(); +} +/*-----------------------------------------------------------*/ + +static void prvSendNextSegment( void ) +{ +volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend; + + /* Is there any data to send? */ + if( pxCharsForTx.ulTotalDataLength > pxCharsForTx.ulNextCharIndex ) + { + ulLengthLeftToSend = pxCharsForTx.ulTotalDataLength - pxCharsForTx.ulNextCharIndex; + + /* We can only send 8 bytes to the fifo at a time. */ + if( ulLengthLeftToSend > usbFIFO_LENGTH ) + { + ulNextLength = usbFIFO_LENGTH; + } + else + { + ulNextLength = ulLengthLeftToSend; + } + + /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT + HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + /* Write the data to the FIFO. */ + while( ulNextLength > ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxCharsForTx.ucTxBuffer[ pxCharsForTx.ulNextCharIndex ]; + + ulNextLength--; + pxCharsForTx.ulNextCharIndex++; + } + + /* Start the transmission. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); + } + else + { + /* There is no data to send. If we were sending a descriptor and the + descriptor was an exact multiple of the max packet size then we need + to send a null to terminate the transmission. */ + if( eDriverState == eSENDING_EVEN_DESCRIPTOR ) + { + prvUSBTransmitNull(); + eDriverState = eNOTHING; + } + } +} + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h new file mode 100644 index 000000000..add756985 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h @@ -0,0 +1,8 @@ +#ifndef USB_DEMO_H +#define USB_DEMO_H + +void vUSBDemoTask( void *pvParameters ); + + +#endif + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 b/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 new file mode 100644 index 000000000..8263f71ff --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vUSB_ISR + PUBLIC vUSBISREntry + +; Wrapper for the USB interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vUSBISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vUSB_ISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/main.c b/Demo/ARM7_AT91SAM7S64_IAR/main.c new file mode 100644 index 000000000..7b7ebb0b0 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/main.c @@ -0,0 +1,252 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. The SAM7 + * includes a sample USB that emulates a Joystick input to a USB host. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" +#include "USB/USBSample.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 3 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) /* Off the board. */ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the Atmel demo board. Setup is minimal + * as the low level init function (called from the startup asm file) takes care + * of most things. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Also start the USB demo which is just for the SAM7. */ + xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* When using the JTAG debugger the hardware is not always initialised to + the correct default state. This line just ensures that this does not + cause all interrupts to be masked at the start. */ + AT91C_BASE_AIC->AIC_EOICR = 0; + + /* Most setup is performed by the low level init function called from the + startup asm file. */ + + /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as + well as the UART Tx line. */ + AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ); + + /* Enable the peripheral clock. */ + AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac new file mode 100644 index 000000000..b1c753dc3 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac @@ -0,0 +1,180 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7.mac +// +// User setup file for CSPY debugger to simulate interrupt +// driven Fibonacchi data input. +// 1.1 16/Jun/04 JPP : Creation +// +// $Revision: 1.3 $ +// +// --------------------------------------------------------- + +__var i; +__var pt; + +execUserPreload() +{ +//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area + CheckRemap(); +//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + i=__readMemory32(0xFFFFF240,"Memory"); + __message " ---------------------------------------- Chip ID 0x",i:%X; + i=__readMemory32(0xFFFFF244,"Memory"); + __message " ---------------------------------------- Extention 0x",i:%X; +//* Get the chip status + +//* Init AIC + AIC(); +//* Watchdog Disable + Watchdog(); + +} + + +//----------------------------------------------------------------------------- +// Watchdog +//------------------------------- +// Normally, the Watchdog is enable at the reset for load it's preferable to +// Disable. +//----------------------------------------------------------------------------- +Watchdog() +{ +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); + __message "------------------------------- Watchdog Disable ----------------------------------------"; +} + + +//----------------------------------------------------------------------------- +// Check Remap +//------------- +//----------------------------------------------------------------------------- +CheckRemap() +{ +//* Read the value at 0x0 + i=__readMemory32(0x00000000,"Memory"); + i=i+1; + __writeMemory32(i,0x00,"Memory"); + pt=__readMemory32(0x00000000,"Memory"); + + if (i == pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; + } + +} + + +execUserSetup() +{ + ini(); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + + + +//----------------------------------------------------------------------------- +// Reset the Interrupt Controller +//------------------------------- +// Normally, the code is executed only if a reset has been actually performed. +// So, the AIC initialization resumes at setting up the default vectors. +//----------------------------------------------------------------------------- +AIC() +{ +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); + + for (i=0;i < 8; i++) + { + // AT91C_BASE_AIC->AIC_EOICR + pt = __readMemory32(0xFFFFF130,"Memory"); + + } + __message "------------------------------- AIC INIT ---------------------------------------------"; +} + +ini() +{ +__writeMemory32(0x0,0x00,"Register"); +__writeMemory32(0x0,0x04,"Register"); +__writeMemory32(0x0,0x08,"Register"); +__writeMemory32(0x0,0x0C,"Register"); +__writeMemory32(0x0,0x10,"Register"); +__writeMemory32(0x0,0x14,"Register"); +__writeMemory32(0x0,0x18,"Register"); +__writeMemory32(0x0,0x1C,"Register"); +__writeMemory32(0x0,0x20,"Register"); +__writeMemory32(0x0,0x24,"Register"); +__writeMemory32(0x0,0x28,"Register"); +__writeMemory32(0x0,0x2C,"Register"); +__writeMemory32(0x0,0x30,"Register"); +__writeMemory32(0x0,0x34,"Register"); +__writeMemory32(0x0,0x38,"Register"); + +// Set CPSR +__writeMemory32(0x0D3,0x98,"Register"); + + +} + +RG() +{ + +i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; +i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; +i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; +i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; +i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; +i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; +i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; +i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; +i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; +i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; +i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; +i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; +i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; +i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; +i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; +i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; +i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; +i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; +i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; +i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; +i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; +i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; +i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; +i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; +i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; +i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; +i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; +i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; +i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; +i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; +i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; +i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; +i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; +i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; +i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; + +i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; + +} + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac new file mode 100644 index 000000000..7471d73b7 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac @@ -0,0 +1,211 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7_RAM.mac +// +// User setup file for CSPY debugger to simulate interrupt +// driven Fibonacchi data input. +// 1.1 16/Jun/04 JPP : Creation +// 1.2 27/Aug/04 JPP : PLL setting +// +// $Revision: 1.3 $ +// +// --------------------------------------------------------- + +__var i; +__var pt; + +execUserPreload() +{ +//* + PllSetting(); +//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area + CheckNoRemap(); +//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + i=__readMemory32(0xFFFFF240,"Memory"); + __message " ---------------------------------------- Chip ID 0x",i:%X; + i=__readMemory32(0xFFFFF244,"Memory"); + __message " ---------------------------------------- Extention 0x",i:%X; + i=__readMemory32(0xFFFFFF6C,"Memory"); + __message " ---------------------------------------- Flash Version 0x",i:%X; +//* Get the chip status + +//* Init AIC + AIC(); +//* Watchdog Disable + Watchdog(); +} +//----------------------------------------------------------------------------- +// PllSetting +//------------------------------- +// Set PLL +//----------------------------------------------------------------------------- +PllSetting() +{ +// -1- Enabling the Main Oscillator: +//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + +//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 +// AT91C_CKGR_MOSCEN )); //0x0000 0001 +__writeMemory32(0x00000601,0xFFFFFC20,"Memory"); + +// -2- Wait +// -3- Setting PLL and divider: +// - div by 5 Fin = 3,6864 =(18,432 / 5) +// - Mul 25+1: Fout = 95,8464 =(3,6864 *26) +// for 96 MHz the erroe is 0.16% +// Field out NOT USED = 0 +// PLLCOUNT pll startup time esrtimate at : 0.844 ms +// PLLCOUNT 28 = 0.000844 /(1/32768) +// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 +// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 +// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 +__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); +// -2- Wait +// -5- Selection of Master Clock and Processor Clock +// select the PLL clock divided by 2 +// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 +// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 +__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); + + __message "------------------------------- PLL Enable ----------------------------------------"; +} + +//----------------------------------------------------------------------------- +// Watchdog +//------------------------------- +// Normally, the Watchdog is enable at the reset for load it's preferable to +// Disable. +//----------------------------------------------------------------------------- +Watchdog() +{ +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); + __message "------------------------------- Watchdog Disable ----------------------------------------"; +} + +CheckNoRemap() +{ +//* Read the value at 0x0 + i=__readMemory32(0x00000000,"Memory"); + i=i+1; + __writeMemory32(i,0x00,"Memory"); + pt=__readMemory32(0x00000000,"Memory"); + + if (i == pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + } + +} + +execUserSetup() +{ + ini(); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + +//----------------------------------------------------------------------------- +// Reset the Interrupt Controller +//------------------------------- +// Normally, the code is executed only if a reset has been actually performed. +// So, the AIC initialization resumes at setting up the default vectors. +//----------------------------------------------------------------------------- +AIC() +{ +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); + + for (i=0;i < 8; i++) + { + // AT91C_BASE_AIC->AIC_EOICR + pt = __readMemory32(0xFFFFF130,"Memory"); + + } + __message "------------------------------- AIC INIT ---------------------------------------------"; +} + +ini() +{ +__writeMemory32(0x0,0x00,"Register"); +__writeMemory32(0x0,0x04,"Register"); +__writeMemory32(0x0,0x08,"Register"); +__writeMemory32(0x0,0x0C,"Register"); +__writeMemory32(0x0,0x10,"Register"); +__writeMemory32(0x0,0x14,"Register"); +__writeMemory32(0x0,0x18,"Register"); +__writeMemory32(0x0,0x1C,"Register"); +__writeMemory32(0x0,0x20,"Register"); +__writeMemory32(0x0,0x24,"Register"); +__writeMemory32(0x0,0x28,"Register"); +__writeMemory32(0x0,0x2C,"Register"); +__writeMemory32(0x0,0x30,"Register"); +__writeMemory32(0x0,0x34,"Register"); +__writeMemory32(0x0,0x38,"Register"); + +// Set CPSR +__writeMemory32(0x0D3,0x98,"Register"); + +} + +RG() +{ + +i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; +i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; +i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; +i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; +i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; +i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; +i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; +i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; +i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; +i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; +i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; +i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; +i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; +i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; +i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; +i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; +i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; +i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; +i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; +i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; +i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; +i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; +i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; +i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; +i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; +i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; +i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; +i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; +i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; +i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; +i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; +i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; +i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; +i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; +i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; + +i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; + +} + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl new file mode 100644 index 000000000..6f304e4f0 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl @@ -0,0 +1,135 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: at91SAM7S64_16KRAM.xlc +// +// 1.1 16/Jun/04 JPP : Creation for 4.11A +// +// $Revision: 1.1.1.1 $ +// +// --------------------------------------------------------- + +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1.1.1 $ +//************************************************************************* + +//************************************************ +// Inform the linker about the CPU family used. +// AT91SAM7S64 Memory mapping +// No remap +// ROMSTART +// Start address 0x0000 0000 +// Size 64 Kbo 0x0001 0000 +// RAMSTART +// Start address 0x0020 0000 +// Size 16 Kbo 0x0000 4000 +// Remap done +// RAMSTART +// Start address 0x0000 0000 +// Size 16 Kbo 0x0000 4000 +// ROMSTART +// Start address 0x0010 0000 +// Size 64 Kbo 0x0001 0000 + +//************************************************ +-carm + +//************************************************************************* +// Internal Ram segments mapped AFTER REMAP 16 K. +//************************************************************************* +// Use these addresses for the . +-Z(CONST)INTRAMSTART_REMAP=00000000 +-Z(CONST)INTRAMEND_REMAP=00003FFF + +//************************************************************************* +// Read-only segments mapped to Flash 64 K. +//************************************************************************* +-DROMSTART=00000000 +-DROMEND=0000FFFF +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* +-DRAMSTART=00000000 +-DRAMEND=00003FFF + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ +-Z(CODE)INTVEC=00-3F + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + +//************************************************ +// Data segments. +//************************************************ +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ +-Z(DATA)CODE_I=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* +-D_CSTACK_SIZE=(100*4) +-D_IRQ_STACK_SIZE=(2*8*4) + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl new file mode 100644 index 000000000..4fa63442a --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl @@ -0,0 +1,136 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: at91SAM7S64_NoRemap.xlc +// +// 1.1 16/Jun/04 JPP : Creation for 4.11A +// +// $Revision: 1.1.1.1 $ +// +// --------------------------------------------------------- + +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1.1.1 $ +//************************************************************************* + +//************************************************ +// Inform the linker about the CPU family used. +// AT91SAM7S64 Memory mapping +// No remap +// ROMSTART +// Start address 0x0000 0000 +// Size 64 Kbo 0x0001 0000 +// RAMSTART +// Start address 0x0020 0000 +// Size 16 Kbo 0x0000 4000 +// Remap done +// RAMSTART +// Start address 0x0000 0000 +// Size 16 Kbo 0x0000 4000 +// ROMSTART +// Start address 0x0010 0000 +// Size 64 Kbo 0x0001 0000 + +//************************************************ +-carm + +//************************************************************************* +// Internal Ram segments mapped AFTER REMAP 16 K. +//************************************************************************* +// Use these addresses for the . +-Z(CONST)INTRAMSTART_REMAP=00200000 +-Z(CONST)INTRAMEND_REMAP=00203FFF + +//************************************************************************* +// Read-only segments mapped to Flash 64 K. +//************************************************************************* +-DROMSTART=00000000 +-DROMEND=0000FFFF +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* +-DRAMSTART=00200000 +-DRAMEND=002003FFF + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ +-Z(CODE)INTVEC=00-3F + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + + +//************************************************ +// Data segments. +//************************************************ +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ +-Z(DATA)CODE_I=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* +//-D_CSTACK_SIZE=(100*4) +//-D_IRQ_STACK_SIZE=(2*8*4) + +//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd new file mode 100644 index 000000000..44815edc8 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd @@ -0,0 +1,905 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + + + Flash Bin + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp new file mode 100644 index 000000000..63e626910 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp @@ -0,0 +1,1738 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + General + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + 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$PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\serial\serialISR.s79 + + + $PROJ_DIR$\USB\USB_ISR.s79 + + + $PROJ_DIR$\USB\USBSample.c + + + + Scheduler Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\SrcIAR\Cstartup.s79 + + + $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c + + + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c b/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c new file mode 100644 index 000000000..b846fa7cb --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c @@ -0,0 +1,246 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Location of the COM0 registers. */ +#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 ) + +/* Interrupt control macros. */ +#define serINTERRUPT_LEVEL ( 5 ) +#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY ) +#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY ) + +/* Misc constants. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) +#define serNO_TIMEGUARD ( ( unsigned portLONG ) 0 ) +#define serNO_PERIPHERAL_B_SETUP ( ( unsigned portLONG ) 0 ) + + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Interrupt entry point written in the assembler file serialISR.s79. */ +extern void vSerialISREntry( void ); + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR )( void ); + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + portENTER_CRITICAL(); + { + /* Enable the USART clock. */ + AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 ); + + AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP ); + + /* Set the required protocol. */ + AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD ); + + /* Enable Rx and Tx. */ + serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; + + /* Enable the Rx interrupts. The Tx interrupts are not enabled + until there are characters to be transmitted. */ + AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY ); + + /* Enable the interrupts in the AIC. */ + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry ); + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +/* Serial port ISR. This can cause a context switch so is not defined as a +standard ISR using the __irq keyword. Instead a wrapper function is defined +within serialISR.s79 which in turn calls this function. See the port +documentation on the FreeRTOS.org website for more information. */ +__arm void vSerialISR( void ) +{ +unsigned portLONG ulStatus; +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt? */ + ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR; + + if( ulStatus & AT91C_US_TXRDY ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + serCOM0->US_THR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + vInterruptOff(); + } + } + + if( ulStatus & AT91C_US_RXRDY ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue or received + characters. */ + cChar = serCOM0->US_RHR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = 0; +} + + + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 b/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt new file mode 100644 index 000000000..5085f2cdb --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt @@ -0,0 +1,71 @@ + + + + + + + + + + + 1892727 + + + + + + 200100 + + + 200188171100100010 + + + + + TabID-23416-30482 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + + + TabID-12145-30489 + Debug Log + Debug-Log + + + + TabID-22894-30492 + Build + Build + + + + + 1 + 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IarIdePM1DebuggerGui1-2-21072265-2-20000166875959785 + + + + diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..fc509a42a --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni @@ -0,0 +1,22 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Low Level] +Pipeline mode=1 +Initialized=0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..2910d9720 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,76 @@ + + + + + + rtosdemo/Flash Debug + + + + + + + + 221272727 + + 18115530877 + + + + + + + + + + + 100010 + + + + + + + TabID-17425-14382 + Workspace + Workspace + + + rtosdemortosdemo/Demo Sourcertosdemo/Scheduler Sourcertosdemo/System Files + + + + 0 + + + TabID-4084-16269 + Build + Build + + + + TabID-25581-16276 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h01800TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Board.h00952969TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7901426503651720100000010000001 + + + + + + + iaridepm1-2-2659295-2-230301875026809185625590705-2-24131602-2-2160441510025003708661875026809 + + + + diff --git a/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h b/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..217d1a412 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2106_GCC/Makefile b/Demo/ARM7_LPC2106_GCC/Makefile new file mode 100644 index 000000000..a51a0c4f3 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/Makefile @@ -0,0 +1,118 @@ +# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + +# Changes from V2.4.2 +# +# + Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c. + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s +WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ + -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + $(OPTIM) + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +main.c \ +serial/serial.c \ +ParTest/ParTest.c \ +$(DEMO_SOURCE_DIR)/integer.c \ +$(DEMO_SOURCE_DIR)/flash.c \ +$(DEMO_SOURCE_DIR)/PollQ.c \ +$(DEMO_SOURCE_DIR)/comtest.c \ +$(DEMO_SOURCE_DIR)/flop.c \ +$(DEMO_SOURCE_DIR)/semtest.c \ +$(DEMO_SOURCE_DIR)/dynamic.c \ +$(DEMO_SOURCE_DIR)/BlockQ.c \ +$(RTOS_SOURCE_DIR)/tasks.c \ +$(RTOS_SOURCE_DIR)/queue.c \ +$(RTOS_SOURCE_DIR)/list.c \ +$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \ +serial/serialISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +rtosdemo.hex : rtosdemo.elf + $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex + +rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch Makefile + + + + + + + + + + + + diff --git a/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c b/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..4a0486d75 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c @@ -0,0 +1,106 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V2.5.2 + + + All LED's are turned off to start. +*/ + + +#include "FreeRTOS.h" +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x400 ) +#define partstNUM_LEDS ( 4 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xffffffff ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. */ + + /* Turn all outputs off. */ + GPIO_IOSET = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set of clear the output. */ + if( xValue ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = GPIO0_IOPIN; + if( ulCurrentState & ulLED ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} + diff --git a/Demo/ARM7_LPC2106_GCC/boot.s b/Demo/ARM7_LPC2106_GCC/boot.s new file mode 100644 index 000000000..33e5226eb --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld b/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld new file mode 100644 index 000000000..c54802c2f --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >ram + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >ram + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld b/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld new file mode 100644 index 000000000..e7cf25a22 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/Demo/ARM7_LPC2106_GCC/lpc210x.h b/Demo/ARM7_LPC2106_GCC/lpc210x.h new file mode 100644 index 000000000..3f1e3042d --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/lpc210x.h @@ -0,0 +1,321 @@ +#ifndef lpc210x_h +#define lpc210x_h +/******************************************************************************* +lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 + + +THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, +EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY +WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY +PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS +OF OTHERS. + +This file may be freely used for commercial and non-commercial applications, +including being redistributed with any tools. + +If you find a problem with the file, please report it so that it can be fixed. + +Created by Sten Larsson (sten_larsson at yahoo com) + +Edited by Richard Barry. +*******************************************************************************/ + +#define REG8 (volatile unsigned char*) +#define REG16 (volatile unsigned short*) +#define REG32 (volatile unsigned int*) + + +/*############################################################################## +## MISC +##############################################################################*/ + + /* Constants for data to put in IRQ/FIQ Exception Vectors */ +#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ +#define VECTDATA_FIQ /* __TODO */ + + +/*############################################################################## +## VECTORED INTERRUPT CONTROLLER +##############################################################################*/ + +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) + +#define VICVectAddr0 (*(REG32 (0xFFFFF100))) +#define VICVectAddr1 (*(REG32 (0xFFFFF104))) +#define VICVectAddr2 (*(REG32 (0xFFFFF108))) +#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF110))) +#define VICVectAddr5 (*(REG32 (0xFFFFF114))) +#define VICVectAddr6 (*(REG32 (0xFFFFF118))) +#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF120))) +#define VICVectAddr9 (*(REG32 (0xFFFFF124))) +#define VICVectAddr10 (*(REG32 (0xFFFFF128))) +#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF130))) +#define VICVectAddr13 (*(REG32 (0xFFFFF134))) +#define VICVectAddr14 (*(REG32 (0xFFFFF138))) +#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) + +#define VICVectCntl0 (*(REG32 (0xFFFFF200))) +#define VICVectCntl1 (*(REG32 (0xFFFFF204))) +#define VICVectCntl2 (*(REG32 (0xFFFFF208))) +#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF210))) +#define VICVectCntl5 (*(REG32 (0xFFFFF214))) +#define VICVectCntl6 (*(REG32 (0xFFFFF218))) +#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF220))) +#define VICVectCntl9 (*(REG32 (0xFFFFF224))) +#define VICVectCntl10 (*(REG32 (0xFFFFF228))) +#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) +#define VICVectCntl12 (*(REG32 (0xFFFFF230))) +#define VICVectCntl13 (*(REG32 (0xFFFFF234))) +#define VICVectCntl14 (*(REG32 (0xFFFFF238))) +#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) + +#define VICITCR (*(REG32 (0xFFFFF300))) +#define VICITIP1 (*(REG32 (0xFFFFF304))) +#define VICITIP2 (*(REG32 (0xFFFFF308))) +#define VICITOP1 (*(REG32 (0xFFFFF30C))) +#define VICITOP2 (*(REG32 (0xFFFFF310))) +#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) +#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) +#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) +#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) + +#define VICIntEnClr VICIntEnClear +#define VICSoftIntClr VICSoftIntClear + + +/*############################################################################## +## PCB - Pin Connect Block +##############################################################################*/ + +#define PCB_PINSEL0 (*(REG32 (0xE002C000))) +#define PCB_PINSEL1 (*(REG32 (0xE002C004))) + + +/*############################################################################## +## GPIO - General Purpose I/O +##############################################################################*/ + +#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO_IOSET (*(REG32 (0xE0028004))) +#define GPIO_IODIR (*(REG32 (0xE0028008))) +#define GPIO_IOCLR (*(REG32 (0xE002800C))) + +#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO0_IOSET (*(REG32 (0xE0028004))) +#define GPIO0_IODIR (*(REG32 (0xE0028008))) +#define GPIO0_IOCLR (*(REG32 (0xE002800C))) + + +/*############################################################################## +## UART0 / UART1 +##############################################################################*/ + +/* ---- UART 0 --------------------------------------------- */ +#define UART0_RBR (*(REG32 (0xE000C000))) +#define UART0_THR (*(REG32 (0xE000C000))) +#define UART0_IER (*(REG32 (0xE000C004))) +#define UART0_IIR (*(REG32 (0xE000C008))) +#define UART0_FCR (*(REG32 (0xE000C008))) +#define UART0_LCR (*(REG32 (0xE000C00C))) +#define UART0_LSR (*(REG32 (0xE000C014))) +#define UART0_SCR (*(REG32 (0xE000C01C))) +#define UART0_DLL (*(REG32 (0xE000C000))) +#define UART0_DLM (*(REG32 (0xE000C004))) + +/* ---- UART 1 --------------------------------------------- */ +#define UART1_RBR (*(REG32 (0xE0010000))) +#define UART1_THR (*(REG32 (0xE0010000))) +#define UART1_IER (*(REG32 (0xE0010004))) +#define UART1_IIR (*(REG32 (0xE0010008))) +#define UART1_FCR (*(REG32 (0xE0010008))) +#define UART1_LCR (*(REG32 (0xE001000C))) +#define UART1_LSR (*(REG32 (0xE0010014))) +#define UART1_SCR (*(REG32 (0xE001001C))) +#define UART1_DLL (*(REG32 (0xE0010000))) +#define UART1_DLM (*(REG32 (0xE0010004))) +#define UART1_MCR (*(REG32 (0xE0010010))) +#define UART1_MSR (*(REG32 (0xE0010018))) + + +/*############################################################################## +## I2C +##############################################################################*/ + +#define I2C_I2CONSET (*(REG32 (0xE001C000))) +#define I2C_I2STAT (*(REG32 (0xE001C004))) +#define I2C_I2DAT (*(REG32 (0xE001C008))) +#define I2C_I2ADR (*(REG32 (0xE001C00C))) +#define I2C_I2SCLH (*(REG32 (0xE001C010))) +#define I2C_I2SCLL (*(REG32 (0xE001C014))) +#define I2C_I2CONCLR (*(REG32 (0xE001C018))) + + +/*############################################################################## +## SPI - Serial Peripheral Interface +##############################################################################*/ + +#define SPI_SPCR (*(REG32 (0xE0020000))) +#define SPI_SPSR (*(REG32 (0xE0020004))) +#define SPI_SPDR (*(REG32 (0xE0020008))) +#define SPI_SPCCR (*(REG32 (0xE002000C))) +#define SPI_SPTCR (*(REG32 (0xE0020010))) +#define SPI_SPTSR (*(REG32 (0xE0020014))) +#define SPI_SPTOR (*(REG32 (0xE0020018))) +#define SPI_SPINT (*(REG32 (0xE002001C))) + + +/*############################################################################## +## Timer 0 and Timer 1 +##############################################################################*/ + +/* ---- Timer 0 -------------------------------------------- */ +#define T0_IR (*(REG32 (0xE0004000))) +#define T0_TCR (*(REG32 (0xE0004004))) +#define T0_TC (*(REG32 (0xE0004008))) +#define T0_PR (*(REG32 (0xE000400C))) +#define T0_PC (*(REG32 (0xE0004010))) +#define T0_MCR (*(REG32 (0xE0004014))) +#define T0_MR0 (*(REG32 (0xE0004018))) +#define T0_MR1 (*(REG32 (0xE000401C))) +#define T0_MR2 (*(REG32 (0xE0004020))) +#define T0_MR3 (*(REG32 (0xE0004024))) +#define T0_CCR (*(REG32 (0xE0004028))) +#define T0_CR0 (*(REG32 (0xE000402C))) +#define T0_CR1 (*(REG32 (0xE0004030))) +#define T0_CR2 (*(REG32 (0xE0004034))) +#define T0_CR3 (*(REG32 (0xE0004038))) +#define T0_EMR (*(REG32 (0xE000403C))) + +/* ---- Timer 1 -------------------------------------------- */ +#define T1_IR (*(REG32 (0xE0008000))) +#define T1_TCR (*(REG32 (0xE0008004))) +#define T1_TC (*(REG32 (0xE0008008))) +#define T1_PR (*(REG32 (0xE000800C))) +#define T1_PC (*(REG32 (0xE0008010))) +#define T1_MCR (*(REG32 (0xE0008014))) +#define T1_MR0 (*(REG32 (0xE0008018))) +#define T1_MR1 (*(REG32 (0xE000801C))) +#define T1_MR2 (*(REG32 (0xE0008020))) +#define T1_MR3 (*(REG32 (0xE0008024))) +#define T1_CCR (*(REG32 (0xE0008028))) +#define T1_CR0 (*(REG32 (0xE000802C))) +#define T1_CR1 (*(REG32 (0xE0008030))) +#define T1_CR2 (*(REG32 (0xE0008034))) +#define T1_CR3 (*(REG32 (0xE0008038))) +#define T1_EMR (*(REG32 (0xE000803C))) + + +/*############################################################################## +## PWM +##############################################################################*/ + +#define PWM_IR (*(REG32 (0xE0014000))) +#define PWM_TCR (*(REG32 (0xE0014004))) +#define PWM_TC (*(REG32 (0xE0014008))) +#define PWM_PR (*(REG32 (0xE001400C))) +#define PWM_PC (*(REG32 (0xE0014010))) +#define PWM_MCR (*(REG32 (0xE0014014))) +#define PWM_MR0 (*(REG32 (0xE0014018))) +#define PWM_MR1 (*(REG32 (0xE001401C))) +#define PWM_MR2 (*(REG32 (0xE0014020))) +#define PWM_MR3 (*(REG32 (0xE0014024))) +#define PWM_MR4 (*(REG32 (0xE0014040))) +#define PWM_MR5 (*(REG32 (0xE0014044))) +#define PWM_MR6 (*(REG32 (0xE0014048))) +#define PWM_EMR (*(REG32 (0xE001403C))) +#define PWM_PCR (*(REG32 (0xE001404C))) +#define PWM_LER (*(REG32 (0xE0014050))) +#define PWM_CCR (*(REG32 (0xE0014028))) +#define PWM_CR0 (*(REG32 (0xE001402C))) +#define PWM_CR1 (*(REG32 (0xE0014030))) +#define PWM_CR2 (*(REG32 (0xE0014034))) +#define PWM_CR3 (*(REG32 (0xE0014038))) + +/*############################################################################## +## RTC +##############################################################################*/ + +/* ---- RTC: Miscellaneous Register Group ------------------ */ +#define RTC_ILR (*(REG32 (0xE0024000))) +#define RTC_CTC (*(REG32 (0xE0024004))) +#define RTC_CCR (*(REG32 (0xE0024008))) +#define RTC_CIIR (*(REG32 (0xE002400C))) +#define RTC_AMR (*(REG32 (0xE0024010))) +#define RTC_CTIME0 (*(REG32 (0xE0024014))) +#define RTC_CTIME1 (*(REG32 (0xE0024018))) +#define RTC_CTIME2 (*(REG32 (0xE002401C))) + +/* ---- RTC: Timer Control Group --------------------------- */ +#define RTC_SEC (*(REG32 (0xE0024020))) +#define RTC_MIN (*(REG32 (0xE0024024))) +#define RTC_HOUR (*(REG32 (0xE0024028))) +#define RTC_DOM (*(REG32 (0xE002402C))) +#define RTC_DOW (*(REG32 (0xE0024030))) +#define RTC_DOY (*(REG32 (0xE0024034))) +#define RTC_MONTH (*(REG32 (0xE0024038))) +#define RTC_YEAR (*(REG32 (0xE002403C))) + +/* ---- RTC: Alarm Control Group --------------------------- */ +#define RTC_ALSEC (*(REG32 (0xE0024060))) +#define RTC_ALMIN (*(REG32 (0xE0024064))) +#define RTC_ALHOUR (*(REG32 (0xE0024068))) +#define RTC_ALDOM (*(REG32 (0xE002406C))) +#define RTC_ALDOW (*(REG32 (0xE0024070))) +#define RTC_ALDOY (*(REG32 (0xE0024074))) +#define RTC_ALMON (*(REG32 (0xE0024078))) +#define RTC_ALYEAR (*(REG32 (0xE002407C))) + +/* ---- RTC: Reference Clock Divider Group ----------------- */ +#define RTC_PREINT (*(REG32 (0xE0024080))) +#define RTC_PREFRAC (*(REG32 (0xE0024084))) + + +/*############################################################################## +## WD - Watchdog +##############################################################################*/ + +#define WD_WDMOD (*(REG32 (0xE0000000))) +#define WD_WDTC (*(REG32 (0xE0000004))) +#define WD_WDFEED (*(REG32 (0xE0000008))) +#define WD_WDTV (*(REG32 (0xE000000C))) + + +/*############################################################################## +## System Control Block +##############################################################################*/ + +#define SCB_EXTINT (*(REG32 (0xE01FC140))) +#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) +#define SCB_MEMMAP (*(REG32 (0xE01FC040))) +#define SCB_PLLCON (*(REG32 (0xE01FC080))) +#define SCB_PLLCFG (*(REG32 (0xE01FC084))) +#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) +#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) +#define SCB_PCON (*(REG32 (0xE01FC0C0))) +#define SCB_PCONP (*(REG32 (0xE01FC0C4))) +#define SCB_VPBDIV (*(REG32 (0xE01FC100))) + +/*############################################################################## +## Memory Accelerator Module (MAM) +##############################################################################*/ + +#define MAM_TIM (*(REG32 (0xE01FC004))) +#define MAM_CR (*(REG32 (0xE01FC000))) + +#endif /* lpc210x_h */ + diff --git a/Demo/ARM7_LPC2106_GCC/lpc221x.h b/Demo/ARM7_LPC2106_GCC/lpc221x.h new file mode 100644 index 000000000..170bb435f --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/lpc221x.h @@ -0,0 +1 @@ +#include "lpc2114.h" \ No newline at end of file diff --git a/Demo/ARM7_LPC2106_GCC/main.c b/Demo/ARM7_LPC2106_GCC/main.c new file mode 100644 index 000000000..01bfc0d55 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/main.c @@ -0,0 +1,474 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * To check the operation of the memory allocator the check task also + * dynamically creates a task before delaying, and deletes it again when it + * wakes. If memory cannot be allocated for the new task the call to xTaskCreate + * will fail and an error is signalled. The dynamically created task itself + * allocates and frees memory just to give the allocator a bit more exercise. + * + */ + +/* + Changes from V2.4.2 + + + The vErrorChecks() task now dynamically creates then deletes a task each + cycle. This tests the operation of the memory allocator. + + Changes from V2.5.2 + + + vParTestInitialise() is called during initialisation to ensure all the + LED's start off. +*/ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup I/O. */ +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) +#define mainP0_14 ( ( unsigned portLONG ) 0x4000 ) +#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/*-----------------------------------------------------------*/ + +/* + * The Olimex demo board has a single built in LED. This function simply + * toggles its state. + */ +void prvToggleOnBoardLED( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; + + /* The parameters are not used in this function. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + xCreatedTask = mainNO_TASK; + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PCB_PINSEL0 |= mainTX_ENABLE; + PCB_PINSEL0 |= mainRX_ENABLE; + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + The JTAG pins are left as input as I'm not sure what will happen if the + Wiggler is connected after powerup - not that it would be a good idea to + do that anyway. */ + GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned portLONG ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + have failed. */ + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} + + + diff --git a/Demo/ARM7_LPC2106_GCC/ram_arm.bat b/Demo/ARM7_LPC2106_GCC/ram_arm.bat new file mode 100644 index 000000000..1f3c5da0a --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/ram_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=lpc2106-ram.ld +make diff --git a/Demo/ARM7_LPC2106_GCC/ram_thumb.bat b/Demo/ARM7_LPC2106_GCC/ram_thumb.bat new file mode 100644 index 000000000..414a3a6b6 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/ram_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=lpc2106-ram.ld +make diff --git a/Demo/ARM7_LPC2106_GCC/readme.txt b/Demo/ARM7_LPC2106_GCC/readme.txt new file mode 100644 index 000000000..af4856965 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/readme.txt @@ -0,0 +1,18 @@ +Use one of the following four batch files to build the demo application: + ++ rom_arm.bat + +Creates an ARM mode release build suitable for programming into flash. + ++ ram_arm.bat + +Creates an ARM mode debug build suitable for running from RAM. + ++ rom_thumb.bat + +Creates a THUMB mode release build suitable for programming into flash. + ++ ram_thumb.bat + +Creates a THUMB mode debug build suitable for running from RAM. + diff --git a/Demo/ARM7_LPC2106_GCC/rom_arm.bat b/Demo/ARM7_LPC2106_GCC/rom_arm.bat new file mode 100644 index 000000000..7f7d88333 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/rom_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG= +set OPTIM=-O3 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=lpc2106-rom.ld +make diff --git a/Demo/ARM7_LPC2106_GCC/rom_thumb.bat b/Demo/ARM7_LPC2106_GCC/rom_thumb.bat new file mode 100644 index 000000000..ea9920402 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/rom_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG= +set OPTIM=-O3 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=lpc2106-rom.ld +make diff --git a/Demo/ARM7_LPC2106_GCC/serial/serial.c b/Demo/ARM7_LPC2106_GCC/serial/serial.c new file mode 100644 index 000000000..9e3f66da0 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/serial/serial.c @@ -0,0 +1,263 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V2.4.0 + + + Made serial ISR handling more complete and robust. + + Changes from V2.4.1 + + + Split serial.c into serial.c and serialISR.c. serial.c can be + compiled using ARM or THUMB modes. serialISR.c must always be + compiled in ARM mode. + + Another small change to cSerialPutChar(). + + Changed from V2.5.1 + + + In cSerialPutChar() an extra check is made to ensure the post to + the queue was successful if then attempting to retrieve the posted + character. + +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serUART0_VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serUART0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serUART0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Communication flag between the interrupt service routine and serial API. */ +static volatile portLONG *plTHREEmpty; + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR )( void ); + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode. */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + UART0_LCR |= serDLAB; + + /* Setup the divisor. */ + UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT ); + VICIntEnable |= serUART0_VIC_CHANNEL_BIT; + VICVectAddr1 = ( portLONG ) vUART_ISR; + VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE; + + /* Enable UART0 interrupts. */ + UART0_IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* This demo driver only supports one port so the parameter is not used. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Demo/ARM7_LPC2106_GCC/serial/serialISR.c b/Demo/ARM7_LPC2106_GCC/serial/serialISR.c new file mode 100644 index 000000000..679260ad3 --- /dev/null +++ b/Demo/ARM7_LPC2106_GCC/serial/serialISR.c @@ -0,0 +1,163 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. + +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the VIC. */ +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty; + +/*-----------------------------------------------------------*/ + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/* UART0 interrupt service routine. This can cause a context switch so MUST +be declared "naked". */ +void vUART_ISR( void ) __attribute__ ((naked)); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; + + /* Initialise the THRE empty flag - and pass back a reference. */ + lTHREEmpty = ( portLONG ) pdTRUE; + *pplTHREEmptyFlag = &lTHREEmpty; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) +{ + /* This ISR can cause a context switch, so the first statement must be a + call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + variable declarations. */ + portENTER_SWITCHING_ISR(); + + /* Now we can declare the local variables. */ + signed portCHAR cChar; + portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; + + /* What caused the interrupt? */ + switch( UART0_IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = UART0_LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + UART0_THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = UART0_RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..0a08f50a9 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Hardware specifics. */ +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c b/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..d3ceca4a3 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c @@ -0,0 +1,102 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's. + *-----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Board specific defines. */ +#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) +#define partstNUM_LEDS ( 8 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* The ports are setup within prvInitialiseHardware(), called by main(). */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set or clear the output. */ + if( xValue ) + { + IO1SET = ulLED; + } + else + { + IO1CLR = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = IO1PIN; + if( ulCurrentState & ulLED ) + { + IO1CLR = ulLED; + } + else + { + IO1SET = ulLED; + } + } +} + + diff --git a/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 b/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 new file mode 100644 index 000000000..c920a210a --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 @@ -0,0 +1,173 @@ +;----------------------------------------------------------------------------- +; This file contains the startup code used by the ICCARM C compiler. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; All code in the modules (except ?RESET) will be placed in the ICODE segment. +; +; $Revision: 1.56 $ +; +;----------------------------------------------------------------------------- + +; +; Naming covention of labels in this file: +; +; ?xxx - External labels only accessed from assembler. +; __xxx - External labels accessed from or defined in C. +; xxx - Labels local to one module (note: this file contains +; several modules). +; main - The starting point of the user program. +; + +;--------------------------------------------------------------- +; Macros and definitions for the whole file +;--------------------------------------------------------------- + +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +I_Bit DEFINE 0x80 ; IRQ Disable Bit +F_Bit DEFINE 0x40 ; FIQ Disable Bit + +;--------------------------------------------------------------- +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other +; addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;--------------------------------------------------------------- + + MODULE ?RESET + COMMON INTVEC:CODE:NOROOT(2) + PUBLIC __program_start + EXTERN ?cstartup + EXTERN undef_handler, swi_handler, prefetch_handler + EXTERN data_handler, irq_handler, fiq_handler + EXTERN vPortYieldProcessor + + CODE32 ; Always ARM mode after reset + +__program_start + + org 0x00 + + B InitReset ; 0x00 Reset handler + undefvec: + B undefvec ; 0x04 Undefined Instruction + swivec: + B vPortYieldProcessor ; 0x08 Software Interrupt + pabtvec: + B pabtvec ; 0x0C Prefetch Abort + dabtvec: + B dabtvec ; 0x10 Data Abort + rsvdvec: + B rsvdvec ; 0x14 reserved + irqvec: + LDR PC, [PC, #-0xFF0] ; Jump directly to the address given by the AIC + + fiqvec: ; 0x1c FIQ + + +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- + + RSEG IRQ_STACK:DATA(2) + RSEG SVC_STACK:DATA:NOROOT(2) + RSEG CSTACK:DATA(2) + RSEG ICODE:CODE:NOROOT(2) + EXTERN ?main + +; Execution starts here. +; After a reset, the mode is ARM, Supervisor, interrupts disabled. + + + CODE32 + +InitReset + +; Add initialization needed before setup of stackpointers here + + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of CSTACK + +; Must start in supervisor mode. + MSR CPSR_c, #SVC_MODE|I_Bit|F_Bit + + +; Add more initialization here + + +; Continue to ?main for more IAR specific system startup + + ldr r0,=?main + bx r0 + + + + +;--------------------------------------------------------------- +; ?EXEPTION_VECTOR +; This module is only linked if needed for closing files. +;--------------------------------------------------------------- + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + CODE32 ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + ENDMOD + + END + + + + + ENDMOD + END + + + + diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c new file mode 100644 index 000000000..e1d8c4900 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/main.c @@ -0,0 +1,284 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 7 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* And finally, constant to setup the port for the LED's. */ +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configures the processor for use with this demo. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup the processor. */ + prvSetupHardware(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. + */ + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL to multiply the XTAL input by 4. */ + PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + PLLCON = mainPLL_ENABLE; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + PLLCON = mainPLL_CONNECT; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAMTIM = mainMAM_TIM_3; + MAMCR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; + + /* LED pins need to be output. */ + IO1DIR = mainLED_TO_OUTPUT; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl b/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl new file mode 100644 index 000000000..5d427ec66 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl @@ -0,0 +1,190 @@ +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1 $ +//************************************************************************* + +//************************************************************************* +// +// ------------- +// Code segments - may be placed anywhere in memory. +// ------------- +// +// INTVEC -- Exception vector table. +// SWITAB -- Software interrupt vector table. +// ICODE -- Startup (cstartup) and exception code. +// DIFUNCT -- Dynamic initialization vectors used by C++. +// CODE -- Compiler generated code. +// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) +// CODE_ID -- Initializer for CODE_I (ROM). +// +// ------------- +// Data segments - may be placed anywhere in memory. +// ------------- +// +// CSTACK -- The stack used by C/C++ programs (system and user mode). +// IRQ_STACK -- The stack used by IRQ service routines. +// SVC_STACK -- The stack used in supervisor mode +// (Define other exception stacks as needed for +// FIQ, ABT, UND). +// HEAP -- The heap used by malloc and free in C and new and +// delete in C++. +// INITTAB -- Table containing addresses and sizes of segments that +// need to be initialized at startup (by cstartup). +// CHECKSUM -- The linker places checksum byte(s) in this segment, +// when the -J linker command line option is used. +// DATA_y -- Data objects. +// +// Where _y can be one of: +// +// _AN -- Holds uninitialized located objects, i.e. objects with +// an absolute location given by the @ operator or the +// #pragma location directive. Since these segments +// contain objects which already have a fixed address, +// they should not be mentioned in this linker command +// file. +// _C -- Constants (ROM). +// _I -- Initialized data (RAM). +// _ID -- The original content of _I (copied to _I by cstartup) (ROM). +// _N -- Uninitialized data (RAM). +// _Z -- Zero initialized data (RAM). +// +// Note: Be sure to use end values for the defined address ranges. +// Otherwise, the linker may allocate space outside the +// intended memory range. +//************************************************************************* + + +//************************************************ +// Inform the linker about the CPU family used. +//************************************************ + +-carm + +//************************************************************************* +// Segment placement - General information +// +// All numbers in the segment placement command lines below are interpreted +// as hexadecimal unless they are immediately preceded by a '.', which +// denotes decimal notation. +// +// When specifying the segment placement using the -P instead of the -Z +// option, the linker is free to split each segment into its segment parts +// and randomly place these parts within the given ranges in order to +// achieve a more efficient memory usage. One disadvantage, however, is +// that it is not possible to find the start or end address (using +// the assembler operators .sfb./.sfe.) of a segment which has been split +// and reformed. +// +// When generating an output file which is to be used for programming +// external ROM/Flash devices, the -M linker option is very useful +// (see xlink.pdf for details). +//************************************************************************* + + +//************************************************************************* +// Read-only segments mapped to ROM. +//************************************************************************* + +-DROMSTART=00000000 +-DROMEND=00001ffff + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ + +-Z(CODE)INTVEC=00000000-0000003f + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ + +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ + +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Original ROM location for __ramfunc code copied +// to and executed from RAM. +//************************************************ + +-Z(CONST)CODE_ID=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ + +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* + +-DRAMSTART=40000000 +-DRAMEND=40003fff + +//************************************************ +// Data segments. +//************************************************ + +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ + +-Z(DATA)CODE_I=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// CODE_ID segment instead, but to keep symbol and +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +-QCODE_I=CODE_ID + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* + +-D_CSTACK_SIZE=200 +-D_SVC_STACK_SIZE=190 +-D_IRQ_STACK_SIZE=190 +-D_HEAP_SIZE=4 + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd new file mode 100644 index 000000000..41a42a723 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd @@ -0,0 +1,913 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + + + Flash Bin + + ARM + + 0 + + C-SPY + 2 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 0 + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + JLINK_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + + + + diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp new file mode 100644 index 000000000..9d363c963 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp @@ -0,0 +1,1732 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + General + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\serial\serialISR.s79 + + + + Scheduler Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\SrcIAR\cstartup.s79 + + + + + diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.eww b/Demo/ARM7_LPC2129_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/Demo/ARM7_LPC2129_IAR/serial/serial.c b/Demo/ARM7_LPC2129_IAR/serial/serial.c new file mode 100644 index 000000000..5729774dc --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/serial/serial.c @@ -0,0 +1,288 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Misc. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* The ISR. Note that this is called by a wrapper written in the file +SerialISR.s79. See the WEB documentation for this port for further +information. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; +extern void ( vSerialISREntry) ( void ); + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Initialise the THRE empty flag. */ + lTHREEmpty = pdTRUE; + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + U0LCR |= serDLAB; + + /* Setup the divisor. */ + U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); + VICIntEnable |= serU0VIC_CHANNEL_BIT; + VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry; + VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; + + /* Enable UART0 interrupts. */ + U0IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + + xReturn = ( xComPortHandle ) 1; + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( lTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + lTHREEmpty = pdFALSE; + U0THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. It is ok to block within a critical section as each + task has it's own critical section management. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( lTHREEmpty == ( portLONG ) pdTRUE ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + lTHREEmpty = pdFALSE; + U0THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +__arm void vSerialISR( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* What caused the interrupt? */ + switch( U0IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = U0LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + U0THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = U0RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 b/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt b/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt new file mode 100644 index 000000000..5085f2cdb --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt @@ -0,0 +1,71 @@ + + + + + + + + + + + 1892727 + + + + + + 200100 + + + 200188171100100010 + + + + + TabID-23416-30482 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + + + TabID-12145-30489 + Debug Log + Debug-Log + + + + TabID-22894-30492 + Build + Build + + + + + 1 + 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TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 + + + + + + + iaridepm1debuggergui1-2-2739212-2-20000133750662198-2-23331602-2-21604335100250029937492500132260 + + + + diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..b3fefed21 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni @@ -0,0 +1,33 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Low Level] +Pipeline mode=1 +Initialized=0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\queue.c}.179.3@1" 1 0 0 0 "" 0 "" +Count=1 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +TypeVolition=1 +UnspecRange=1 +ActionState=1 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..90d8027fe --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,60 @@ + + + + + + rtosdemo/Flash Debug + + + + + + + + 229272727 + + 18115530877 + + + + + + + + + + + 10001055278946 + + + + + + + TabID-17425-14382 + Workspace + Workspace + + + rtosdemortosdemo/Scheduler Sourcertosdemo/System Files + + + + 0TabID-22109-27077BuildBuildTabID-12074-10873BreakpointsBreakpointsTabID-18349-15872Debug LogDebug-LogTabID-30013-18825Find in FilesFind-in-Files0 + + + + + + TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 + + + + + + + iaridepm1-2-2944303-2-20000190625845397-2-21281602-2-2160413010025001161755500078641 + + + + diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par new file mode 100644 index 000000000..738732e18 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=200; +$IRQSTACK_SIZE=400; +$HEAP_SIZE=4; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl"; +% \ No newline at end of file diff --git a/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..8c7aae165 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c b/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c new file mode 100644 index 000000000..37508e571 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c @@ -0,0 +1,97 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#include "FreeRTOS.h" +#include "portable.h" +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) +#define partstNUM_LEDS ( 8 ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set or clear the output. */ + if( xValue ) + { + IOSET1 = ulLED; + } + else + { + IOCLR1 = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = IOPIN1; + if( ulCurrentState & ulLED ) + { + IOCLR1 = ulLED; + } + else + { + IOSET1 = ulLED; + } + } +} + diff --git a/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL b/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL new file mode 100644 index 000000000..7df396ed8 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL @@ -0,0 +1,40 @@ +[Signal 1] +DispName=Port1 +PlotType=1 +Color=16711935 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=65536 +Offset=16 +[Signal 2] +DispName=Port1 +PlotType=1 +Color=255 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=131072 +Offset=17 +[Signal 3] +DispName=Port1 +PlotType=1 +Color=32768 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=262144 +Offset=18 +[Signal 4] +DispName=Port1 +PlotType=1 +Color=16711680 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=524288 +Offset=19 diff --git a/Demo/ARM7_LPC2129_Keil/Startup.s b/Demo/ARM7_LPC2129_Keil/Startup.s new file mode 100644 index 000000000..769ed7890 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/Startup.s @@ -0,0 +1,379 @@ +/***********************************************************************/ +/* This file is part of the uVision/ARM development tools */ +/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */ +/***********************************************************************/ +/* */ +/* STARTUP.S: Startup file for Philips LPC2000 device series */ +/* */ +/***********************************************************************/ + + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +// *** Startup Code (executed after Reset) *** + + +// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + + Mode_USR EQU 0x10 + Mode_FIQ EQU 0x11 + Mode_IRQ EQU 0x12 + Mode_SVC EQU 0x13 + Mode_ABT EQU 0x17 + Mode_UND EQU 0x1B + Mode_SYS EQU 0x1F + + I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */ + F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */ + + +/* +// Stack Configuration (Stack Sizes in Bytes) +// Undefined Mode <0x0-0xFFFFFFFF> +// Supervisor Mode <0x0-0xFFFFFFFF> +// Abort Mode <0x0-0xFFFFFFFF> +// Fast Interrupt Mode <0x0-0xFFFFFFFF> +// Interrupt Mode <0x0-0xFFFFFFFF> +// User/System Mode <0x0-0xFFFFFFFF> +// +*/ + UND_Stack_Size EQU 0x00000004 + SVC_Stack_Size EQU 0x00000100 + ABT_Stack_Size EQU 0x00000004 + FIQ_Stack_Size EQU 0x00000004 + IRQ_Stack_Size EQU 0x00000300 + USR_Stack_Size EQU 0x00000200 + +AREA STACK, DATA, READWRITE, ALIGN=2 + DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode + DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode + DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode + DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode + DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode + DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode +Top_Stack: + + +// Phase Locked Loop (PLL) definitions + PLL_BASE EQU 0xE01FC080 /* PLL Base Address */ + PLLCON_OFS EQU 0x00 /* PLL Control Offset*/ + PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */ + PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */ + PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */ + PLLCON_PLLE EQU (1<<0) /* PLL Enable */ + PLLCON_PLLC EQU (1<<1) /* PLL Connect */ + PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */ + PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */ + PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */ + +/* +// PLL Setup +// Phase Locked Loop +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value +// PSEL: PLL Divider Selection +// <0=> 1 <1=> 2 <2=> 4 <3=> 8 +// P Value +// +*/ + PLL_SETUP EQU 1 + PLLCFG_Val EQU 0x00000024 + + +// Memory Accelerator Module (MAM) definitions + MAM_BASE EQU 0xE01FC000 /* MAM Base Address */ + MAMCR_OFS EQU 0x00 /* MAM Control Offset*/ + MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */ + +/* +// MAM Setup +// Memory Accelerator Module +// MAM Control +// <0=> Disabled +// <1=> Partially Enabled +// <2=> Fully Enabled +// Mode +// MAM Timing +// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// Fetch Cycles +// +*/ + MAM_SETUP EQU 1 + MAMCR_Val EQU 0x00000002 + MAMTIM_Val EQU 0x00000003 + + +// External Memory Controller (EMC) definitions + EMC_BASE EQU 0xFFE00000 /* EMC Base Address */ + BCFG0_OFS EQU 0x00 /* BCFG0 Offset */ + BCFG1_OFS EQU 0x04 /* BCFG1 Offset */ + BCFG2_OFS EQU 0x08 /* BCFG2 Offset */ + BCFG3_OFS EQU 0x0C /* BCFG3 Offset */ + +/* +// External Memory Controller (EMC) +*/ + EMC_SETUP EQU 0 + +/* +// Bank Configuration 0 (BCFG0) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG0_SETUP EQU 0 + BCFG0_Val EQU 0x0000FBEF + +/* +// Bank Configuration 1 (BCFG1) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG1_SETUP EQU 0 + BCFG1_Val EQU 0x0000FBEF + +/* +// Bank Configuration 0 (BCFG2) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG2_SETUP EQU 0 + BCFG2_Val EQU 0x0000FBEF + +/* +// Bank Configuration 3 (BCFG3) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG3_SETUP EQU 0 + BCFG3_Val EQU 0x0000FBEF + +/* +// End of EMC +*/ + + +// External Memory Pins definitions + PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */ + PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, + D0..31, A2..23, JTAG Pins */ + + +// Starupt Code must be linked first at Address at which it expects to run. + +$IF (EXTERNAL_MODE) + CODE_BASE EQU 0x80000000 +$ELSE + CODE_BASE EQU 0x00000000 +$ENDIF + +AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4 + PUBLIC __startup + + EXTERN CODE32 (?C?INIT) + +__startup PROC CODE32 + +// Pre-defined interrupt handlers that may be directly +// overwritten by C interrupt functions +EXTERN CODE32 (Undef_Handler?A) +EXTERN CODE32 (vPortYieldProcessor?A) +EXTERN CODE32 (PAbt_Handler?A) +EXTERN CODE32 (DAbt_Handler?A) +EXTERN CODE32 (IRQ_Handler?A) +EXTERN CODE32 (FIQ_Handler?A) + +// Exception Vectors +// Mapped to Address 0. +// Absolute addressing mode must be used. + +Vectors: LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP /* Reserved Vector */ +; LDR PC,IRQ_Addr + LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */ + LDR PC,FIQ_Addr + +Reset_Addr: DD Reset_Handler +Undef_Addr: DD Undef_Handler?A +SWI_Addr: DD vPortYieldProcessor?A +PAbt_Addr: DD PAbt_Handler?A +DAbt_Addr: DD DAbt_Handler?A + DD 0 /* Reserved Address */ +IRQ_Addr: DD IRQ_Handler?A +FIQ_Addr: DD FIQ_Handler?A + + +// Reset Handler + +Reset_Handler: + + +$IF (EXTERNAL_MODE) + LDR R0, =PINSEL2 + LDR R1, =PINSEL2_Val + STR R1, [R0] +$ENDIF + + +IF (EMC_SETUP != 0) + LDR R0, =EMC_BASE + +IF (BCFG0_SETUP != 0) + LDR R1, =BCFG0_Val + STR R1, [R0, #BCFG0_OFS] +ENDIF + +IF (BCFG1_SETUP != 0) + LDR R1, =BCFG1_Val + STR R1, [R0, #BCFG1_OFS] +ENDIF + +IF (BCFG2_SETUP != 0) + LDR R1, =BCFG2_Val + STR R1, [R0, #BCFG2_OFS] +ENDIF + +IF (BCFG3_SETUP != 0) + LDR R1, =BCFG3_Val + STR R1, [R0, #BCFG3_OFS] +ENDIF + +ENDIF + + +IF (PLL_SETUP != 0) + LDR R0, =PLL_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +// Configure and Enable PLL + MOV R3, #PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + +// Wait until PLL Locked +PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + +// Switch to PLL Clock + MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] +ENDIF + + +IF (MAM_SETUP != 0) + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] +ENDIF + + +// Memory Mapping (when Interrupt Vectors are in RAM) + MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */ + +$IF (RAM_INTVEC) + LDR R0, =MEMMAP + MOV R1, #2 + STR R1, [R0] +$ENDIF + + +// Setup Stack for each mode + LDR R0, =Top_Stack + +// Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +// Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +// Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +// Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +// Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +// Enter S Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SYS + MOV SP, R0 + +// Start in supervisor mode + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit + +// Enter the C code + LDR R0,=?C?INIT + TST R0,#1 ; Bit-0 set: INIT is Thumb + LDREQ LR,=exit?A ; ARM Mode + LDRNE LR,=exit?T ; Thumb Mode + BX R0 + ENDP + +PUBLIC exit?A +exit?A PROC CODE32 + B exit?A + ENDP + +PUBLIC exit?T +exit?T PROC CODE16 +exit: B exit?T + ENDP + + + END diff --git a/Demo/ARM7_LPC2129_Keil/main.c b/Demo/ARM7_LPC2129_Keil/main.c new file mode 100644 index 000000000..ab4971389 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/main.c @@ -0,0 +1,282 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "serial.h" + +#ifdef KEIL_THUMB_INTERWORK + /* + THUMB mode allows more tasks to be created without the executable + binary exceeding the limits allowed by the evaluation version of + uVision3. + */ + #include "PollQ.h" + #include "BlockQ.h" + #include "semtest.h" + #include "dynamic.h" + +#endif + +/*-----------------------------------------------------------*/ + +/* Constants to setup I/O and processor. */ +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) + +/* Constants for the ComTest demo application tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) + +/* Constants used by the "check" task. As described at the head of this file +the check task toggles an LED. The rate at which the LED flashes is used to +indicate whether an error has been detected or not. If the LED toggles every +3 seconds then no errors have been detected. If the rate increases to 500ms +then an error has been detected in at least one of the demo application tasks. */ +#define mainCHECK_LED ( 7 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the Keil demo board. This is very + * minimal as most of the setup is managed by the settings in the project + * file. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + + + +/* + * Application entry point: + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Keil demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + + #ifdef KEIL_THUMB_INTERWORK + /* When using THUMB mode we can start more tasks without the executable + exceeding the size limit imposed by the evaluation version of uVision3. */ + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + #endif + + /* Start the check task - which is defined in this file. This is the task + that periodically checks to see that all the other tasks are executing + without error. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* Parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + This task runs at the highest priority. */ + + for( ;; ) + { + /* The period of the delay depends on whether an error has been + detected or not. If an error has been detected then the period + is reduced to increase the LED flash rate. */ + vTaskDelay( xDelayPeriod ); + + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Toggle the LED before going back to wait for the next cycle. */ + vParTestToggleLED( mainCHECK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Perform the hardware setup required. This is minimal as most of the + setup is managed by the settings in the project file. */ + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; + + /* LED pins need to be output. */ + IODIR1 = mainLED_TO_OUTPUT; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + if( xAreIntegerMathsTaskStillRunning() != pdPASS ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdPASS ) + { + lReturn = pdFAIL; + } + + #ifdef KEIL_THUMB_INTERWORK + + /* When using THUMB mode we can start more tasks without the executable + exceeding the size limit imposed by the evaluation version of uVision3. */ + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + #endif + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt new file mode 100644 index 000000000..268345f18 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt @@ -0,0 +1,58 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS), 0x0005 // Tools: '' +GRPOPT 1,(ARM_DEMO),1,0,0 + +OPTFFF 1,1,1,2,0,127,137,0,<.\main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 } +OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> +OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> +OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> +OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> +OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c> +OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> + + +TARGOPT 1, (FreeRTOS) + KACLK=12000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTBL 0,(Data Sheet) + OPTBL 1,(User Manual) + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) + OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTMM 1,0,(0x40001800) + OPTDF 0x1000080 + OPTLE <> + OPTLC <> + OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) +EndOpt + diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 new file mode 100644 index 000000000..2b4655ff1 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 @@ -0,0 +1,106 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS), 0x0005 // Tools: '' + +Group (ARM_DEMO) + +File 1,1,<.\main.c> 0x4162D96A +File 1,2,<.\Startup.s> 0x415AF382 +File 1,1,<.\ParTest\ParTest.c> 0x415AF50E +File 1,1,<.\serial\serial.c> 0x4162D488 +File 1,1,<.\serial\serialISR.c> 0x4162D404 +File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 +File 1,1,<..\..\Source\queue.c> 0x411B5F14 +File 1,1,<..\..\Source\list.c> 0x411B5F24 +File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 +File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 +File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 +File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE +File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 + + +Options 1,0,0 // Target 'FreeRTOS' + Device (LPC2129) + Vendor (Philips) + Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) + FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) + StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) + FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) + Rgf (LPC21xx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) + EnvInc () + EnvLib () + EnvReg (ÿPhilips\) + OrgReg (ÿPhilips\) + TgStat=16 + OutDir (.\) + OutName (rtosdemo_ARM) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + KACPU (ARM7TDMI) + TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KIROM { 1,0,0,0,0,0,0,4,0 } + KIRAM { 0,0,0,0,64,0,64,0,0 } + KXRAM { 0,0,0,0,0,0,0,0,0 } + KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAMSC (INTERWORK) + KCADEF (KEIL_ARM7) + KCAUDF () + KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) + KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KAAMSC () + KAASET () + KAARST () + KAAINC () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KLAMSC () + KLADWN (25) + KLACFI () + KLAASN () + KLARES () + KLACCL () + KLAUCL () + KLACSC () + KLAUCS () + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2ARM.DLL) + FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) + FLASH4 () +EndOpt + diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt new file mode 100644 index 000000000..39909fa34 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt @@ -0,0 +1,63 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS), 0x0005 // Tools: '' +GRPOPT 1,(THUMB_DEMO),1,0,0 + +OPTFFF 1,1,1,1,0,121,137,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 } +OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> +OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> +OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> +OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> +OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c> +OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c> +OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> +OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c> + +ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 } + +TARGOPT 1, (FreeRTOS) + KACLK=12000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTBL 0,(Data Sheet) + OPTBL 1,(User Manual) + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) + OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTMM 1,0,(0x40000840) + OPTDF 0x1000086 + OPTLE <> + OPTLC <> + OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) +EndOpt + diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 new file mode 100644 index 000000000..8e6cb20e7 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 @@ -0,0 +1,110 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS), 0x0005 // Tools: '' + +Group (THUMB_DEMO) + +File 1,1,<.\main.c> 0x4162D96A +File 1,2,<.\Startup.s> 0x415AF382 +File 1,1,<.\ParTest\ParTest.c> 0x415AF50E +File 1,1,<.\serial\serial.c> 0x4162D488 +File 1,1,<.\serial\serialISR.c> 0x4162D404 +File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 +File 1,1,<..\..\Source\queue.c> 0x411B5F14 +File 1,1,<..\..\Source\list.c> 0x411B5F24 +File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 +File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 +File 1,1,<..\Common\Minimal\BlockQ.c> 0x411B5F8C +File 1,1,<..\Common\Minimal\semtest.c> 0x411B5F8C +File 1,1,<..\Common\Minimal\PollQ.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 +File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE +File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 +File 1,1,<..\Common\Minimal\dynamic.c> 0x0 + + +Options 1,0,0 // Target 'FreeRTOS' + Device (LPC2129) + Vendor (Philips) + Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) + FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) + StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) + FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) + Rgf (LPC21xx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) + EnvInc () + EnvLib () + EnvReg (ÿPhilips\) + OrgReg (ÿPhilips\) + TgStat=16 + OutDir (.\) + OutName (rtosdemo_THUMB) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + KACPU (ARM7TDMI) + TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KIROM { 1,0,0,0,0,0,0,4,0 } + KIRAM { 0,0,0,0,64,0,64,0,0 } + KXRAM { 0,0,0,0,0,0,0,0,0 } + KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAMSC (INTERWORK) + KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK) + KCAUDF () + KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) + KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KAAMSC () + KAASET () + KAARST () + KAAINC () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KLAMSC () + KLADWN (25) + KLACFI () + KLAASN () + KLARES () + KLACCL () + KLAUCL () + KLACSC () + KLAUCS () + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2ARM.DLL) + FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) + FLASH4 () +EndOpt + diff --git a/Demo/ARM7_LPC2129_Keil/serial/serial.c b/Demo/ARM7_LPC2129_Keil/serial/serial.c new file mode 100644 index 000000000..f389d1a83 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/serial/serial.c @@ -0,0 +1,247 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Misc. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Communication flag between the interrupt service routine and serial API. */ +static volatile portLONG *plTHREEmpty; + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode). */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* The reference to the ISR function is required to load into the + interrupt controller. The prototype is slightly different + depending on whether in ARM or THUMB mode. */ + #ifdef KEIL_THUMB_INTERWORK + extern void ( vUART_ISR )( void ) __arm __task; + #else + extern void ( vUART_ISR )( void ) __task; + #endif + + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + U0LCR |= serDLAB; + + /* Setup the divisor. */ + U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); + VICIntEnable |= serU0VIC_CHANNEL_BIT; + VICVectAddr1 = ( unsigned portLONG ) vUART_ISR; + VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; + + /* Enable UART0 interrupts. */ + U0IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + *plTHREEmpty = pdFALSE; + U0THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. It is ok to block within a critical section as each + task has it's own critical section management. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + *plTHREEmpty = pdFALSE; + U0THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + + + + + + + diff --git a/Demo/ARM7_LPC2129_Keil/serial/serialISR.c b/Demo/ARM7_LPC2129_Keil/serial/serialISR.c new file mode 100644 index 000000000..66a57f4a0 --- /dev/null +++ b/Demo/ARM7_LPC2129_Keil/serial/serialISR.c @@ -0,0 +1,160 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. +*/ + +/* This file must always be compiled to ARM mode as it contains ISR +definitions. */ +#pragma ARM + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the VIC. */ +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty; + +/*-----------------------------------------------------------*/ + +/* UART0 interrupt service routine. This can cause a context switch so MUST +be declared "naked". */ +void vUART_ISR( void ); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; + + /* Initialise the THRE empty flag - and pass back a reference. */ + lTHREEmpty = pdTRUE; + *pplTHREEmptyFlag = &lTHREEmpty; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) __task +{ + portENTER_SWITCHING_ISR() + + /* Now we can declare the local variables. */ + static signed portCHAR cChar; + static portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx; + + xTaskWokenByTx = pdFALSE; + xTaskWokenByRx = pdFALSE; + + /* What caused the interrupt? */ + switch( U0IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = U0LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + U0THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = U0RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h b/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..1d3b1ccf5 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h @@ -0,0 +1,75 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 20480 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_STR71x_IAR/Library/71x_lib.c b/Demo/ARM7_STR71x_IAR/Library/71x_lib.c new file mode 100644 index 000000000..53af3c5f0 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/71x_lib.c @@ -0,0 +1,157 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Peripherals pointers initialization +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +#include "71x_map.h" + +#ifdef DEBUG + +extern u32 T0TIMI_Addr; + +/******************************************************************************* +* Function Name : debug +* Description : Initialize the pointers to peripherals +* Input : none +* Output : none +* Return : none +*******************************************************************************/ +void debug(void) +{ + #ifdef _ADC12 + ADC12 = (ADC12_TypeDef *)ADC12_BASE; + #endif + + #ifdef _APB + #ifdef _APB1 + APB1 = (APB_TypeDef *)APB1_BASE; + #endif + #ifdef _APB2 + APB2 = (APB_TypeDef *)APB2_BASE; + #endif + #endif + + #ifdef _BSPI + #ifdef _BSPI0 + BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; + #endif + #ifdef _BSPI1 + BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; + #endif + #endif + + #ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; + #endif + + #ifdef _EIC + EIC = (EIC_TypeDef *)EIC_BASE; + #endif + + #ifdef _EMI + EMI = (EMI_TypeDef *)EMI_BASE; + #endif + + #ifdef _FLASH + FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; + FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; + #endif + + #ifdef _GPIO + #ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; + #endif + #ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; + #endif + #ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; + #endif + #endif + + #ifdef _I2C + #ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; + #endif + #ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; + #endif + #endif + + #ifdef _PCU + PCU = (PCU_TypeDef *)PCU_BASE; + #endif + + #ifdef _RCCU + RCCU = (RCCU_TypeDef *)RCCU_BASE; + #endif + + #ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; + #endif + + #ifdef _TIM + #ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; + #endif + #ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; + #endif + #ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; + #endif + #ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; + #endif + #endif + + #ifdef _UART + #ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; + #endif + #ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; + #endif + #ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; + #endif + #ifdef _UART3 + UART3 = (UART_TypeDef *)UART3_BASE; + #endif + #endif + + #ifdef _USB + USB = (USB_TypeDef *)USB_BASE; + #endif + + #ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; + #endif + + #ifdef _XTI + XTI = (XTI_TypeDef *)XTI_BASE; + #endif + + #ifdef _IRQVectors + IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; + #endif +} + +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/gpio.c b/Demo/ARM7_STR71x_IAR/Library/gpio.c new file mode 100644 index 000000000..7c1bbb119 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/gpio.c @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : gpio.c +* Author : MCD Application Team +* Date First Issued : 06/08/2003 +* Description : This file provides all the GPIO software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "gpio.h" + +/******************************************************************************* +* Function Name : GPIO_Config +* Description : Configure the GPIO port pins +* Input 1 : GPIOx (x can be 0,1 or 2) the desired port +* Input 2 : Port_Pins : pins placements +* Input 3 : Pins Mode +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) +{ + switch (GPIO_Mode) + { + case GPIO_HI_AIN_TRI: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IN_TRI_TTL: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IN_TRI_CMOS: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IPUPD_WP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_OUT_OD: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_OUT_PP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_AF_OD: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_AF_PP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_BitWrite +* Description : Set or reset the selected port pin +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Input 3 : bit value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) +{ + if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) + : (GPIOx->PD&0xFF00) | Port_Val; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h new file mode 100644 index 000000000..26e5383a3 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h @@ -0,0 +1,91 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_conf.h +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : Library configuration for the ADC12 example +******************************************************************************** +* History: +* 16/05/2003 : Created +* 30/11/2004 : V2.0 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __71x_CONF_H +#define __71x_CONF_H + + +/* Comment the line below to put the library in release mode */ +//#define DEBUG + +//#define inline inline + +//#define USE_SERIAL_PORT +//#define USE_UART0 + +// Main Oscillator Frequency value = 4 Mhz +#define RCCU_Main_Osc 4000000 + +/* Comment the lines below corresponding to unwanted peripherals */ +//#define _ADC12 + +//#define _APB +//#define _APB1 +//#define _APB2 + +//#define _BSPI +//#define _BSPI0 +//#define _BSPI1 + +//#define _CAN + +//#define _EIC + +//#define _EMI + +//#define _FLASH + +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 + +//#define _I2C +//#define _I2C0 +//#define _I2C1 + +#define _PCU + +#define _RCCU + +//#define _RTC + +#define _TIM +#define _TIM0 +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 + +//#define _UART +//#define _UART0 +//#define _UART1 +//#define _UART2 +//#define _UART3 + +//#define _USB + +//#define _WDG + +//#define _XTI + + +//#define _IRQVectors + + +#endif /* __71x_CONF_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h new file mode 100644 index 000000000..ebfc97296 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h @@ -0,0 +1,61 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_it.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Interrupt handlers +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _71x_IT_H +#define _71x_IT_H + +#include "71x_lib.h" + + +void Undefined_Handler (void); +void FIQ_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void T0TIMI_IRQHandler (void); +void FLASH_IRQHandler (void); +void RCCU_IRQHandler (void); +void RTC_IRQHandler (void); +void WDG_IRQHandler (void); +void XTI_IRQHandler (void); +void USBHP_IRQHandler (void); +void I2C0ITERR_IRQHandler(void); +void I2C1ITERR_IRQHandler(void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void UART3_IRQHandler (void); +void BSPI0_IRQHandler (void); +void BSPI1_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void CAN_IRQHandler (void); +void ADC12_IRQHandler (void); +void T1TIMI_IRQHandler (void); +void T2TIMI_IRQHandler (void); +void T3TIMI_IRQHandler (void); +void HDLC_IRQHandler (void); +void USBLP_IRQHandler (void); +void T0TOI_IRQHandler (void); +void T0OC1_IRQHandler (void); +void T0OC2_IRQHandler (void); + +#endif /* _71x_IT_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h new file mode 100644 index 000000000..8da0d658c --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Global include for all peripherals +******************************************************************************** +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __71x_LIB_H +#define __71x_LIB_H + +#include "71x_map.h" +#include "71x_conf.h" + + +#ifdef _ADC12 + #include "adc12.h" +#endif + +#ifdef _APB + #include "apb.h" +#endif + +#ifdef _BSPI + #include "bspi.h" +#endif + +#ifdef _CAN + #include "can.h" +#endif + +#ifdef _EIC + #include "eic.h" +#endif + +#ifdef _EMI + #include "emi.h" +#endif + +#ifdef _FLASH + #include "flash.h" +#endif + +#ifdef _GPIO + #include "gpio.h" +#endif + +#ifdef _I2C + #include "i2c.h" +#endif + +#ifdef _PCU + #include "pcu.h" +#endif + +#ifdef _RCCU + #include "rccu.h" +#endif + +#ifdef _RTC + #include "rtc.h" +#endif + +#ifdef _TIM + #include "tim.h" +#endif + +#ifdef _UART + #include "uart.h" +#endif + +#ifdef _USB +#endif + +#ifdef _WDG + #include "wdg.h" +#endif + +#ifdef _XTI + #include "xti.h" +#endif + + +#ifdef DEBUG + void debug(void); +#endif + +#endif /* __71x_LIB_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h new file mode 100644 index 000000000..fe1089ece --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h @@ -0,0 +1,610 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_map.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Peripherals memory mapping and registers structures +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __71x_map_H +#define __71x_map_H + +#ifndef EXT + #define EXT extern +#endif + +#include "71x_conf.h" +#include "71x_type.h" + + +/* IP registers structures */ + +typedef volatile struct +{ + vu16 DATA0; + vu16 EMPTY1[3]; + vu16 DATA1; + vu16 EMPTY2[3]; + vu16 DATA2; + vu16 EMPTY3[3]; + vu16 DATA3; + vu16 EMPTY4[3]; + vu16 CSR; + vu16 EMPTY5[7]; + vu16 CPR; +} ADC12_TypeDef; + +typedef volatile struct +{ + vu32 CKDIS; + vu32 SWRES; +} APB_TypeDef; + +typedef volatile struct +{ + vu16 RXR; + vu16 EMPTY1; + vu16 TXR; + vu16 EMPTY2; + vu16 CSR1; + vu16 EMPTY3; + vu16 CSR2; + vu16 EMPTY4; + vu16 CLK; +} BSPI_TypeDef; + +typedef volatile struct +{ + vu16 CRR; + vu16 EMPTY1; + vu16 CMR; + vu16 EMPTY2; + vu16 M1R; + vu16 EMPTY3; + vu16 M2R; + vu16 EMPTY4; + vu16 A1R; + vu16 EMPTY5; + vu16 A2R; + vu16 EMPTY6; + vu16 MCR; + vu16 EMPTY7; + vu16 DA1R; + vu16 EMPTY8; + vu16 DA2R; + vu16 EMPTY9; + vu16 DB1R; + vu16 EMPTY10; + vu16 DB2R; + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef volatile struct +{ + vu16 CR; + vu16 EMPTY1; + vu16 SR; + vu16 EMPTY2; + vu16 ERR; + vu16 EMPTY3; + vu16 BTR; + vu16 EMPTY4; + vu16 IDR; + vu16 EMPTY5; + vu16 TESTR; + vu16 EMPTY6; + vu16 BRPR; + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TR1R; + vu16 EMPTY9; + vu16 TR2R; + vu16 EMPTY10[13]; + vu16 ND1R; + vu16 EMPTY11; + vu16 ND2R; + vu16 EMPTY12[13]; + vu16 IP1R; + vu16 EMPTY13; + vu16 IP2R; + vu16 EMPTY14[13]; + vu16 MV1R; + vu16 EMPTY15; + vu16 MV2R; + vu16 EMPTY16; +} CAN_TypeDef; + +typedef volatile struct +{ + vu32 ICR; + vu32 CICR; + vu32 CIPR; + vu32 EMPTY1[3]; + vu32 IVR; + vu32 FIR; + vu32 IER; + vu32 EMPTY2[7]; + vu32 IPR; + vu32 EMPTY3[7]; + vu32 SIR[32]; +} EIC_TypeDef; + +typedef volatile struct +{ + vu16 BCON0; + vu16 EMPTY1; + vu16 BCON1; + vu16 EMPTY2; + vu16 BCON2; + vu16 EMPTY3; + vu16 BCON3; + vu16 EMPTY4; +} EMI_TypeDef; + +typedef volatile struct +{ + vu32 CR0; + vu32 CR1; + vu32 DR0; + vu32 DR1; + vu32 AR; + vu32 ER; +} FLASHR_TypeDef; + +typedef volatile struct +{ + vu32 NVWPAR; + vu32 EMPTY; + vu32 NVAPR0; + vu32 NVAPR1; +} FLASHPR_TypeDef; + +typedef volatile struct +{ + vu16 PC0; + vu16 EMPTY1; + vu16 PC1; + vu16 EMPTY2; + vu16 PC2; + vu16 EMPTY3; + vu16 PD; + vu16 EMPTY4; +} GPIO_TypeDef; + +typedef volatile struct +{ + vu8 CR; + vu8 EMPTY1[3]; + vu8 SR1; + vu8 EMPTY2[3]; + vu8 SR2; + vu8 EMPTY3[3]; + vu8 CCR; + vu8 EMPTY4[3]; + vu8 OAR1; + vu8 EMPTY5[3]; + vu8 OAR2; + vu8 EMPTY6[3]; + vu8 DR; + vu8 EMPTY7[3]; + vu8 ECCR; +} I2C_TypeDef; + +typedef volatile struct +{ + vu32 CCR; + vu32 EMPTY1; + vu32 CFR; + vu32 EMPTY2[3]; + vu32 PLL1CR; + vu32 PER; + vu32 SMR; +} RCCU_TypeDef; + +typedef volatile struct +{ + vu16 MDIVR; + vu16 EMPTY1; + vu16 PDIVR; + vu16 EMPTY2; + vu16 RSTR; + vu16 EMPTY3; + vu16 PLL2CR; + vu16 EMPTY4; + vu16 BOOTCR; + vu16 EMPTY5; + vu16 PWRCR; +} PCU_TypeDef; + +typedef volatile struct +{ + vu16 CRH; + vu16 EMPTY1; + vu16 CRL; + vu16 EMPTY2; + vu16 PRLH; + vu16 EMPTY3; + vu16 PRLL; + vu16 EMPTY4; + vu16 DIVH; + vu16 EMPTY5; + vu16 DIVL; + vu16 EMPTY6; + vu16 CNTH; + vu16 EMPTY7; + vu16 CNTL; + vu16 EMPTY8; + vu16 ALRH; + vu16 EMPTY9; + vu16 ALRL; +} RTC_TypeDef; + +typedef volatile struct +{ + vu16 ICAR; + vu16 EMPTY1; + vu16 ICBR; + vu16 EMPTY2; + vu16 OCAR; + vu16 EMPTY3; + vu16 OCBR; + vu16 EMPTY4; + vu16 CNTR; + vu16 EMPTY5; + vu16 CR1; + vu16 EMPTY6; + vu16 CR2; + vu16 EMPTY7; + vu16 SR; +} TIM_TypeDef; + +typedef volatile struct +{ + vu16 BR; + vu16 EMPTY1; + vu16 TxBUFR; + vu16 EMPTY2; + vu16 RxBUFR; + vu16 EMPTY3; + vu16 CR; + vu16 EMPTY4; + vu16 IER; + vu16 EMPTY5; + vu16 SR; + vu16 EMPTY6; + vu16 GTR; + vu16 EMPTY7; + vu16 TOR; + vu16 EMPTY8; + vu16 TxRSTR; + vu16 EMPTY9; + vu16 RxRSTR; +} UART_TypeDef; + +typedef volatile struct +{ + vu32 EP0R; + vu32 EP1R; + vu32 EP2R; + vu32 EP3R; + vu32 EP4R; + vu32 EP5R; + vu32 EP6R; + vu32 EP7R; + vu32 EP8R; + vu32 EP9R; + vu32 EP10R; + vu32 EP11R; + vu32 EP12R; + vu32 EP13R; + vu32 EP14R; + vu32 EP15R; + vu32 CNTR; + vu32 ISTR; + vu32 FNR; + vu32 DADDR; + vu32 BTABLE; +} USB_TypeDef; + +typedef volatile struct +{ + vu16 CR; + vu16 EMPTY1; + vu16 PR; + vu16 EMPTY2; + vu16 VR; + vu16 EMPTY3; + vu16 CNT; + vu16 EMPTY4; + vu16 SR; + vu16 EMPTY5; + vu16 MR; + vu16 EMPTY6; + vu16 KR; +} WDG_TypeDef; + +typedef volatile struct +{ + vu8 SR; + vu8 EMPTY1[7]; + vu8 CTRL; + vu8 EMPTY2[3]; + vu8 MRH; + vu8 EMPTY3[3]; + vu8 MRL; + vu8 EMPTY4[3]; + vu8 TRH; + vu8 EMPTY5[3]; + vu8 TRL; + vu8 EMPTY6[3]; + vu8 PRH; + vu8 EMPTY7[3]; + vu8 PRL; +} XTI_TypeDef; + + +/* IRQ vectors */ +typedef volatile struct +{ + vu32 T0TIMI_IRQHandler; + vu32 FLASH_IRQHandler; + vu32 RCCU_IRQHandler; + vu32 RTC_IRQHandler; + vu32 WDG_IRQHandler; + vu32 XTI_IRQHandler; + vu32 USBHP_IRQHandler; + vu32 I2C0ITERR_IRQHandler; + vu32 I2C1ITERR_IRQHandler; + vu32 UART0_IRQHandler; + vu32 UART1_IRQHandler; + vu32 UART2_IRQHandler; + vu32 UART3_IRQHandler; + vu32 BSPI0_IRQHandler; + vu32 BSPI1_IRQHandler; + vu32 I2C0_IRQHandler; + vu32 I2C1_IRQHandler; + vu32 CAN_IRQHandler; + vu32 ADC12_IRQHandler; + vu32 T1TIMI_IRQHandler; + vu32 T2TIMI_IRQHandler; + vu32 T3TIMI_IRQHandler; + vu32 EMPTY1[3]; + vu32 HDLC_IRQHandler; + vu32 USBLP_IRQHandler; + vu32 EMPTY2[2]; + vu32 T0TOI_IRQHandler; + vu32 T0OC1_IRQHandler; + vu32 T0OC2_IRQHandler; +} IRQVectors_TypeDef; + +/*===================================================================*/ + +/* Memory mapping */ + +#define RAM_BASE 0x20000000 + +#define FLASHR_BASE 0x40100000 +#define FLASHPR_BASE 0x4010DFB0 + +#define EXTMEM_BASE 0x60000000 +#define RCCU_BASE 0xA0000000 +#define PCU_BASE 0xA0000040 +#define APB1_BASE 0xC0000000 +#define APB2_BASE 0xE0000000 +#define EIC_BASE 0xFFFFF800 + +#define I2C0_BASE (APB1_BASE + 0x1000) +#define I2C1_BASE (APB1_BASE + 0x2000) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x5000) +#define UART2_BASE (APB1_BASE + 0x6000) +#define UART3_BASE (APB1_BASE + 0x7000) +#define CAN_BASE (APB1_BASE + 0x9000) +#define BSPI0_BASE (APB1_BASE + 0xA000) +#define BSPI1_BASE (APB1_BASE + 0xB000) +#define USB_BASE (APB1_BASE + 0x8800) + +#define XTI_BASE (APB2_BASE + 0x101C) +#define GPIO0_BASE (APB2_BASE + 0x3000) +#define GPIO1_BASE (APB2_BASE + 0x4000) +#define GPIO2_BASE (APB2_BASE + 0x5000) +#define ADC12_BASE (APB2_BASE + 0x7000) +#define TIM0_BASE (APB2_BASE + 0x9000) +#define TIM1_BASE (APB2_BASE + 0xA000) +#define TIM2_BASE (APB2_BASE + 0xB000) +#define TIM3_BASE (APB2_BASE + 0xC000) +#define RTC_BASE (APB2_BASE + 0xD000) +#define WDG_BASE (APB2_BASE + 0xE000) + +#define EMI_BASE (EXTMEM_BASE + 0x0C000000) + +/*===================================================================*/ + +/* IP data access */ + +#ifndef DEBUG + #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) + + #define APB1 ((APB_TypeDef *)APB1_BASE) + #define APB2 ((APB_TypeDef *)APB2_BASE+0x10) + + #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) + #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) + + #define CAN ((CAN_TypeDef *)CAN_BASE) + + #define EIC ((EIC_TypeDef *)EIC_BASE) + + #define EMI ((EMI_TypeDef *)EMI_BASE) + + #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) + #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) + + #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) + #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) + #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) + + #define I2C0 ((I2C_TypeDef *)I2C0_BASE) + #define I2C1 ((I2C_TypeDef *)I2C1_BASE) + + #define PCU ((PCU_TypeDef *)PCU_BASE) + + #define RCCU ((RCCU_TypeDef *)RCCU_BASE) + + #define RTC ((RTC_TypeDef *)RTC_BASE) + + #define TIM0 ((TIM_TypeDef *)TIM0_BASE) + #define TIM1 ((TIM_TypeDef *)TIM1_BASE) + #define TIM2 ((TIM_TypeDef *)TIM2_BASE) + #define TIM3 ((TIM_TypeDef *)TIM3_BASE) + + #define UART0 ((UART_TypeDef *)UART0_BASE) + #define UART1 ((UART_TypeDef *)UART1_BASE) + #define UART2 ((UART_TypeDef *)UART2_BASE) + #define UART3 ((UART_TypeDef *)UART3_BASE) + + #define USB ((USB_TypeDef *)USB_BASE) + + #define WDG ((WDG_TypeDef *)WDG_BASE) + + #define XTI ((XTI_TypeDef *)XTI_BASE) + + #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) + +#else /* DEBUG */ + + #ifdef _ADC12 + EXT ADC12_TypeDef *ADC12; + #endif + + #ifdef _APB + #ifdef _APB1 + EXT APB_TypeDef *APB1; + #endif + #ifdef _APB2 + EXT APB_TypeDef *APB2; + #endif + #endif + + #ifdef _BSPI + #ifdef _BSPI0 + EXT BSPI_TypeDef *BSPI0; + #endif + #ifdef _BSPI1 + EXT BSPI_TypeDef *BSPI1; + #endif + #endif + + #ifdef _CAN + EXT CAN_TypeDef *CAN; + #endif + + #ifdef _EIC + EXT EIC_TypeDef *EIC; + #endif + + #ifdef _EMI + EXT EMI_TypeDef *EMI; + #endif + + #ifdef _FLASH + EXT FLASHR_TypeDef *FLASHR; + EXT FLASHPR_TypeDef *FLASHPR; + #endif + + #ifdef _GPIO + #ifdef _GPIO0 + EXT GPIO_TypeDef *GPIO0; + #endif + #ifdef _GPIO1 + EXT GPIO_TypeDef *GPIO1; + #endif + #ifdef _GPIO2 + EXT GPIO_TypeDef *GPIO2; + #endif + #endif + + #ifdef _I2C + #ifdef _I2C0 + EXT I2C_TypeDef *I2C0; + #endif + #ifdef _I2C1 + EXT I2C_TypeDef *I2C1; + #endif + #endif + + #ifdef _PCU + EXT PCU_TypeDef *PCU; + #endif + + #ifdef _RCCU + EXT RCCU_TypeDef *RCCU; + #endif + + #ifdef _RTC + EXT RTC_TypeDef *RTC; + #endif + + #ifdef _TIM + #ifdef _TIM0 + EXT TIM_TypeDef *TIM0; + #endif + #ifdef _TIM1 + EXT TIM_TypeDef *TIM1; + #endif + #ifdef _TIM2 + EXT TIM_TypeDef *TIM2; + #endif + #ifdef _TIM3 + EXT TIM_TypeDef *TIM3; + #endif + #endif + + #ifdef _UART + #ifdef _UART0 + EXT UART_TypeDef *UART0; + #endif + #ifdef _UART1 + EXT UART_TypeDef *UART1; + #endif + #ifdef _UART2 + EXT UART_TypeDef *UART2; + #endif + #ifdef _UART3 + EXT UART_TypeDef *UART3; + #endif + #endif + + #ifdef _USB + EXT USB_TypeDef *USB; + #endif + + #ifdef _WDG + EXT WDG_TypeDef *WDG; + #endif + + #ifdef _XTI + EXT XTI_TypeDef *XTI; + #endif + + #ifdef _IRQVectors + EXT IRQVectors_TypeDef *IRQVectors; + #endif + +#endif /* DEBUG */ + +#endif /* __71x_map_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h new file mode 100644 index 000000000..39e2175f2 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_type.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Common data types +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef _71x_type_H +#define _71x_type_H + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +/*===================================================================*/ +typedef enum { FALSE = 0, TRUE = !FALSE } bool; +/*===================================================================*/ +typedef enum { RESET = 0, SET = !RESET } FlagStatus; +/*===================================================================*/ +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +/*===================================================================*/ +typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; +/*===================================================================*/ + +#endif /* _71x_type_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/eic.h b/Demo/ARM7_STR71x_IAR/Library/include/eic.h new file mode 100644 index 000000000..cbe149b56 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/eic.h @@ -0,0 +1,199 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : eic.h +* Author : MCD Application Team +* Date First Issued : 25/06/2003 +* Description : This file contains all the functions prototypes for the +* EIC software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __eic_H +#define __eic_H + +#include "71x_map.h" + +typedef enum +{ + T0TIMI_IRQChannel = 0, + FLASH_IRQChannel = 1, + RCCU_IRQChannel = 2, + RTC_IRQChannel = 3, + WDG_IRQChannel = 4, + XTI_IRQChannel = 5, + USBHP_IRQChannel = 6, + I2C0ITERR_IRQChannel = 7, + I2C1ITERR_IRQChannel = 8, + UART0_IRQChannel = 9, + UART1_IRQChannel = 10, + UART2_IRQChannel = 11, + UART3_IRQChannel = 12, + SPI0_IRQChannel = 13, + SPI1_IRQChannel = 14, + I2C0_IRQChannel = 15, + I2C1_IRQChannel = 16, + CAN_IRQChannel = 17, + ADC_IRQChannel = 18, + T1TIMI_IRQChannel = 19, + T2TIMI_IRQChannel = 20, + T3TIMI_IRQChannel = 21, + HDLC_IRQChannel = 25, + USBLP_IRQChannel = 26, + T0TOI_IRQChannel = 29, + T0OC1_IRQChannel = 30, + T0OC2_IRQChannel = 31 +} IRQChannel_TypeDef; + +typedef enum +{ + T0TIMI_FIQChannel = 0x00000001, + WDG_FIQChannel = 0x00000002, + WDGT0TIMI_FIQChannels = 0x00000003 +} FIQChannel_TypeDef; + +/******************************************************************************* +* Function Name : EIC_Init +* Description : Initialise the EIC using the load PC instruction +* (PC = PC +offset) +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EIC_Init(void); + +/******************************************************************************* +* Function Name : EIC_IRQConfig +* Description : Enable or Disable IRQ interrupts +* Input 1 : New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; +} + +/******************************************************************************* +* Function Name : EIC_FIQConfig +* Description : Enable or Disable FIQ interrupts +* Input 1 : New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; +} + +/******************************************************************************* +* Function Name : EIC_IRQChannelConfig +* Description : Configure the IRQ Channel +* Input 1 : IRQ channel name +* Input 2 : Channel New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; + else EIC->IER &= ~(0x0001 << IRQChannel); +} + +/******************************************************************************* +* Function Name : EIC_FIQChannelConfig +* Description : Configure the FIQ Channel +* Input 1 : FIQ channel name +* Input 2 : Channel New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, + FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->FIR |= FIQChannel; + else EIC->FIR &= ~FIQChannel; +} + +/******************************************************************************* +* Function Name : EIC_IRQChannelPriorityConfig +* Description : Configure the selected IRQ channel priority +* Input 1 : IRQ channel name +* Input 2 : IRQ channel priority +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) +{ + EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; +} + +/******************************************************************************* +* Function Name : EIC_CurrentPriorityLevelConfig +* Description : Change the current priority level of the srved IRQ routine +* Input 1 : New priority +* Output : None +* Return : None +*******************************************************************************/ +void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); + +/******************************************************************************* +* Function Name : EIC_CurrentPriorityLevelValue +* Description : Return the current priority level of the current served IRQ +* routine +* Input : None +* Output : None +* Return : The current priority level +*******************************************************************************/ +inline u8 EIC_CurrentPriorityLevelValue(void) +{ + return EIC->CIPR & 0xF; +} + +/******************************************************************************* +* Function Name : EIC_CurrentIRQChannelValue +* Description : Return the current served IRQ channel number +* Input 0 : None +* Output : None +* Return : The current served IRQ channel number +*******************************************************************************/ +inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) +{ + return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); +} + +/******************************************************************************* +* Function Name : EIC_CurrentFIQChannelValue +* Description : Return the current served FIQ channel number +* Input : None +* Output : None +* Return : The current served FIQ channel number +*******************************************************************************/ +inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) +{ + return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); +} + +/******************************************************************************* +* Function Name : EIC_FIPendingBitClear +* Description : Clear the FIQ pending bit +* Input 1 : FIQ channel +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) +{ + EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); +} + +#endif /* __eic_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/gpio.h b/Demo/ARM7_STR71x_IAR/Library/include/gpio.h new file mode 100644 index 000000000..2ea6decf6 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/gpio.h @@ -0,0 +1,126 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : gpio.h +* Author : MCD Application Team +* Date First Issued : 08/06/2003 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __gpio_H +#define __gpio_H + +#include "71x_map.h" + +typedef enum +{ + GPIO_HI_AIN_TRI, + GPIO_IN_TRI_TTL, + GPIO_IN_TRI_CMOS, + GPIO_IPUPD_WP, + GPIO_OUT_OD, + GPIO_OUT_PP, + GPIO_AF_OD, + GPIO_AF_PP +} GpioPinMode_TypeDef; + +#define GPIO_LSB 0x00 +#define GPIO_MSB 0x08 + +/******************************************************************************* +* Function Name : GPIO_Config +* Description : Configure the GPIO port pins +* Input 1 : GPIOx (x can be 0,1 or 2) the desired port +* Input 2 : Port_Pins : pins placements +* Input 3 : Pins Mode +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); + +/******************************************************************************* +* Function Name : GPIO_BitRead +* Description : Read the desired port pin value +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Output : None +* Return : The selected pin value +*******************************************************************************/ +inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) +{ + return (GPIOx->PD >> Port_Pin) & 0x0001; +} + +/******************************************************************************* +* Function Name : GPIO_ByteRead +* Description : Read the desired port Byte value +* Input 1 : Selected GPIO port +* Input 2 : GPIO_MSB or GPIO_LSB +* Output : None +* Return : The GPIO_MSB or GPIO_LSB of the selected PD register +*******************************************************************************/ +inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) +{ + return (u8)(GPIOx->PD >> Port_Byte); +} + +/******************************************************************************* +* Function Name : GPIO_WordRead +* Description : Read the desired port word value +* Input 1 : Selected GPIO port +* Output : None +* Return : The selected PD register value +*******************************************************************************/ +inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) +{ + return GPIOx->PD; +} + +/******************************************************************************* +* Function Name : GPIO_BitWrite +* Description : Set or reset the selected port pin +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Input 3 : bit value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); + +/******************************************************************************* +* Function Name : GPIO_ByteWrite +* Description : Write byte value to the selected PD register +* Input 1 : Selected GPIO port +* Input 2 : GPIO_MSB or GPIO_LSB +* Input 3 : Byte value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); + +/******************************************************************************* +* Function Name : GPIO_WordWrite +* Description : Write word value to the selected PD register +* Input 1 : Selected GPIO port +* Input 2 : Value +* Output : None +* Return : None +*******************************************************************************/ +inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) +{ + GPIOx->PD = Port_Val; +} + +#endif /* __gpio_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/pcu.h b/Demo/ARM7_STR71x_IAR/Library/include/pcu.h new file mode 100644 index 000000000..b36296330 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/pcu.h @@ -0,0 +1,193 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : pcu.h +* Author : MCD Application Team +* Date First Issued : 30/05/2003 +* Description : This file contains all the functions prototypes for the +* PCU software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __PCU_H +#define __PCU_H + +#include "71x_map.h" + +typedef enum +{ + PCU_WREN = 0x8000, + PCU_VROK = 0x1000 +} PCU_Flags; + +typedef enum +{ + PCU_STABLE, + PCU_UNSTABLE +} PCU_VR_Status; + +typedef enum +{ + PCU_MVR = 0x0008, + PCU_LPR = 0x0020 +} PCU_VR; + +typedef enum +{ + WFI_CLOCK2_16, + WFI_EXTERNAL +} WFI_CLOCKS; + +typedef enum +{ + PCU_SLOW, + PCU_STOP, + PCU_STANDBY +} LPM_MODES; + + +// VR_OK : Voltage Regulator OK +#define PCU_VROK_Mask 0x1000 + +// Main Voltage Regulator +#define PCU_MVR_Mask 0x0008 + +// Low Power Voltage Regulator +#define PCU_LPR_Mask 0x0020 + +// PCU register Write Enable Bit +#define PCU_WREN_Mask 0x8000 + +// Low Voltage Detector +#define PCU_LVD_Mask 0x0100 + +// Power Down Flag +#define PCU_PWRDWN_Mask 0x0040 + +// WFI Mode Clock Selection Bit +#define PCU_WFI_CKSEL_Mask 0x00000002 + +// Halt Mode Enable Bit +#define PCU_EN_HALT_Mask 0x00000800 + +// Halt Mode Flag +#define PCU_HALT_Mask 0x0002 + +// Stop Mode Enable Bit +#define PCU_STOP_EN_Mask 0x00000400 + +// Low Power Regulator in Wait For interrupt Mode +#define PCU_LPRWFI_Mask 0x0020 + +// Low Power Mode in Wait For interrupt Mode +#define PCU_LPOWFI_Mask 0x00000001 + +// Software Reset Enable +#define PCU_SRESEN_Mask 0x00000001 + + +/******************************************************************************* +* Function Name : PCU_MVRStatus +* Description : This routine is used to check the Main Voltage Regulator +* : NewState. +* Input : None +* Return : STABLE, UNSTABLE +*******************************************************************************/ +inline PCU_VR_Status PCU_MVRStatus ( void ) +{ + return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; +} + +/******************************************************************************* +* Function Name : PCU_FlagStatus +* Description : This routine is used to return the PCU register flag +* Input 1 : The flag to get +* Return : RESET, SET +*******************************************************************************/ +inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) +{ + return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : PCU_VRConfig +* Description : This routine is used to configure PCU voltage regultors +* Input 1 : MVR : Main voltage Regulator + LPR : Low Power Regulator +* Input 2 : ENABLE : Enable the Voltage Regulator + DISABLE: Disable ( ByPass ) the VR +* Return : None +*******************************************************************************/ +void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); + +/******************************************************************************* +* Function Name : PCU_VRStatus +* Description : This routine is used to get the PCU voltage regultors status +* Input : MVR : Main voltage Regulator + LPR : Low Power Regulator +* Return : ENABLE : Enable the Voltage Regulator + DISABLE: Disable ( ByPass ) the VR +*******************************************************************************/ +inline FunctionalState PCU_VRStatus ( PCU_VR xVR ) +{ + return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; +} + +/******************************************************************************* +* Function Name : PCU_LVDDisable +* Description : This routine is used to disable the Low Voltage Detector. +* Input : None +* Return : None +*******************************************************************************/ +inline void PCU_LVDDisable ( void ) +{ + PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register + PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag +} + +/******************************************************************************* +* Function Name : PCU_LVDStatus +* Description : This routine is used to get the LVD NewState. +* Input : None +* Return : ENABLE, DISABLE +*******************************************************************************/ +inline FunctionalState PCU_LVDStatus ( void ) +{ + return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; +} + +/******************************************************************************* +* Function Name : PCU_WFIEnter +* Description : This routine is used to force the Device to enter in WFI mode +* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode +* EXTERNAL : external clock as system clock for WFI mode +* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode +* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode +* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode +* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode +* Return : None +*******************************************************************************/ +void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); + +/******************************************************************************* +* Function Name : PCU_LPMEnter +* Description : This routine is used to force the Device to enter low +* power mode +* Input : SLOW : Slow Mode + STOP : Stop Mode + HALT : Halt Mode +* Return : None +*******************************************************************************/ +void PCU_LPMEnter ( LPM_MODES Xmode); + +#endif // __PCU_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/rccu.h b/Demo/ARM7_STR71x_IAR/Library/include/rccu.h new file mode 100644 index 000000000..86c76130a --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/rccu.h @@ -0,0 +1,319 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : rccu.h +* Author : MCD Application Team +* Date First Issued : 28/07/2003 +* Description : This file contains all the functions prototypes for the +* RCCU software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __RCCU_H +#define __RCCU_H + +#include "71x_map.h" + +typedef enum { + RCCU_DEFAULT=0x00, + RCCU_RCLK_2 =0x01, + RCCU_RCLK_4 =0x02, + RCCU_RCLK_8 =0x03 + } RCCU_Clock_Div; + +typedef enum { + RCCU_PLL1_Output, + RCCU_CLOCK2_16, + RCCU_CLOCK2, + RCCU_RTC_CLOCK + } RCCU_RCLK_Clocks; + + + typedef enum { + RCCU_PLL1_Mul_12=0x01, + RCCU_PLL1_Mul_16=0x03, + RCCU_PLL1_Mul_20=0x00, + RCCU_PLL1_Mul_24=0x02 + } RCCU_PLL1_Mul; + +typedef enum { + RCCU_PLL2_Mul_12=0x01, + RCCU_PLL2_Mul_16=0x03, + RCCU_PLL2_Mul_20=0x00, + RCCU_PLL2_Mul_28=0x02 + } RCCU_PLL2_Mul; + +typedef enum { + RCCU_Div_1=0x00, + RCCU_Div_2=0x01, + RCCU_Div_3=0x02, + RCCU_Div_4=0x03, + RCCU_Div_5=0x04, + RCCU_Div_6=0x05, + RCCU_Div_7=0x06 + } RCCU_PLL_Div; + +typedef enum { + RCCU_PLL2_Output = 0x01, + RCCU_USBCK = 0x00 + } RCCU_USB_Clocks; + +typedef enum { + RCCU_CLK2, + RCCU_RCLK, + RCCU_MCLK, + RCCU_PCLK, + RCCU_FCLK + } RCCU_Clocks; + +typedef enum { + RCCU_PLL1_LOCK_IT = 0x0080, + RCCU_CKAF_IT = 0x0100, + RCCU_CK2_16_IT = 0x0200, + RCCU_STOP_IT = 0x0400 + } RCCU_Interrupts; + +typedef enum { + RCCU_PLL1_LOCK = 0x0002, + RCCU_CKAF_ST = 0x0004, + RCCU_PLL1_LOCK_I = 0x0800, + RCCU_CKAF_I = 0x1000, + RCCU_CK2_16_I = 0x2000, + RCCU_STOP_I = 0x4000 + } RCCU_Flags; + +typedef enum { + RCCU_ExternalReset = 0x00000000, + RCCU_SoftwareReset = 0x00000020, + RCCU_WDGReset = 0x00000040, + RCCU_RTCAlarmReset = 0x00000080, + RCCU_LVDReset = 0x00000200, + RCCU_WKPReset = 0x00000400 + }RCCU_ResetSources; + + +#define RCCU_Div2_Mask 0x00008000 +#define RCCU_Div2_Index 0x0F +#define RCCU_FACT_Mask 0x0003 + +#define RCCU_FACT1_Mask 0x0003 + +#define RCCU_FACT2_Mask 0x0300 +#define RCCU_FACT2_Index 0x08 + +#define RCCU_MX_Mask 0x00000030 +#define RCCU_MX_Index 0x04 + +#define RCCU_DX_Mask 0x00000007 + +#define RCCU_FREEN_Mask 0x00000080 + +#define RCCU_CSU_CKSEL_Mask 0x00000001 + +#define RCCU_CK2_16_Mask 0x00000008 + +#define RCCU_CKAF_SEL_Mask 0x00000004 + +#define RCCU_LOCK_Mask 0x00000002 + +#define RCCU_USBEN_Mask 0x0100 +#define RCCU_USBEN_Index 0x08 +#define RCCU_ResetSources_Mask 0x000006E0 + +// RTC Oscillator Frequency value = 32 768 Hz +#define RCCU_RTC_Osc 32768 + + +/******************************************************************************* +* Function Name : RCCU_Div2Config +* Description : Enables/Disables the clock division by two +* Input : NewState : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void RCCU_Div2Config ( FunctionalState NewState ) +{ + if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; + else RCCU->CFR &= ~RCCU_Div2_Mask; +} + +/******************************************************************************* +* Function Name : RCCU_Div2Status +* Description : Gets the Div2 Flag status +* Input : None +* Input : FlagStatus +* Return : None +*******************************************************************************/ +inline FlagStatus RCCU_Div2Status ( void ) +{ + return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : RCCU_MCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* MCLK clock for the CPU +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; +} + +/******************************************************************************* +* Function Name : RCCU_FCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* FCLK clock for the APB1 fast peripherals (PCLK1). +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, +* RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; +} + +/******************************************************************************* +* Function Name : RCCU_PCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* PCLK clock for the APB2 peripherals (PCLK2). +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, +* RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); +} + +/******************************************************************************* +* Function Name : RCCU_PLL1Config +* Description : Configures the PLL1 div & mul factors. +* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 +* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, +* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 +* Return : None +*******************************************************************************/ +void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); + +/******************************************************************************* +* Function Name : RCCU_PLL2Config +* Description : Configures the PLL2 div & mul factors. +* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 +* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 +* Return : None +*******************************************************************************/ +void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); + +/******************************************************************************* +* Function Name : RCCU_RCLKSourceConfig +* Description : Selects the RCLK source clock +* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 +* Return : None +*******************************************************************************/ +void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); + +/******************************************************************************* +* Function Name : RCCU_RCLKClockSource +* Description : Returns the current RCLK source clock +* Input : None +* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 +*******************************************************************************/ +RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); + +/******************************************************************************* +* Function Name : RCCU_USBCLKConfig +* Description : Selects the USB source clock +* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK +* Return : None +*******************************************************************************/ +inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) +{ + PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); +} + +/******************************************************************************* +* Function Name : RCCU_USBClockSource +* Description : Gets the USB source clock +* Input : None +* Return : RCCU_USB_Clocks +*******************************************************************************/ +RCCU_USB_Clocks RCCU_USBClockSource ( void ); + +/******************************************************************************* +* Function Name : RCCU_FrequencyValue +* Description : Calculates & Returns any internal RCCU clock freuqency +* passed in parametres +* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, +* RCCU_PCLK, RCCU_FCLK +* Return : u32 +*******************************************************************************/ +u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); + +/******************************************************************************* +* Function Name : RCCU_ITConfig +* Description : Configures the RCCU interrupts +* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, +* RCCU_PLL1_LOCK_IT +* Return : None +*******************************************************************************/ +inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) +{ + if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; +} + +/******************************************************************************* +* Function Name : RCCU_FlagStatus +* Description : Checks the RCCU clock flag register status +* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK +* Return : FlagStatus : SET or RESET +*******************************************************************************/ +inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) +{ + return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : RCCU_FlagClear +* Description : Clears a specified flag in the RCCU registers +* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK +* Return : None +*******************************************************************************/ +inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) +{ + RCCU->CFR |= RCCU_IT; +} + +/******************************************************************************* +* Function Name : RCCU_ResetSources +* Description : Return the source of the system reset +* Input : None +* Return : The reset source +*******************************************************************************/ +inline RCCU_ResetSources RCCU_ResetSource () +{ + + switch(RCCU->CFR & RCCU_ResetSources_Mask) + { + case 0x00000020: return RCCU_SoftwareReset; + case 0x00000040: return RCCU_WDGReset; + case 0x00000080: return RCCU_RTCAlarmReset; + case 0x00000200: return RCCU_LVDReset; + case 0x00000400: return RCCU_WKPReset; + default : return RCCU_ExternalReset; + } +} + +#endif // __RCCU_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/tim.h b/Demo/ARM7_STR71x_IAR/Library/include/tim.h new file mode 100644 index 000000000..fbb3ff080 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/tim.h @@ -0,0 +1,345 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : tim.h +* Author : MCD Application Team +* Date First Issued : 08/09/2003 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __TIM_H +#define __TIM_H + +#include "71x_map.h" + +typedef enum { TIM_EXTERNAL, + TIM_INTERNAL + } TIM_Clocks; + +typedef enum { TIM_RISING, + TIM_FALLING + } TIM_Clock_Edges; + +typedef enum { TIM_CHANNEL_A, + TIM_CHANNEL_B + } TIM_Channels; + +typedef enum { TIM_WITH_IT, + TIM_WITHOUT_IT + } TIM_IT_Mode; + +typedef enum { TIM_TIMING, + TIM_WAVE + } TIM_OC_Modes; + +typedef enum { TIM_HIGH, + TIM_LOW + } TIM_Logic_Levels; + +typedef enum { TIM_START, + TIM_STOP, + TIM_CLEAR + } TIM_CounterOperations; + +typedef enum { TIM_ICFA = 0x8000, + TIM_OCFA = 0x4000, + TIM_TOF = 0x2000, + TIM_ICFB = 0x1000, + TIM_OCFB = 0x0800 + } TIM_Flags; + +typedef struct { u16 Pulse; + u16 Period; + } PWMI_parameters; + +#define TIM_ECKEN_Mask 0x0001 +#define TIM_EXEDG_Mask 0x0002 + +#define TIM_IEDGA_Mask 0x0004 +#define TIM_IEDGB_Mask 0x0008 + +#define TIM_PWM_Mask 0x0010 + +#define TIM_OMP_Mask 0x0020 + +#define TIM_OCAE_Mask 0x0040 +#define TIM_OCBE_Mask 0x0080 + +#define TIM_OLVLA_Mask 0x0100 +#define TIM_OLVLB_Mask 0x0200 + +#define TIM_FOLVA_Mask 0x0400 +#define TIM_FOLVB_Mask 0x0800 + +#define TIM_PWMI_Mask 0x4000 + +#define TIM_EN_Mask 0x8000 + +#define TIM_OCBIE_mask 0x0800 +#define TIM_ICBIE_Mask 0x1000 +#define TIM_TOE_Mask 0x2000 +#define TIM_ICAIE_Mask 0x8000 +#define TIM_OCAIE_mask 0x4000 + +#define TIM_ICA_IT 0x8000 // Input Capture Channel A +#define TIM_OCA_IT 0x4000 // Output Compare Channel A +#define TIM_TO_IT 0x2000 // Timer OverFlow +#define TIM_ICB_IT 0x1000 // Input Capture Channel B +#define TIM_OCB_IT 0x0800 // Input Capture Channel A + + +/******************************************************************************* +* Function Name : TIM_Init +* Description : This routine is used to Initialize the TIM peripheral +* Input : TIM Timer to Initialize +* Return : None +*******************************************************************************/ +void TIM_Init( TIM_TypeDef *TIMx ); + +/******************************************************************************* +* Function Name : TIM_ClockSourceConfig +* Description : This routine is used to configure the TIM clock source +* Input : (1) TIM Timer +* : (2) TIM_Clocks : Specifies the TIM source clock +* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency +* divided by the prescaler value. +* - TIM_EXTERNAL : The TIM is clocked by an external Clock +* Return : None +*******************************************************************************/ +inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) +{ + if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; +} + +/******************************************************************************* +* Function Name : TIM_ClockSourceValue +* Description : This routine is used to get the TIM clock source +* Input : TIM Timer +* Return : TIM_Clocks : Specifies the TIM source clock +* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency +* divided by the prescaler value. +* - TIM_EXTERNAL : The TIM is clocked by an external Clock +*******************************************************************************/ +inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) +{ + return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIM prescaler value +* ( using an internal clock ) +* Input : (1) TIM Timer +* : (2) Prescaler ( u8 ) +* Return : None +*******************************************************************************/ +inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) +{ + TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerValue +* Description : This routine is used to get the TIM prescaler value +* ( when using using an internal clock ) +* Input : TIM Timer +* Return : Prescaler ( u8 ) +*******************************************************************************/ +inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_ClockLevelConfig +* Description : This routine is used to configure the TIM clock level +* ( using an external clock ) +* Input : TIM Timer +* : TIM_Clock_Edges : Specifies the active adge of the external clock +* - TIM_RISING : The rising edge +* - TIM_FALLING : The falling edge +* Return : None +*******************************************************************************/ +inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) +{ + if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; +} + +/******************************************************************************* +* Function Name : TIM_ClockLevelValue +* Description : This routine is used to get the TIM clock level +* Input : TIM Timer +* Output : TIM_Clock_Edges : Specifies the active adge of the external clock +* - TIM_RISING : The rising edge +* - TIM_FALLING : The falling edge +*******************************************************************************/ +inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) +{ + return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; +} + +/******************************************************************************* +* Function Name : TIM_ICAPModeConfig +* Description : This routine is used to configure the input capture feature +* Input : (1) TIM Timer +* : (2) Input Capture Channel ( Channel_A or Channel_B ) +* : (3) Active Edge : Rising edge or Falling edge. +* Output : None +*******************************************************************************/ +void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, + TIM_Channels Xchannel, + TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_ICAPValue +* Description : This routine is used to get the Input Capture value +* Input : (1) TIM Timer +* : (2) Input Capture Channel ( Channel_A or Channel_B ) +* Output : None +*******************************************************************************/ +inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) +{ + return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; +} + +/******************************************************************************* +* Function Name : TIM_OCMPModeConfig +* Description : This routine is used to configure the output compare feature +* Input : (1) TIM Timer +* : (2) OCMP Channel ( Channel_A or Channel_B ) +* : (3) Pulse Length +* : (4) OC_Mode : output wave, or only timing. +* : (5) Level : Rising edge or Falling edge after the == +* Output : None +*******************************************************************************/ +void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, + TIM_Channels Xchannel, + u16 XpulseLength, + TIM_OC_Modes Xmode, + TIM_Logic_Levels Xlevel ); + +/******************************************************************************* +* Function Name : TIM_OPModeConfig +* Description : This routine is used to configure the one pulse mode +* Input : (1) TIM Timer +* : (3) XpulseLength : Length of the pulse +* : (4) Level1 : Level during the pulse +* : (5) Level2 : Level after the pulse +* : (6) Activation Edge : High or Low on ICAP A +* Output : None +*******************************************************************************/ +void TIM_OPModeConfig ( TIM_TypeDef *TIMx, + u16 XpulseLength, + TIM_Logic_Levels XLevel1, + TIM_Logic_Levels XLevel2, + TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_PWMOModeConfig +* Description : This routine is used to configure the PWM in output mode +* Input : (1) TIM Timer +* : (2) DutyCycle : u16 +* : (3) Level 1 : During the Duty Cycle +* : (4) Level 2 : During the after the pulse +* : (5) Full period : u16 +* Output : None +*******************************************************************************/ +void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, + u16 XDutyCycle, + TIM_Logic_Levels XLevel1, + u16 XFullperiod, + TIM_Logic_Levels XLevel2 + ); + +/******************************************************************************* +* Function Name : TIM_PWMInputConfig +* Description : This routine is used to configure the PWM in input mode +* Input : (1) TIM Timer +* : (2) First Activation Edge +* Output : None +*******************************************************************************/ +void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_PWMIValue +* Description : This routine is used to get the PWMI values +* Input : (1) TIM Timer +* Output : PWMI_parameters : - u16 Dyty cycle + - u16 Full period +*******************************************************************************/ +PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); + +/******************************************************************************* +* Function Name : TIM_CounterConfig +* Description : This routine is used to start/stop and clear the selected +* timer counter +* Input : (1) TIM Timer +* : (2) TIM_CounterOperations + TIM_START Enables or resumes the counter +* TIM_STOP Stops the TIM counter +* TIM_CLEAR Set the TIM counter value to FFFCh +* Output : None +*******************************************************************************/ +void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : This routine is used to configure the TIM IT +* Input : (1) TIM Timer +* : (2) TIM interrupt +* : (2) ENABLE / DISABLE +* Output : None +*******************************************************************************/ +inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) +{ + if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; +} + +/******************************************************************************* +* Function Name : TIM_FlagStatus +* Description : This routine is used to check whether a Flag is Set. +* Input : (1) TIM Timer +* : (2) The TIM FLag +* Output : Flag NewState +*******************************************************************************/ +inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) +{ + return (TIMx->SR & Xflag) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : TIM_FlagClear +* Description : This routine is used to clear Flags. +* Input : (1) TIM Timer +* : (2) The TIM FLag +* Output : None +*******************************************************************************/ +inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) +{ + TIMx->SR &= ~Xflag; +} + +/******************************************************************************* +* Function Name : TIM_CounterValue +* Description : This routine returns the timer counter value. +* Input : TIM Timer +* Output : The counter value +*******************************************************************************/ +inline u16 TIM_CounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} +#endif // __TIM_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/uart.h b/Demo/ARM7_STR71x_IAR/Library/include/uart.h new file mode 100644 index 000000000..7ca40bc4e --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/uart.h @@ -0,0 +1,390 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : uart.h +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef _UART_H +#define _UART_H + +#include "71x_map.h" +#include "rccu.h" + +typedef enum +{ + UART_RxFIFO, + UART_TxFIFO +} UARTFIFO_TypeDef; + +typedef enum +{ + UART_EVEN_PARITY = 0x0000, + UART_ODD_PARITY = 0x0020, + UART_NO_PARITY +} UARTParity_TypeDef; + +typedef enum +{ + UART_0_5_StopBits = 0x00, + UART_1_StopBits = 0x08, + UART_1_5_StopBits = 0x10, + UART_2_StopBits = 0x18 +} UARTStopBits_TypeDef; + +typedef enum +{ + UARTM_8D = 0x01, + UARTM_7D_P = 0x03, + UARTM_9D = 0x04, + UARTM_8D_W = 0x05, + UARTM_8D_P = 0x07 +} UARTMode_TypeDef; + + +#define DUMMY 0 + +// UART flags definition +#define UART_TxFull 0x0200 +#define UART_RxHalfFull 0x0100 +#define UART_TimeOutIdle 0x0080 +#define UART_TimeOutNotEmpty 0x0040 +#define UART_OverrunError 0x0020 +#define UART_FrameError 0x0010 +#define UART_ParityError 0x0008 +#define UART_TxHalfEmpty 0x0004 +#define UART_TxEmpty 0x0002 +#define UART_RxBufFull 0x0001 + +// CR regiter bit definition +#define UART_FIFOEnableBit 10 +#define UART_RxEnableBit 8 +#define UART_RunBit 7 +#define UART_LoopBackBit 6 +#define UART_ParityOddBit 5 +#define UART_StopBits 3 + +// Stop bits definition +#define UART_05StopBits 0x00 +#define UART_1StopBit (0x01<<3) +#define UART_15StopBits (0x02<<3) +#define UART_2StopBits (0x03<<3) + +// Modes definition +#define UART_8BitsData 0x01 +#define UART_7BitsData 0x03 +#define UART_9BitsData 0x04 +#define UART_8BitsDataWakeUp 0x05 +#define UART_8BitsDataParity 0x07 + +/******************************************************************************* +* Function Name : UART_Init +* Description : This function initializes the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef *UARTx); + +/******************************************************************************* +* Function Name : UART_ModeConfig +* Description : This function configures the mode of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) +{ + UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; +} + +/******************************************************************************* +* Function Name : UART_BaudRateConfig +* Description : This function configures the baud rate of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Output : None +* Return : None +*******************************************************************************/ +void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); + +/******************************************************************************* +* Function Name : UART_ParityConfig +* Description : This function configures the data parity of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The parity type +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) +{ + UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; +} + +/******************************************************************************* +* Function Name : UART_StopBitsConfig +* Description : This function configures the number of stop bits of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The number of stop bits +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) +{ + UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; +} + +/******************************************************************************* +* Function Name : UART_Config +* Description : This function configures the baudrate, the mode, the data +* parity and the number of stop bits of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Input 3 : The parity type +* Input 4 : The number of stop bits +* Input 5 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, + UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); + +/******************************************************************************* +* Function Name : UART_ItConfig +* Description : This function enables or disables the interrupts of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The new interrupt flag +* Input 3 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_FifoConfig +* Description : This function enables or disables the Rx and Tx FIFOs of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_FifoReset +* Description : This function resets the Rx and the Tx FIFOs of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : RxFIFO or TxFIFO +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : This function enables or disables the loop back mode of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_TimeOutPeriodConfig +* Description : This function configure the Time Out Period. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The time-out period value +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) +{ + UARTx->TOR = TimeOutPeriod; +} + +/******************************************************************************* +* Function Name : UART_GuardTimeConfig +* Description : This function configure the Guard Time. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The guard time value +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) +{ + UARTx->GTR = GuardTime; +} + +/******************************************************************************* +* Function Name : UART_RxConfig +* Description : This function enable and disable the UART data reception. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_OnOffConfig +* Description : This function sets On/Off the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_ByteSend +* Description : This function sends a data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data byte to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); + +/******************************************************************************* +* Function Name : UART_9BitByteSend +* Description : This function sends a 9 bits data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); + +/******************************************************************************* +* Function Name : UART_DataSend +* Description : This function sends several data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length in bytes +* Output : None +* Return : None +*******************************************************************************/ +void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); + +/******************************************************************************* +* Function Name : UART_9BitDataSend +* Description : This function sends several 9 bits data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); + +/******************************************************************************* +* Function Name : UART_StringSend +* Description : This function sends a string to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the string to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_StringSend(UART_TypeDef *UARTx, u8 *String); + +/******************************************************************************* +* Function Name : UART_ByteReceive +* Description : This function gets a data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_9BitByteReceive +* Description : This function gets a 9 bits data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_DataReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_9BitDataReceive +* Description : This function gets 9 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_StringReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the string will be stored +* Output : None +* Return : None +*******************************************************************************/ +u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); + +/******************************************************************************* +* Function Name : UART_FlagStatus +* Description : This function gets the flags status of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +inline u16 UART_FlagStatus(UART_TypeDef *UARTx) +{ + return UARTx->SR; +} + +#ifdef USE_SERIAL_PORT +/******************************************************************************* +* Function Name : sendchar +* Description : This function sends a character to the selected UART. +* Input 1 : A pointer to the character to send. +* Output : None +* Return : None +*******************************************************************************/ +void sendchar( char *ch ); +#endif /* USE_SERIAL_PORT */ + +#endif /* _UART_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/wdg.h b/Demo/ARM7_STR71x_IAR/Library/include/wdg.h new file mode 100644 index 000000000..2a592ef79 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/include/wdg.h @@ -0,0 +1,129 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : wdg.h +* Author : MCD Application Team +* Date First Issued : 25/08/2003 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __WDG_H +#define __WDG_H + +#include "71x_map.h" +#include "rccu.h" + +/******************************************************************************* +* Function Name : WDG_Enable +* Description : Enable the Watchdog Mode +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_Enable ( void ) +{ + WDG->CR |= 0x01; +} + +/******************************************************************************* +* Function Name : WDG_CntRefresh +* Description : Refresh and update the WDG counter to avoid a system reset. +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_CntRefresh ( void ) +{ + //write the first value in the key register + WDG->KR = 0xA55A; + //write the consecutive value + WDG->KR = 0x5AA5; +} + +/******************************************************************************* +* Function Name : WDG_PrescalerConfig +* Description : Set the counter prescaler value. +* Divide the counter clock by (Prescaler + 1) +* Input : Prescaler data value (8 bit) +* Return : None +*******************************************************************************/ +inline void WDG_PrescalerConfig ( u8 Prescaler ) +{ + WDG->PR = Prescaler; +} + +/******************************************************************************* +* Function Name : WDG_CntReloadUpdate +* Description : Update the counter pre-load value. +* Input : Pre-load data value (16 bit) +* Return : None +*******************************************************************************/ +inline void WDG_CntReloadUpdate ( u16 PreLoadValue ) +{ + WDG->VR = PreLoadValue; +} + +/******************************************************************************* +* Function Name : WDG_PeriodValueConfig +* Description : Set the prescaler and counter reload value based on the +* time needed +* Input : Amount of time (us) needed, peripheral clock2 value +* Return : None +*******************************************************************************/ +void WDG_PeriodValueConfig ( u32 Time ); + +/******************************************************************************* +* Function Name : WDG_CntOnOffConfig +* Description : Start or stop the free auto-reload timer to countdown. +* Input : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void WDG_CntOnOffConfig ( FunctionalState NewState ) +{ + if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; +} + +/******************************************************************************* +* Function Name : WDG_ECITConfig +* Description : Enable or Disable the end of count interrupt +* Input : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void WDG_ECITConfig (FunctionalState NewState) +{ + if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; +} + +/******************************************************************************* +* Function Name : WDG_ECFlagClear +* Description : Clear the end of count flag +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_ECFlagClear ( void ) +{ + WDG->SR = 0x0000; +} + +/******************************************************************************* +* Function Name : WDG_ECStatus +* Description : Return the end of count status +* Input : None +* Return : NewState value +*******************************************************************************/ +inline u16 WDG_ECStatus ( void ) +{ + return WDG->SR; +} + +#endif // __WDG_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/rccu.c b/Demo/ARM7_STR71x_IAR/Library/rccu.c new file mode 100644 index 000000000..70e0aac1c --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/rccu.c @@ -0,0 +1,183 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : rccu.c +* Author : MCD Application Team +* Date First Issued : 07/28/2003 +* Description : This file provides all the RCCU software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "rccu.h" + +/******************************************************************************* +* Function Name : RCCU_PLL1Config +* Description : Configures the PLL1 div & mul factors. +* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, +* RCCU_PLL1_Mul_24 ) +* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) +* Return : None +*******************************************************************************/ +void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) +{ + u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); + RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; +} + +/******************************************************************************* +* Function Name : RCCU_PLL2Config +* Description : Configures the PLL2 div & mul factors. +* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, +* RCCU_Mul_PLL2_28 ) +* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) +* Return : None +*******************************************************************************/ +void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) +{ + u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); + PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); +} + +/******************************************************************************* +* Function Name : RCCU_RCLKSourceConfig +* Description : Selects the RCLK source clock +* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) +* Return : None +*******************************************************************************/ +void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) +{ + switch ( New_Clock ) + { + case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag + RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; + // Set the CK2_16 Bit in the CFR + RCCU->CFR |= RCCU_CK2_16_Mask; + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // switch off the PLL1 + RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ + |0x00000003) & ~RCCU_FREEN_Mask; + break;} + case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR + RCCU->CFR &= ~RCCU_CK2_16_Mask; + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // switch off the PLL1 + RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ + |0x00000003) & ~RCCU_FREEN_Mask; + break;} + case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR + RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; + // Waits the PLL1 to lock if DX bits are different from '111' + // If all DX bit are set the PLL lock flag in meaningless + if (( RCCU->PLL1CR & 0x0007 ) != 7) + while(!(RCCU->CFR & RCCU_LOCK_Mask)); + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // Select The CSU_CKSEL + RCCU->CFR |= RCCU_CSU_CKSEL_Mask; + break;} + case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; + break;} + } +} + +/******************************************************************************* +* Function Name : RCCU_RCLKClockSource +* Description : Returns the current RCLK source clock +* Input : None +* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK +*******************************************************************************/ +RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) +{ + if ((RCCU->CCR & 0x04)==0x04) + return RCCU_RTC_CLOCK; + + else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) + return RCCU_CLOCK2_16; + + else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) + return RCCU_PLL1_Output; + + else + return RCCU_CLOCK2; +} + +/******************************************************************************* +* Function Name : RCCU_USBClockSource +* Description : Gets the RCLK source clock +* Input : None +* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) +*******************************************************************************/ +RCCU_USB_Clocks RCCU_USBClockSource ( void ) +{ + if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) + return RCCU_PLL2_Output; + else return RCCU_USBCK; +} + +/******************************************************************************* +* Function Name : RCCU_FrequencyValue +* Description : Calculates & Returns any internal RCCU clock frequency +* passed in parametres +* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) +* Return : u32 +*******************************************************************************/ +u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) +{ + u32 Tmp; + u8 Div, Mul; + RCCU_RCLK_Clocks CurrentRCLK; + + Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; + + if ( Internal_Clk == RCCU_CLK2 ) + { + Div = 1; + Mul = 1; + } + else + { CurrentRCLK = RCCU_RCLKClockSource (); + switch ( CurrentRCLK ){ + case RCCU_CLOCK2_16 : Div = 16; + Mul = 1; + break; + case RCCU_CLOCK2 : Div = 1; + Mul = 1; + break; + case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; + switch ( Mul ) + {case 0: Mul = 20; break; + case 1: Mul = 12; break; + case 2: Mul = 28; break; + case 3: Mul = 16; break; + } + Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; + break;} + case RCCU_RTC_CLOCK : Mul = 1; + Div = 1; + Tmp = RCCU_RTC_Osc; + break;}} + + switch ( Internal_Clk ){ + case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; + break;} + case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; + break;} + case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; + break;}} + + return (Tmp * Mul) / Div; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/uart.c b/Demo/ARM7_STR71x_IAR/Library/uart.c new file mode 100644 index 000000000..c299345ca --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/uart.c @@ -0,0 +1,365 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : uart.c +* Author : MCD Application Team +* Date First Issued : 06/08/2003 +* Description : This file provides all the UART software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "uart.h" + +/******************************************************************************* +* Function Name : UART_Init +* Description : This function initializes the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef *UARTx) +{ + UARTx->IER = 0x00; + UARTx->CR = 0x00; + (void)UARTx->RxBUFR; + UARTx->RxRSTR = 0xFFFF; + UARTx->TxRSTR = 0xFFFF; +} + +/******************************************************************************* +* Function Name : UART_BaudRateConfig +* Description : This function configures the baud rate of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Output : None +* Return : None +*******************************************************************************/ +void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) +{ + UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate)); +} + +/******************************************************************************* +* Function Name : UART_Config +* Description : This function configures the baudrate, the mode, the data +* parity and the number of stop bits of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Input 3 : The parity type +* Input 4 : The number of stop bits +* Input 5 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, + UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) +{ + UART_ModeConfig(UARTx, Mode); + UART_BaudRateConfig(UARTx, BaudRate); + UART_ParityConfig(UARTx, Parity); + UART_StopBitsConfig(UARTx, StopBits); +} + +/******************************************************************************* +* Function Name : UART_ItConfig +* Description : This function enables or disables the interrupts of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The new interrupt flag +* Input 3 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; +} + +/******************************************************************************* +* Function Name : UART_FifoConfig +* Description : This function enables or disables the Rx and Tx FIFOs of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; +} + +/******************************************************************************* +* Function Name : UART_FifoReset +* Description : This function resets the Rx and the Tx FIFOs of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : UART_RxFIFO or UART_TxFIFO +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) +{ + if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : This function enables or disables the loop back mode of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; +} + +/******************************************************************************* +* Function Name : UART_RxConfig +* Description : This function enables or disables the UART data reception. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; +} + +/******************************************************************************* +* Function Name : UART_OnOffConfig +* Description : This function sets On/Off the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; +} + +/******************************************************************************* +* Function Name : UART_ByteSend +* Description : This function sends a data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data byte to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) +{ + if (UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. + else // if FIFO DISABLED + while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty + UARTx->TxBUFR = *Data; +} + +/******************************************************************************* +* Function Name : UART_9BitByteSend +* Description : This function sends a 9 bits data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) +{ + if(UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. + else // if FIFO DISABLED + while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty + UARTx->TxBUFR = *Data; +} + +/******************************************************************************* +* Function Name : UART_DataSend +* Description : This function sends several data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length in bytes +* Output : None +* Return : None +*******************************************************************************/ +void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) +{ + while(DataLength--) + { + UART_ByteSend(UARTx,Data); + Data++; + } +} + +/******************************************************************************* +* Function Name : UART_9BitDataSend +* Description : This function sends several 9 bits data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) +{ + while(DataLength--) + { + UART_9BitByteSend(UARTx,Data); + Data++; + } +} + +/******************************************************************************* +* Function Name : UART_StringSend +* Description : This function sends a string to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the string to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_StringSend(UART_TypeDef *UARTx, u8 *String) +{ + u8 *Data=String; + while(*Data != '\0') + UART_ByteSend(UARTx, Data++); + *Data='\0'; + UART_ByteSend(UARTx, Data); +} + +/******************************************************************************* +* Function Name : UART_ByteReceive +* Description : This function gets a data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) +{ + u16 wStatus; + UARTx->TOR=TimeOut;// reload the Timeout counter + while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_9BitByteReceive +* Description : This function gets a 9 bits data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) +{ + u16 wStatus; + UARTx->TOR=TimeOut;// reload the Timeout counter + while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_DataReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) +{ + u16 wStatus; + while(DataLength--) + wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_9BitDataReceive +* Description : This function gets 9 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) +{ + u16 wStatus; + while(DataLength--) + wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_StringReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the string will be stored +* Output : The received string +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) +{ + u8 *pSTRING=Data; + u16 wStatus; + do + { + while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR + } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); + *(pSTRING - 1)='\0'; + return wStatus; +} + +#ifdef USE_SERIAL_PORT +/******************************************************************************* +* Function Name : sendchar +* Description : This function sends a character to the selected UART. +* Input 1 : A pointer to the character to send. +* Output : None +* Return : None +*******************************************************************************/ +void sendchar( char *ch ) +{ + #ifdef USE_UART0 + #define UARTx UART0 + #endif /* Use_UART0 */ + + #ifdef USE_UART1 + #define UARTx UART1 + #endif /* Use_UART1 */ + + #ifdef USE_UART2 + #define UARTx UART2 + #endif /* Use_UART2 */ + + #ifdef USE_UART3 + #define UARTx UART3 + #endif /* Use_UART3 */ + + UART_ByteSend(UARTx,(u8 *)ch); +} +#endif /* USE_SERIAL_PORT */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/wdg.c b/Demo/ARM7_STR71x_IAR/Library/wdg.c new file mode 100644 index 000000000..efd656c49 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/wdg.c @@ -0,0 +1,83 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : WDG.c +* Author : MCD Application Team +* Date First Issued : 10/24/2003 +* Description : This file provides all the WDG software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "wdg.h" + +#ifndef abs + #define abs(x) ((x)>0 ? (x) : -(x)) +#endif + +/******************************************************************************* +* Function Name : FindFactors +* Description : Search for the best (a,b) values that fit n = a*b +* with the following constraints: 1<=a<=256, 1<=b<=65536 +* Input 1 : n: the number to decompose +* Input/Output 2 : a: a pointer to the first factor +* Input/Output 3 : b: a pointer to the second factor +* Return : None +*******************************************************************************/ +static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b) +{ + unsigned long b0; + unsigned int a0; + long err, err_min=n; + + *a = a0 = ((n-1)/65536ul) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (long)*a * (long)*b - (long)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (long)*a * (long)*b - (long)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; +} + +/******************************************************************************* +* Function Name : WDG_PeriodValueConfig +* Description : Set the prescaler and counter reload value +* Input : Amount of time (us) needed +* Return : None +*******************************************************************************/ +void WDG_PeriodValueConfig ( u32 Time ) +{ + unsigned int a; + unsigned long n, b; + + n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); + FindFactors(n, &a, &b); + WDG->PR = a - 1; + WDG->VR = b - 1; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c b/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..0090c7d56 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c @@ -0,0 +1,107 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Library includes. */ +#include "GPIO.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's - which are + * connected to the second nibble of GPIO port 1. + *-----------------------------------------------------------*/ + +#define partstLED_3 0x0080 +#define partstLED_2 0x0040 +#define partstLED_1 0x0020 +#define partstLED_0 0x0010 +#define partstON_BOARD 0x0100 /* The LED built onto the KickStart board. */ + +#define partstALL_LEDs ( partstLED_0 | partstLED_1 | partstLED_2 | partstLED_3 | partstON_BOARD ) + +#define partstFIRST_LED_BIT 4 + +/* This demo application uses files that are common to all port demo +applications. These files assume 6 LED's are available, whereas I have +only 5 (including the LED built onto the development board). To prevent +two tasks trying to use the same LED a bit of remapping is performed. +The ComTest tasks will try and use LED's 6 and 7. LED 6 is ignored and +has no effect, LED 7 is mapped to LED3. The LED usage is described in +the port documentation available from the FreeRTOS.org WEB site. */ +#define partstCOM_TEST_LED 7 +#define partstRX_CHAR_LED 3 + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Configure the bits used to flash LED's on port 1 as output. */ + GPIO_Config(GPIO1, partstALL_LEDs, GPIO_OUT_OD); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED == partstCOM_TEST_LED ) + { + /* Remap as described above. */ + uxLED = partstRX_CHAR_LED; + } + + /* Adjust the LED value to map to the port pins actually being used, + then write the required value to the port. */ + uxLED += partstFIRST_LED_BIT; + GPIO_BitWrite( GPIO1, uxLED, !xValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED == partstCOM_TEST_LED ) + { + /* Remap as described above. */ + uxLED = partstRX_CHAR_LED; + } + + /* Adjust the LED value to map to the port pins actually being used, + then write the opposite value to the current state to the port pin. */ + uxLED += partstFIRST_LED_BIT; + GPIO_BitWrite(GPIO1, uxLED, ~GPIO_BitRead( GPIO1, uxLED ) ); +} + + + + diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.dep b/Demo/ARM7_STR71x_IAR/RTOSDemo.dep new file mode 100644 index 000000000..800760c68 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.dep @@ -0,0 +1,866 @@ + + + + 2 + + Debug + + $PROJ_DIR$\..\Common\Minimal\comtest.c + $PROJ_DIR$\Debug\Obj\tasks.pbi + $PROJ_DIR$\Debug\Obj\serial.pbi + $PROJ_DIR$\Debug\Obj\71x_lib.pbi + $PROJ_DIR$\Debug\Obj\wdg.pbi + $PROJ_DIR$\Debug\Obj\semtest.r79 + $TOOLKIT_DIR$\inc\string.h + $TOOLKIT_DIR$\inc\ysizet.h + $PROJ_DIR$\..\Common\include\comtest.h + $PROJ_DIR$\Debug\Obj\BlockQ.pbi + $PROJ_DIR$\..\Common\include\dynamic.h + $PROJ_DIR$\Library\include\71x_map.h + $PROJ_DIR$\Debug\Obj\list.r79 + $PROJ_DIR$\Library\include\eic.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $PROJ_DIR$\Debug\Obj\list.pbi + $PROJ_DIR$\Debug\Obj\ParTest.r79 + $PROJ_DIR$\Debug\Obj\BlockQ.r79 + $TOOLKIT_DIR$\inc\yvals.h + $PROJ_DIR$\Debug\Obj\main.r79 + $PROJ_DIR$\..\Common\include\partest.h + $PROJ_DIR$\Library\include\rccu.h + $PROJ_DIR$\Debug\Obj\portasm.r79 + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\ISR_Support.h + $PROJ_DIR$\..\Common\include\PollQ.h + $PROJ_DIR$\Debug\Obj\cstartup.r79 + $TOOLKIT_DIR$\inc\DLib_Threads.h + $PROJ_DIR$\FreeRTOSConfig.h + $PROJ_DIR$\Debug\Obj\dynamic.pbi + $PROJ_DIR$\..\..\Source\include\FreeRTOS.h + $PROJ_DIR$\Debug\Obj\heap_2.r79 + $PROJ_DIR$\Debug\Obj\queue.r79 + $PROJ_DIR$\..\..\Source\include\queue.h + $TOOLKIT_DIR$\inc\stdlib.h + $PROJ_DIR$\Library\include\wdg.h + $PROJ_DIR$\Debug\Obj\serialISR.r79 + $TOOLKIT_DIR$\lib\dl4tptinl8n.h + $PROJ_DIR$\Debug\Obj\heap_2.pbi + $PROJ_DIR$\Debug\Obj\integer.pbi + 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$PROJ_DIR$\Debug\Exe\RTOSDemo.d79 + $TOOLKIT_DIR$\lib\dl4tptinl8n.r79 + $PROJ_DIR$\..\..\Source\include\task.h + $PROJ_DIR$\Debug\Obj\uart.pbi + $PROJ_DIR$\Debug\Obj\gpio.pbi + $PROJ_DIR$\Debug\Obj\flash.pbi + $PROJ_DIR$\Debug\Obj\vect.r79 + $PROJ_DIR$\..\Common\include\serial.h + $PROJ_DIR$\..\Common\include\flash.h + $PROJ_DIR$\Debug\Obj\rccu.r79 + $PROJ_DIR$\Debug\Obj\ParTest.pbi + $PROJ_DIR$\Debug\Obj\PollQ.pbi + $PROJ_DIR$\Debug\Obj\semtest.pbi + $PROJ_DIR$\..\..\Source\include\projdefs.h + $PROJ_DIR$\..\..\Source\include\list.h + $PROJ_DIR$\Debug\Obj\comtest.pbi + $PROJ_DIR$\Library\include\71x_type.h + $PROJ_DIR$\Debug\Obj\gpio.r79 + $PROJ_DIR$\..\..\Source\include\portable.h + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portmacro.h + $PROJ_DIR$\Debug\Obj\wdg.r79 + $PROJ_DIR$\..\Common\include\semtest.h + $PROJ_DIR$\cstartup.s79 + $PROJ_DIR$\lnkarm.xcl + $PROJ_DIR$\vect.s79 + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\serial\serialISR.s79 + $PROJ_DIR$\Library\rccu.c + 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$PROJ_DIR$\Release\Obj\queue.r79 + $PROJ_DIR$\cstartup.s79 + $PROJ_DIR$\vect.s79 + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\serial\serialISR.s79 + $PROJ_DIR$\Library\rccu.c + $PROJ_DIR$\Library\uart.c + $PROJ_DIR$\Library\wdg.c + $PROJ_DIR$\..\..\Source\list.c + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 + $PROJ_DIR$\..\..\Source\queue.c + $PROJ_DIR$\..\..\Source\tasks.c + $PROJ_DIR$\..\Common\Minimal\flash.c + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + $PROJ_DIR$\..\Common\Minimal\dynamic.c + $PROJ_DIR$\..\Common\Minimal\integer.c + $PROJ_DIR$\main.c + $PROJ_DIR$\ParTest\ParTest.c + $PROJ_DIR$\..\Common\Minimal\PollQ.c + $PROJ_DIR$\..\Common\Minimal\semtest.c + $PROJ_DIR$\serial\serial.c + $PROJ_DIR$\Library\gpio.c + $PROJ_DIR$\Library\71x_lib.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + ICCARM + 23 + + + + + [ROOT_NODE] + + + XLINK + 20 + + + + + $PROJ_DIR$\cstartup.s79 + + + AARM + 6 + + + + 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$PROJ_DIR$\ParTest\ParTest.c + + + ICCARM + 3 + + + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + ICCARM + 15 + + + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + ICCARM + 19 + + + + + $PROJ_DIR$\serial\serial.c + + + ICCARM + 24 + + + + + $PROJ_DIR$\Library\gpio.c + + + ICCARM + 18 + + + + + $PROJ_DIR$\Library\71x_lib.c + + + ICCARM + 4 + + + + + [MULTI_TOOL] + XLINK + + + + + diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..bf7182a47 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd @@ -0,0 +1,913 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + 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1 + 0 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + + + + diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..b87cca4f9 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp @@ -0,0 +1,1733 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\serial\serialISR.s79 + + + + Library Source + + $PROJ_DIR$\Library\71x_lib.c + + + $PROJ_DIR$\Library\gpio.c + + + $PROJ_DIR$\Library\rccu.c + + + $PROJ_DIR$\Library\uart.c + + + $PROJ_DIR$\Library\wdg.c + + + + RTOS Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\cstartup.s79 + + + $PROJ_DIR$\lnkarm.xcl + + + $PROJ_DIR$\vect.s79 + + + + + diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.eww b/Demo/ARM7_STR71x_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/Demo/ARM7_STR71x_IAR/cstartup.s79 b/Demo/ARM7_STR71x_IAR/cstartup.s79 new file mode 100644 index 000000000..74e9763f8 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/cstartup.s79 @@ -0,0 +1,212 @@ +;----------------------------------------------------------------------------- +; This file contains the startup code used by the ICCARM C compiler. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; All code in the modules (except ?RESET) will be placed in the ICODE segment. +; +; $Revision: 1.1 $ +; +;----------------------------------------------------------------------------- + +; +; Naming covention of labels in this file: +; +; ?xxx - External labels only accessed from assembler. +; __xxx - External labels accessed from or defined in C. +; xxx - Labels local to one module (note: this file contains +; several modules). +; main - The starting point of the user program. +; + +;--------------------------------------------------------------- +; Macros and definitions for the whole file +;--------------------------------------------------------------- + + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + + + +Mode_USR DEFINE 0x10 +Mode_FIQ DEFINE 0x11 +Mode_IRQ DEFINE 0x12 +Mode_SVC DEFINE 0x13 +Mode_ABT DEFINE 0x17 +Mode_UNDEF DEFINE 0x1B +Mode_SYS DEFINE 0x1F ; available on ARM Arch 4 and later + +I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled +F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled + + +; --- System memory locations + +RAM_Base DEFINE 0x20000000 +RAM_Limit DEFINE 0x20010000 +SRAM_Base DEFINE 0x60000000 + +SVC_Stack DEFINE RAM_Limit ; 512 byte SVC stack at + ; top of memory - used by kernel. +IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack +USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in + ; system mode but task stacks are allocated + ; when the task is created. +FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack +ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack +UNDEF_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack + +EIC_Base_addr DEFINE 0xFFFFF800 ; EIC base address +ICR_off_addr DEFINE 0x00 ; Interrupt Control register offset +CIPR_off_addr DEFINE 0x08 ; Current Interrupt Priority Register offset +IVR_off_addr DEFINE 0x18 ; Interrupt Vector Register offset +FIR_off_addr DEFINE 0x1C ; Fast Interrupt Register offset +IER_off_addr DEFINE 0x20 ; Interrupt Enable Register offset +IPR_off_addr DEFINE 0x40 ; Interrupt Pending Bit Register offset +SIR0_off_addr DEFINE 0x60 ; Source Interrupt Register 0 + +EMI_Base_addr DEFINE 0x6C000000 ; EMI base address +BCON0_off_addr DEFINE 0x00 ; Bank 0 configuration register offset +BCON1_off_addr DEFINE 0x04 ; Bank 1 configuration register offset +BCON2_off_addr DEFINE 0x08 ; Bank 2 configuration register offset +BCON3_off_addr DEFINE 0x0C ; Bank 3 configuration register offset + +GPIO2_Base_addr DEFINE 0xE0005000 ; GPIO2 base address +PC0_off_addr DEFINE 0x00 ; Port Configuration Register 0 offset +PC1_off_addr DEFINE 0x04 ; Port Configuration Register 1 offset +PC2_off_addr DEFINE 0x08 ; Port Configuration Register 2 offset +PD_off_addr DEFINE 0x0C ; Port Data Register offset + +CPM_Base_addr DEFINE 0xA0000040 ; CPM Base Address +BOOTCONF_off_addr DEFINE 0x10 ; CPM - Boot Configuration Register +FLASH_mask DEFINE 0x0000 ; to remap FLASH at 0x0 +RAM_mask DEFINE 0x0002 ; to remap RAM at 0x0 +EXTMEM_mask DEFINE 0x0003 ; to remap EXTMEM at 0x0 + +;--------------------------------------------------------------- +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other +; addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;--------------------------------------------------------------- + + MODULE ?RESET + COMMON INTVEC:CODE:NOROOT(2) + PUBLIC __program_start + EXTERN ?cstartup + CODE32 ; Always ARM mode after reset + +__program_start + ldr pc,=?cstartup ; Absolute jump can reach 4 GByte + b ?cstartup ; Relative branch allows remap, limited to 32 MByte + + LTORG + ENDMOD + + +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- + MODULE ?CSTARTUP + +; RSEG IRQ_STACK:DATA(2) +; RSEG SVC_STACK:DATA:NOROOT(2) +; RSEG CSTACK:DATA(2) + RSEG ICODE:CODE:NOROOT(2) + PUBLIC ?cstartup + EXTERN ?main + + + + + CODE32 +?cstartup + + + NOP ; Wait for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + msr CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /* Undefined Instruction Mode */ + LDR SP, =UNDEF_Stack + + msr CPSR_c, #Mode_ABT|I_Bit|F_Bit /* Abort Mode */ + LDR SP, =ABT_Stack + + msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /* FIQ Mode */ + LDR SP, =FIQ_Stack + + msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* IRQ Mode */ + LDR SP, =IRQ_Stack + + msr CPSR_c, #Mode_SVC|I_Bit|F_Bit /* Supervisor Mode */ + LDR SP, =SVC_Stack + + msr CPSR_c, #Mode_SYS|I_Bit|F_Bit /* System Mode */ + LDR SP, =USR_Stack + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #Mode_SVC|I_Bit|F_Bit + + + IMPORT T0TIMI_Addr + +EIC_INIT + LDR r3, =EIC_Base_addr + LDR r4, =0x00000000 + STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ + STR r4, [r3, #IER_off_addr] ; Disable all channels interrupts + LDR r4, =0xFFFFFFFF + STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits + LDR r4, =0x0C + STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits + LDR r4, =0x00000000 + STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register + LDR r4, =0xE59F0000 + STR r4, [r3, #IVR_off_addr] ; Write the LDR pc,pc,#offset instruction code in IVR[31:16] + LDR r2, =32 ; 32 Channel to initialize + LDR r0, =T0TIMI_Addr ; Read the address of the IRQs address table + LDR r1, =0x00000FFF + AND r0,r0,r1 + LDR r5, =SIR0_off_addr ; Read SIR0 address + SUB r4,r0,#8 ; subtract 8 for prefetch + LDR r1, =0xF7E8 ; add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000) + ; 0xF7E8 used to complete the LDR pc,pc,#offset opcode + ADD r1,r4,r1 ; compute the jump offset +EIC_INI MOV r4, r1, LSL #16 ; Left shift the result + STR r4, [r3, r5] ; Store the result in SIRx register + ADD r1, r1, #4 ; Next IRQ address + ADD r5, r5, #4 ; Next SIR + SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize + BNE EIC_INI ; If more then continue + + + ldr r0,=?main + bx r0 + + LTORG + + ENDMOD + + + END + + diff --git a/Demo/ARM7_STR71x_IAR/lnkarm.xcl b/Demo/ARM7_STR71x_IAR/lnkarm.xcl new file mode 100644 index 000000000..eb3403a7c --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/lnkarm.xcl @@ -0,0 +1,201 @@ +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1 $ +//************************************************************************* + +// Code memory in flash +-DROMSTART=0x00000000 +-DROMEND=0x0003FFFF +-DVECSTART=ROMSTART + +// Data memory +-DRAMSTART=0x20000000 +-DRAMEND=0x2000FFFF + + +//************************************************************************* +// In this file it is assumed that the system has the following +// memory layout: +// +// Exception vectors [0x000000--0x00001F] RAM or ROM +// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory) +// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory) +// +// ------------- +// Code segments - may be placed anywhere in memory. +// ------------- +// +// INTVEC -- Exception vector table. +// SWITAB -- Software interrupt vector table. +// ICODE -- Startup (cstartup) and exception code. +// DIFUNCT -- Dynamic initialization vectors used by C++. +// CODE -- Compiler generated code. +// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) +// CODE_ID -- Initializer for CODE_I (ROM). +// +// ------------- +// Data segments - may be placed anywhere in memory. +// ------------- +// +// CSTACK -- The stack used by C/C++ programs (system and user mode). +// IRQ_STACK -- The stack used by IRQ service routines. +// SVC_STACK -- The stack used in supervisor mode +// (Define other exception stacks as needed for +// FIQ, ABT, UND). +// HEAP -- The heap used by malloc and free in C and new and +// delete in C++. +// INITTAB -- Table containing addresses and sizes of segments that +// need to be initialized at startup (by cstartup). +// CHECKSUM -- The linker places checksum byte(s) in this segment, +// when the -J linker command line option is used. +// DATA_y -- Data objects. +// +// Where _y can be one of: +// +// _AN -- Holds uninitialized located objects, i.e. objects with +// an absolute location given by the @ operator or the +// #pragma location directive. Since these segments +// contain objects which already have a fixed address, +// they should not be mentioned in this linker command +// file. +// _C -- Constants (ROM). +// _I -- Initialized data (RAM). +// _ID -- The original content of _I (copied to _I by cstartup) (ROM). +// _N -- Uninitialized data (RAM). +// _Z -- Zero initialized data (RAM). +// +// Note: Be sure to use end values for the defined address ranges. +// Otherwise, the linker may allocate space outside the +// intended memory range. +//************************************************************************* + + +//************************************************ +// Inform the linker about the CPU family used. +//************************************************ + +-carm + +//************************************************************************* +// Segment placement - General information +// +// All numbers in the segment placement command lines below are interpreted +// as hexadecimal unless they are immediately preceded by a '.', which +// denotes decimal notation. +// +// When specifying the segment placement using the -P instead of the -Z +// option, the linker is free to split each segment into its segment parts +// and randomly place these parts within the given ranges in order to +// achieve a more efficient memory usage. One disadvantage, however, is +// that it is not possible to find the start or end address (using +// the assembler operators .sfb./.sfe.) of a segment which has been split +// and reformed. +// +// When generating an output file which is to be used for programming +// external ROM/Flash devices, the -M linker option is very useful +// (see xlink.pdf for details). +//************************************************************************* + + +//************************************************************************* +// Read-only segments mapped to ROM. +//************************************************************************* + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ + +-Z(CODE)INTVEC=VECSTART:+0x940 + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ + +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ + +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Original ROM location for __ramfunc code copied +// to and executed from RAM. +//************************************************ + +-Z(CONST)CODE_ID=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ + +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + + +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* + +//************************************************ +// Data segments. +//************************************************ + +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ + +-Z(DATA)CODE_I=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// CODE_ID segment instead, but to keep symbol and +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +-QCODE_I=CODE_ID + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* + +//-D_CSTACK_SIZE=400 +// -D_SVC_STACK_SIZE=10 +//-D_IRQ_STACK_SIZE=500 +//-D_HEAP_SIZE=4 + +//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +//-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND +//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/Demo/ARM7_STR71x_IAR/main.c b/Demo/ARM7_STR71x_IAR/main.c new file mode 100644 index 000000000..f1913785f --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/main.c @@ -0,0 +1,246 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Library includes. */ +#include "RCCU.h" +#include "wdg.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 4 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the IAR STR71x demo board. This + * just sets the PLL for the required frequency. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. Called by vErrorChecks(). + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL to generate a 48MHz clock from the 4MHz CLK. */ + + /* Turn of the div by two. */ + RCCU_Div2Config( DISABLE ); + + /* 48MHz = ( 4MHz * 12 ) / 1 */ + RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 ); + RCCU_RCLKSourceConfig( RCCU_PLL1_Output ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +portTickType xLastWakeTime; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error so the LED flashes faster. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/ARM7_STR71x_IAR/serial/serial.c b/Demo/ARM7_STR71x_IAR/serial/serial.c new file mode 100644 index 000000000..11e1d5b14 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/serial/serial.c @@ -0,0 +1,242 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Library includes. */ +#include "uart.h" +#include "gpio.h" +#include "eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +#define UART0_Rx_Pin ( 0x0001<< 8 ) +#define UART0_Tx_Pin ( 0x0001<< 9 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/* Macros to turn on and off the Tx empty interrupt. */ +#define serINTERRUPT_ON() UART0->IER |= UART_TxHalfEmpty +#define serINTERRUPT_OFF() UART0->IER &= ~UART_TxHalfEmpty + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Interrupt entry point written in the assembler file serialISR.s79. */ +extern void vSerialISREntry( void ); + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + portENTER_CRITICAL(); + { + /* Setup the UART port pins. */ + GPIO_Config( GPIO0, UART0_Tx_Pin, GPIO_AF_PP ); + GPIO_Config( GPIO0, UART0_Rx_Pin, GPIO_IN_TRI_CMOS ); + + /* Configure the UART. */ + UART_OnOffConfig( UART0, ENABLE ); + UART_FifoConfig( UART0, DISABLE ); + UART_FifoReset( UART0, UART_RxFIFO ); + UART_FifoReset( UART0, UART_TxFIFO ); + UART_LoopBackConfig(UART0, DISABLE ); + UART_Config( UART0, ulWantedBaud, UART_NO_PARITY, UART_1_StopBits, UARTM_8D ); + UART_RxConfig( UART0, ENABLE ); + + /* Configure the IEC for the UART interrupts. */ + EIC_IRQChannelPriorityConfig( UART0_IRQChannel, 1 ); + EIC_IRQChannelConfig( UART0_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + UART_ItConfig( UART0, UART_RxBufFull, ENABLE ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + serINTERRUPT_ON(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +/* Serial port ISR. This can cause a context switch so is not defined as a +standard ISR using the __irq keyword. Instead a wrapper function is defined +within serialISR.s79 which in turn calls this function. See the port +documentation on the FreeRTOS.org website for more information. */ +__arm void vSerialISR( void ) +{ +unsigned portSHORT usStatus; +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt? */ + usStatus = UART_FlagStatus( UART0 ); + + if( usStatus & UART_TxHalfEmpty ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + UART0->TxBUFR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + serINTERRUPT_OFF(); + } + } + + if( usStatus & UART_RxBufFull ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue of received + characters. */ + cChar = UART0->RxBUFR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); + + /* End the interrupt in the EIC. */ + portCLEAR_EIC(); +} + + + + + + diff --git a/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 b/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..cd1e2ee2f --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,81 @@ + + + + + + + + + + + + 129272727 + + + + + + + + 200 + + + + 100 + + + + + + + 20115330776 + 200 + + + + + + + TabID-24393-22702 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo SourceRTOSDemo/RTOS SourceRTOSDemo/System FilesRTOSDemo/System Files/vect.s79 + + + + 0 + + + TabID-13122-22708 + Debug Log + Debug-Log + + + + TabID-23870-22711 + Build + Build + + + TabID-19116-28152BreakpointsBreakpoints + + 0TabID-10243-6871RegisterRegister0001CPSR0 + + + + + + 0100000010000001 + + + + + + + iaridepm1debuggergui1-2-2853203-2-212512578125111706128124764075-2-2853447-2-2200200125000178731280625764075-2-22191602-2-21604221100250019749778125111706 + + + + diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..e6db9e63b --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni @@ -0,0 +1,23 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 +Watch1=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 +[Low Level] +Pipeline mode=0 +Initialized=0 +[Disassemble mode] +mode=0 +[Breakpoints] +Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\STR71x\port.c}.240.4@1" 1 0 0 0 "" 0 "" +Count=1 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..5acc21f72 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,75 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 227272727 + + + + + + + 20115330776 + + + + + + + + + + + TabID-14962-21036 + Workspace + Workspace + + + RTOSDemoRTOSDemo/source + + + + 0 + + + TabID-24623-22493 + Build + Build + + + + TabID-13645-22698 + Debug Log + Debug-Log + + + TabID-25855-25419BreakpointsBreakpoints + + 0 + + + + + + TextEditorE:\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c0984693469300100000010000001 + + + + + + + iaridepm1debuggergui1-2-2675301-2-221211312518766189375605004-2-23971602-2-2160439910025003565681312518766 + + + + diff --git a/Demo/ARM7_STR71x_IAR/vect.s79 b/Demo/ARM7_STR71x_IAR/vect.s79 new file mode 100644 index 000000000..f363a0d35 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/vect.s79 @@ -0,0 +1,127 @@ +#include "FreeRTOSConfig.h" + +IVR_ADDR DEFINE 0xFFFFF818 + +;******************************************************************************* +; Import the Reset_Handler address from 71x_init.s +;******************************************************************************* + + IMPORT __program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT vPortYieldProcessor ; FreeRTOS SWI handler + +;******************************************************************************* +; Import IRQ handlers from 71x_it.c +;******************************************************************************* + + IMPORT vPortNonPreemptiveTick ; Cooperative FreeRTOS tick handler + IMPORT vPortPreemptiveTickISR ; Preemptive FreeRTOS tick handler + IMPORT vSerialISREntry ; Demo serial port handler + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + + CODE32 + + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, =IVR_ADDR + LDR PC, FIQ_Addr + + + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler +FIQ_Addr DCD FIQHandler + +;******************************************************************************* +; Peripherals IRQ handlers address table +;******************************************************************************* + + EXPORT T0TIMI_Addr + +T0TIMI_Addr DCD DefaultISR +FLASH_Addr DCD DefaultISR +RCCU_Addr DCD DefaultISR +RTC_Addr DCD DefaultISR +#if configUSE_PREEMPTION == 0 +WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used. +#else +WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used. +#endif +XTI_Addr DCD DefaultISR +USBHP_Addr DCD DefaultISR +I2C0ITERR_Addr DCD DefaultISR +I2C1ITERR_ADDR DCD DefaultISR +UART0_Addr DCD vSerialISREntry +UART1_Addr DCD DefaultISR +UART2_ADDR DCD DefaultISR +UART3_ADDR DCD DefaultISR +BSPI0_ADDR DCD DefaultISR +BSPI1_Addr DCD DefaultISR +I2C0_Addr DCD DefaultISR +I2C1_Addr DCD DefaultISR +CAN_Addr DCD DefaultISR +ADC12_Addr DCD DefaultISR +T1TIMI_Addr DCD DefaultISR +T2TIMI_Addr DCD DefaultISR +T3TIMI_Addr DCD DefaultISR + DCD 0 ; reserved + DCD 0 ; reserved + DCD 0 ; reserved +HDLC_Addr DCD DefaultISR +USBLP_Addr DCD DefaultISR + DCD 0 ; reserved + DCD 0 ; reserved +T0TOI_Addr DCD DefaultISR +T0OC1_Addr DCD DefaultISR +T0OC2_Addr DCD DefaultISR + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + + +UndefinedHandler + b UndefinedHandler + +PrefetchAbortHandler + b PrefetchAbortHandler + +DataAbortHandler + b DataAbortHandler + +IRQHandler + b DefaultISR + +FIQHandler + b FIQHandler + +DefaultISR + b DefaultISR + + + + LTORG + + END diff --git a/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..e489f0d15 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h @@ -0,0 +1,79 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +#define configCALL_STACK_SIZE 20 + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) +#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c b/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..25f5e3d8b --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c @@ -0,0 +1,123 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set port B direction to outputs. Start with all output off. */ + DDRB = partstALL_BITS_OUTPUT; + PORTB = ucCurrentOutputValue; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); + } +} + + diff --git a/Demo/AVR_ATMega323_IAR/main.c b/Demo/AVR_ATMega323_IAR/main.c new file mode 100644 index 000000000..c473288d7 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/main.c @@ -0,0 +1,249 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task that does not flash an LED maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles an LED. Should any task contain an error at any time the LED toggle + * will stop. + * + * The LED flash and communications test tasks do not maintain a count. + */ + +/* +Changes from V1.2.0 + + + Changed the baud rate for the serial test from 19200 to 57600. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.5 + + + Set the baud rate to 38400. This has a smaller error percentage with an + 8MHz clock (according to the manual). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.2.0 + + + File can now be built using either the IAR or WinAVR compiler. + +Changes from V2.6.1 + + + The IAR and WinAVR AVR ports are now maintained separately. +*/ + +#include +#include + +#ifdef GCC_MEGA_AVR + /* EEPROM routines used only with the WinAVR compiler. */ + #include +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo file headers. */ +#include "PollQ.h" +#include "integer.h" +#include "serial.h" +#include "comtest.h" +#include "flash.h" +#include "print.h" +#include "partest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled. If an error is found at any time the LED is never toggles +again. */ +#define mainCHECK_TASK_LED ( 7 ) + +/* The period between executions of the check task. */ +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +/* An address in the EEPROM used to count resets. This is used to check that +the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Flashes an LED if everything is okay. + */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* + * Called on boot to increment a count stored in the EEPROM. This is used to + * ensure the CPU does not reset unexpectedly. + */ +static void prvIncrementResetCount( void ); + +portSHORT main( void ) +{ + prvIncrementResetCount(); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + vTaskDelay( mainCHECK_PERIOD ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise. The result here is not important - + see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + prvCheckOtherTasksAreStillRunning(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementResetCount( void ) +{ +unsigned portCHAR ucCount; +const unsigned portCHAR ucReadBit = ( unsigned portCHAR ) 0x01; +const unsigned portCHAR ucWrite1 = ( unsigned portCHAR ) 0x04; +const unsigned portCHAR ucWrite2 = ( unsigned portCHAR ) 0x02; + + /* Increment the EEPROM value at 0x00. + + Setup the EEPROM address. */ + EEARH = 0x00; + EEARL = 0x00; + + /* Set the read enable bit. */ + EECR |= ucReadBit; + + /* Wait for the read. */ + while( EECR & ucReadBit ); + + /* The byte is ready. */ + ucCount = EEDR; + + /* Increment the reset count, then write the byte back. */ + ucCount++; + EEDR = ucCount; + EECR = ucWrite1; + EECR = ( ucWrite1 | ucWrite2 ); +} + diff --git a/Demo/AVR_ATMega323_IAR/rtosdemo.dep b/Demo/AVR_ATMega323_IAR/rtosdemo.dep new file mode 100644 index 000000000..4413b92f4 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/rtosdemo.dep @@ -0,0 +1,141 @@ + + + + 1 + + Debug + + $PROJ_DIR$\ParTest\ParTest.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\ParTest.r90 + + + + + $PROJ_DIR$\serial\serial.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\serial.r90 + + + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90 + + + AAVR + $PROJ_DIR$\Output\Obj\portmacro.r90 + + + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\comtest.r90 + + + + + $PROJ_DIR$\..\..\Source\tasks.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\tasks.r90 + + + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\integer.r90 + + + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\heap_1.r90 + + + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\port.r90 + + + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\PollQ.r90 + + + + + $PROJ_DIR$\..\..\Source\queue.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\queue.r90 + + + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\flash.r90 + + + + + $PROJ_DIR$\main.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\main.r90 + + + + + $PROJ_DIR$\..\..\Source\list.c + + + ICCAVR + $PROJ_DIR$\Output\Obj\list.r90 + + + + + [ROOT_NODE] + + + XLINK + $PROJ_DIR$\Output\Exe\rtosdemo.a90 + $PROJ_DIR$\Output\Exe\rtosdemo.d90 + + + + + [MULTI_TOOL] + XLINK + + + + + diff --git a/Demo/AVR_ATMega323_IAR/rtosdemo.ewd b/Demo/AVR_ATMega323_IAR/rtosdemo.ewd new file mode 100644 index 000000000..b12d95928 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/rtosdemo.ewd @@ -0,0 +1,613 @@ + + + + 1 + + Debug + + AVR + + 1 + + C-SPY + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + CCRAVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + ICE200AVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + JTAGICEAVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JTAGICEMKIIAVR + 1 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SIMAVR + 2 + + 1 + 1 + 1 + + + + + + + THIRDPARTYAVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + + + + diff --git a/Demo/AVR_ATMega323_IAR/rtosdemo.ewp b/Demo/AVR_ATMega323_IAR/rtosdemo.ewp new file mode 100644 index 000000000..b18aa583c --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/rtosdemo.ewp @@ -0,0 +1,1006 @@ + + + + 1 + + Debug + + AVR + + 1 + + General + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCAVR + 3 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AAVR + 3 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + diff --git a/Demo/AVR_ATMega323_IAR/rtosdemo.eww b/Demo/AVR_ATMega323_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/Demo/AVR_ATMega323_IAR/serial/serial.c b/Demo/AVR_ATMega323_IAR/serial/serial.c new file mode 100644 index 000000000..146fd2173 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/serial/serial.c @@ -0,0 +1,195 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR IAR AVR PORT. */ + + +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) + +/* Constants for writing to UCSRB. */ +#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) +#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* Constants for writing to UCSRC. */ +#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) +#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +#define vInterruptOn() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte |= serTX_INT_ENABLE; \ + outb( UCSRB, ucByte ); \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte &= ~serTX_INT_ENABLE; \ + outb( UCSRB, ucByte ); \ +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulBaudRateCounter; +unsigned portCHAR ucByte; + + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Calculate the baud rate register value from the equation in the + data sheet. */ + ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; + + /* Set the baud rate. */ + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + outb( UBRRL, ucByte ); + + ulBaudRateCounter >>= ( unsigned portLONG ) 8; + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + outb( UBRRH, ucByte ); + + /* Enable the Rx interrupt. The Tx interrupt will get enabled + later. Also enable the Rx and Tx. */ + outb( UCSRB, serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); + + /* Set the data bits to 8. */ + outb( UCSRC, serUCSRC_SELECT | serEIGHT_DATA_BITS ); + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portCHAR ucByte; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + vInterruptOff(); + ucByte = UCSRB; + ucByte &= ~serRX_INT_ENABLE; + outb( UCSRB, ucByte ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +__interrupt void SIG_UART_RECV( void ) +{ +signed portCHAR cChar; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = UDR; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +__interrupt void SIG_UART_DATA( void ) +{ +signed portCHAR cChar, cTaskWoken; + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + outb( UDR, cChar ); + } + else + { + /* Queue empty, nothing to send. */ + vInterruptOff(); + } +} + diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt new file mode 100644 index 000000000..33f4649c2 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt @@ -0,0 +1,5 @@ + + + + + diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..cdd173771 --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni @@ -0,0 +1,38 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Watch] +Watch 1=_ 1 "usCurrentNumberOfTasks" +Watch 2= +Watch 3= +[CodeCoverage] +State=_ 0 +[Profiling] +State=_ 0 +[TermIOSettings] +Filename=_ "" +InputMode=_ 1 +[QWatch] +WindowContent=_ 100 100 100 100 +[Desktop-Debug] +Wnd0=_ "Watch" "open" 44 0 1 -1 -1 -1 -1 1139 276 1595 524 100 100 100 100 +Wnd1=_ "Memory" "open" 44 0 1 -1 -1 -1 -1 1139 217 1591 939 1 1872 0 1872 0 1 0 1 0 +Wnd2=_ "CallStack" "open" 44 0 1 -1 -1 -1 -1 30 699 277 1037 1 +Wnd3=_ "Register" "open" 44 0 1 -1 -1 -1 -1 1237 0 1569 1019 0 0 0 0 +Wnd4=_ "Register" "open" 44 0 1 -1 -1 -1 -1 40 264 1312 986 0 0 0 0 +Wnd5=_ "Editor-DebugSource" "open" 44 0 1 -1 -1 -1 -1 169 991 1062 2036 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.s90" 1 1 0 206 6825 6825 +Wnd6=_ "Disassembly" "open" 44 0 1 -1 -1 -4 -28 586 28 1196 854 +Wnd7=_ "Log" "closed" 44 0 1 -1 -1 -4 -28 872 845 1595 1069 +Wnd8=_ "Locals" "closed" 44 0 1 -1 -1 -1 -1 1139 0 1595 276 100 100 100 100 +Wnd9=_ "Terminal I/O" "closed" 44 0 1 -1 -1 -1 -1 1138 522 1595 826 +Maximized=_ 0 +Count=_ 10 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt new file mode 100644 index 000000000..63403ba0c --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt @@ -0,0 +1,4 @@ +[struct types] +Count=_ 0 +[watch formats] +Count=_ 0 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini new file mode 100644 index 000000000..e433ec84f --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini @@ -0,0 +1,10 @@ +[WorkspaceWindow] +ExpandedNodes=_ 1 "rtosdemo" 1 "rtosdemo/Debug" +SelectedTab=_ 0 +[Desktop-Workspace] +Wnd0=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 378 14 1227 671 "E:\Dev\FreeRTOS\Source\tasks.c" 1 1 0 1170 37742 37742 +Wnd1=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 81 81 930 738 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.h" 1 1 0 66 3233 3233 +Wnd2=_ "Workspace2" "open" 44 0 1 -1 -1 -4 -28 0 0 352 713 276 27 27 +Wnd3=_ "Messages2" "open" 44 0 1 -1 -1 -4 -28 -6 714 1590 1104 5 "Build\Messages" 1580 "Find in Files\Line" 79 "Find in Files\Path" 474 "Find in Files\String" 948 "Tool Output\Output" 1560 +Maximized=_ 0 +Count=_ 4 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..f12a20b8b --- /dev/null +++ b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,49 @@ + + + + + + rtosdemo/Debug + + + + + + + + + 109272727 + + 20115330776 + + + + + + TabID-12388-19520 + Workspace + Workspace + + + rtosdemortosdemo/portheap.c + + + + 0TabID-19172-8303BuildBuild0 + + + + + + 0100000010000001 + + + + + + + iaridepm1-2-2718183-2-2185185115625165326115625643431-2-23541602-2-216043561002500318141116250166219 + + + + diff --git a/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h new file mode 100644 index 000000000..247dffb36 --- /dev/null +++ b/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h @@ -0,0 +1,77 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) +#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c b/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c new file mode 100644 index 000000000..25f5e3d8b --- /dev/null +++ b/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c @@ -0,0 +1,123 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set port B direction to outputs. Start with all output off. */ + DDRB = partstALL_BITS_OUTPUT; + PORTB = ucCurrentOutputValue; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); + } +} + + diff --git a/Demo/AVR_ATMega323_WinAVR/main.c b/Demo/AVR_ATMega323_WinAVR/main.c new file mode 100644 index 000000000..3cedbc603 --- /dev/null +++ b/Demo/AVR_ATMega323_WinAVR/main.c @@ -0,0 +1,225 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task that does not flash an LED maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles an LED. Should any task contain an error at any time the LED toggle + * will stop. + * + * The LED flash and communications test tasks do not maintain a count. + */ + +/* +Changes from V1.2.0 + + + Changed the baud rate for the serial test from 19200 to 57600. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.5 + + + Set the baud rate to 38400. This has a smaller error percentage with an + 8MHz clock (according to the manual). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.6.1 + + + The IAR and WinAVR AVR ports are now maintained separately. +*/ + +#include +#include + +#ifdef GCC_MEGA_AVR + /* EEPROM routines used only with the WinAVR compiler. */ + #include +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo file headers. */ +#include "PollQ.h" +#include "integer.h" +#include "serial.h" +#include "comtest.h" +#include "flash.h" +#include "print.h" +#include "partest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled. If an error is found at any time the LED is never toggles +again. */ +#define mainCHECK_TASK_LED ( 7 ) + +/* The period between executions of the check task. */ +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +/* An address in the EEPROM used to count resets. This is used to check that +the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Flashes an LED if everything is okay. + */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* + * Called on boot to increment a count stored in the EEPROM. This is used to + * ensure the CPU does not reset unexpectedly. + */ +static void prvIncrementResetCount( void ); + +portSHORT main( void ) +{ + prvIncrementResetCount(); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + vTaskDelay( mainCHECK_PERIOD ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise. The result here is not important - + see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + prvCheckOtherTasksAreStillRunning(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementResetCount( void ) +{ +unsigned portCHAR ucCount; + + eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) ); + ucCount++; + eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount ); +} + diff --git a/Demo/AVR_ATMega323_WinAVR/makefile b/Demo/AVR_ATMega323_WinAVR/makefile new file mode 100644 index 000000000..5c48ba064 --- /dev/null +++ b/Demo/AVR_ATMega323_WinAVR/makefile @@ -0,0 +1,426 @@ +# WinAVR Sample makefile written by Eric B. Weddington, Jörg Wunsch, et al. +# Released to the Public Domain +# Please read the make user manual! +# +# Additional material for this makefile was submitted by: +# Tim Henigan +# Peter Fleury +# Reiner Patommel +# Sander Pool +# Frederik Rouleau +# Markus Pfaff +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF (for use with AVR Studio 3.x or VMLAB). +# +# make extcoff = Convert ELF to AVR Extended COFF (for use with AVR Studio +# 4.07 or greater). +# +# make program = Download the hex file to the device, using avrdude. Please +# customize the avrdude settings below first! +# +# make filename.s = Just compile filename.c into the assembler code only +# +# To rebuild project do "make clean" then "make all". +# + + +# MCU name +MCU = atmega323 + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + +# Target file name (without extension). +TARGET = rtosdemo + +# Optimization level, can be [0, 1, 2, 3, s]. 0 turns off optimization. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s + + +# List C source files here. (C dependencies are automatically generated.) +DEMO_DIR = ../Common/Minimal +SOURCE_DIR = ../../Source +PORT_DIR = ../../Source/portable/GCC/ATMega323 + +SRC = \ +main.c \ +ParTest/ParTest.c \ +serial/serial.c \ +$(SOURCE_DIR)/tasks.c \ +$(SOURCE_DIR)/queue.c \ +$(SOURCE_DIR)/list.c \ +$(SOURCE_DIR)/portable/MemMang/heap_1.c \ +$(PORT_DIR)/port.c \ +$(DEMO_DIR)/flash.c \ +$(DEMO_DIR)/integer.c \ +$(DEMO_DIR)/PollQ.c \ +$(DEMO_DIR)/comtest.c + + +# If there is more than one source file, append them above, or modify and +# uncomment the following: +#SRC += foo.c bar.c + +# You can also wrap lines by appending a backslash to the end of the line: +#SRC += baz.c \ +#xyzzy.c + + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = + + +# Optional compiler flags. +# -g: generate debugging information (for GDB, or for COFF conversion) +# -O*: optimization level +# -f...: tuning, see gcc manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create assembler listing + +DEBUG_LEVEL=-g +WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ + -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused + +CFLAGS = -D GCC_MEGA_AVR -I. -I../../Source/include -I../Common/include \ +$(DEBUG_LEVEL) -O$(OPT) \ +-fsigned-char -funsigned-bitfields -fpack-struct -fshort-enums \ +$(WARNINGS) \ +-Wa,-adhlns=$(<:.c=.lst) \ +$(patsubst %,-I%,$(EXTRAINCDIRS)) + + +# Set a "language standard" compiler flag. +# Unremark just one line below to set the language standard to use. +# gnu99 = C99 + GNU extensions. See GCC manual for more information. +#CFLAGS += -std=c89 +#CFLAGS += -std=gnu89 +#CFLAGS += -std=c99 +CFLAGS += -std=gnu99 + + + +# Optional assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs + + + +# Optional linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref + + + +# Additional libraries + +# Minimalistic printf version +#LDFLAGS += -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires -lm below) +#LDFLAGS += -Wl,-u,vfprintf -lprintf_flt + +# -lm = math library +LDFLAGS += -lm + + + + +# Programming support using avrdude. Settings and variables. + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + + +AVRDUDE_PORT = com1 # programmer connected to serial device +#AVRDUDE_PORT = lpt1 # programmer connected to parallel port + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE += -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_FLAGS += -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_FLAGS += -v -v + + + + +# --------------------------------------------------------------------------- + +# Define directories, if needed. +DIRAVR = c:/winavr +DIRAVRBIN = $(DIRAVR)/bin +DIRAVRUTILS = $(DIRAVR)/utils/bin +DIRINC = . +DIRLIB = $(DIRAVR)/avr/lib + + +# Define programs and commands. +SHELL = sh + +CC = avr-gcc + +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size + + +# Programming support using avrdude. +AVRDUDE = avrdude + + +REMOVE = rm -f +COPY = cp + +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf + + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: + + + + +# Define all object files. +OBJ = $(SRC:.c=.o) $(ASRC:.S=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(SRC:.c=.lst) + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + +# Default target. +all: begin gccversion sizebefore $(TARGET).elf $(TARGET).hex $(TARGET).eep \ + $(TARGET).lss $(TARGET).sym sizeafter finished end + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + + +# Convert ELF to COFF for use in debugging / simulating in +# AVR Studio or VMLAB. +COFFCONVERT=$(OBJCOPY) --debugging \ + --change-section-address .data-0x800000 \ + --change-section-address .bss-0x800000 \ + --change-section-address .noinit-0x800000 \ + --change-section-address .eeprom-0x810000 + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 -O $(FORMAT) $< $@ + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + avr-nm -n $< > $@ + + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $(OBJ) --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + + + + + +# Target: clean project. +clean: begin clean_list finished end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(OBJ) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + + +# Automatically generate C source code dependencies. +# (Code originally taken from the GNU make user manual and modified +# (See README.txt Credits).) +# +# Note that this will work with sh (bash) and sed that is shipped with WinAVR +# (see the SHELL variable defined above). +# This may not work with other shells or other seds. +# +%.d: %.c + set -e; $(CC) -MM $(ALL_CFLAGS) $< \ + | sed 's,\(.*\)\.o[ :]*,\1.o \1.d : ,g' > $@; \ + [ -s $@ ] || rm -f $@ + + +# Remove the '-' if you want to see the dependency files generated. +-include $(SRC:.c=.d) + + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion coff extcoff \ + clean clean_list program + diff --git a/Demo/AVR_ATMega323_WinAVR/serial/serial.c b/Demo/AVR_ATMega323_WinAVR/serial/serial.c new file mode 100644 index 000000000..ab26a2a65 --- /dev/null +++ b/Demo/AVR_ATMega323_WinAVR/serial/serial.c @@ -0,0 +1,224 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + xQueueReceiveFromISR() used in place of xQueueReceive() within the ISR. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ + + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) + +/* Constants for writing to UCSRB. */ +#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) +#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* Constants for writing to UCSRC. */ +#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) +#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +#define vInterruptOn() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte |= serTX_INT_ENABLE; \ + UCSRB = ucByte; \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff() \ +{ \ + unsigned portCHAR ucInByte; \ + \ + ucInByte = UCSRB; \ + ucInByte &= ~serTX_INT_ENABLE; \ + UCSRB = ucInByte; \ +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulBaudRateCounter; +unsigned portCHAR ucByte; + + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Calculate the baud rate register value from the equation in the + data sheet. */ + ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; + + /* Set the baud rate. */ + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + UBRRL = ucByte; + + ulBaudRateCounter >>= ( unsigned portLONG ) 8; + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + UBRRH = ucByte; + + /* Enable the Rx interrupt. The Tx interrupt will get enabled + later. Also enable the Rx and Tx. */ + UCSRB = ( serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); + + /* Set the data bits to 8. */ + UCSRC = ( serUCSRC_SELECT | serEIGHT_DATA_BITS ); + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portCHAR ucByte; + + /* The parameter is not used. */ + ( void ) xPort; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + vInterruptOff(); + ucByte = UCSRB; + ucByte &= ~serRX_INT_ENABLE; + UCSRB = ucByte; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +SIGNAL( SIG_UART_RECV ) +{ +signed portCHAR cChar; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = UDR; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +SIGNAL( SIG_UART_DATA ) +{ +signed portCHAR cChar, cTaskWoken; + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + UDR = cChar; + } + else + { + /* Queue empty, nothing to send. */ + vInterruptOff(); + } +} + diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..d456a83ea --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/Demo/CORTEX_LM3S102_GCC/Demo1/main.c new file mode 100644 index 000000000..36705de43 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo1/main.c @@ -0,0 +1,604 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt b/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt new file mode 100644 index 000000000..208a58805 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..4cefcb544 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/Demo/CORTEX_LM3S102_GCC/Demo2/main.c new file mode 100644 index 000000000..da55d6810 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo2/main.c @@ -0,0 +1,600 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt b/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt new file mode 100644 index 000000000..e22c810ac --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..d456a83ea --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Makefile b/Demo/CORTEX_LM3S102_GCC/Makefile new file mode 100644 index 000000000..d587fd2e7 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/Makefile @@ -0,0 +1,86 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library and examples. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +include makedefs + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal + +CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= + +VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:ParTest:hw_include + + +OBJS= ${COMPILER}/main.o \ + ${COMPILER}/pdc.o \ + ${COMPILER}/list.o \ + ${COMPILER}/queue.o \ + ${COMPILER}/tasks.o \ + ${COMPILER}/port.o \ + ${COMPILER}/heap_1.o \ + ${COMPILER}/ParTest.o \ + ${COMPILER}/crflash.o \ + ${COMPILER}/croutine.o +# ${COMPILER}/pendsv_handler.o + +INIT_OBJS= ${COMPILER}/startup.o + +LIBS= hw_include/libdriver.a + + +# +# The default rule, which causes init to be built. +# +all: ${COMPILER} \ + ${COMPILER}/RTOSDemo.axf \ + +# +# The rule to clean out all the build products +# + +clean: + @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf + +# +# The rule to create the target directory +# +${COMPILER}: + @mkdir ${COMPILER} + +${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} +SCATTER_RTOSDemo=standalone.ld +ENTRY_RTOSDemo=ResetISR + +# +# +# Include the automatically generated dependency files. +# +-include ${wildcard ${COMPILER}/*.d} __dummy__ + + + + + + diff --git a/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..d61e6bd89 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h b/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h new file mode 100644 index 000000000..f8383de66 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h @@ -0,0 +1,18 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" + +#endif diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h b/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h new file mode 100644 index 000000000..2f259bd23 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h b/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h new file mode 100644 index 000000000..cdc9a5b19 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h new file mode 100644 index 000000000..d32cec40b --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h new file mode 100644 index 000000000..bef5dc618 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h new file mode 100644 index 000000000..77dfe716a --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h new file mode 100644 index 000000000..37472329f --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h new file mode 100644 index 000000000..044fec21d --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h new file mode 100644 index 000000000..a944f6662 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h new file mode 100644 index 000000000..40b6ab2a6 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h b/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h new file mode 100644 index 000000000..23424af4e --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a b/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a new file mode 100644 index 000000000..e1c1ec8e7 Binary files /dev/null and b/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a differ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c new file mode 100644 index 000000000..1e82ed8a8 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h new file mode 100644 index 000000000..aba74cd71 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h b/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h new file mode 100644 index 000000000..ef53b348b --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h b/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h new file mode 100644 index 000000000..2e1d1e48c --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h b/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h new file mode 100644 index 000000000..ea39859d2 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/init/startup.c b/Demo/CORTEX_LM3S102_GCC/init/startup.c new file mode 100644 index 000000000..c68821e32 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/init/startup.c @@ -0,0 +1,174 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +void FaultISR(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void entry(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 51 +#endif +static unsigned long pulMainStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section("vectors"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)), + ResetISR, + NmiSR, + FaultISR, //FAULT + 0, // The MPU fault handler + 0, // The bus fault handler + 0, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // SVCall handler + 0, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + 0, // GPIO Port A + 0, // GPIO Port B + 0, // GPIO Port C + 0, // GPIO Port D + 0, // GPIO Port E + vUART_ISR // UART0 Rx and Tx +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + Main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} diff --git a/Demo/CORTEX_LM3S102_GCC/main.c b/Demo/CORTEX_LM3S102_GCC/main.c new file mode 100644 index 000000000..36705de43 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/main.c @@ -0,0 +1,604 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/makedefs b/Demo/CORTEX_LM3S102_GCC/makedefs new file mode 100644 index 000000000..8f7a62be5 --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/makedefs @@ -0,0 +1,193 @@ +#****************************************************************************** +# +# makedefs - Definitions common to all makefiles. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +#****************************************************************************** +# +# The compiler to be used. +# +#****************************************************************************** +ifndef COMPILER +COMPILER=gcc +endif + +#****************************************************************************** +# +# The debugger to be used. +# +#****************************************************************************** +ifndef DEBUGGER +DEBUGGER=gdb +endif + +#****************************************************************************** +# +# Definitions for using GCC. +# +#****************************************************************************** +ifeq (${COMPILER}, gcc) + +# +# The command for calling the compiler. +# +CC=arm-stellaris-eabi-gcc + +# +# The flags passed to the assembler. +# +AFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -MD + +# +# The flags passed to the compiler. +# +CFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -O2 \ + -MD + +# +# The command for calling the library archiver. +# +AR=arm-stellaris-eabi-ar + +# +# The command for calling the linker. +# +LD=arm-stellaris-eabi-ld + +# +# The flags passed to the linker. +# +LDFLAGS= -Map gcc/out.map + +# +# Get the location of libgcc.a from the GCC front-end. +# +LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} + +# +# Get the location of libc.a from the GCC front-end. +# +LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} + +# +# The command for extracting images from the linked executables. +# +OBJCOPY=arm-stellaris-eabi-objcopy + +endif + +#****************************************************************************** +# +# Tell the compiler to include debugging information if the DEBUG environment +# variable is set. +# +#****************************************************************************** +ifdef DEBUG +CFLAGS += -g +endif + +#****************************************************************************** +# +# The rule for building the object file from each C source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.c + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi + @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} +ifeq (${COMPILER}, rvds) + @mv -f ${notdir ${@:.o=.d}} ${COMPILER} +endif + +#****************************************************************************** +# +# The rule for building the object file from each assembly source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi +ifeq (${COMPILER}, rvds) + @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} + @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} + @rm ${@:.o=_.S} + @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} + @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} + @rm ${notdir ${<:.S=.d}} +endif +ifeq (${COMPILER}, gcc) + @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} +endif + +#****************************************************************************** +# +# The rule for creating an object library. +# +#****************************************************************************** +${COMPILER}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr ${@} ${^}; \ + fi + @${AR} -cr ${@} ${^} + +#****************************************************************************** +# +# The rule for linking the application. +# +#****************************************************************************** +${COMPILER}/%.axf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@}"; \ + fi +ifeq (${COMPILER}, gcc) + @if [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}'; \ + fi + @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}' + @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} +endif diff --git a/Demo/CORTEX_LM3S102_GCC/standalone.ld b/Demo/CORTEX_LM3S102_GCC/standalone.ld new file mode 100644 index 000000000..1f1d7baab --- /dev/null +++ b/Demo/CORTEX_LM3S102_GCC/standalone.ld @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's Stellaris Family of microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K +} + +SECTIONS +{ + .text : + { + *(vectors) + *(.text) + *(.rodata*) + *(.constdata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss) + _ebss = .; + } > SRAM +} diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..d456a83ea --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c new file mode 100644 index 000000000..d8a132aa7 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c @@ -0,0 +1,599 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt b/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt new file mode 100644 index 000000000..10334b9be --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..4cefcb544 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c new file mode 100644 index 000000000..ebf058577 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c @@ -0,0 +1,604 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt b/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt new file mode 100644 index 000000000..2ddb358de --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt new file mode 100644 index 000000000..548f3b365 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt @@ -0,0 +1,47 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Source),1,0,0 +GRPOPT 2,(Demo),1,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<..\..\Source\croutine.c> +OPTFFF 1,2,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,3,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,5,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_1.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 2,7,1,0,0,0,0,0,<.\main.c> +OPTFFF 2,8,2,0,0,0,0,0,<.\init\Startup.s> +OPTFFF 2,9,1,0,0,0,0,0,<..\Common\Minimal\crflash.c> +OPTFFF 2,10,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 2,11,1,0,0,0,0,0,<.\include\pdc.c> +OPTFFF 2,12,4,0,0,0,0,0, + + +TARGOPT 1, (LM3S1xx) + ADSCLK=20000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\uvision\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + OPTKEY 0,(UL2CM3)(-U -O14 -S0 -C-1 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000) + OPTDF 0x0 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 new file mode 100644 index 000000000..3afecbd5b --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 @@ -0,0 +1,109 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' + +Group (Source) +Group (Demo) + +File 1,1,<..\..\Source\croutine.c> 0x440790D8 +File 1,1,<..\..\Source\list.c> 0x440790D8 +File 1,1,<..\..\Source\queue.c> 0x440790D8 +File 1,1,<..\..\Source\tasks.c> 0x440790D8 +File 1,1,<..\..\Source\portable\MemMang\heap_1.c> 0x440790D8 +File 1,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x440790D8 +File 2,1,<.\main.c> 0x441EE317 +File 2,2,<.\init\Startup.s> 0x44172A20 +File 2,1,<..\Common\Minimal\crflash.c> 0x440790D8 +File 2,1,<.\ParTest\ParTest.c> 0x440790D8 +File 2,1,<.\include\pdc.c> 0x44187439 +File 2,4, 0x44206F94 + + +Options 1,0,0 // Target 'LM3S1xx' + Device (LM3S101) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) + DevID (4079) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=0 + OutDir (.\uvision\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\uvision\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP (Cortex-M3) + ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,8,0,0 } + OCMADSIROM { 1,0,0,0,0,0,32,0,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (C:\Keil\ARM\RV30\LIB\Luminary;..\CORTEX_LM3S102_KEIL;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;.\include) + ADSASFLG { 65,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC (--diag_suppress 1581) + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler) + ADSLDIF () + ADSLDDW (6306) + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2CM3.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h new file mode 100644 index 000000000..d456a83ea --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c new file mode 100644 index 000000000..d61e6bd89 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/Demo/CORTEX_LM3S102_KEIL/include/pdc.c b/Demo/CORTEX_LM3S102_KEIL/include/pdc.c new file mode 100644 index 000000000..9e40fc925 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/include/pdc.c @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include "LM3Sxxx.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} diff --git a/Demo/CORTEX_LM3S102_KEIL/include/pdc.h b/Demo/CORTEX_LM3S102_KEIL/include/pdc.h new file mode 100644 index 000000000..e787cf937 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/include/pdc.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_KEIL/init/Startup.s b/Demo/CORTEX_LM3S102_KEIL/init/Startup.s new file mode 100644 index 000000000..c58ab3d14 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/init/Startup.s @@ -0,0 +1,162 @@ +;/*****************************************************************************/ +;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The STARTUP.S code is executed after CPU Reset. +; */ + + +;// Stack Configuration +;// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Stack_Size EQU 51 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +Heap_Mem SPACE Heap_Size + + +; System Control Register Addresses +SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address +PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control +LDOPC_OFS EQU 0x0034 ; LDO Power +SRCR0_OFS EQU 0x0040 ; Software Reset Control 0 +SRCR1_OFS EQU 0x0044 ; Software Reset Control 1 +SRCR2_OFS EQU 0x0048 ; Software Reset Control 2 +RCC_OFS EQU 0x0060 ; Run-Mode Clock Control +RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0 +RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1 +RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2 +SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0 +SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1 +SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2 +DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0 +DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1 +DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address 0. + + AREA RESET, CODE, READONLY + THUMB + + IMPORT xPortPendSVHandler + IMPORT xPortSysTickHandler + IMPORT vUART_ISR + +; Vector Table +Vectors DCD Stack_Mem + Stack_Size ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD DefaultISR ; Hard Fault Handler + DCD DefaultISR ; MPU Fault Handler + DCD DefaultISR ; Bus Fault Handler + DCD DefaultISR ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; SVCall Handler + DCD DefaultISR ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + DCD DefaultISR ; GPIO Port A Handler + DCD DefaultISR ; GPIO Port B Handler + DCD DefaultISR ; GPIO Port C Handler + DCD DefaultISR ; GPIO Port D Handler + DCD DefaultISR ; GPIO Port E Handler + DCD vUART_ISR ; UART0 Rx/Tx Handler + DCD DefaultISR ; UART1 Rx/Tx Handler + DCD DefaultISR ; SSI Rx/Tx Handler + DCD DefaultISR ; I2C Master/Slave Handler + DCD DefaultISR ; PWM Fault Handler + DCD DefaultISR ; PWM Generator 0 Handler + DCD DefaultISR ; PWM Generator 1 Handler + DCD DefaultISR ; PWM Generator 2 Handler + DCD DefaultISR ; Quadrature Encoder Handler + DCD DefaultISR ; ADC Sequence 0 Handler + DCD DefaultISR ; ADC Sequence 1 Handler + DCD DefaultISR ; ADC Sequence 2 Handler + DCD DefaultISR ; ADC Sequence 3 Handler + DCD DefaultISR ; Watchdog Timer Handler + DCD DefaultISR ; Timer 0 Subtimer A Handler + DCD DefaultISR ; Timer 0 Subtimer B Handler + DCD DefaultISR ; Timer 1 Subtimer A Handler + DCD DefaultISR ; Timer 1 Subtimer B Handler + DCD DefaultISR ; Timer 2 Subtimer A Handler + DCD DefaultISR ; Timer 2 Subtimer B Handler + DCD DefaultISR ; Analog Comparator 0 Handler + DCD DefaultISR ; Analog Comparator 1 Handler + DCD DefaultISR ; Analog Comparator 2 Handler + DCD DefaultISR ; System Control Handler + DCD DefaultISR ; Flash Control Handler + +; Dummy Handlers are implemented as infinite loops which can be modified. + +NmiSR B NmiSR +FaultISR B FaultISR + EXPORT FaultISR +DefaultISR B DefaultISR + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + +; Enable Clock Gating for Peripherals +; LDR R0, =SYSCTL_BASE ; System Control Base Address +; MVN R1, #0 ; Value 0xFFFFFFFF +; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0 +; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1 +; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2 + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + + END diff --git a/Demo/CORTEX_LM3S102_KEIL/main.c b/Demo/CORTEX_LM3S102_KEIL/main.c new file mode 100644 index 000000000..d8a132aa7 --- /dev/null +++ b/Demo/CORTEX_LM3S102_KEIL/main.c @@ -0,0 +1,599 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..d456a83ea --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c new file mode 100644 index 000000000..d61e6bd89 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c new file mode 100644 index 000000000..aa295a826 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c @@ -0,0 +1,617 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s new file mode 100644 index 000000000..66f29fb70 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s @@ -0,0 +1,115 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ + .word reset_handler + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + + + + diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..4cefcb544 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c new file mode 100644 index 000000000..d61e6bd89 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c new file mode 100644 index 000000000..68b59bdfb --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c @@ -0,0 +1,622 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s new file mode 100644 index 000000000..66f29fb70 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s @@ -0,0 +1,115 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ + .word reset_handler + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + + + + diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h new file mode 100644 index 000000000..ec86a804d --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 0 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 0 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c new file mode 100644 index 000000000..8e4bd49cb --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Kernel include files. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +/* Hardware specific include files. */ +#include "DriverLib.h" + +static const unsigned portLONG ulLEDs[] = +{ + GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0 +}; + +#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 ) + +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 3 ) + +/*-----------------------------------------------------------*/ +void vParTestInitialise( void ) +{ +portBASE_TYPE xLED; + + /* The LED's are on port B. */ + GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT ); + + for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ ) + { + vParTestSetLED( xLED, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + if( xValue == pdFALSE ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +portBASE_TYPE xCurrentValue; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] ); + if( xCurrentValue ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c new file mode 100644 index 000000000..0203f5ad8 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c @@ -0,0 +1,290 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * This is a mini co-routine demo for the Rowley CrossFire LM3S102 development + * board. It makes use of the boards tri-colour LED and analogue input. + * + * Four co-routines are created - an 'I2C' co-routine and three 'flash' + * co-routines. + * + * The I2C co-routine triggers an ADC conversion then blocks on a queue to + * wait for the conversion result - which it receives on the queue directly + * from the I2C interrupt service routine. The conversion result is then + * scalled to a delay period. The I2C interrupt then wakes each of the + * flash co-routines before itself delaying for the calculated period and + * then repeating the whole process. + * + * When woken by the I2C co-routine the flash co-routines each block for + * a given period, illuminate an LED for a fixed period, then go back to + * sleep to wait for the next cycle. The uxIndex parameter of the flash + * co-routines is used to ensure that each flashes a different LED, and that + * the delay periods are such that the LED's get flashed in sequence. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* States of the I2C master interface. */ +#define mainI2C_IDLE 0 +#define mainI2C_READ_1 1 +#define mainI2C_READ_2 2 +#define mainI2C_READ_DONE 3 + +#define mainZERO_LENGTH 0 + +/* Address of the A2D IC on the CrossFire board. */ +#define mainI2CAddress 0x4D + +/* The queue used to send data from the I2C ISR to the co-routine should never +contain more than one item as the same co-routine is used to trigger the I2C +activity. */ +#define mainQUEUE_LENGTH 1 + +/* The CrossFire board contains a tri-colour LED. */ +#define mainNUM_LEDs 3 + +/* The I2C co-routine has a higher priority than the flash co-routines. This +is not really necessary as when the I2C co-routine is active the other +co-routines are delaying. */ +#define mainI2c_CO_ROUTINE_PRIORITY 1 + + +/* The current state of the I2C master. */ +static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE; + +/* The delay period derived from the A2D value. */ +static volatile portBASE_TYPE uxDelay = 250; + +/* The queue used to communicate between the I2C interrupt and the I2C +co-routine. */ +static xQueueHandle xADCQueue; + +/* The queue used to synchronise the flash co-routines. */ +static xQueueHandle xDelayQueue; + +/* + * Sets up the PLL, I2C and GPIO used by the demo. + */ +static void prvSetupHardware( void ); + +/* The co-routines as described at the top of the file. */ +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +unsigned portBASE_TYPE uxCoRoutine; + + /* Setup all the hardware used by this demo. */ + prvSetupHardware(); + + /* Create the queue used to communicate between the ISR and I2C co-routine. + This can only ever contain one value. */ + xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) ); + + /* Create the queue used to synchronise the flash co-routines. The queue + is used to trigger three tasks, but is for synchronisation only and does + not pass any data. It therefore has three position each of zero length. */ + xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH ); + + /* Create the co-routine that initiates the i2c. */ + xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 ); + + /* Create the flash co-routines. */ + for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ ) + { + xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine ); + } + + /* Start the scheduler. From this point on the co-routines should + execute. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Enable the I2C used to read the pot. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB ); + GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 ); + + /* Initialize the I2C master. */ + I2CMasterInit( I2C_MASTER_BASE, pdFALSE ); + + /* Enable the I2C master interrupt. */ + I2CMasterIntEnable( I2C_MASTER_BASE ); + IntEnable( INT_I2C ); + + /* Initialise the hardware used to talk to the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xADCResult; +static portBASE_TYPE xResult = 0, xMilliSecs, xLED; + + crSTART( xHandle ); + + for( ;; ) + { + /* Start the I2C off to read the ADC. */ + uxState = mainI2C_READ_1; + I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE ); + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START ); + + /* Wait to receive the conversion result. */ + crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult ); + + /* Scale the result to give a useful range of values for a visual + demo. */ + xADCResult >>= 2; + xMilliSecs = xADCResult / portTICK_RATE_MS; + + /* The delay is split between the four co-routines so they remain in + synch. */ + uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 ); + + /* Trigger each of the flash co-routines. */ + for( xLED = 0; xLED < mainNUM_LEDs; xLED++ ) + { + crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult ); + } + + /* Wait for the full delay time then start again. This delay is long + enough to ensure the flash co-routines have done their thing and gone + back to sleep. */ + crDELAY( xHandle, xMilliSecs ); + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portBASE_TYPE xResult, xNothing; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for start of next round. */ + crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult ); + + /* Wait until it is this co-routines turn to flash. */ + crDELAY( xHandle, uxDelay * uxIndex ); + + /* Turn on the LED for a fixed period. */ + vParTestSetLED( uxIndex, pdTRUE ); + crDELAY( xHandle, uxDelay ); + vParTestSetLED( uxIndex, pdFALSE ); + + /* Go back and wait for the next round. */ + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +void vI2C_ISR(void) +{ +static portTickType xReading; + + /* Clear the interrupt. */ + I2CMasterIntClear( I2C_MASTER_BASE ); + + /* Determine what to do based on the current uxState. */ + switch (uxState) + { + case mainI2C_IDLE: break; + + case mainI2C_READ_1: /* Read ADC result high byte. */ + xReading = I2CMasterDataGet( I2C_MASTER_BASE ); + xReading <<= 8; + + /* Continue the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT ); + uxState = mainI2C_READ_2; + break; + + case mainI2C_READ_2: /* Read ADC result low byte. */ + xReading |= I2CMasterDataGet( I2C_MASTER_BASE ); + + /* Finish the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH ); + uxState = mainI2C_READ_DONE; + break; + + case mainI2C_READ_DONE: /* Complete. */ + I2CMasterDataGet( I2C_MASTER_BASE ); + uxState = mainI2C_IDLE; + + /* Send the result to the co-routine. */ + crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE ); + break; + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + for( ;; ) + { + vCoRoutineSchedule(); + } +} + diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s new file mode 100644 index 000000000..08d745339 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s @@ -0,0 +1,116 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vI2C_ISR + .extern faultisr + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ + .word reset_handler + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word UART0_ISR + .word UART1_ISR + .word SSI_ISR + .word vI2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + + + + diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp new file mode 100644 index 000000000..1111b0c89 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs new file mode 100644 index 000000000..4bc06d1fc --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h new file mode 100644 index 000000000..3eb2ebcb6 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h @@ -0,0 +1,20 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" +#include "hw_i2c.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" +#include "i2c.h" + +#endif diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt b/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt new file mode 100644 index 000000000..cba31f7dc --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h new file mode 100644 index 000000000..a4c307b8c --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h @@ -0,0 +1,112 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h new file mode 100644 index 000000000..a93771bdb --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h new file mode 100644 index 000000000..2f259bd23 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h new file mode 100644 index 000000000..633254874 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h new file mode 100644 index 000000000..cdc9a5b19 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h new file mode 100644 index 000000000..81fb0b064 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1 +// registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1 +// registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register + +#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h new file mode 100644 index 000000000..8dd755c2b --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask +#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h new file mode 100644 index 000000000..ddba2fd9d --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h new file mode 100644 index 000000000..3e2e9ee93 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h @@ -0,0 +1,157 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status + +#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h new file mode 100644 index 000000000..d32cec40b --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h new file mode 100644 index 000000000..bef5dc618 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h new file mode 100644 index 000000000..77dfe716a --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h new file mode 100644 index 000000000..37472329f --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h new file mode 100644 index 000000000..044fec21d --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h new file mode 100644 index 000000000..9bad906b2 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h @@ -0,0 +1,233 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h new file mode 100644 index 000000000..a944f6662 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h new file mode 100644 index 000000000..40b6ab2a6 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h new file mode 100644 index 000000000..6ae5dff54 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h @@ -0,0 +1,99 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_CAUSE 0x0000041C // Cause register +#define WDT_O_LOCK 0x00000C00 // Lock register + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CAUSE register. +// +//***************************************************************************** +#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred +#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register + +#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h new file mode 100644 index 000000000..e48c98d87 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h new file mode 100644 index 000000000..23424af4e --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a b/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a new file mode 100644 index 000000000..c465e8f71 Binary files /dev/null and b/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a differ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c new file mode 100644 index 000000000..1e82ed8a8 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h new file mode 100644 index 000000000..aba74cd71 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h new file mode 100644 index 000000000..ef53b348b --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h new file mode 100644 index 000000000..2e1d1e48c --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h new file mode 100644 index 000000000..4f70259ba --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h @@ -0,0 +1,53 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h new file mode 100644 index 000000000..306b141db --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h new file mode 100644 index 000000000..ea39859d2 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h new file mode 100644 index 000000000..2a82b7200 --- /dev/null +++ b/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/Demo/Common/Full/BlockQ.c b/Demo/Common/Full/BlockQ.c new file mode 100644 index 000000000..6d1699762 --- /dev/null +++ b/Demo/Common/Full/BlockQ.c @@ -0,0 +1,308 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + * \page BlockQC blockQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + Reversed the priority and block times of the second two demo tasks so + they operate as per the description above. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" +#include "print.h" + +#define blckqSTACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static void vBlockingQueueProducer( void *pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static void vBlockingQueueConsumer( void *pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueProducer( void *pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const portCHAR * const pcTaskStartMsg = "Blocking queue producer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Could not post on blocking queue\r\n"; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueConsumer( void *pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const portCHAR * const pcTaskStartMsg = "Blocking queue consumer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n"; +portSHORT sErrorEverOccurred = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/Demo/Common/Full/PollQ.c b/Demo/Common/Full/PollQ.c new file mode 100644 index 000000000..b8ab81506 --- /dev/null +++ b/Demo/Common/Full/PollQ.c @@ -0,0 +1,225 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/** + * This is a very simple queue test. See the BlockQ. c documentation for a more + * comprehensive version. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + * + * \page PollQC pollQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "print.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE ( ( unsigned portSHORT ) 128 ) + +/* The task that posts the incrementing number onto the queue. */ +static void vPolledQueueProducer( void *pvParameters ); + +/* The task that empties the queue. */ +static void vPolledQueueConsumer( void *pvParameters ); + +/* Variables that are used to check that the tasks are still running with no errors. */ +static volatile portSHORT sPollingConsumerCount = 0, sPollingProducerCount = 0; +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; +const unsigned portBASE_TYPE uxQueueSize = 10; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); + xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueProducer( void *pvParameters ) +{ +unsigned portSHORT usValue = 0, usLoop; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const unsigned portSHORT usNumToProduce = 3; +const portCHAR * const pcTaskStartMsg = "Polled queue producer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Could not post on polled queue.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + for( usLoop = 0; usLoop < usNumToProduce; ++usLoop ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSend( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS ) + { + /* We should never find the queue full - this is an error. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + } + else + { + if( sError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + ++sPollingProducerCount; + } + + /* Update the value we are going to post next time around. */ + ++usValue; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueConsumer( void *pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const portCHAR * const pcTaskStartMsg = "Polled queue consumer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *pxQueue ) ) + { + if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + /* Catch-up to the value we received so our next expected value + should again be correct. */ + usExpectedValue = usData; + } + else + { + if( sError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + ++sPollingConsumerCount; + } + } + ++usExpectedValue; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +static portSHORT sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0; +portBASE_TYPE xReturn; + + if( ( sLastPollingConsumerCount == sPollingConsumerCount ) || + ( sLastPollingProducerCount == sPollingProducerCount ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastPollingConsumerCount = sPollingConsumerCount; + sLastPollingProducerCount = sPollingProducerCount; + + return xReturn; +} diff --git a/Demo/Common/Full/comtest.c b/Demo/Common/Full/comtest.c new file mode 100644 index 000000000..16f7637ca --- /dev/null +++ b/Demo/Common/Full/comtest.c @@ -0,0 +1,332 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Creates two tasks that operate on an interrupt driven serial port. A loopback + * connector should be used so that everything that is transmitted is also received. + * The serial port does not use any flow control. On a standard 9way 'D' connector + * pins two and three should be connected together. + * + * The first task repeatedly sends a string to a queue, character at a time. The + * serial port interrupt will empty the queue and transmit the characters. The + * task blocks for a pseudo random period before resending the string. + * + * The second task blocks on a queue waiting for a character to be received. + * Characters received by the serial port interrupt routine are posted onto the + * queue - unblocking the task making it ready to execute. If this is then the + * highest priority task ready to run it will run immediately - with a context + * switch occurring at the end of the interrupt service routine. The task + * receiving characters is spawned with a higher priority than the task + * transmitting the characters. + * + * With the loop back connector in place, one task will transmit a string and the + * other will immediately receive it. The receiving task knows the string it + * expects to receive so can detect an error. + * + * This also creates a third task. This is used to test semaphore usage from an + * ISR and does nothing interesting. + * + * \page ComTestC comtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + The priority of the Rx task has been lowered. Received characters are + now processed (read from the queue) at the idle priority, allowing low + priority tasks to run evenly at times of a high communications overhead. + +Changes from V1.01: + + + The Tx task now waits a pseudo random time between transissions. + Previously a fixed period was used but this was not such a good test as + interrupts fired at regular intervals. + +Changes From V1.2.0: + + + Use vSerialPutString() instead of single character puts. + + Only stop the check variable incrementing after two consecutive errors. + +Changed from V1.2.5 + + + Made the Rx task 2 priorities higher than the Tx task. Previously it was + only 1. This is done to tie in better with the other demo application + tasks. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + Slight modification to task priorities. + +*/ + + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "print.h" + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 ) + +#define comMAX_CONSECUTIVE_ERRORS ( 2 ) + +#define comSTACK_SIZE ( ( unsigned portSHORT ) 256 ) + +#define comRX_RELATIVE_PRIORITY ( 1 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort; + +/* The transmit function as described at the top of the file. */ +static void vComTxTask( void *pvParameters ); + +/* The receive function as described at the top of the file. */ +static void vComRxTask( void *pvParameters ); + +/* The semaphore test function as described at the top of the file. */ +static void vSemTestTask( void * pvParameters ); + +/* The string that is repeatedly transmitted. */ +const portCHAR * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. " + "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"; + +/* Variables that are incremented on each cycle of each task. These are used to +check that both tasks are still executing. */ +volatile portSHORT sTxCount = 0, sRxCount = 0, sSemCount = 0; + + +/*-----------------------------------------------------------*/ + +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ) +{ +const unsigned portBASE_TYPE uxBufferLength = 255; + + /* Initialise the com port then spawn both tasks. */ + xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength ); + xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL ); + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL ); + xTaskCreate( vSemTestTask, "ISRSemTst", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vComTxTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "COM Tx task started.\r\n"; +portTickType xTimeToWait; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Send the string to the serial port. */ + vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) ); + + /* We have posted all the characters in the string - increment the variable + used to check that this task is still running, then wait before re-sending + the string. */ + sTxCount++; + + xTimeToWait = xTaskGetTickCount(); + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vComRxTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "COM Rx task started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "COM read error\r\n"; +const portCHAR * const pcTaskRestartMsg = "COM resynced\r\n"; +const portCHAR * const pcTaskTimeoutMsg = "COM Rx timed out\r\n"; +const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS; +const portCHAR *pcExpectedChar; +portBASE_TYPE xGotChar; +portCHAR cRxedChar; +portSHORT sResyncRequired, sConsecutiveErrors, sLatchedError; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The first expected character is the first character in the string. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + sConsecutiveErrors = 0; + sLatchedError = pdFALSE; + + for( ;; ) + { + /* Receive a message from the com port interrupt routine. If a message is + not yet available the call will block the task. */ + xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime ); + if( xGotChar == pdTRUE ) + { + if( sResyncRequired == pdTRUE ) + { + /* We got out of sequence and are waiting for the start of the next + transmission of the string. */ + if( cRxedChar == '\n' ) + { + /* This is the end of the message so we can start again - with + the first character in the string being the next thing we expect + to receive. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + + /* Queue a message for printing to say that we are going to try + again. */ + vPrintDisplayMessage( &pcTaskRestartMsg ); + + /* Stop incrementing the check variable, if consecutive errors occur. */ + sConsecutiveErrors++; + if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS ) + { + sLatchedError = pdTRUE; + } + } + } + else + { + /* We have received a character, but is it the expected character? */ + if( cRxedChar != *pcExpectedChar ) + { + /* This was not the expected character so post a message for + printing to say that an error has occurred. We will then wait + to resynchronise. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sResyncRequired = pdTRUE; + } + else + { + /* This was the expected character so next time we will expect + the next character in the string. Wrap back to the beginning + of the string when the null terminator has been reached. */ + pcExpectedChar++; + if( *pcExpectedChar == '\0' ) + { + pcExpectedChar = pcMessageToExchange; + + /* We have got through the entire string without error. */ + sConsecutiveErrors = 0; + } + } + } + + /* Increment the count that is used to check that this task is still + running. This is only done if an error has never occurred. */ + if( sLatchedError == pdFALSE ) + { + sRxCount++; + } + } + else + { + vPrintDisplayMessage( &pcTaskTimeoutMsg ); + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vSemTestTask( void * pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "ISR Semaphore test started.\r\n"; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xSerialWaitForSemaphore( xPort ) ) + { + sSemCount++; + } + } +} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +static portSHORT sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0; +portBASE_TYPE xReturn; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. */ + + if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastTxCount = sTxCount; + sLastRxCount = sRxCount; + sLastSemCount = sSemCount; + + return xReturn; +} + diff --git a/Demo/Common/Full/death.c b/Demo/Common/Full/death.c new file mode 100644 index 000000000..765932dfe --- /dev/null +++ b/Demo/Common/Full/death.c @@ -0,0 +1,208 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * four tasks. The original task is called the creator task, the four tasks it + * creates are called suicidal tasks. + * + * Two of the created suicidal tasks kill one other suicidal task before killing + * themselves - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" +#include "print.h" + +#define deathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static void vCreateTasks( void *pvParameters ); + +/* The task function of the dynamically created tasks. */ +static void vSuicidalTask( void *pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile portSHORT sCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. */ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5; + +/* Used to store a handle to the tasks that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask1, xCreatedTask2; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = uxTaskGetNumberOfTasks(); +} +/*-----------------------------------------------------------*/ + +static void vSuicidalTask( void *pvParameters ) +{ +portDOUBLE d1, d2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Tow created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + d1 = 2.4; + d2 = 89.2; + d2 *= d1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static void vCreateTasks( void *pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; +const portCHAR * const pcTaskStartMsg = "Create task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); + + ++sCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static portSHORT sLastCreationCount = 0; +portSHORT sReturn = pdTRUE; +unsigned portBASE_TYPE uxTasksRunningNow; + + if( sLastCreationCount == sCreationCount ) + { + sReturn = pdFALSE; + } + + uxTasksRunningNow = uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + sReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + sReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return sReturn; +} + + diff --git a/Demo/Common/Full/dynamic.c b/Demo/Common/Full/dynamic.c new file mode 100644 index 000000000..6529f441a --- /dev/null +++ b/Demo/Common/Full/dynamic.c @@ -0,0 +1,571 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + * + * The final set of two tasks implements a third test. This simply raises the + * priority of a task while the scheduler is suspended. Again this test was + * added to exercise parts of the code not covered by the first test. + * + * \page Priorities dynamic.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + Added a second, simple test that uses the functions + vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask(). + +Changes from V3.1.1 + + + Added a third simple test that uses the vTaskPrioritySet() function + while the scheduler is suspended. + + Modified the controller task slightly to test the calling of + vTaskResumeAll() while the scheduler is suspended. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" +#include "print.h" + +/* Function that implements the "limited count" task as described above. */ +static void vLimitedIncrementTask( void * pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static void vContinuousIncrementTask( void * pvParameters ); + +/* Function that implements the controller task as described above. */ +static void vCounterControlTask( void * pvParameters ); + +/* The simple test functions that check sending and receiving while the +scheduler is suspended. */ +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ); +static void vQueueSendWhenSuspendedTask( void *pvParameters ); + +/* The simple test functions that check raising and lowering of task priorities +while the scheduler is suspended. */ +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ); +static void prvChangePriorityHelperTask( void *pvParameters ); + + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define priSLEEP_TIME ( ( portTickType ) 50 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static unsigned portLONG ulCounter; + +/* Variable used in a similar way by the test that checks the raising and +lowering of task priorities while the scheduler is suspended. */ +static unsigned portLONG ulPrioritySetCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; +static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ +/* + * Start the seven tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); + xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + xTaskCreate( prvChangePriorityHelperTask, "2nt_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static void vLimitedIncrementTask( void * pvParameters ) +{ +unsigned portLONG *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static void vContinuousIncrementTask( void * pvParameters ) +{ +unsigned portLONG *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise our priority above the controller task to ensure a context + switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static void vCounterControlTask( void * pvParameters ) +{ +unsigned portLONG ulLastCounter; +portSHORT sLoops; +portSHORT sError = pdFALSE; +const portCHAR * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned portLONG ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. */ + vTaskSuspend( xContinuousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinuousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + } + xTaskResumeAll(); + } + + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned portLONG ) 0; + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. + The scheduler suspension is not necessary but is included for test + purposes. */ + vTaskSuspendAll(); + vTaskResume( xLimitedIncrementHandle ); + xTaskResumeAll(); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static void vQueueSendWhenSuspendedTask( void *pvParameters ) +{ +static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; +const portCHAR * const pcTaskStartMsg = "Queue send while suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Queue send while suspended failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + if( xSuspendedQueueSendError == pdFALSE ) + { + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ) +{ +static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; +const portCHAR * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n"; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + if( xSuspendedQueueReceiveError == pdFALSE ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + } + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "Priority change when suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at 0 so we know what the counter should be + when we check it next. */ + ulPrioritySetCounter = ( unsigned portLONG ) 0; + + /* Resume the helper task. At this time it has a priority lower than + ours so no context switch should occur. */ + vTaskResume( xChangePriorityWhenSuspendedHandle ); + + /* Check to ensure the task just resumed has not executed. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Now try raising the priority while the scheduler is suspended. */ + vTaskSuspendAll(); + { + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) ); + + /* Again, even though the helper task has a priority greater than + ours, it should not have executed yet because the scheduler is + suspended. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + } + xTaskResumeAll(); + + /* Now the scheduler has been resumed the helper task should + immediately preempt us and execute. When it executes it will increment + the ulPrioritySetCounter exactly once before suspending itself. + + We should now always find the counter set to 1. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 1 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Delay until we try this again. */ + vTaskDelay( priSLEEP_TIME * 2 ); + + /* Set the priority of the helper task back ready for the next + execution of this task. */ + vTaskSuspendAll(); + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityHelperTask( void *pvParameters ) +{ + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This is the helper task for prvChangePriorityWhenSuspendedTask(). + It has it's priority raised and lowered. When it runs it simply + increments the counter then suspends itself again. This allows + prvChangePriorityWhenSuspendedTask() to know how many times it has + executed. */ + ulPrioritySetCounter++; + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xPriorityRaiseWhenSuspendedError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} + + + + diff --git a/Demo/Common/Full/events.c b/Demo/Common/Full/events.c new file mode 100644 index 000000000..4ec348081 --- /dev/null +++ b/Demo/Common/Full/events.c @@ -0,0 +1,375 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * This file exercises the event mechanism whereby more than one task is + * blocked waiting for the same event. + * + * The demo creates five tasks - four 'event' tasks, and a controlling task. + * The event tasks have various different priorities and all block on reading + * the same queue. The controlling task writes data to the queue, then checks + * to see which of the event tasks read the data from the queue. The + * controlling task has the lowest priority of all the tasks so is guaranteed + * to always get preempted immediately upon writhing to the queue. + * + * By selectively suspending and resuming the event tasks the controlling task + * can check that the highest priority task that is blocked on the queue is the + * task that reads the posted data from the queue. + * + * Two of the event tasks share the same priority. When neither of these tasks + * are suspended they should alternate - one reading one message from the queue, + * the other the next message, etc. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "mevents.h" +#include "print.h" + +/* Demo specific constants. */ +#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) 128 ) +#define evtNUM_TASKS ( 4 ) +#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 ) +#define evtNO_DELAY 0 + +/* Just indexes used to uniquely identify the tasks. Note that two tasks are +'highest' priority. */ +#define evtHIGHEST_PRIORITY_INDEX_2 3 +#define evtHIGHEST_PRIORITY_INDEX_1 2 +#define evtMEDIUM_PRIORITY_INDEX 1 +#define evtLOWEST_PRIORITY_INDEX 0 + +/* Each event task increments one of these counters each time it reads data +from the queue. */ +static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Each time the controlling task posts onto the queue it increments the +expected count of the task that it expected to read the data from the queue +(i.e. the task with the highest priority that should be blocked on the queue). + +xExpectedTaskCounters are incremented from the controlling task, and +xTaskCounters are incremented from the individual event tasks - therefore +comparing xTaskCounters to xExpectedTaskCounters shows whether or not the +correct task was unblocked by the post. */ +static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Handles to the four event tasks. These are required to suspend and resume +the tasks. */ +static xTaskHandle xCreatedTasks[ evtNUM_TASKS ]; + +/* The single queue onto which the controlling task posts, and the four event +tasks block. */ +static xQueueHandle xQueue; + +/* Flag used to indicate whether or not an error has occurred at any time. +An error is either the queue being full when not expected, or an unexpected +task reading data from the queue. */ +static portBASE_TYPE xHealthStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* Function that implements the event task. This is created four times. */ +static void prvMultiEventTask( void *pvParameters ); + +/* Function that implements the controlling task. */ +static void prvEventControllerTask( void *pvParameters ); + +/* This is a utility function that posts data to the queue, then compares +xExpectedTaskCounters with xTaskCounters to ensure everything worked as +expected. + +The event tasks all have higher priorities the controlling task. Therefore +the controlling task will always get preempted between writhing to the queue +and checking the task counters. + +@param xExpectedTask The index to the task that the controlling task thinks + should be the highest priority task waiting for data, and + therefore the task that will unblock. + +@param xIncrement The number of items that should be written to the queue. +*/ +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ); + +/* This is just incremented each cycle of the controlling tasks function so +the main application can ensure the test is still running. */ +static portBASE_TYPE xCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartMultiEventTasks( void ) +{ + /* Create the queue to be used for all the communications. */ + xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + /* Start the controlling task. This has the idle priority to ensure it is + always preempted by the event tasks. */ + xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the four event tasks. Note that two have priority 3, one + priority 2 and the other priority 1. */ + xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) ); + xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void prvMultiEventTask( void *pvParameters ) +{ +portBASE_TYPE *pxCounter; +unsigned portBASE_TYPE uxDummy; +const portCHAR * const pcTaskStartMsg = "Multi event task started.\r\n"; + + /* The variable this task will increment is passed in as a parameter. */ + pxCounter = ( portBASE_TYPE * ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Block on the queue. */ + if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) ) + { + /* We unblocked by reading the queue - so simply increment + the counter specific to this task instance. */ + ( *pxCounter )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvEventControllerTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "Multi event controller task started.\r\n"; +portBASE_TYPE xDummy = 0; + + /* Just to stop warnings. */ + ( void ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* All tasks are blocked on the queue. When a message is posted one of + the two tasks that share the highest priority should unblock to read + the queue. The next message written should unblock the other task with + the same high priority, and so on in order. No other task should + unblock to read data as they have lower priorities. */ + + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* For the rest of these tests we don't need the second 'highest' + priority task - so it is suspended. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + + + /* Now suspend the other highest priority task. The medium priority + task will then be the task with the highest priority that remains + blocked on the queue. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + /* This time, when we post onto the queue we will expect the medium + priority task to unblock and preempt us. */ + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + /* Now try resuming the highest priority task while the scheduler is + suspended. The task should start executing as soon as the scheduler + is resumed - therefore when we post to the queue again, the highest + priority task should again preempt us. */ + vTaskSuspendAll(); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now we are going to suspend the high and medium priority tasks. The + low priority task should then preempt us. Again the task suspension is + done with the whole scheduler suspended just for test purposes. */ + vTaskSuspendAll(); + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + + + /* Do the same basic test another few times - selectively suspending + and resuming tasks and each time calling prvCheckTaskCounters() passing + to the function the number of the task we expected to be unblocked by + the post. */ + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for even more test. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + xTaskResumeAll(); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + + + + + /* Now a slight change, first suspend all tasks. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* Now when we resume the low priority task and write to the queue 3 + times. We expect the low priority task to service the queue three + times. */ + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH ); + + /* Again suspend all tasks (only the low priority task is not suspended + already). */ + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* This time we are going to suspend the scheduler, resume the low + priority task, then resume the high priority task. In this state we + will write to the queue three times. When the scheduler is resumed + we expect the high priority task to service all three messages. */ + vTaskSuspendAll(); + { + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + xHealthStatus = pdFAIL; + } + } + + /* The queue should not have been serviced yet!. The scheduler + is still suspended. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + } + xTaskResumeAll(); + + /* We should have been preempted by resuming the scheduler - so by the + time we are running again we expect the high priority task to have + removed three items from the queue. */ + xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH; + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + + /* The medium priority and second high priority tasks are still + suspended. Make sure to resume them before starting again. */ + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + /* Just keep incrementing to show the task is still executing. */ + xCheckVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ) +{ +portBASE_TYPE xDummy = 0; + + /* Write to the queue the requested number of times. The data written is + not important. */ + for( xDummy = 0; xDummy < xIncrement; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + /* Did not expect to ever find the queue full. */ + xHealthStatus = pdFAIL; + } + } + + /* All the tasks blocked on the queue have a priority higher than the + controlling task. Writing to the queue will therefore have caused this + task to be preempted. By the time this line executes the event task will + have executed and incremented its counter. Increment the expected counter + to the same value. */ + ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement; + + /* Check the actual counts and expected counts really are the same. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + /* The counters were not the same. This means a task we did not expect + to unblock actually did unblock. */ + xHealthStatus = pdFAIL; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreMultiEventTasksStillRunning( void ) +{ +static portBASE_TYPE xPreviousCheckVariable = 0; + + /* Called externally to periodically check that this test is still + operational. */ + + if( xPreviousCheckVariable == xCheckVariable ) + { + xHealthStatus = pdFAIL; + } + + xPreviousCheckVariable = xCheckVariable; + + return xHealthStatus; +} + + diff --git a/Demo/Common/Full/flash.c b/Demo/Common/Full/flash.c new file mode 100644 index 000000000..3d3ca391f --- /dev/null +++ b/Demo/Common/Full/flash.c @@ -0,0 +1,133 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/** + * Creates eight tasks, each of which flash an LED at a different rate. The first + * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F. + * + * \page flashC flash.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" +#include "print.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE + +/* Structure used to pass parameters to the LED tasks. */ +typedef struct LED_PARAMETERS +{ + unsigned portBASE_TYPE uxLED; /*< The output the task should use. */ + portTickType xFlashRate; /*< The rate at which the LED should flash. */ +} xLEDParameters; + +/* The task that is created eight times - each time with a different xLEDParaemtes +structure passed in as the parameter. */ +static void vLEDFlashTask( void *pvParameters ); + +/* String to print if USE_STDIO is defined. */ +const portCHAR * const pcTaskStartMsg = "LED flash task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE uxLEDTask; +xLEDParameters *pxLEDParameters; +const unsigned portBASE_TYPE uxNumOfLEDs = 8; +const portTickType xFlashRate = 125; + + /* Create the eight tasks. */ + for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask ) + { + /* Create and complete the structure used to pass parameters to the next + created task. */ + pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) ); + pxLEDParameters->uxLED = uxLEDTask; + pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) ); + pxLEDParameters->xFlashRate /= portTICK_RATE_MS; + + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void vLEDFlashTask( void *pvParameters ) +{ +xLEDParameters *pxParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxParameters = ( xLEDParameters * ) pvParameters; + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + } +} + diff --git a/Demo/Common/Full/flop.c b/Demo/Common/Full/flop.c new file mode 100644 index 000000000..4b9b2c98f --- /dev/null +++ b/Demo/Common/Full/flop.c @@ -0,0 +1,336 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * \page FlopC flop.c + * \ingroup DemoFiles + *
+ */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static void vCompetingMathTask1( void *pvParameters ); +static void vCompetingMathTask2( void *pvParameters ); +static void vCompetingMathTask3( void *pvParameters ); +static void vCompetingMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask1( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222; +const portCHAR * const pcTaskStartMsg = "Math task 1 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 1 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask2( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001; +const portCHAR * const pcTaskStartMsg = "Math task 2 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 2 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask3( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Math task 3 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 3 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5; + dTotal1 += ( portDOUBLE ) usPosition + 5.5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask4( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Math task 4 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 4 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123; + dTotal1 += ( portDOUBLE ) usPosition * 12.123; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/Demo/Common/Full/integer.c b/Demo/Common/Full/integer.c new file mode 100644 index 000000000..0b571ea43 --- /dev/null +++ b/Demo/Common/Full/integer.c @@ -0,0 +1,332 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * This does the same as flop. c, but uses variables of type long instead of + * type double. + * + * As with flop. c, the tasks created in this file are a good test of the + * scheduler context switch mechanism. The processor has to access 32bit + * variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See the flop. c documentation for + * more information. + * + * \page IntegerC integer.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.1 + + + The constants used in the calculations are larger to ensure the + optimiser does not truncate them to 16 bits. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "integer.h" + +#define intgSTACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define intgNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different calculation on four byte +variables. Each of the four is created twice. */ +static void vCompeteingIntMathTask1( void *pvParameters ); +static void vCompeteingIntMathTask2( void *pvParameters ); +static void vCompeteingIntMathTask3( void *pvParameters ); +static void vCompeteingIntMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask1( void *pvParameters ) +{ +portLONG l1, l2, l3, l4; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portLONG lAnswer = ( ( portLONG ) 74565L + ( portLONG ) 1234567L ) * ( portLONG ) -918L; +const portCHAR * const pcTaskStartMsg = "Integer math task 1 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 1 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + l1 = ( portLONG ) 74565L; + l2 = ( portLONG ) 1234567L; + l3 = ( portLONG ) -918L; + + l4 = ( l1 + l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask2( void *pvParameters ) +{ +portLONG l1, l2, l3, l4; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portLONG lAnswer = ( ( portLONG ) -389000L / ( portLONG ) 329999L ) * ( portLONG ) -89L; +const portCHAR * const pcTaskStartMsg = "Integer math task 2 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 2 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + l1 = -389000L; + l2 = 329999L; + l3 = -89L; + + l4 = ( l1 / l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask3( void *pvParameters ) +{ +portLONG *plArray, lTotal1, lTotal2; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = ( unsigned portSHORT ) 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Integer math task 3 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 3 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( portLONG ) 0; + lTotal2 = ( portLONG ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( portLONG ) usPosition + ( portLONG ) 5; + lTotal1 += ( portLONG ) usPosition + ( portLONG ) 5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask4( void *pvParameters ) +{ +portLONG *plArray, lTotal1, lTotal2; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Integer math task 4 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 4 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( portLONG ) 0; + lTotal2 = ( portLONG ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( portLONG ) usPosition * ( portLONG ) 12; + lTotal1 += ( portLONG ) usPosition * ( portLONG ) 12; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/Demo/Common/Full/print.c b/Demo/Common/Full/print.c new file mode 100644 index 000000000..a6e849a70 --- /dev/null +++ b/Demo/Common/Full/print.c @@ -0,0 +1,111 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Manages a queue of strings that are waiting to be displayed. This is used to + * ensure mutual exclusion of console output. + * + * A task wishing to display a message will call vPrintDisplayMessage (), with a + * pointer to the string as the parameter. The pointer is posted onto the + * xPrintQueue queue. + * + * The task spawned in main. c blocks on xPrintQueue. When a message becomes + * available it calls pcPrintGetNextMessage () to obtain a pointer to the next + * string, then uses the functions defined in the portable layer FileIO. c to + * display the message. + * + * NOTE: + * Using console IO can disrupt real time performance - depending on the port. + * Standard C IO routines are not designed for real time applications. While + * standard IO is useful for demonstration and debugging an alternative method + * should be used if you actually require console IO as part of your application. + * + * \page PrintC print.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo program include files. */ +#include "print.h" + +static xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +void vPrintInitialise( void ) +{ +const unsigned portBASE_TYPE uxQueueSize = 20; + + /* Create the queue on which errors will be reported. */ + xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( portCHAR * ) ); +} +/*-----------------------------------------------------------*/ + +void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ) +{ + #ifdef USE_STDIO + xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 ); + #else + /* Stop warnings. */ + ( void ) ppcMessageToSend; + #endif +} +/*-----------------------------------------------------------*/ + +const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ) +{ +portCHAR *pcMessage; + + if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS ) + { + return pcMessage; + } + else + { + return NULL; + } +} + + diff --git a/Demo/Common/Full/semtest.c b/Demo/Common/Full/semtest.c new file mode 100644 index 000000000..32025bc73 --- /dev/null +++ b/Demo/Common/Full/semtest.c @@ -0,0 +1,290 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + * \page SemTestC semtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.0: + + + The tasks that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority tasks from signaling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the high value. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" +#include "print.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static void prvSemaphoreTest( void *pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned portLONG *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile portSHORT sNextCheckVariable = 0; + +/* Strings to print if USE_STDIO is defined. */ +const portCHAR * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n"; +const portCHAR * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSemaphoreTest( void *pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; +unsigned portLONG ulCounter; +portSHORT sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcSemaphoreTaskStart ); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + if( sError == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + } + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/Demo/Common/Minimal/BlockQ.c b/Demo/Common/Minimal/BlockQ.c new file mode 100644 index 000000000..364bca045 --- /dev/null +++ b/Demo/Common/Minimal/BlockQ.c @@ -0,0 +1,280 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable to and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/Demo/Common/Minimal/PollQ.c b/Demo/Common/Minimal/PollQ.c new file mode 100644 index 000000000..df19b87c0 --- /dev/null +++ b/Demo/Common/Minimal/PollQ.c @@ -0,0 +1,216 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This version of PollQ. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqDELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) +#define pollqNO_DELAY ( ( portTickType ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) +#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no +errors. */ +static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, ( const signed portCHAR * const ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( vPolledQueueProducer, ( const signed portCHAR * const ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE, xLoop; + + for( ;; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( pollqDELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) + { + if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( pollqDELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* Check both the consumer and producer poll count to check they have both + been changed since out last trip round. We do not need a critical section + around the check variables as this is called from a higher priority than + the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/Demo/Common/Minimal/comtest.c b/Demo/Common/Minimal/comtest.c new file mode 100644 index 000000000..4a672765a --- /dev/null +++ b/Demo/Common/Minimal/comtest.c @@ -0,0 +1,287 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * This version of comtest. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that operate on an interrupt driven serial port. A + * loopback connector should be used so that everything that is transmitted is + * also received. The serial port does not use any flow control. On a + * standard 9way 'D' connector pins two and three should be connected together. + * + * The first task posts a sequence of characters to the Tx queue, toggling an + * LED on each successful post. At the end of the sequence it sleeps for a + * pseudo-random period before resending the same sequence. + * + * The UART Tx end interrupt is enabled whenever data is available in the Tx + * queue. The Tx end ISR removes a single character from the Tx queue and + * passes it to the UART for transmission. + * + * The second task blocks on the Rx queue waiting for a character to become + * available. When the UART Rx end interrupt receives a character it places + * it in the Rx queue, waking the second task. The second task checks that the + * characters removed from the Rx queue form the same sequence as those posted + * to the Tx queue, and toggles an LED for each correct character. + * + * The receiving task is spawned with a higher priority than the transmitting + * task. The receiver will therefore wake every time a character is + * transmitted so neither the Tx or Rx queue should ever hold more than a few + * characters. + * + */ + +/* +Changes from V1.2.0: + + + Reduced the maximum time between successive transmissions. This provides + for a more rigorous test. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.5.1 + + + The constant comOFFSET_TIME added to the delay period to ensure a more + random delay period is used. +*/ + +/* Scheduler include files. */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "partest.h" + +#define comSTACK_SIZE configMINIMAL_STACK_SIZE +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) +#define comTOTAL_PERMISSIBLE_ERRORS ( 2 ) + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 ) +#define comOFFSET_TIME ( ( portTickType ) 3 ) + +/* We should find that each character can be queued for Tx immediately and we +don't have to block to send. */ +#define comNO_BLOCK ( ( portTickType ) 0 ) + +/* The Rx task will block on the Rx queue for a long period. */ +#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff ) + +/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */ +#define comFIRST_BYTE ( 'A' ) +#define comLAST_BYTE ( 'X' ) + +#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 ) +#define comINITIAL_RX_COUNT_VALUE ( 0 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The transmit task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters ); + +/* The receive task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters ); + +/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will +toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED +( uxBaseLED + comTX_LED_OFFSET ). */ +static unsigned portBASE_TYPE uxBaseLED = 0; + +/* Check variable used to ensure no error have occurred. The Rx task will +increment this variable after every successfully received sequence. If at any +time the sequence is incorrect the the variable will stop being incremented. */ +static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE; + +/*-----------------------------------------------------------*/ + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ) +{ + /* Initialise the com port then spawn the Rx and Tx tasks. */ + uxBaseLED = uxLED; + xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN ); + + /* The Tx task is spawned with a lower priority than the Rx task. */ + xTaskCreate( vComTxTask, ( const signed portCHAR * const ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL ); + xTaskCreate( vComRxTask, ( const signed portCHAR * const ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComTxTask, pvParameters ) +{ +signed portCHAR cByteToSend; +portTickType xTimeToWait; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Simply transmit a sequence of characters from comFIRST_BYTE to + comLAST_BYTE. */ + for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ ) + { + if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS ) + { + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE ); + + /* We have posted all the characters in the string - wait before + re-sending. Wait a pseudo-random time as this will provide a better + test. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComRxTask, pvParameters ) +{ +signed portCHAR cExpectedByte, cByteRxed; +portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* We expect to receive the characters from comFIRST_BYTE to + comLAST_BYTE in an incrementing order. Loop to receive each byte. */ + for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ ) + { + /* Block on the queue that contains received bytes until a byte is + available. */ + if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) ) + { + /* Was this the byte we were expecting? If so, toggle the LED, + otherwise we are out on sync and should break out of the loop + until the expected character sequence is about to restart. */ + if( cByteRxed == cExpectedByte ) + { + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + else + { + xResyncRequired = pdTRUE; + break; /*lint !e960 Non-switch break allowed. */ + } + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE ); + + /* Did we break out of the loop because the characters were received in + an unexpected order? If so wait here until the character sequence is + about to restart. */ + if( xResyncRequired == pdTRUE ) + { + while( cByteRxed != comLAST_BYTE ) + { + /* Block until the next char is available. */ + xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ); + } + + /* Note that an error occurred which caused us to have to resync. + We use this to stop incrementing the loop counter so + sAreComTestTasksStillRunning() will return false - indicating an + error. */ + xErrorOccurred++; + + /* We have now resynced with the Tx task and can continue. */ + xResyncRequired = pdFALSE; + } + else + { + if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS ) + { + /* Increment the count of successful loops. As error + occurring (i.e. an unexpected character being received) will + prevent this counter being incremented for the rest of the + execution. Don't worry about mutual exclusion on this + variable - it doesn't really matter as we just want it + to change. */ + uxRxLoops++; + } + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If the count of successful reception loops has not changed than at + some time an error occurred (i.e. a character was received out of sequence) + and we will return false. */ + if( uxRxLoops == comINITIAL_RX_COUNT_VALUE ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + again we expect this to have been incremented. */ + uxRxLoops = comINITIAL_RX_COUNT_VALUE; + + return xReturn; +} + diff --git a/Demo/Common/Minimal/crflash.c b/Demo/Common/Minimal/crflash.c new file mode 100644 index 000000000..c22b2d7ea --- /dev/null +++ b/Demo/Common/Minimal/crflash.c @@ -0,0 +1,212 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo application file demonstrates the use of queues to pass data + * between co-routines. + * + * N represents the number of 'fixed delay' co-routines that are created and + * is set during initialisation. + * + * N 'fixed delay' co-routines are created that just block for a fixed + * period then post the number of an LED onto a queue. Each such co-routine + * uses a different block period. A single 'flash' co-routine is also created + * that blocks on the same queue, waiting for the number of the next LED it + * should flash. Upon receiving a number it simply toggle the instructed LED + * then blocks on the queue once more. In this manner each LED from LED 0 to + * LED N-1 is caused to flash at a different rate. + * + * The 'fixed delay' co-routines are created with co-routine priority 0. The + * flash co-routine is created with co-routine priority 1. This means that + * the queue should never contain more than a single item. This is because + * posting to the queue will unblock the 'flash' co-routine, and as this has + * a priority greater than the tasks posting to the queue it is guaranteed to + * have emptied the queue and blocked once again before the queue can contain + * any more date. An error is indicated if an attempt to post data to the + * queue fails - indicating that the queue is already full. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "crflash.h" + +/* The queue should only need to be of length 1. See the description at the +top of the file. */ +#define crfQUEUE_LENGTH 1 + +#define crfFIXED_DELAY_PRIORITY 0 +#define crfFLASH_PRIORITY 1 + +/* Only one flash co-routine is created so the index is not significant. */ +#define crfFLASH_INDEX 0 + +/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be +created. */ +#define crfMAX_FLASH_TASKS 8 + +/* We don't want to block when posting to the queue. */ +#define crfPOSTING_BLOCK_TIME 0 + +/* + * The 'fixed delay' co-routine as described at the top of the file. + */ +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The 'flash' co-routine as described at the top of the file. + */ +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* The queue used to pass data between the 'fixed delay' co-routines and the +'flash' co-routine. */ +static xQueueHandle xFlashQueue; + +/* This will be set to pdFALSE if we detect an error. */ +static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* + * See the header file for details. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate ) +{ +unsigned portBASE_TYPE uxIndex; + + if( uxNumberToCreate > crfMAX_FLASH_TASKS ) + { + uxNumberToCreate = crfMAX_FLASH_TASKS; + } + + /* Create the queue used to pass data between the co-routines. */ + xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + if( xFlashQueue ) + { + /* Create uxNumberToCreate 'fixed delay' co-routines. */ + for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) + { + xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); + } + + /* Create the 'flash' co-routine. */ + xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); + } +} +/*-----------------------------------------------------------*/ + +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the xResult variable does not need to be +static as we do not need it to maintain its state between blocks. */ +portBASE_TYPE xResult; +/* The uxIndex parameter of the co-routine function is used as an index into +the xFlashRates array to obtain the delay period to use. */ +static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, + 200 / portTICK_RATE_MS, + 250 / portTICK_RATE_MS, + 300 / portTICK_RATE_MS, + 350 / portTICK_RATE_MS, + 400 / portTICK_RATE_MS, + 450 / portTICK_RATE_MS, + 500 / portTICK_RATE_MS }; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ;; ) + { + /* Post our uxIndex value onto the queue. This is used as the LED to + flash. */ + crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* For the reasons stated at the top of the file we should always + find that we can post to the queue. If we could not then an error + has occurred. */ + uxCoRoutineFlashStatus = pdFAIL; + } + + crDELAY( xHandle, xFlashRates[ uxIndex ] ); + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the variable do not need to be +static as we do not need it to maintain their state between blocks. */ +portBASE_TYPE xResult; +unsigned portBASE_TYPE uxLEDToFlash; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ;; ) + { + /* Block to wait for the number of the LED to flash. */ + crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + + if( xResult != pdPASS ) + { + /* We would not expect to wake unless we received something. */ + uxCoRoutineFlashStatus = pdFAIL; + } + else + { + /* We received the number of an LED to flash - flash it! */ + vParTestToggleLED( uxLEDToFlash ); + } + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ) +{ + /* Return pdPASS or pdFAIL depending on whether an error has been detected + or not. */ + return uxCoRoutineFlashStatus; +} + diff --git a/Demo/Common/Minimal/crhook.c b/Demo/Common/Minimal/crhook.c new file mode 100644 index 000000000..ee9952201 --- /dev/null +++ b/Demo/Common/Minimal/crhook.c @@ -0,0 +1,237 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This demo file demonstrates how to send data between an ISR and a + * co-routine. A tick hook function is used to periodically pass data between + * the RTOS tick and a set of 'hook' co-routines. + * + * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks + * to wait for a character to be received on a queue from the tick ISR, checks + * to ensure the character received was that expected, then sends the number + * back to the tick ISR on a different queue. + * + * The tick ISR checks the numbers received back from the 'hook' co-routines + * matches the number previously sent. + * + * If at any time a queue function returns unexpectedly, or an incorrect value + * is received either by the tick hook or a co-routine then an error is + * latched. + * + * This demo relies on each 'hook' co-routine to execute between each + * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of + * queues from within an interrupt may result in an error being detected on + * slower targets simply due to timing. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "crhook.h" + +/* The number of 'hook' co-routines that are to be created. */ +#define hookNUM_HOOK_CO_ROUTINES ( 4 ) + +/* The number of times the tick hook should be called before a character is +posted to the 'hook' co-routines. */ +#define hookTICK_CALLS_BEFORE_POST ( 250 ) + +/* There should never be more than one item in any queue at any time. */ +#define hookHOOK_QUEUE_LENGTH ( 1 ) + +/* Don't block when initially posting to the queue. */ +#define hookNO_BLOCK_TIME ( 0 ) + +/* The priority relative to other co-routines (rather than tasks) that the +'hook' co-routines should take. */ +#define mainHOOK_CR_PRIORITY ( 1 ) +/*-----------------------------------------------------------*/ + +/* + * The co-routine function itself. + */ +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + + +/* + * The tick hook function. This receives a number from each 'hook' co-routine + * then sends a number to each co-routine. An error is flagged if a send or + * receive fails, or an unexpected number is received. + */ +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* Queues used to send data FROM a co-routine TO the tick hook function. +The hook functions received (Rx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Queues used to send data FROM the tick hook TO a co-routine function. +The hood function transmits (Tx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Set to true if an error is detected at any time. */ +static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartHookCoRoutines( void ) +{ +unsigned portBASE_TYPE uxIndex, uxValueToPost = 0; + + for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ ) + { + /* Create a queue to transmit to and receive from each 'hook' + co-routine. */ + xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + /* To start things off the tick hook function expects the queue it + uses to receive data to contain a value. */ + xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME ); + + /* Create the 'hook' co-routine itself. */ + xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex ); + } +} +/*-----------------------------------------------------------*/ + +static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0; +void vApplicationTickHook( void ) +{ +unsigned portBASE_TYPE uxReceivedNumber; +signed portBASE_TYPE xIndex, xCoRoutineWoken; + + /* Is it time to talk to the 'hook' co-routines again? */ + uxCallCounter++; + if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST ) + { + uxCallCounter = 0; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + xCoRoutineWoken = pdFALSE; + if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS ) + { + /* There is no reason why we would not expect the queue to + contain a value. */ + xCoRoutineErrorDetected = pdTRUE; + } + else + { + /* Each queue used to receive data from the 'hook' co-routines + should contain the number we last posted to the same co-routine. */ + if( uxReceivedNumber != uxNumberToPost ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Nothing should be blocked waiting to post to the queue. */ + if( xCoRoutineWoken != pdFALSE ) + { + xCoRoutineErrorDetected = pdTRUE; + } + } + } + + /* Start the next cycle by posting the next number onto each Tx queue. */ + uxNumberToPost++; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE ) + { + /* Posting to the queue should have woken the co-routine that + was blocked on the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ]; +portBASE_TYPE xResult; + + /* Each co-routine MUST start with a call to crSTART(); */ + crSTART( xHandle ); + + for( ;; ) + { + /* Wait to receive a value from the tick hook. */ + xResult = pdFAIL; + crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult ); + + /* There is no reason why we should not have received something on + the queue. */ + if( xResult != pdPASS ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Send the same number back to the idle hook so it can verify it. */ + xResult = pdFAIL; + crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult ); + if( xResult != pdPASS ) + { + /* There is no reason why we should not have been able to post to + the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + + /* Each co-routine MUST end with a call to crEND(). */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ) +{ + if( xCoRoutineErrorDetected ) + { + return pdFALSE; + } + else + { + return pdTRUE; + } +} + + + diff --git a/Demo/Common/Minimal/death.c b/Demo/Common/Minimal/death.c new file mode 100644 index 000000000..32bb725c1 --- /dev/null +++ b/Demo/Common/Minimal/death.c @@ -0,0 +1,226 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * four tasks. The original task is called the creator task, the four tasks it + * creates are called suicidal tasks. + * + * Two of the created suicidal tasks kill one other suicidal task before killing + * themselves - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V3.0.0 + + CreationCount sizes changed from unsigned portBASE_TYPE to + unsigned portSHORT to minimize the risk of overflowing. + + + Reset of usLastCreationCount added + +Changes from V3.1.0 + + Changed the dummy calculation to use variables of type long, rather than + float. This allows the file to be used with ports that do not support + floating point. + +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" + +#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 24 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters ); + +/* The task function of the dynamically created tasks. */ +static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile unsigned portSHORT usCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. +*/ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; + +/* Tasks are deleted by the idle task. Under heavy load the idle task might +not get much processing time, so it would be legitimate for several tasks to +remain undeleted for a short period. */ +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 4; + +/* Used to store a handle to the tasks that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask1, xCreatedTask2; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + /* FreeRTOS versions before V3.0 started the idle-task as the very + first task. The idle task was then already included in uxTasksRunningAtStart. + From FreeRTOS V3.0 on, the idle task is started when the scheduler is + started. Therefore the idle task is not yet accounted for. We correct + this by increasing uxTasksRunningAtStart by 1. */ + uxTasksRunningAtStart++; +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vSuicidalTask, pvParameters ) +{ +volatile portLONG l1, l2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Two created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + l1 = 2; + l2 = 89; + l2 *= l1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCreateTasks, pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); + xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); + + xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); + xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); + + ++usCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static portSHORT usLastCreationCount = -1; +portBASE_TYPE xReturn = pdTRUE; +static unsigned portBASE_TYPE uxTasksRunningNow; + + if( usLastCreationCount == usCreationCount ) + { + xReturn = pdFALSE; + } + else + { + usLastCreationCount = usCreationCount; + } + + uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + xReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + xReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return xReturn; +} + + diff --git a/Demo/Common/Minimal/dynamic.c b/Demo/Common/Minimal/dynamic.c new file mode 100644 index 000000000..9481d2d6a --- /dev/null +++ b/Demo/Common/Minimal/dynamic.c @@ -0,0 +1,391 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" + +/* Function that implements the "limited count" task as described above. */ +static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters ); + +/* Function that implements the controller task as described above. */ +static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters ); + +static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters ); +static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters ); + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define priSLEEP_TIME ( ( portTickType ) 50 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static unsigned portLONG ulCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ +/* + * Start the three tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); + xTaskCreate( vContinuousIncrementTask, ( signed portCHAR * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, ( signed portCHAR * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, ( signed portCHAR * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, ( signed portCHAR * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed portCHAR * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters ) +{ +unsigned portLONG *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters ) +{ +unsigned portLONG *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise our priority above the controller task to ensure a context + switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static portTASK_FUNCTION( vCounterControlTask, pvParameters ) +{ +unsigned portLONG ulLastCounter; +portSHORT sLoops; +portSHORT sError = pdFALSE; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned portLONG ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. */ + vTaskSuspend( xContinousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + } + } + xTaskResumeAll(); + } + + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned portLONG ) 0; + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. */ + vTaskResume( xLimitedIncrementHandle ); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters ) +{ +static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters ) +{ +static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} diff --git a/Demo/Common/Minimal/flash.c b/Demo/Common/Minimal/flash.c new file mode 100644 index 000000000..edbd46959 --- /dev/null +++ b/Demo/Common/Minimal/flash.c @@ -0,0 +1,138 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * This version of flash .c is for use on systems that have limited stack space + * and no display facilities. The complete version can be found in the + * Demo/Common/Full directory. + * + * Three tasks are created, each of which flash an LED at a different rate. The first + * LED flashes every 200ms, the second every 400ms, the third every 600ms. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F and the AVR port port B. + * + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.5.5 + + + Calls to vTaskDelay() have been replaced with vTaskDelayUntil(). + +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE +#define ledNUMBER_OF_LEDS ( 3 ) +#define ledFLASH_RATE_BASE ( ( portTickType ) 333 ) + +/* Variable used by the created tasks to calculate the LED number to use, and +the rate at which they should flash the LED. */ +static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0; + +/* The task that is created three times. */ +static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +signed portBASE_TYPE xLEDTask; + + /* Create the three tasks. */ + for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask ) + { + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, ( const signed portCHAR * const ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vLEDFlashTask, pvParameters ) +{ +portTickType xFlashRate, xLastFlashTime; +unsigned portBASE_TYPE uxLED; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Calculate the LED and flash rate. */ + portENTER_CRITICAL(); + { + /* See which of the eight LED's we should use. */ + uxLED = uxFlashTaskNumber; + + /* Update so the next task uses the next LED. */ + uxFlashTaskNumber++; + } + portEXIT_CRITICAL(); + + xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED ); + xFlashRate /= portTICK_RATE_MS; + + /* We will turn the LED on and off again in the delay period, so each + delay is only half the total period. */ + xFlashRate /= ( portTickType ) 2; + + /* We need to initialise xLastFlashTime prior to the first call to + vTaskDelayUntil(). */ + xLastFlashTime = xTaskGetTickCount(); + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + } +} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */ + diff --git a/Demo/Common/Minimal/flop.c b/Demo/Common/Minimal/flop.c new file mode 100644 index 000000000..6046d7e26 --- /dev/null +++ b/Demo/Common/Minimal/flop.c @@ -0,0 +1,330 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +portSHORT sError = pdFALSE; + + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + dAnswer = ( d1 + d2 ) * d3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +portSHORT sError = pdFALSE; + + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + dAnswer = ( d1 / d2 ) * d3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5; + dTotal1 += ( portDOUBLE ) xPosition + 5.5; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123; + dTotal1 += ( portDOUBLE ) xPosition * 12.123; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/Demo/Common/Minimal/integer.c b/Demo/Common/Minimal/integer.c new file mode 100644 index 000000000..272826f52 --- /dev/null +++ b/Demo/Common/Minimal/integer.c @@ -0,0 +1,191 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * This version of integer. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * As with the full version, the tasks created in this file are a good test + * of the scheduler context switch mechanism. The processor has to access + * 32bit variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See flop. c documentation for + * more information. + * + */ + +/* +Changes from V1.2.1 + + + The constants used in the calculations are larger to ensure the + optimiser does not truncate them to 16 bits. + +Changes from V1.2.3 + + + uxTaskCheck is now just used as a boolean. Instead of incrementing + the variable each cycle of the task, the variable is simply set to + true. sAreIntegerMathsTaskStillRunning() sets it back to false and + expects it to have been set back to true by the time it is called + again. + + A division has been included in the calculation. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "integer.h" + +/* The constants used in the calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +#define intgSTACK_SIZE configMINIMAL_STACK_SIZE + +/* As this is the minimal version, we will only create one task. */ +#define intgNUMBER_OF_TASKS ( 1 ) + +/* The task function. Repeatedly performs a 32 bit calculation, checking the +result against the expected result. If the result is incorrect then the +context switch must have caused some corruption. */ +static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters ); + +/* Variables that are set to true within the calculation task to indicate +that the task is still executing. The check task sets the variable back to +false, flagging an error if the variable is still false the next time it +is called. */ +static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE }; + +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ +portSHORT sTask; + + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + xTaskCreate( vCompeteingIntMathTask, ( const signed portCHAR * const ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters ) +{ +/* These variables are all effectively set to constants so they are volatile to +ensure the compiler does not just get rid of them. */ +volatile portLONG lValue; +portSHORT sError = pdFALSE; +volatile signed portBASE_TYPE *pxTaskHasExecuted; + + /* Set a pointer to the variable we are going to set to true each + iteration. This is also a good test of the parameter passing mechanism + within each port. */ + pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + /* Finish off the calculation. */ + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* If the calculation is found to be incorrect we stop setting the + TaskHasExecuted variable so the check task can see an error has + occurred. */ + if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */ + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* We have not encountered any errors, so set the flag that show + we are still executing. This will be periodically cleared by + the check task. */ + portENTER_CRITICAL(); + *pxTaskHasExecuted = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +portBASE_TYPE xReturn = pdTRUE; +portSHORT sTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still being set to true. */ + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + if( xTaskCheck[ sTask ] == pdFALSE ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + /* Reset the check variable so we can tell if it has been set by + the next time around. */ + xTaskCheck[ sTask ] = pdFALSE; + } + + return xReturn; +} + diff --git a/Demo/Common/Minimal/semtest.c b/Demo/Common/Minimal/semtest.c new file mode 100644 index 000000000..6536532e9 --- /dev/null +++ b/Demo/Common/Minimal/semtest.c @@ -0,0 +1,254 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned portLONG *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile portSHORT sNextCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvSemaphoreTest, pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; +unsigned portLONG ulCounter; +portSHORT sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/Demo/Common/include/BlockQ.h b/Demo/Common/include/BlockQ.h new file mode 100644 index 000000000..a11c105b1 --- /dev/null +++ b/Demo/Common/include/BlockQ.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef BLOCK_Q_H +#define BLOCK_Q_H + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreBlockingQueuesStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/PollQ.h b/Demo/Common/include/PollQ.h new file mode 100644 index 000000000..fcc843690 --- /dev/null +++ b/Demo/Common/include/PollQ.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef POLLED_Q_H +#define POLLED_Q_H + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xArePollingQueuesStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/comtest.h b/Demo/Common/include/comtest.h new file mode 100644 index 000000000..a0d860abb --- /dev/null +++ b/Demo/Common/include/comtest.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); + +#endif + diff --git a/Demo/Common/include/comtest2.h b/Demo/Common/include/comtest2.h new file mode 100644 index 000000000..4f6d4a346 --- /dev/null +++ b/Demo/Common/include/comtest2.h @@ -0,0 +1,40 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); + +#endif + diff --git a/Demo/Common/include/crflash.h b/Demo/Common/include/crflash.h new file mode 100644 index 000000000..5d70fc5f7 --- /dev/null +++ b/Demo/Common/include/crflash.h @@ -0,0 +1,52 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef CRFLASH_LED_H +#define CRFLASH_LED_H + +/* + * Create the co-routines used to flash the LED's at different rates. + * + * @param uxPriority The number of 'fixed delay' co-routines to create. This + * also effects the number of LED's that will be utilised. For example, + * passing in 3 will cause LED's 0 to 2 to be utilised. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxPriority ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ); + +#endif + diff --git a/Demo/Common/include/crhook.h b/Demo/Common/include/crhook.h new file mode 100644 index 000000000..a470dd34e --- /dev/null +++ b/Demo/Common/include/crhook.h @@ -0,0 +1,48 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef CRHOOK_H +#define CRHOOK_H + +/* + * Create the co-routines used to communicate wit the tick hook. + */ +void vStartHookCoRoutines( void ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ); + +#endif + diff --git a/Demo/Common/include/death.h b/Demo/Common/include/death.h new file mode 100644 index 000000000..227ca6f59 --- /dev/null +++ b/Demo/Common/include/death.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef SUICIDE_TASK_H +#define SUICIDE_TASK_H + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xIsCreateTaskStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/dynamic.h b/Demo/Common/include/dynamic.h new file mode 100644 index 000000000..af772f853 --- /dev/null +++ b/Demo/Common/include/dynamic.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef DYNAMIC_MANIPULATION_H +#define DYNAMIC_MANIPULATION_H + +void vStartDynamicPriorityTasks( void ); +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/fileIO.h b/Demo/Common/include/fileIO.h new file mode 100644 index 000000000..5f016bf8d --- /dev/null +++ b/Demo/Common/include/fileIO.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FILE_IO_H +#define FILE_OI_H + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ); +void vWriteMessageToDisk( const portCHAR * const pcMessage ); +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ); + +#endif + diff --git a/Demo/Common/include/flash.h b/Demo/Common/include/flash.h new file mode 100644 index 000000000..6048d88e1 --- /dev/null +++ b/Demo/Common/include/flash.h @@ -0,0 +1,39 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FLASH_LED_H +#define FLASH_LED_H + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ); + +#endif + diff --git a/Demo/Common/include/flop.h b/Demo/Common/include/flop.h new file mode 100644 index 000000000..3b8dff8f1 --- /dev/null +++ b/Demo/Common/include/flop.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FLOP_TASKS_H +#define FLOP_TASKS_H + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreMathsTaskStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/integer.h b/Demo/Common/include/integer.h new file mode 100644 index 000000000..5cb039c6b --- /dev/null +++ b/Demo/Common/include/integer.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef INTEGER_TASKS_H +#define INTEGER_TASKS_H + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/mevents.h b/Demo/Common/include/mevents.h new file mode 100644 index 000000000..8d487ba0b --- /dev/null +++ b/Demo/Common/include/mevents.h @@ -0,0 +1,41 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef EVENTS_TEST_H +#define EVENTS_TEST_H + +void vStartMultiEventTasks( void ); +portBASE_TYPE xAreMultiEventTasksStillRunning( void ); + +#endif + + diff --git a/Demo/Common/include/partest.h b/Demo/Common/include/partest.h new file mode 100644 index 000000000..70cc3fec5 --- /dev/null +++ b/Demo/Common/include/partest.h @@ -0,0 +1,43 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PARTEST_H +#define PARTEST_H + +#define partstDEFAULT_PORT_ADDRESS ( ( unsigned portSHORT ) 0x378 ) + +void vParTestInitialise( void ); +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ); + +#endif + diff --git a/Demo/Common/include/print.h b/Demo/Common/include/print.h new file mode 100644 index 000000000..f3744f713 --- /dev/null +++ b/Demo/Common/include/print.h @@ -0,0 +1,42 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PRINT_H +#define PRINT_H + +void vPrintInitialise( void ); +void vPrintDisplayMessage( const portCHAR * const * pcMessageToSend ); +const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ); + +#endif + + diff --git a/Demo/Common/include/semtest.h b/Demo/Common/include/semtest.h new file mode 100644 index 000000000..984b87edb --- /dev/null +++ b/Demo/Common/include/semtest.h @@ -0,0 +1,40 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef SEMAPHORE_TEST_H +#define SEMAPHORE_TEST_H + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ); + +#endif + diff --git a/Demo/Common/include/serial.h b/Demo/Common/include/serial.h new file mode 100644 index 000000000..d9734b321 --- /dev/null +++ b/Demo/Common/include/serial.h @@ -0,0 +1,103 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef SERIAL_COMMS_H +#define SERIAL_COMMS_H + +typedef void * xComPortHandle; + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ); +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ); +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); +void vSerialClose( xComPortHandle xPort ); + +#endif + diff --git a/Demo/Cygnal/FreeRTOSConfig.h b/Demo/Cygnal/FreeRTOSConfig.h new file mode 100644 index 000000000..48e1d4f92 --- /dev/null +++ b/Demo/Cygnal/FreeRTOSConfig.h @@ -0,0 +1,85 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "c8051f120.h" + +/* THE VALUE FOR configSTACK_START MUST BE OBTAINED FROM THE .MEM FILE. */ +#define configSTACK_START ( 0x0e ) + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 98000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 - ( unsigned portSHORT ) configSTACK_START ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Cygnal/Makefile b/Demo/Cygnal/Makefile new file mode 100644 index 000000000..fa6be414f --- /dev/null +++ b/Demo/Cygnal/Makefile @@ -0,0 +1,101 @@ +# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large -I. -I../Common/include -I../include -I../../Source/include \ + -DSDCC_CYGNAL $(DEBUG) --less-pedantic --xram-size 8448 --stack-auto \ + --no-peep --int-long-reent --float-reent + +DEMO_DIR = ../Common +SOURCE_DIR = ../../Source +PORT_DIR = ../../Source/portable/SDCC/Cygnal + +SRC = \ +ParTest/ParTest.c \ +serial/serial.c \ +$(DEMO_DIR)/Full/flash.c \ +$(DEMO_DIR)/Full/print.c \ +$(DEMO_DIR)/Minimal/integer.c \ +$(DEMO_DIR)/Minimal/PollQ.c \ +$(DEMO_DIR)/Minimal/comtest.c \ +$(DEMO_DIR)/Full/semtest.c \ +$(SOURCE_DIR)/tasks.c \ +$(SOURCE_DIR)/queue.c \ +$(SOURCE_DIR)/list.c \ +$(SOURCE_DIR)/portable/MemMang/heap_1.c \ +$(PORT_DIR)/port.c + + +# Define all object files. +OBJ = $(SRC:.c=.rel) + + + + + +###################################### +# THIS VERSION WILL ONLY BUILD FILES THAT HAVE CHANGED, BUT MAY HAVE A DANGEROUS +# COMMAND LINE. IT WORKS FINE UNDER WINDOWS, BUT I HAVE COMMENTED IT OUT IN +# CASE IT CAUSES PROBLEMS ON OTHER SYSTEMS. + +#main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) +# $(CC) $(CFLAGS) main.c $(OBJ) + +#%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h +# $(CC) -c $(CFLAGS) -o$< $< + + + + + +###################################### +# INSTEAD OF THE FOUR LINES ABOVE, THIS VERSION CAN BE USED BUT WILL CAUSE ALL +# FILES TO BUILD EVERY TIME. + +main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) + $(CC) $(CFLAGS) main.c $(OBJ) + +%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h + $(CC) -c $(CFLAGS) $< + + + + + + + + + + + diff --git a/Demo/Cygnal/ParTest/ParTest.c b/Demo/Cygnal/ParTest/ParTest.c new file mode 100644 index 000000000..737011644 --- /dev/null +++ b/Demo/Cygnal/ParTest/ParTest.c @@ -0,0 +1,181 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstPUSH_PULL ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) + +/* LED to output is dependent on how the LED's are wired. */ +#define partstOUTPUT_0 ( ( unsigned portCHAR ) 0x02 ) +#define partstOUTPUT_1 ( ( unsigned portCHAR ) 0x08 ) +#define partstOUTPUT_2 ( ( unsigned portCHAR ) 0x20 ) +#define partstOUTPUT_3 ( ( unsigned portCHAR ) 0x01 ) +#define partstOUTPUT_4 ( ( unsigned portCHAR ) 0x04 ) +#define partstOUTPUT_5 ( ( unsigned portCHAR ) 0x10 ) +#define partstOUTPUT_6 ( ( unsigned portCHAR ) 0x40 ) +#define partstOUTPUT_7 ( ( unsigned portCHAR ) 0x80 ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page before it is changed so it can get set back + before the function exits. */ + ucOriginalSFRPage = SFRPAGE; + + /* Setup the SFR page to access the config SFR's. */ + SFRPAGE = CONFIG_PAGE; + + /* Set the on board LED to push pull. */ + P3MDOUT |= partstPUSH_PULL; + + /* Return the SFR page. */ + SFRPAGE = ucOriginalSFRPage; + + P3 = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +portBASE_TYPE xError = pdFALSE; + + vTaskSuspendAll(); + { + if( xValue == pdFALSE ) + { + switch( uxLED ) + { + case 0 : P3 |= partstOUTPUT_0; + break; + case 1 : P3 |= partstOUTPUT_1; + break; + case 2 : P3 |= partstOUTPUT_2; + break; + case 3 : P3 |= partstOUTPUT_3; + break; + case 4 : P3 |= partstOUTPUT_4; + break; + case 5 : P3 |= partstOUTPUT_5; + break; + case 6 : P3 |= partstOUTPUT_6; + break; + case 7 : P3 |= partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + xError = pdTRUE; + break; + } + } + else + { + switch( uxLED ) + { + case 0 : P3 &= ~partstOUTPUT_0; + break; + case 1 : P3 &= ~partstOUTPUT_1; + break; + case 2 : P3 &= ~partstOUTPUT_2; + break; + case 3 : P3 &= ~partstOUTPUT_3; + break; + case 4 : P3 &= ~partstOUTPUT_4; + break; + case 5 : P3 &= ~partstOUTPUT_5; + break; + case 6 : P3 &= ~partstOUTPUT_6; + break; + case 7 : P3 &= ~partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + break; + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; +portBASE_TYPE xError = pdFALSE; + + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 0 : ucBit = partstOUTPUT_0; + break; + case 1 : ucBit = partstOUTPUT_1; + break; + case 2 : ucBit = partstOUTPUT_2; + break; + case 3 : ucBit = partstOUTPUT_3; + break; + case 4 : ucBit = partstOUTPUT_4; + break; + case 5 : ucBit = partstOUTPUT_5; + break; + case 6 : ucBit = partstOUTPUT_6; + break; + case 7 : ucBit = partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + xError = pdTRUE; + break; + } + + if( xError != pdTRUE ) + { + if( P3 & ucBit ) + { + P3 &= ~ucBit; + } + else + { + P3 |= ucBit; + } + } + } + xTaskResumeAll(); +} + + diff --git a/Demo/Cygnal/c8051f120.h b/Demo/Cygnal/c8051f120.h new file mode 100644 index 000000000..ef9df9ad8 --- /dev/null +++ b/Demo/Cygnal/c8051f120.h @@ -0,0 +1,456 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal C8051F12x Processor Range + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F120_H +#define C8051F120_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2 ; /* ADC 2 DATA */ +sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ + +/* Page 0x02 */ +sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ +sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ +sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ +sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ +sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ +sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ +sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ +sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ +sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ +sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ +sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ +sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ +sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ + +/* Page 0x0F */ +sfr at 0x88 FLSTAT ; /* FLASH STATUS */ +sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ +sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ +sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ +sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ +sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* FLSTAT 0x88 */ +sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN D8H */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN E8H */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC2CN E8H */ +sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN F8H */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define PLL0_PAGE 0x0F /* PLL 0 */ + +#endif diff --git a/Demo/Cygnal/main.c b/Demo/Cygnal/main.c new file mode 100644 index 000000000..51d64ab07 --- /dev/null +++ b/Demo/Cygnal/main.c @@ -0,0 +1,563 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates four other tasks: + * + * 1) vErrorChecks() + * This only executes every few seconds but has the highest priority so is + * guaranteed to get processor time. Its main function is to check that all + * the standard demo application tasks are still operational and have not + * experienced any errors. vErrorChecks() will toggle the on board LED + * every mainNO_ERROR_FLASH_PERIOD milliseconds if none of the demo application + * tasks have reported an error. Should any task report an error at any time + * the rate at which the on board LED is toggled is increased to + * mainERROR_FLASH_PERIOD - providing visual feedback that something has gone + * wrong. + * + * 2) vRegisterCheck() + * This is a very simple task that checks that all the registers are always + * in their expected state. The task only makes use of the A register, so + * all the other registers should always contain their initial values. + * An incorrect value indicates an error in the context switch mechanism. + * The task operates at the idle priority so will be preempted regularly. + * Any error will cause the toggle rate of the on board LED to increase to + * mainERROR_FLASH_PERIOD milliseconds. + * + * 3 and 4) vFLOPCheck1() and vFLOPCheck2() + * These are very basic versions of the standard FLOP tasks. They are good + * at detecting errors in the context switch mechanism, and also check that + * the floating point libraries are correctly built to be re-enterant. The + * stack restrictions of the 8051 prevent the use of the standard FLOP demo + * tasks. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" + +/* Demo task priorities. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_PRIORITY tskIDLE_PRIORITY + +/* Constants required to disable the watchdog. */ +#define mainDISABLE_BYTE_1 ( ( unsigned portCHAR ) 0xde ) +#define mainDISABLE_BYTE_2 ( ( unsigned portCHAR ) 0xad ) + +/* Constants to setup and use the on board LED. */ +#define ucLED_BIT ( ( unsigned portCHAR ) 0x40 ) +#define mainPORT_1_BIT_6 ( ( unsigned portCHAR ) 0x40 ) +#define mainENABLE_CROSS_BAR ( ( unsigned portCHAR ) 0x40 ) + +/* Constants to set the clock frequency. */ +#define mainSELECT_INTERNAL_OSC ( ( unsigned portCHAR ) 0x80 ) +#define mainDIVIDE_CLOCK_BY_1 ( ( unsigned portCHAR ) 0x03 ) +#define mainPLL_USES_INTERNAL_OSC ( ( unsigned portCHAR ) 0x04 ) +#define mainFLASH_READ_TIMING ( ( unsigned portCHAR ) 0x30 ) +#define mainPLL_POWER_ON ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_NO_PREDIVIDE ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_FILTER ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_MULTIPLICATION ( ( unsigned portCHAR ) 0x04 ) +#define mainENABLE_PLL ( ( unsigned portCHAR ) 0x02 ) +#define mainPLL_LOCKED ( ( unsigned portCHAR ) 0x10 ) +#define mainSELECT_PLL_AS_SOURCE ( ( unsigned portCHAR ) 0x02 ) + +/* Toggle rate for the on board LED - which is dependent on whether or not +an error has been detected. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 5000 ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 250 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) + +/* Pass an invalid LED number to the COM test task as we don't want it to flash +an LED. There are only 8 LEDs (excluding the on board LED) wired in and these +are all used by the flash tasks. */ +#define mainCOM_TEST_LED ( 200 ) + +/* We want the Cygnal to act as much as possible as a standard 8052. */ +#define mainAUTO_SFR_OFF ( ( unsigned portCHAR ) 0 ) + +/* Constants required to setup the IO pins for serial comms. */ +#define mainENABLE_COMS ( ( unsigned portCHAR ) 0x04 ) +#define mainCOMS_LINES_TO_PUSH_PULL ( ( unsigned portCHAR ) 0x03 ) + +/* Pointer passed as a parameter to vRegisterCheck() just so it has some know +values to check for in the DPH, DPL and B registers. */ +#define mainDUMMY_POINTER ( ( xdata void * ) 0xabcd ) + +/* Macro that lets vErrorChecks() know that one of the tasks defined in +main. c has detected an error. A critical region is used around xLatchError +as it is accessed from vErrorChecks(), which has a higher priority. */ +#define mainLATCH_ERROR() \ +{ \ + portENTER_CRITICAL(); \ + xLatchedError = pdTRUE; \ + portEXIT_CRITICAL(); \ +} + +/* + * Setup the Cygnal microcontroller for its fastest operation. + */ +static void prvSetupSystemClock( void ); + +/* + * Setup the peripherals, including the on board LED. + */ +static void prvSetupHardware( void ); + +/* + * Toggle the state of the on board LED. + */ +static void prvToggleOnBoardLED( void ); + +/* + * See comments at the top of the file for details. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vRegisterCheck( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vFLOPCheck1( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vFLOPCheck2( void *pvParameters ); + +/* File scope variable used to communicate the occurrence of an error between +tasks. */ +static portBASE_TYPE xLatchedError = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Initialise the hardware including the system clock and on board + LED. */ + prvSetupHardware(); + + /* Initialise the port that controls the external LED's utilized by the + flash tasks. */ + vParTestInitialise(); + + /* Start the used standard demo tasks. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + + /* Start the tasks defined in this file. The first three never block so + must not be used with the co-operative scheduler. */ + #if configUSE_PREEMPTION == 1 + { + xTaskCreate( vRegisterCheck, "RegChck", configMINIMAL_STACK_SIZE, mainDUMMY_POINTER, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( vFLOPCheck1, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( vFLOPCheck2, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + #endif + + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, ( xTaskHandle * ) NULL ); + + /* Finally kick off the scheduler. This function should never return. */ + vTaskStartScheduler(); + + /* Should never reach here as the tasks will now be executing under control + of the scheduler. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the hardware prior to using the scheduler. Most of the Cygnal + * specific initialisation is performed here leaving standard 8052 setup + * only in the driver code. + */ +static void prvSetupHardware( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page before it is changed so it can get set back + before the function exits. */ + ucOriginalSFRPage = SFRPAGE; + + /* Setup the SFR page to access the config SFR's. */ + SFRPAGE = CONFIG_PAGE; + + /* Don't allow the microcontroller to automatically switch SFR page, as the + SFR page is not stored as part of the task context. */ + SFRPGCN = mainAUTO_SFR_OFF; + + /* Disable the watchdog. */ + WDTCN = mainDISABLE_BYTE_1; + WDTCN = mainDISABLE_BYTE_2; + + /* Set the on board LED to push pull. */ + P1MDOUT |= mainPORT_1_BIT_6; + + /* Setup the cross bar to enable serial comms here as it is not part of the + standard 8051 setup and therefore is not in the driver code. */ + XBR0 |= mainENABLE_COMS; + P0MDOUT |= mainCOMS_LINES_TO_PUSH_PULL; + + /* Enable the cross bar so our hardware setup takes effect. */ + XBR2 = mainENABLE_CROSS_BAR; + + /* Setup a fast system clock. */ + prvSetupSystemClock(); + + /* Return the SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} +/*-----------------------------------------------------------*/ + +static void prvSetupSystemClock( void ) +{ +volatile unsigned portSHORT usWait; +const unsigned portSHORT usWaitTime = ( unsigned portSHORT ) 0x2ff; +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page so we can set it back at the end. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = CONFIG_PAGE; + + /* Use the internal oscillator set to its fasted frequency. */ + OSCICN = mainSELECT_INTERNAL_OSC | mainDIVIDE_CLOCK_BY_1; + + /* Ensure the clock is stable. */ + for( usWait = 0; usWait < usWaitTime; usWait++ ); + + /* Setup the clock source for the PLL. */ + PLL0CN &= ~mainPLL_USES_INTERNAL_OSC; + + /* Change the read timing for the flash ready for the fast clock. */ + SFRPAGE = LEGACY_PAGE; + FLSCL |= mainFLASH_READ_TIMING; + + /* Turn on the PLL power. */ + SFRPAGE = CONFIG_PAGE; + PLL0CN |= mainPLL_POWER_ON; + + /* Don't predivide the clock. */ + PLL0DIV = mainPLL_NO_PREDIVIDE; + + /* Set filter for fastest clock. */ + PLL0FLT = mainPLL_FILTER; + PLL0MUL = mainPLL_MULTIPLICATION; + + /* Ensure the clock is stable. */ + for( usWait = 0; usWait < usWaitTime; usWait++ ); + + /* Enable the PLL and wait for it to lock. */ + PLL0CN |= mainENABLE_PLL; + for( usWait = 0; usWait < usWaitTime; usWait++ ) + { + if( PLL0CN & mainPLL_LOCKED ) + { + break; + } + } + + /* Select the PLL as the clock source. */ + CLKSEL |= mainSELECT_PLL_AS_SOURCE; + + /* Return the SFR back to its original value. */ + SFRPAGE = ucOriginalSFRPage; +} +/*-----------------------------------------------------------*/ + +static void prvToggleOnBoardLED( void ) +{ + /* If the on board LED is on, turn it off and visa versa. */ + if( P1 & ucLED_BIT ) + { + P1 &= ~ucLED_BIT; + } + else + { + P1 |= ucLED_BIT; + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vErrorChecks( void *pvParameters ) +{ +portBASE_TYPE xErrorHasOccurred = pdFALSE; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The delay period depends on whether an error + has ever been detected. */ + for( ;; ) + { + if( xLatchedError == pdFALSE ) + { + /* No errors have been detected so delay for a longer period. The + on board LED will get toggled every mainNO_ERROR_FLASH_PERIOD ms. */ + vTaskDelay( mainNO_ERROR_FLASH_PERIOD ); + } + else + { + /* We have at some time recognised an error in one of the demo + application tasks, delay for a shorter period. The on board LED + will get toggled every mainERROR_FLASH_PERIOD ms. */ + vTaskDelay( mainERROR_FLASH_PERIOD ); + } + + + + /* Check the demo application tasks for errors. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + /* If an error has occurred, latch it to cause the LED flash rate to + increase. */ + if( xErrorHasOccurred == pdTRUE ) + { + xLatchedError = pdTRUE; + } + + /* Toggle the LED to indicate the completion of a check cycle. The + frequency of check cycles is dependent on whether or not we have + latched an error. */ + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. Also see the standard FLOP + * demo task documentation for the rationale of these tasks. + */ +static void vFLOPCheck1( void *pvParameters ) +{ +volatile portFLOAT fVal1, fVal2, fResult; + + ( void ) pvParameters; + + for( ;; ) + { + fVal1 = ( portFLOAT ) -1234.5678; + fVal2 = ( portFLOAT ) 2345.6789; + + fResult = fVal1 + fVal2; + if( ( fResult > ( portFLOAT ) 1111.15 ) || ( fResult < ( portFLOAT ) 1111.05 ) ) + { + mainLATCH_ERROR(); + } + + fResult = fVal1 / fVal2; + if( ( fResult > ( portFLOAT ) -0.51 ) || ( fResult < ( portFLOAT ) -0.53 ) ) + { + mainLATCH_ERROR(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vFLOPCheck2( void *pvParameters ) +{ +volatile portFLOAT fVal1, fVal2, fResult; + + ( void ) pvParameters; + + for( ;; ) + { + fVal1 = ( portFLOAT ) -12340.5678; + fVal2 = ( portFLOAT ) 23450.6789; + + fResult = fVal1 + fVal2; + if( ( fResult > ( portFLOAT ) 11110.15 ) || ( fResult < ( portFLOAT ) 11110.05 ) ) + { + mainLATCH_ERROR(); + } + + fResult = fVal1 / -fVal2; + if( ( fResult > ( portFLOAT ) 0.53 ) || ( fResult < ( portFLOAT ) 0.51 ) ) + { + mainLATCH_ERROR(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vRegisterCheck( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + if( SP != configSTACK_START ) + { + mainLATCH_ERROR(); + } + + _asm + MOV ACC, ar0 + _endasm; + + if( ACC != 0 ) + { + mainLATCH_ERROR(); + } + + _asm + MOV ACC, ar1 + _endasm; + + if( ACC != 1 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar2 + _endasm; + + if( ACC != 2 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar3 + _endasm; + + if( ACC != 3 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar4 + _endasm; + + if( ACC != 4 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar5 + _endasm; + + if( ACC != 5 ) + { + mainLATCH_ERROR(); + } + _asm + MOV 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+MDIChild=False +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=PeriphWnd +WindowName=Ports +ResourceID=0 +[WorkState_v1_1.DockState.Bar-40] +BarID=268 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=0 +MRUDockTopPos=0 +MRUDockRightPos=12634464 +MRUDockBottomPos=12638152 +MRUFloatStyle=4 +MRUFloatXPos=-2147483648 +MRUFloatYPos=524545 +Style=20372 +ExStyle=3857 +PrevFloating=False +MDIChild=False +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=PeriphWnd +WindowName=SMBus +ResourceID=0 +[WorkState_v1_1.DockState.Bar-41] +BarID=269 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=0 +MRUDockTopPos=0 +MRUDockRightPos=12583540 +MRUDockBottomPos=12590424 +MRUFloatStyle=4 +MRUFloatXPos=-2147483648 +MRUFloatYPos=12590448 +Style=20372 +ExStyle=3857 +PrevFloating=False +MDIChild=False +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=PeriphWnd +WindowName=SPI Bus +ResourceID=0 +[WorkState_v1_1.DockState.Bar-42] +BarID=270 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=0 +MRUDockTopPos=0 +MRUDockRightPos=12597004 +MRUDockBottomPos=12590096 +MRUFloatStyle=4 +MRUFloatXPos=-2147483648 +MRUFloatYPos=12590120 +Style=20372 +ExStyle=3857 +PrevFloating=False +MDIChild=False +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=PeriphWnd +WindowName=Timers +ResourceID=0 +[WorkState_v1_1.DockState.Bar-43] +BarID=271 +Visible=False +XPos=0 +YPos=0 +Docking=True +MRUDockID=0 +MRUDockLeftPos=0 +MRUDockTopPos=0 +MRUDockRightPos=20028888 +MRUDockBottomPos=12616360 +MRUFloatStyle=4 +MRUFloatXPos=-2147483648 +MRUFloatYPos=12616360 +Style=20372 +ExStyle=3857 +PrevFloating=False +MDIChild=False +PctWidth=1000000 +MRUFloatCX=300 +MRUFloatCY=180 +MRUHorzDockCX=300 +MRUHorzDockCY=180 +MRUVertDockCX=150 +MRUVertDockCY=180 +MRUDockingState=0 +DockingStyle=61440 +TypeID=0 +ClassName=PeriphWnd +WindowName=UART +ResourceID=0 +[WorkState_v1_1.ToolBarMgr] +ToolTips=True +CoolLook=True +LargeButtons=False +[WorkState_v1_1.Frames] +ptn_Child1=MainFrame +ptn_Child2=ChildFrames +[WorkState_v1_1.Frames.MainFrame] +WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPOPPPPPPPHGBAAAAACAFAAAAACODAAAAA +Title=Silicon Laboratories IDE - main.c +[WorkState_v1_1.Frames.ChildFrames] +ptn_Child1=Document-0 +[WorkState_v1_1.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[WorkState_v1_1.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=E:\Dev\FreeRTOS\Demo\Cygnal\main.c +DocumentString=ide Document +DocTemplateIndex=0 +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPGDAAAAAAGDAAAAAAMPDAAAAAIFCAAAAA +IsActiveChildFrame=True +[WorkState_v1_1.ProjectTarget] +ProjectTarget=SC88F000 +[WorkState_v1_1.WorkSpaceName] +WorkSpaceName=E:\Dev\FreeRTOS\Demo\Cygnal\sdcc.wsp +[WorkState_v1_1.SerialPort] +SerialPort=1 +[WorkState_v1_1.StepInc] +StepInc=0 +[WorkState_v1_1.DisassemblyAutoView] +DisassemblyAutoView=0 +[WorkState_v1_1.Watch0Base] +Watch0Base=1 +[WorkState_v1_1.Watch1Base] +Watch1Base=1 +[WorkState_v1_1.Vendor] +Vendor=3 +[WorkState_v1_1.Assembler] +Assembler=D:\devtools\Cygnal\IDEfiles\C51\BIN\a51.exe +[WorkState_v1_1.AssFlag] +AssFlag=-f -i -s +[WorkState_v1_1.AssFormat] +AssFormat= +[WorkState_v1_1.Compiler] +Compiler=D:\devtools\Cygnal\IDEfiles\C51\BIN\C51.exe +[WorkState_v1_1.CompFlag] +CompFlag=-c -l -s m=3 +[WorkState_v1_1.CompFormat] +CompFormat= +[WorkState_v1_1.RunOptimizer] +RunOptimizer=0 +[WorkState_v1_1.Linker] +Linker=D:\devtools\Cygnal\IDEfiles\C51\BIN\bl51.exe +[WorkState_v1_1.LinkFlag] +LinkFlag=i=\mc\lib51\medium.lib -l l=\mc\lib51 -s +[WorkState_v1_1.LinkFormat] +LinkFormat= +[WorkState_v1_1.PreprocFlag] +PreprocFlag=-c -l +[WorkState_v1_1.PreprocFormat] +PreprocFormat= +[WorkState_v1_1.DisList] +DisList=1 +[WorkState_v1_1.DisOP] +DisOP=1 +[WorkState_v1_1.ParseErr] +ParseErr=1 +[WorkState_v1_1.Download] +Download=0 +[WorkState_v1_1.AutoSave] +AutoSave=1 +[WorkState_v1_1.UseMake] +UseMake=1 +[WorkState_v1_1.ErrorFormat] +ErrorFormat=CS CS CS CS CS LN +[WorkState_v1_1.ErrorString] +ErrorString=%s %s %s %s %s %d +[WorkState_v1_1.MultiDeviceJTAG] +DevicesAfterTarget=0 +DevicesBeforeTarget=0 +BitsAfterTargetIR=0 +BitsBeforeTargetIR=0 +[WorkState_v1_1.BankingPN] +BankingPN=32767 +[WorkState_v1_1.OutputFile] +OutputFile=main. +[WorkState_v1_1.MakeFile] +MakeFile= +[WorkState_v1_1.CExt] +CExt=.obj +[WorkState_v1_1.IDEVer] +IDEVer=2.3 +[WorkState_v1_1.ECProtocol] +ECProtocol=0 +[WorkState_v1_1.Adapter] +Adapter=2 +[WorkState_v1_1.PFiles] +[WorkState_v1_1.AFiles] +[WorkState_v1_1.CFiles] +[WorkState_v1_1.LFiles] +[WorkState_v1_1.BankMap] +[WorkState_v1_1.Folders] +ptn_Child1=FolderName +[WorkState_v1_1.Folders.FolderName] +FolderName=Demo App Files +ptn_Child1=FolderName +[WorkState_v1_1.Folders.FolderName.FolderName] +FolderName=FreeRTOS Files +[WorkState_v1_1.Demo App Files] +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName] +FileName=main.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName] +FileName=serial\serial.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName] +FileName=ParTest\ParTest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\semtest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\print.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\flash.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\PollQ.c +[WorkState_v1_1.FreeRTOS Files] +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName] +FileName=E:\Dev\FreeRTOS\Source\tasks.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\queue.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\list.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\portable\SDCC\Cygnal\port.c diff --git a/Demo/Cygnal/serial/serial.c b/Demo/Cygnal/serial/serial.c new file mode 100644 index 000000000..431d4288a --- /dev/null +++ b/Demo/Cygnal/serial/serial.c @@ -0,0 +1,215 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR DEMO PURPOSES */ +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +/* Constants required to setup the serial control register. */ +#define ser8_BIT_MODE ( ( unsigned portCHAR ) 0x40 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* Constants to setup the timer used to generate the baud rate. */ +#define serCLOCK_DIV_48 ( ( unsigned portCHAR ) 0x03 ) +#define serUSE_PRESCALED_CLOCK ( ( unsigned portCHAR ) 0x10 ) +#define ser8BIT_WITH_RELOAD ( ( unsigned portCHAR ) 0x20 ) +#define serSMOD ( ( unsigned portCHAR ) 0x10 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +data static unsigned portBASE_TYPE uxTxEmpty; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulReloadValue; +const portFLOAT fBaudConst = ( portFLOAT ) configCPU_CLOCK_HZ * ( portFLOAT ) 2.0; +unsigned portCHAR ucOriginalSFRPage; + + portENTER_CRITICAL(); + { + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + uxTxEmpty = pdTRUE; + + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Calculate the baud rate to use timer 1. */ + ulReloadValue = ( unsigned portLONG ) ( ( ( portFLOAT ) 256 - ( fBaudConst / ( portFLOAT ) ( 32 * ulWantedBaud ) ) ) + ( portFLOAT ) 0.5 ); + + /* Set timer one for desired mode of operation. */ + TMOD &= 0x08; + TMOD |= ser8BIT_WITH_RELOAD; + SSTA0 |= serSMOD; + + /* Set the reload and start values for the time. */ + TL1 = ( unsigned portCHAR ) ulReloadValue; + TH1 = ( unsigned portCHAR ) ulReloadValue; + + /* Setup the control register for standard n, 8, 1 - variable baud rate. */ + SCON = ser8_BIT_MODE | serRX_ENABLE; + + /* Enable the serial port interrupts */ + ES = 1; + + /* Start the timer. */ + TR1 = 1; + + SFRPAGE = ucOriginalSFRPage; + } + portEXIT_CRITICAL(); + + /* Unlike some ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +void vSerialISR( void ) interrupt 4 +{ +portCHAR cChar; +portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* 8051 port interrupt routines MUST be placed within a critical section + if taskYIELD() is used within the ISR! */ + + portENTER_CRITICAL(); + { + if( RI ) + { + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = SBUF; + RI = 0; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = ( portBASE_TYPE ) pdTRUE; + } + } + + if( TI ) + { + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == ( portBASE_TYPE ) pdTRUE ) + { + /* Send the next character queued for Tx. */ + SBUF = cChar; + } + else + { + /* Queue empty, nothing to send. */ + uxTxEmpty = pdTRUE; + } + + TI = 0; + } + + if( xTaskWokenByRx || xTaskWokenByTx ) + { + portYIELD(); + } + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* There is only one port supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return ( portBASE_TYPE ) pdTRUE; + } + else + { + return ( portBASE_TYPE ) pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn; + + /* There is only one port supported. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + if( uxTxEmpty == pdTRUE ) + { + SBUF = cOutChar; + uxTxEmpty = pdFALSE; + xReturn = ( portBASE_TYPE ) pdTRUE; + } + else + { + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + if( xReturn == ( portBASE_TYPE ) pdFALSE ) + { + xReturn = ( portBASE_TYPE ) pdTRUE; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not implemented in this port. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/Demo/Flshlite/FRConfig.h b/Demo/Flshlite/FRConfig.h new file mode 100644 index 000000000..645ee8255 --- /dev/null +++ b/Demo/Flshlite/FRConfig.h @@ -0,0 +1,87 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions for the x86 port. + *----------------------------------------------------------*/ + +/* These are the only definitions that can be modified!. */ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* The maximum number of characters a task name can take, +including the null terminator. */ +#define configMAX_TASK_NAME_LEN ( 16 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +/* Use/don't use the trace visualisation. */ +#define configUSE_TRACE_FACILITY 0 + +/* + * The tick count (and times defined in tick count units) can be either a 16bit + * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide + * which to use. + */ +#define configUSE_16_BIT_TICKS 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Flshlite/FileIO/fileIO.c b/Demo/Flshlite/FileIO/fileIO.c new file mode 100644 index 000000000..7c65fc426 --- /dev/null +++ b/Demo/Flshlite/FileIO/fileIO.c @@ -0,0 +1,106 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "fileio.h" + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ) +{ + #ifdef USE_STDIO + taskENTER_CRITICAL(); + printf( "%s", pcMessageToPrint ); + fflush( stdout ); + taskEXIT_CRITICAL(); + #else + /* Stop warnings. */ + ( void ) pcMessageToPrint; + #endif +} +/*-----------------------------------------------------------*/ + +void vWriteMessageToDisk( const portCHAR * const pcMessage ) +{ +#ifdef USE_STDIO +const portCHAR * const pcFileName = "c:\\RTOSlog.txt"; +const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "a" ); + if( pf != NULL ) + { + fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); + fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +#else + /* Stop warnings. */ + ( void ) pcMessage; +#endif /*USE_STDIO*/ +} +/*-----------------------------------------------------------*/ + +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) +{ +#ifdef USE_STDIO +const portCHAR * const pcFileName = "c:\\trace.bin"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "wb" ); + if( pf ) + { + fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +#else + /* Stop warnings. */ + ( void ) pcBuffer; + ( void ) ulBufferLength; +#endif /*USE_STDIO*/ +} + + diff --git a/Demo/Flshlite/FreeRTOSConfig.h b/Demo/Flshlite/FreeRTOSConfig.h new file mode 100644 index 000000000..b375008c5 --- /dev/null +++ b/Demo/Flshlite/FreeRTOSConfig.h @@ -0,0 +1,79 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Flshlite/ParTest/ParTest.c b/Demo/Flshlite/ParTest/ParTest.c new file mode 100644 index 000000000..1ef024cad --- /dev/null +++ b/Demo/Flshlite/ParTest/ParTest.c @@ -0,0 +1,130 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.01: + + + Types used updated. + + Add vParTestToggleLED(); + +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstALL_OUTPUTS_OFF ( ( unsigned portSHORT) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) +#define partstPORT_F_ADDR ( ( unsigned portSHORT ) 0x605 ) +#define partstPORT_DIRECTION_REG ( ( unsigned portSHORT ) 0x606 ) +#define partstPORT_F_DIR_BIT ( ( unsigned portSHORT ) 0x20 ) + +/*lint -e956 File scope parameters okay here. */ +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; +/*lint +e956 */ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +unsigned portSHORT usInput; + + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set the direction to output for port F. */ + usInput = portINPUT_BYTE( partstPORT_DIRECTION_REG ); + usInput |= partstPORT_F_DIR_BIT; + portOUTPUT_BYTE( partstPORT_DIRECTION_REG, usInput ); + + /* Start with all outputs off. */ + portOUTPUT_BYTE( partstPORT_F_ADDR, partstALL_OUTPUTS_OFF ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); + } +} + diff --git a/Demo/Flshlite/RTOSDEMO.IDE b/Demo/Flshlite/RTOSDEMO.IDE new file mode 100644 index 000000000..00741f4b4 Binary files /dev/null and b/Demo/Flshlite/RTOSDEMO.IDE differ diff --git a/Demo/Flshlite/main.c b/Demo/Flshlite/main.c new file mode 100644 index 000000000..de6fecedc --- /dev/null +++ b/Demo/Flshlite/main.c @@ -0,0 +1,385 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. + * + * Main. c also creates a task called "Print". This only executes every five + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Nearly all the tasks in the demo application maintain a unique count that is + * incremented each time the task successfully completes its function. Should any + * error occur within the task the count is permanently halted. The print task + * checks the count of each task to ensure it has changed since the last time the + * print task executed. If any count is found not to have changed the print task + * displays an appropriate message, halts, and flashes the on board LED rapidly. + * If all the tasks are still incrementing their unique counts the print task + * displays an "OK" message. + * + * The LED flash tasks do not maintain a count as they already provide visual + * feedback of their status. + * + * The print task blocks on the queue into which messages that require displaying + * are posted. It will therefore only block for the full 5 seconds if no messages + * are posted onto the queue. + * + * Main. c also provides a demonstration of how the trace visualisation utility can + * be used, and how the scheduler can be stopped. + * + * On the Flashlite it is preferable not to try to write to the console during + * real time operation. The built in LED is toggled every cycle of the print task + * that does not encounter any errors, so the console IO may be removed if required. + * The build in LED will start flashing rapidly if any task reports an error. + */ + +/* +Changes from V1.01: + + + Previously, if an error occurred in a task the on board LED was stopped from + toggling. Now if an error occurs the check task enters an infinite loop, + toggling the LED rapidly. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.5 + + + Made the communications RX task a higher priority. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" +#include "serial.h" + +/* Demo file headers. */ +#include "BlockQ.h" +#include "PollQ.h" +#include "death.h" +#include "flash.h" +#include "integer.h" +#include "print.h" +#include "comtest.h" +#include "fileio.h" +#include "semtest.h" + +/* Priority definitions for all the tasks in the demo application. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) + +/* Constant definitions for accessing the build in LED on the Flashlite 186. */ +#define mainLED_REG_DIR ( ( unsigned portSHORT ) 0xff78 ) +#define mainLED_REG ( ( unsigned portSHORT ) 0xff7a ) + +/* If an error is detected in a task then the vErrorChecks() task will enter +an infinite loop flashing the LED at this rate. */ +#define mainERROR_FLASH_RATE ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* Task function for the "Print" task as described at the top of the file. */ +static void vErrorChecks( void *pvParameters ); + +/* Function that checks the unique count of all the other tasks as described at +the top of the file. */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* Functions to setup and use the built in LED on the Flashlite 186 board. */ +static void prvToggleLED( void ); +static void prvInitLED( void ); + +/* Key presses can be used to start/stop the trace visualisation utility or stop +the scheduler. */ +static void prvCheckForKeyPresses( void ); + +/* Buffer used by the trace visualisation utility. */ +static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; + +/*-----------------------------------------------------------*/ +portSHORT main( void ) +{ + /* Initialise hardware and utilities. */ + vParTestInitialise(); + vPrintInitialise(); + prvInitLED(); + + /* CREATE ALL THE DEMO APPLICATION TASKS. */ + + vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser38400 ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); + + /* Create the "Print" task as described at the top of the file. */ + xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Set the scheduler running. This function will not return unless a task + calls vTaskEndScheduler(). */ + vTaskStartScheduler(); + + return 1; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xExpectedWakeTime; +const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; +const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; +portTickType xWakeTime; +portLONG lTimeDifference; +const portCHAR *pcReceivedMessage; +const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Loop continuously, blocking, then checking all the other tasks are still + running, before blocking once again. This task blocks on the queue of messages + that require displaying so will wake either by its time out expiring, or a + message becoming available. */ + for( ;; ) + { + /* Calculate the time we will unblock if no messages are received + on the queue. This is used to check that we have not blocked for too long. */ + xExpectedWakeTime = xTaskGetTickCount(); + xExpectedWakeTime += xPrintRate; + + /* Block waiting for either a time out or a message to be posted that + required displaying. */ + pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); + + /* Was a message received? */ + if( pcReceivedMessage == NULL ) + { + /* A message was not received so we timed out, did we unblock at the + expected time? */ + xWakeTime = xTaskGetTickCount(); + + /* Calculate the difference between the time we unblocked and the + time we should have unblocked. */ + if( xWakeTime > xExpectedWakeTime ) + { + lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); + } + else + { + lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); + } + + if( lTimeDifference > lMaxAllowableTimeDifference ) + { + /* We blocked too long - create a message that will get + printed out the next time around. */ + vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); + } + + /* Check the other tasks are still running, just in case. */ + prvCheckOtherTasksAreStillRunning(); + } + else + { + /* We unblocked due to a message becoming available. Send the message + for printing. */ + vDisplayMessage( pcReceivedMessage ); + } + + /* Key presses are used to invoke the trace visualisation utility, or + end the program. */ + prvCheckForKeyPresses(); + } +} /*lint !e715 !e818 pvParameters is not used but all task functions must take this form. */ +/*-----------------------------------------------------------*/ + +static void prvCheckForKeyPresses( void ) +{ + #ifdef USE_STDIO + + portSHORT sIn; + + + taskENTER_CRITICAL(); + sIn = kbhit(); + taskEXIT_CRITICAL(); + + if( sIn ) + { + unsigned portLONG ulBufferLength; + + /* Key presses can be used to start/stop the trace utility, or end the + program. */ + sIn = getch(); + switch( sIn ) + { + /* Only define keys for turning on and off the trace if the trace + is being used. */ + #if configUSE_TRACE_FACILITY == 1 + case 't' : vTaskList( pcWriteBuffer ); + vWriteMessageToDisk( pcWriteBuffer ); + break; + + case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); + break; + + case 'e' : ulBufferLength = ulTaskEndTrace(); + vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); + break; + #endif + + default : vTaskEndScheduler(); + break; + } + } + + #else + ( void ) pcWriteBuffer; + #endif +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +portSHORT sErrorHasOccurred = pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Com test count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Integer maths task count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Blocking queues count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Polling queue count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Incorrect number of tasks running!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Semaphore take count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( sErrorHasOccurred == pdFALSE ) + { + vDisplayMessage( "OK " ); + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + prvToggleLED(); + } + else + { + for( ;; ) + { + /* An error has occurred in one of the tasks. Don't go any further and + flash the LED rapidly in case console IO is not being used. */ + prvToggleLED(); + vTaskDelay( mainERROR_FLASH_RATE ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvInitLED( void ) +{ +unsigned portSHORT usPortDirection; +const unsigned portSHORT usLEDOut = 0x400; + + /* Set the LED bit to an output. */ + + usPortDirection = inpw( mainLED_REG_DIR ); + usPortDirection &= ~usLEDOut; + outpw( mainLED_REG_DIR, usPortDirection ); +} +/*-----------------------------------------------------------*/ + +static void prvToggleLED( void ) +{ +static portSHORT sLED = pdTRUE; +unsigned portSHORT usLEDState; +const unsigned portSHORT usLEDBit = 0x400; + + /* Flip the state of the LED. */ + usLEDState = inpw( mainLED_REG ); + if( sLED ) + { + usLEDState &= ~usLEDBit; + } + else + { + usLEDState |= usLEDBit; + } + outpw( mainLED_REG, usLEDState ); + + sLED = !sLED; +} + + diff --git a/Demo/Flshlite/rtosdemo.DSW b/Demo/Flshlite/rtosdemo.DSW new file mode 100644 index 000000000..003116e97 Binary files /dev/null and b/Demo/Flshlite/rtosdemo.DSW differ diff --git a/Demo/Flshlite/rtosdemo.lk1 b/Demo/Flshlite/rtosdemo.lk1 new file mode 100644 index 000000000..9ce583f24 --- /dev/null +++ b/Demo/Flshlite/rtosdemo.lk1 @@ -0,0 +1,2 @@ +FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.obj,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj + diff --git a/Demo/Flshlite/rtosdemo.mk b/Demo/Flshlite/rtosdemo.mk new file mode 100644 index 000000000..cc665e818 --- /dev/null +++ b/Demo/Flshlite/rtosdemo.mk @@ -0,0 +1,3 @@ +project : E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe .SYMBOLIC + +!include E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.mk1 diff --git a/Demo/Flshlite/rtosdemo.mk1 b/Demo/Flshlite/rtosdemo.mk1 new file mode 100644 index 000000000..789b4302e --- /dev/null +++ b/Demo/Flshlite/rtosdemo.mk1 @@ -0,0 +1,191 @@ +!define BLANK "" +E:\Dev\FreeRTOS\Demo\Flshlite\list.obj : E:\Dev\FreeRTOS\source\list.c .AUTO& +DEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\list.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\& +source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s& + -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -m& +l + +E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj : E:\Dev\FreeRTOS\SOURCE\PORTABLE\M& +EMMANG\heap_2.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\SOURCE\PORTABLE\MEMMANG\heap_2.c -i=D:\DEVTOOLS\OPENWA~1\h;..\co& +mmon\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\com& +mon -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fp& +c -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\portcomn.obj : E:\Dev\FreeRTOS\source\portable& +\owatcom\16bitdos\common\portcomn.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\portable\owatcom\16bitdos\common\portcomn.c -i=D:\DEVTOOL& +S\OPENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\ow& +atcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -& +zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\port.obj : E:\Dev\FreeRTOS\source\portable\owa& +tcom\16bitdos\flsh186\port.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\portable\owatcom\16bitdos\flsh186\port.c -i=D:\DEVTOOLS\O& +PENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\owatc& +om\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq & +-otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\queue.obj : E:\Dev\FreeRTOS\source\queue.c .AU& +TODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\queue.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& +\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& +s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& +ml + +E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj : E:\Dev\FreeRTOS\source\tasks.c .AU& +TODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\tasks.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& +\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& +s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& +ml + +E:\Dev\FreeRTOS\Demo\Flshlite\blockq.obj : E:\Dev\FreeRTOS\Demo\common\full\& +blockq.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\blockq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..& +\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -z& +a -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=do& +s -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj : E:\Dev\FreeRTOS\Demo\common\full& +\comtest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\comtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\death.obj : E:\Dev\FreeRTOS\Demo\common\full\d& +eath.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\death.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj : E:\Dev\FreeRTOS\Demo\common\full\f& +lash.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\flash.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\integer.obj : E:\Dev\FreeRTOS\Demo\common\full& +\integer.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\integer.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj : E:\Dev\FreeRTOS\Demo\common\full\p& +ollq.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\pollq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\print.obj : E:\Dev\FreeRTOS\Demo\common\full\p& +rint.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\print.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\semtest.obj : E:\Dev\FreeRTOS\Demo\common\full& +\semtest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\semtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj : E:\Dev\FreeRTOS\Demo\Flshlite\fil& +eio\fileio.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc fileio\fileio.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& +ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& +PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\main.obj : E:\Dev\FreeRTOS\Demo\Flshlite\main.& +c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc main.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\source\includ& +e;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCO& +M_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj : E:\Dev\FreeRTOS\Demo\Flshlite\pa& +rtest\partest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc partest\partest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\so& +urce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -& +dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\serial.obj : E:\Dev\FreeRTOS\Demo\Flshlite\ser& +ial\serial.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc serial\serial.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& +ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& +PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe : E:\Dev\FreeRTOS\Demo\Flshlite\l& +ist.obj E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj E:\Dev\FreeRTOS\Demo\Flshli& +te\portcomn.obj E:\Dev\FreeRTOS\Demo\Flshlite\port.obj E:\Dev\FreeRTOS\Demo\& +Flshlite\queue.obj E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj E:\Dev\FreeRTOS\D& +emo\Flshlite\blockq.obj E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj E:\Dev\Fre& +eRTOS\Demo\Flshlite\death.obj E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj E:\Dev& +\FreeRTOS\Demo\Flshlite\integer.obj E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj & +E:\Dev\FreeRTOS\Demo\Flshlite\print.obj E:\Dev\FreeRTOS\Demo\Flshlite\semtes& +t.obj E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj E:\Dev\FreeRTOS\Demo\Flshlite& +\main.obj E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj E:\Dev\FreeRTOS\Demo\Fls& +hlite\serial.obj E:\Dev\FreeRTOS\source\include\list.h E:\Dev\FreeRTOS\sourc& +e\include\portable.h E:\Dev\FreeRTOS\source\include\projdefs.h E:\Dev\FreeRT& +OS\source\include\queue.h E:\Dev\FreeRTOS\source\include\semphr.h E:\Dev\Fre& +eRTOS\source\include\task.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos& +\common\portasm.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos\flsh186\p& +ortmacro.h E:\Dev\FreeRTOS\Demo\common\include\blockq.h E:\Dev\FreeRTOS\Demo& +\common\include\comtest.h E:\Dev\FreeRTOS\Demo\common\include\death.h E:\Dev& +\FreeRTOS\Demo\common\include\fileio.h E:\Dev\FreeRTOS\Demo\common\include\f& +lash.h E:\Dev\FreeRTOS\Demo\common\include\flop.h E:\Dev\FreeRTOS\Demo\commo& +n\include\partest.h E:\Dev\FreeRTOS\Demo\common\include\pollq.h E:\Dev\FreeR& +TOS\Demo\common\include\print.h E:\Dev\FreeRTOS\Demo\common\include\semtest.& +h E:\Dev\FreeRTOS\Demo\common\include\serial.h E:\Dev\FreeRTOS\Demo\Flshlite& +\FreeRTOSConfig.h .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + @%write rtosdemo.lk1 FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.ob& +j,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj& +,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj + @%append rtosdemo.lk1 + *wlink name rtosdemo SYS dos op m op maxe=25 op d op q op symf op el @rtosd& +emo.lk1 + diff --git a/Demo/Flshlite/rtosdemo.tgt b/Demo/Flshlite/rtosdemo.tgt new file mode 100644 index 000000000..367e27550 --- /dev/null +++ b/Demo/Flshlite/rtosdemo.tgt @@ -0,0 +1,1159 @@ +40 +targetIdent +0 +MProject +1 +MComponent +0 +2 +WString +3 +EXE +3 +WString +5 +de6en +1 +0 +0 +4 +MCommand +0 +5 +MCommand +0 +6 +MItem +12 +rtosdemo.exe +7 +WString +3 +EXE +8 +WVList +4 +9 +MRState +10 +WString +5 +WLINK +11 +WString +14 +?????Debug All +1 +0 +12 +MRState +13 +WString +5 +WLINK +14 +WString +16 +?????Debug Dwarf +1 +1 +15 +MCState +16 +WString +5 +WLINK +17 +WString +11 +?????Dosseg +0 +1 +18 +MCState +19 +WString +5 +WLINK +20 +WString +24 +?????Eliminate dead code +0 +1 +21 +WVList +2 +22 +ActionStates +23 +WString +6 +&Debug +24 +WVList +0 +25 +ActionStates +26 +WString +5 +&Make +27 +WVList +0 +-1 +1 +1 +0 +28 +WPickList +40 +29 +MItem +3 +*.c +30 +WString +4 +COBJ +31 +WVList +26 +32 +MVState +33 +WString +3 +WCC +34 +WString +25 +d????Include directories: +1 +35 +WString +97 +$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common +0 +36 +MCState +37 +WString +3 +WCC +38 +WString +26 +?????Force ANSI compliance +1 +1 +39 +MCState +40 +WString +3 +WCC +41 +WString +33 +?????Disable stack depth checking +1 +1 +42 +MVState +43 +WString +3 +WCC +44 +WString +23 +?????Macro definitions: +1 +45 +WString +43 +OPEN_WATCOM_FLASH_LITE_186_PORT DEBUG_BUILD +0 +46 +MCState +47 +WString +3 +WCC +48 +WString +34 +?????Change char default to signed +1 +1 +49 +MRState +50 +WString +3 +WCC +51 +WString +21 +?????Compiler default +1 +0 +52 +MRState +53 +WString +3 +WCC +54 +WString +21 +?????Compiler default +1 +0 +55 +MRState +56 +WString +3 +WCC +57 +WString +25 +?????Floating-point calls +1 +1 +58 +MCState +59 +WString +3 +WCC +60 +WString +31 +???e?SS not assumed equal to DS +1 +1 +61 +MRState +62 +WString +3 +WCC +63 +WString +9 +??6??8086 +1 +0 +64 +MRState +65 +WString +3 +WCC +66 +WString +10 +??6??80186 +1 +1 +67 +MVState +68 +WString +3 +WCC +69 +WString +25 +d????Include directories: +0 +70 +WString +97 +$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common +0 +71 +MCState +72 +WString +3 +WCC +73 +WString +26 +?????Force ANSI compliance +0 +1 +74 +MCState +75 +WString +3 +WCC +76 +WString +33 +?????Disable stack depth checking +0 +1 +77 +MVState +78 +WString +3 +WCC +79 +WString +23 +?????Macro definitions: +0 +80 +WString +31 +OPEN_WATCOM_FLASH_LITE_186_PORT +0 +81 +MCState +82 +WString +3 +WCC +83 +WString +34 +?????Change char default to signed +0 +1 +84 +MRState +85 +WString +3 +WCC +86 +WString +33 +?????Do not generate stack frames +0 +0 +87 +MRState +88 +WString +3 +WCC +89 +WString +23 +?????Generate as needed +0 +1 +90 +MRState +91 +WString +3 +WCC +92 +WString +29 +?????No debugging information +0 +1 +93 +MRState +94 +WString +3 +WCC +95 +WString +28 +?????Line number information +0 +0 +96 +MRState +97 +WString +3 +WCC +98 +WString +21 +?????Compiler default +0 +0 +99 +MRState +100 +WString +3 +WCC +101 +WString +21 +?????Compiler default +0 +0 +102 +MRState +103 +WString +3 +WCC +104 +WString +25 +?????Floating-point calls +0 +1 +105 +MCState +106 +WString +3 +WCC +107 +WString +31 +???e?SS not assumed equal to DS +0 +1 +108 +MRState +109 +WString +3 +WCC +110 +WString +9 +??6??8086 +0 +0 +111 +MRState +112 +WString +3 +WCC +113 +WString +10 +??6??80186 +0 +1 +114 +WVList +0 +-1 +1 +1 +0 +115 +MItem +19 +..\..\source\list.c +116 +WString +4 +COBJ +117 +WVList +0 +118 +WVList +0 +29 +1 +1 +0 +119 +MItem +38 +..\..\SOURCE\PORTABLE\MEMMANG\heap_2.c +120 +WString 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+..\common\full\integer.c +156 +WString +4 +COBJ +157 +WVList +0 +158 +WVList +0 +29 +1 +1 +0 +159 +MItem +22 +..\common\full\pollq.c +160 +WString +4 +COBJ +161 +WVList +0 +162 +WVList +0 +29 +1 +1 +0 +163 +MItem +22 +..\common\full\print.c +164 +WString +4 +COBJ +165 +WVList +0 +166 +WVList +0 +29 +1 +1 +0 +167 +MItem +24 +..\common\full\semtest.c +168 +WString +4 +COBJ +169 +WVList +0 +170 +WVList +0 +29 +1 +1 +0 +171 +MItem +15 +fileio\fileio.c +172 +WString +4 +COBJ +173 +WVList +0 +174 +WVList +0 +29 +1 +1 +0 +175 +MItem +6 +main.c +176 +WString +4 +COBJ +177 +WVList +0 +178 +WVList +0 +29 +1 +1 +0 +179 +MItem +17 +partest\partest.c +180 +WString +4 +COBJ +181 +WVList +0 +182 +WVList +0 +29 +1 +1 +0 +183 +MItem +15 +serial\serial.c +184 +WString +4 +COBJ +185 +WVList +0 +186 +WVList +0 +29 +1 +1 +0 +187 +MItem +3 +*.h +188 +WString +3 +NIL +189 +WVList +0 +190 +WVList +0 +-1 +1 +0 +0 +191 +MItem +27 +..\..\source\include\list.h +192 +WString +3 +NIL +193 +WVList +0 +194 +WVList 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+MItem +27 +..\common\include\comtest.h +228 +WString +3 +NIL +229 +WVList +0 +230 +WVList +0 +187 +1 +1 +0 +231 +MItem +25 +..\common\include\death.h +232 +WString +3 +NIL +233 +WVList +0 +234 +WVList +0 +187 +1 +1 +0 +235 +MItem +26 +..\common\include\fileio.h +236 +WString +3 +NIL +237 +WVList +0 +238 +WVList +0 +187 +1 +1 +0 +239 +MItem +25 +..\common\include\flash.h +240 +WString +3 +NIL +241 +WVList +0 +242 +WVList +0 +187 +1 +1 +0 +243 +MItem +24 +..\common\include\flop.h +244 +WString +3 +NIL +245 +WVList +0 +246 +WVList +0 +187 +1 +1 +0 +247 +MItem +27 +..\common\include\partest.h +248 +WString +3 +NIL +249 +WVList +0 +250 +WVList +0 +187 +1 +1 +0 +251 +MItem +25 +..\common\include\pollq.h +252 +WString +3 +NIL +253 +WVList +0 +254 +WVList +0 +187 +1 +1 +0 +255 +MItem +25 +..\common\include\print.h +256 +WString +3 +NIL +257 +WVList +0 +258 +WVList +0 +187 +1 +1 +0 +259 +MItem +27 +..\common\include\semtest.h +260 +WString +3 +NIL +261 +WVList +0 +262 +WVList +0 +187 +1 +1 +0 +263 +MItem +26 +..\common\include\serial.h +264 +WString +3 +NIL +265 +WVList +0 +266 +WVList +0 +187 +1 +1 +0 +267 +MItem +16 +FreeRTOSConfig.h +268 +WString +3 +NIL +269 +WVList +0 +270 +WVList +0 +187 +1 +1 +0 diff --git a/Demo/Flshlite/rtosdemo.wpj b/Demo/Flshlite/rtosdemo.wpj new file mode 100644 index 000000000..c6a320465 --- /dev/null +++ b/Demo/Flshlite/rtosdemo.wpj @@ -0,0 +1,43 @@ +40 +projectIdent +0 +VpeMain +1 +WRect +-25 +-34 +10291 +10026 +2 +MProject +3 +MCommand +0 +4 +MCommand +0 +1 +5 +WFileName +12 +rtosdemo.tgt +6 +WVList +1 +7 +VComponent +8 +WRect +0 +0 +7200 +5888 +0 +0 +9 +WFileName +12 +rtosdemo.tgt +0 +19 +7 diff --git a/Demo/Flshlite/serial/serial.c b/Demo/Flshlite/serial/serial.c new file mode 100644 index 000000000..b807cb84b --- /dev/null +++ b/Demo/Flshlite/serial/serial.c @@ -0,0 +1,480 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to the more efficient portSWITCH_CONTEXT() replaces the call to + taskYIELD() in the ISR. + +Changes from V1.01: + + + The semaphore task is not operational. This does nothing but check + the semaphore from ISR functionality. + + ISR modified slightly so only Rx or Tx is serviced per ISR - not both. + +Changes from V1.2.0: + + + Change so Tx uses a DMA channel, and Rx uses an interrupt. + +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes from V1.2.5 + + + Reverted back to the non-DMA serial port driver, with a slightly modified + ISR. This is a better test of the scheduler mechanisms. + + A critical section is now used in vInterruptOn(). + + Flag sTxInterruptOn has been added to the port structure. This allows + checking of the interrupt enable status without performing any IO. + +Changes from V2.0.0 + + + Use portTickType in place of unsigned pdLONG for delay periods. + + Slightly more efficient vSerialSendString() implementation. + + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. +*/ + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "portasm.h" +#include "semphr.h" + +#define serMAX_PORTS ( ( unsigned portSHORT ) 2 ) + +#define serPORT_0_INT_REG ( 0xff44 ) +#define serPORT_0_BAUD_REG ( 0xff88 ) +#define serPORT_0_RX_REG ( 0xff86 ) +#define serPORT_0_TX_REG ( 0xff84 ) +#define serPORT_0_STATUS_REG ( 0xff82 ) +#define serPORT_0_CTRL_REG ( 0xff80 ) +#define serPORT_0_IRQ ( 0x14 ) + +#define serPORT_1_INT_REG ( 0xff42 ) +#define serPORT_1_BAUD_REG ( 0xff18 ) +#define serPORT_1_RX_REG ( 0xff16 ) +#define serPORT_1_TX_REG ( 0xff14 ) +#define serPORT_1_STATUS_REG ( 0xff12 ) +#define serPORT_1_CTRL_REG ( 0xff10 ) +#define serPORT_1_IRQ ( 0x11 ) + +#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 ) +#define serRX_READY ( ( unsigned portSHORT ) 0x80 ) + +#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE ) +#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 ) + +#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 ) +#define serMODE ( ( unsigned portSHORT ) 0x01 ) +#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 ) +#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 ) +#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 ) +#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 ) +#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */ + +#define serDONT_BLOCK ( ( portTickType ) 0 ) + +typedef enum +{ + serCOM1 = 0, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50 = 0, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +/* Must be same order as eBaud definitions. */ +static const unsigned portSHORT usBaudRateDivisor[] = +{ + 0, /* Not sure if the first 6 are correct. First cannot be used. */ + 29127, + 19859, + 16302, + 14564, + 10923, + 6879, + 3437, + 1718, + 1145, + 859, + 429, + 214, + 107, + 54, + 35, + 18 +}; + + +typedef struct xCOM_PORT +{ + /* Hardware parameters for this port. */ + portSHORT sTxInterruptOn; + unsigned portSHORT usIntReg; + unsigned portSHORT usBaudReg; + unsigned portSHORT usRxReg; + unsigned portSHORT usTxReg; + unsigned portSHORT usStatusReg; + unsigned portSHORT usCtrlReg; + + unsigned portSHORT usIRQVector; + + /* Queues used for communications with com test task. */ + xQueueHandle xRxedChars; + xQueueHandle xCharsForTx; + + /* This semaphore does nothing useful except test a feature of the + scheduler. */ + xSemaphoreHandle xTestSem; + +} xComPort; + +static xComPort xPorts[ serMAX_PORTS ] = +{ + { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL }, + { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL } +}; + +typedef xComPort * xComPortHandle; + +/* These prototypes are repeated here so we don't have to include the serial header. This allows +the xComPortHandle structure details to be private to this file. */ +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); +void vSerialClose( xComPortHandle xPort ); +portSHORT sSerialWaitForSemaphore( xComPortHandle xPort ); +/*-----------------------------------------------------------*/ + +static portSHORT xComPortISR( xComPort * const pxPort ); + +#define vInterruptOn( pxPort, usInterrupt ) \ +{ \ +unsigned portSHORT usIn; \ + \ + portENTER_CRITICAL(); \ + { \ + if( pxPort->sTxInterruptOn == pdFALSE ) \ + { \ + usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \ + \ + pxPort->sTxInterruptOn = pdTRUE; \ + } \ + } \ + portEXIT_CRITICAL(); \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff( pxPort, usInterrupt ) \ +{ \ + unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + if( usIn & usInterrupt ) \ + { \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \ + pxPort->sTxInterruptOn = pdFALSE; \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Define an interrupt handler for each port */ +#define COM_IRQ_WRAPPER(N) \ + static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ + { \ + if( xComPortISR( &( xPorts[##N##] ) ) ) \ + { \ + portSWITCH_CONTEXT(); \ + } \ + } + + + +COM_IRQ_WRAPPER( 0 ) +COM_IRQ_WRAPPER( 1 ) + +static pxISR xISRs[ serMAX_PORTS ] = +{ + COM_IRQ0_WRAPPER, + COM_IRQ1_WRAPPER +}; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ +unsigned portSHORT usPort; +xComPortHandle pxPort = NULL; + +/* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */ + + /* Only n, 8, 1 is supported so these parameters are not required for this + port. */ + ( void ) eWantedParity; + ( void ) eWantedDataBits; + ( void ) eWantedStopBits; + + /* Currently only n,8,1 is supported. */ + + usPort = ( unsigned portSHORT ) ePort; + + if( usPort < serMAX_PORTS ) + { + pxPort = &( xPorts[ usPort ] ); + + portENTER_CRITICAL(); + { + unsigned portSHORT usInWord; + + /* Create the queues used by the com test task. */ + pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ + vSemaphoreCreateBinary( pxPort->xTestSem ); + + /* There is no ISR here already to restore later. */ + _dos_setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] ); + + usInWord = portINPUT_WORD( pxPort->usIntReg ); + usInWord &= ~serINTERRUPT_MASK; + usInWord |= serINTERRUPT_PRIORITY; + portOUTPUT_WORD( pxPort->usIntReg, usInWord ); + + portOUTPUT_WORD( pxPort->usBaudReg, usBaudRateDivisor[ eWantedBaud ] ); + portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES ); + + portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS ); + } + portEXIT_CRITICAL(); + } + + return pxPort; +} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */ +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +unsigned portSHORT usByte; +portCHAR *pcNextChar; + + pcNextChar = ( portCHAR * ) pcString; + + for( usByte = 0; usByte < usStringLength; usByte++ ) + { + xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK ); + pcNextChar++; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer, note that this routine is only + called having checked that the is (at least) one to get */ + if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) +{ +const portTickType xBlockTime = ( portTickType ) 0xffff; + + /* This function does nothing interesting, but test the + semaphore from ISR mechanism. */ + return xSemaphoreTake( xPort->xTestSem, xBlockTime ); +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portSHORT usOutput; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + usOutput = portINPUT_WORD( xPort->usCtrlReg ); + + usOutput &= ~serENABLE_INTERRUPTS; + usOutput &= ~serENABLE_TX_MACHINES; + usOutput &= ~serENABLE_RX_MACHINES; + portOUTPUT_WORD( xPort->usCtrlReg, usOutput ); + + usOutput = portINPUT_WORD( xPort->usIntReg ); + usOutput |= serINTERRUPT_MASK; + portOUTPUT_WORD( xPort->usIntReg, usOutput ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE xComPortISR( xComPort * const pxPort ) +{ +unsigned portSHORT usStatusRegister; +portCHAR cChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE, xContinue = pdTRUE; + + /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST + THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS + FUNCTION. */ + + + while( xContinue == pdTRUE ) + { + xContinue = pdFALSE; + usStatusRegister = portINPUT_WORD( pxPort->usStatusReg ); + + if( usStatusRegister & serRX_READY ) + { + cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. */ + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + /* We have performed an action this cycle - there may be other to perform. */ + xContinue = pdTRUE; + } + + if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) ) + { + if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar ); + + /* We have performed an action this cycle - there may be others to perform. */ + xContinue = pdTRUE; + } + else + { + /* Queue empty, nothing to send */ + vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT ); + } + } + } + + serRESET_PIC( pxPort->usIRQVector ); + + /* If posting to the queue woke a task that was blocked on the queue we may + want to switch to the woken task - depending on its priority relative to + the task interrupted by this ISR. */ + if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} + + + + + diff --git a/Demo/H8S/RTOSDemo.hws b/Demo/H8S/RTOSDemo.hws new file mode 100644 index 000000000..8899830b2 --- /dev/null +++ b/Demo/H8S/RTOSDemo.hws @@ -0,0 +1,38 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"7.0" +[WORKSPACE_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S" "C:\E\Dev\FreeRTOS\Demo\H8S\RTOSDemo.hws" "H8S,H8/300" "KPIT GNUH8 [ELF]" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[SYSMENUTOOLS] +"GNUH8 Archive Editor" "1.1" +"Hitachi Mapview" "1.0" +"Hitachi H Series Librarian Interface" "1.1" +"Hitachi Call Walker" "1.1" +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(WORKSPNAME).mak" "" 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[END] diff --git a/Demo/H8S/RTOSDemo.tws b/Demo/H8S/RTOSDemo.tws new file mode 100644 index 000000000..8815cdd95 --- /dev/null +++ b/Demo/H8S/RTOSDemo.tws @@ -0,0 +1,28 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.0" +[CURRENT_PROJECT] +"RTOSDemo" +[GENERAL_DATA] +"EDITOR_WINDOWS_MAXIMISED" "1" +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" +"c:\e\Dev\FreeRTOS\Source\queue.c" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" +[WORKSPACE_FILE_STATES] +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" "0,0,954,459,0" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" "44,66,958,463,0" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" "-4,-34,1098,699,1" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" "66,99,958,463,0" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" "88,132,958,463,0" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" "110,165,958,463,0" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" "132,198,958,463,0" +"c:\e\Dev\FreeRTOS\Source\queue.c" "0,0,958,463,0" +[END] diff --git a/Demo/H8S/RTOSDemo/2329S.h b/Demo/H8S/RTOSDemo/2329S.h new file mode 100644 index 000000000..eafb53788 --- /dev/null +++ b/Demo/H8S/RTOSDemo/2329S.h @@ -0,0 +1,142 @@ +#ifndef INC_2329_H +#define INC_2329_H + +/* DATA TYPES MIGHT NOT BE CORRECT. */ + +#define BASE2329 0xFF0000 + +/* Definitions for GPIO. */ + +#define P1DDR ( *( ( volatile unsigned char * ) 0xFFFEB0 ) ) +#define P1DR ( *( ( volatile unsigned char * ) 0xFFFF60 ) ) +#define PORT1 ( *( ( volatile unsigned char * ) 0xFFFF50 ) ) +#define P2DDR ( *( ( volatile unsigned char * ) 0xFFFEB1 ) ) +#define P2DR ( *( ( volatile unsigned char * ) 0xFFFF61 ) ) +#define PORT2 ( *( ( volatile unsigned char * ) 0xFFFF51 ) ) +#define P3DDR ( *( ( volatile unsigned char * ) 0xFFFEB2 ) ) +#define P3DR ( *( ( volatile unsigned char * ) 0xFFFF62 ) ) +#define PORT3 ( *( ( volatile unsigned char * ) 0xFFFF52 ) ) +#define P3ODR ( *( ( volatile unsigned char * ) 0xFFFF76 ) ) +#define PORT4 ( *( ( volatile unsigned char * ) 0xFFFF53 ) ) +#define P5DDR ( *( ( volatile unsigned char * ) 0xFFFEB4 ) ) +#define P5DR ( *( ( volatile unsigned char * ) 0xFFFF64 ) ) +#define PORT5 ( *( ( volatile unsigned char * ) 0xFFFF54 ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) +#define P6DDR ( *( ( volatile unsigned char * ) 0xFFFEB5 ) ) +#define P6DR ( *( ( volatile unsigned char * ) 0xFFFF65 ) ) +#define PORT6 ( *( ( volatile unsigned char * ) 0xFFFF55 ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define PADDR ( *( ( volatile unsigned char * ) 0xFFFEB9 ) ) +#define PADR ( *( ( volatile unsigned char * ) 0xFFFF69 ) ) +#define PORTA ( *( ( volatile unsigned char * ) 0xFFFF59 ) ) +#define PAPCR ( *( ( volatile unsigned char * ) 0xFFFF70 ) ) +#define PAODR ( *( ( volatile unsigned char * ) 0xFFFF77 ) ) +#define PFCR1 ( *( ( volatile unsigned char * ) 0xFFFF45 ) ) +#define PBDDR ( *( ( volatile unsigned char * ) 0xFFFEBA ) ) +#define PBDR ( *( ( volatile unsigned char * ) 0xFFFF6A ) ) +#define PORTB ( *( ( volatile unsigned char * ) 0xFFFF5A ) ) +#define PBPCR ( *( ( volatile unsigned char * ) 0xFFFF71 ) ) +#define PCDDR ( *( ( volatile unsigned char * ) 0xFFFEBB ) ) +#define PCDR ( *( ( volatile unsigned char * ) 0xFFFF6B ) ) +#define PORTC ( *( ( volatile unsigned char * ) 0xFFFF5B ) ) +#define PCPCR ( *( ( volatile unsigned char * ) 0xFFFF72 ) ) +#define PDDDR ( *( ( volatile unsigned char * ) 0xFFFEBC ) ) +#define PDDR ( *( ( volatile unsigned char * ) 0xFFFF6C ) ) +#define PORTD ( *( ( volatile unsigned char * ) 0xFFFF5C ) ) +#define PDPCR ( *( ( volatile unsigned char * ) 0xFFFF73 ) ) +#define PEDDR ( *( ( volatile unsigned char * ) 0xFFFEBD ) ) +#define PEDR ( *( ( volatile unsigned char * ) 0xFFFF6D ) ) +#define PORTE ( *( ( volatile unsigned char * ) 0xFFFF5D ) ) +#define PEPCR ( *( ( volatile unsigned char * ) 0xFFFF74 ) ) +#define PFDDR ( *( ( volatile unsigned char * ) 0xFFFEBE ) ) +#define PFDR ( *( ( volatile unsigned char * ) 0xFFFF6E ) ) +#define PORTF ( *( ( volatile unsigned char * ) 0xFFFF5E ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) +#define PGDDR ( *( ( volatile unsigned char * ) 0xFFFEBF ) ) +#define PGDR ( *( ( volatile unsigned char * ) 0xFFFF6F ) ) +#define PORTG ( *( ( volatile unsigned char * ) 0xFFFF5F ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) + + +/* Definitions for TPU. */ + +#define TCR0 ( *( ( volatile unsigned char * ) 0xFFFFD0 ) ) +#define TMDR0 ( *( ( volatile unsigned char * ) 0xFFFFD1 ) ) +#define TIOR0H ( *( ( volatile unsigned char * ) 0xFFFFD2 ) ) +#define TIOR0L ( *( ( volatile unsigned char * ) 0xFFFFD3 ) ) +#define TIER0 ( *( ( volatile unsigned char * ) 0xFFFFD4 ) ) +#define TSR0 ( *( ( volatile unsigned char * ) 0xFFFFD5 ) ) +#define TCNT0 ( *( ( volatile unsigned short * ) 0xFFFFD6 ) ) +#define TGR0A ( *( ( volatile unsigned short * ) 0xFFFFD8 ) ) +#define TGR0B ( *( ( volatile unsigned short * ) 0xFFFFDA ) ) +#define TGR0C ( *( ( volatile unsigned short * ) 0xFFFFDC ) ) +#define TGR0D ( *( ( volatile unsigned short * ) 0xFFFFDE ) ) +#define TCR1 ( *( ( volatile unsigned char * ) 0xFFFFE0 ) ) +#define TMDR1 ( *( ( volatile unsigned char * ) 0xFFFFE1 ) ) +#define TIOR1 ( *( ( volatile unsigned char * ) 0xFFFFE2 ) ) +#define TIER1 ( *( ( volatile unsigned char * ) 0xFFFFE4 ) ) +#define TSR1 ( *( ( volatile unsigned char * ) 0xFFFFE5 ) ) +#define TCNT1 ( *( ( volatile unsigned short * ) 0xFFFFE6 ) ) +#define TGR1A ( *( ( volatile unsigned short * ) 0xFFFFE8 ) ) +#define TGR1B ( *( ( volatile unsigned short * ) 0xFFFFEA ) ) +#define TCR2 ( *( ( volatile unsigned char * ) 0xFFFFF0 ) ) +#define TMDR2 ( *( ( volatile unsigned char * ) 0xFFFFF1 ) ) +#define TIOR2 ( *( ( volatile unsigned char * ) 0xFFFFF2 ) ) +#define TIER2 ( *( ( volatile unsigned char * ) 0xFFFFF4 ) ) +#define TSR2 ( *( ( volatile unsigned char * ) 0xFFFFF5 ) ) +#define TCNT2 ( *( ( volatile unsigned short * ) 0xFFFFF6 ) ) +#define TGR2A ( *( ( volatile unsigned short * ) 0xFFFFF8 ) ) +#define TGR2B ( *( ( volatile unsigned short * ) 0xFFFFFA ) ) +#define TCR3 ( *( ( volatile unsigned char * ) 0xFFFE80 ) ) +#define TMDR3 ( *( ( volatile unsigned char * ) 0xFFFE81 ) ) +#define TIOR3H ( *( ( volatile unsigned char * ) 0xFFFE82 ) ) +#define TIOR3L ( *( ( volatile unsigned char * ) 0xFFFE83 ) ) +#define TIER3 ( *( ( volatile unsigned char * ) 0xFFFE84 ) ) +#define TSR3 ( *( ( volatile unsigned char * ) 0xFFFE85 ) ) +#define TCNT3 ( *( ( volatile unsigned short * ) 0xFFFE86 ) ) +#define TGR3A ( *( ( volatile unsigned short * ) 0xFFFE88 ) ) +#define TGR3B ( *( ( volatile unsigned short * ) 0xFFFE8A ) ) +#define TGR3C ( *( ( volatile unsigned short * ) 0xFFFE8C ) ) +#define TGR3D ( *( ( volatile unsigned short * ) 0xFFFE8E ) ) +#define TCR4 ( *( ( volatile unsigned char * ) 0xFFFE90 ) ) +#define TMDR4 ( *( ( volatile unsigned char * ) 0xFFFE91 ) ) +#define TIOR4 ( *( ( volatile unsigned char * ) 0xFFFE92 ) ) +#define TIER4 ( *( ( volatile unsigned char * ) 0xFFFE94 ) ) +#define TSR4 ( *( ( volatile unsigned char * ) 0xFFFE95 ) ) +#define TCNT4 ( *( ( volatile unsigned short * ) 0xFFFE96 ) ) +#define TGR4A ( *( ( volatile unsigned short * ) 0xFFFE98 ) ) +#define TGR4B ( *( ( volatile unsigned short * ) 0xFFFE9A ) ) +#define TCR5 ( *( ( volatile unsigned char * ) 0xFFFEA0 ) ) +#define TMDR5 ( *( ( volatile unsigned char * ) 0xFFFEA1 ) ) +#define TIOR5 ( *( ( volatile unsigned char * ) 0xFFFEA2 ) ) +#define TIER5 ( *( ( volatile unsigned char * ) 0xFFFEA4 ) ) +#define TSR5 ( *( ( volatile unsigned char * ) 0xFFFEA5 ) ) +#define TCNT5 ( *( ( volatile unsigned short * ) 0xFFFEA6 ) ) +#define TGR5A ( *( ( volatile unsigned short * ) 0xFFFEA8 ) ) +#define TGR5B ( *( ( volatile unsigned short * ) 0xFFFEAA ) ) +#define TSTR ( *( ( volatile unsigned char * ) 0xFFFFC0 ) ) +#define TSYR ( *( ( volatile unsigned char * ) 0xFFFFC1 ) ) + + +#define MSTPCR ( *( ( volatile unsigned short * ) 0xFFFF3C ) ) +#define SCKCR ( *( ( volatile unsigned short * ) 0xFFFF3A ) ) + +/* Serial port. */ + +#define SMR0 ( *( ( volatile unsigned char * ) 0xFFFF78 ) ) +#define BRR0 ( *( ( volatile unsigned char * ) 0xFFFF79 ) ) +#define SCR0 ( *( ( volatile unsigned char * ) 0xFFFF7A ) ) +#define TDR0 ( *( ( volatile unsigned char * ) 0xFFFF7B ) ) +#define SSR0 ( *( ( volatile unsigned char * ) 0xFFFF7C ) ) +#define RDR0 ( *( ( volatile unsigned char * ) 0xFFFF7D ) ) +#define SCMR0 ( *( ( volatile unsigned char * ) 0xFFFF7E ) ) +#define SMR1 ( *( ( volatile unsigned char * ) 0xFFFF80 ) ) +#define BRR1 ( *( ( volatile unsigned char * ) 0xFFFF81 ) ) +#define SCR1 ( *( ( volatile unsigned char * ) 0xFFFF82 ) ) +#define TDR1 ( *( ( volatile unsigned char * ) 0xFFFF83 ) ) +#define SSR1 ( *( ( volatile unsigned char * ) 0xFFFF84 ) ) +#define RDR1 ( *( ( volatile unsigned char * ) 0xFFFF85 ) ) + +#endif diff --git a/Demo/H8S/RTOSDemo/Debug/Debug.hdp b/Demo/H8S/RTOSDemo/Debug/Debug.hdp new file mode 100644 index 000000000..cb97e96b1 Binary files /dev/null and b/Demo/H8S/RTOSDemo/Debug/Debug.hdp differ diff --git a/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x b/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x new file mode 100644 index 000000000..83575eff8 Binary files /dev/null and b/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x differ diff --git a/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini b/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini new file mode 100644 index 000000000..894ac975f --- /dev/null +++ b/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini @@ -0,0 +1,6 @@ +[HEWGNUBARNEYMCGREW] +SELECTEDCPU=H8/S2000 +SELECTEDMODE=Advanced +INT32=N +SELECTEDRENESAS=N +SELECTEDENDIAN=Big endian diff --git a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..f267babd5 --- /dev/null +++ b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,81 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* IO definitions for the chosen device. */ +#include <2329S.h> + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 22118400 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/Demo/H8S/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 000000000..2aaf32984 --- /dev/null +++ b/Demo/H8S/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,146 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + * + * This is for the demo application which uses port 2 for LED outputs. + *-----------------------------------------------------------*/ + +/* Value for the LED to be off. */ +#define partstLED_OUTPUTS ( ( unsigned portCHAR ) 0xff ) + +/* P2.0 is not used as an output so there are only 7 LEDs on port 2. */ +#define partstMAX_LEDs ( 7 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0 ) + +/* Maps the LED outputs used by the standard demo application files to +convenient outputs for the EDK2329. Mainly this insures that the LED +used by the Check task is one of the on board LEDs so the demo can be +executed on an EDK without any modification. */ +static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ); + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* LED's are connected to port 2. P2.1 and P2.2 are built onto the EDK. + P2.3 to P2.7 are soldered onto the expansion port. */ + P2DDR = partstLED_OUTPUTS; + P2DR = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +/* + * Described at the top of the file. + */ +static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ) +{ + switch( uxLED ) + { + case 0 : return ( unsigned portCHAR ) 2; + case 1 : return ( unsigned portCHAR ) 3; + case 2 : return ( unsigned portCHAR ) 4; + case 3 : return ( unsigned portCHAR ) 5; + case 4 : return ( unsigned portCHAR ) 6; + case 5 : return ( unsigned portCHAR ) 0; + case 6 : return ( unsigned portCHAR ) 1; + default : return 0; + } +} +/*-----------------------------------------------------------*/ + +/* + * Turn an LED on or off. + */ +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucLED; + + if( uxLED < partstMAX_LEDs ) + { + ucLED = prvMapLED( uxLED ); + + /* Set a bit in the required LED position. LED 0 is bit 1. */ + ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); + + if( xValue ) + { + portENTER_CRITICAL(); + P2DR |= ucLED; + portEXIT_CRITICAL(); + } + else + { + portENTER_CRITICAL(); + P2DR &= ~ucLED; + portEXIT_CRITICAL(); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucLED; + + if( uxLED < partstMAX_LEDs ) + { + ucLED = prvMapLED( uxLED ); + + /* Set a bit in the required LED position. LED 0 is bit 1. */ + ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); + + portENTER_CRITICAL(); + { + if( P2DR & ucLED ) + { + P2DR &= ~ucLED; + } + else + { + P2DR |= ucLED; + } + } + portEXIT_CRITICAL(); + } +} + + + diff --git a/Demo/H8S/RTOSDemo/RTOSDemo.hwp b/Demo/H8S/RTOSDemo/RTOSDemo.hwp new file mode 100644 index 000000000..0181e689d --- /dev/null +++ b/Demo/H8S/RTOSDemo/RTOSDemo.hwp @@ -0,0 +1,243 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.7" +[PROJECT_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" "H8S,H8/300" "KPIT GNUH8 [ELF]" "C Application" "" "" +[INFORMATION] +"No project information available" +[TOOL_CHAIN] +"KPIT GNUH8 [ELF] Toolchain" "v0601" +[CONFIGURATIONS] +"Release" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\release" +"Debug" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\debug" +[BUILD_PHASES] +"GNU Assembler" 1 +"GNU Compiler" 1 +"GNU Linker" 1 +[DEFINITION_PARSERS] +[TOOL_ENVIRONMENT] +[EXTENSIONS] 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+[CURRENT_SESSION] +"Release session" +[GENERAL_DATA_PROJECT] +"FDT_UserBootAreaFiles" "" +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug] +"Release session" +"Simulator" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Release] +"Release session" +"Simulator" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator] +[GENERAL_DATA_SESSION_Release session] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator] +[GENERAL_DATA_SESSION_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session] +[END] diff --git a/Demo/H8S/RTOSDemo/Release session.hsf b/Demo/H8S/RTOSDemo/Release session.hsf new file mode 100644 index 000000000..496933dae --- /dev/null +++ b/Demo/H8S/RTOSDemo/Release session.hsf @@ -0,0 +1,247 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.0" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] 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+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" "" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0" +"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}ViewB" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," +"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxCreatedTask," +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" 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+"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" +"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0" +"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 0 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 0 8 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"TCL Toolkit" "WINDOW" 59422 1 0 "-1.000000" -1 -1000 -1000 -1 -1 17 0 "" "-1" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 0 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000017_FDT}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_00000001_MAP}RTOSDemoRelease session" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 0 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 7 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 0 0 350 200 18 0 "" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 280 0 0 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 0 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" +"c:\e\Dev\FreeRTOS\Source\queue.c" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" +[TARGET_NAME] +"" +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"TRUE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/H8S/RTOSDemo/Release/gnuconfig.ini b/Demo/H8S/RTOSDemo/Release/gnuconfig.ini new file mode 100644 index 000000000..894ac975f --- /dev/null +++ b/Demo/H8S/RTOSDemo/Release/gnuconfig.ini @@ -0,0 +1,6 @@ +[HEWGNUBARNEYMCGREW] +SELECTEDCPU=H8/S2000 +SELECTEDMODE=Advanced +INT32=N +SELECTEDRENESAS=N +SELECTEDENDIAN=Big endian diff --git a/Demo/H8S/RTOSDemo/Simulator sessions.hsf b/Demo/H8S/RTOSDemo/Simulator sessions.hsf new file mode 100644 index 000000000..96edb92f7 --- /dev/null +++ b/Demo/H8S/RTOSDemo/Simulator sessions.hsf @@ -0,0 +1,245 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.0" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulator" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP4" "0x00E00000,0x00EFFFFF, 8, 3,EXT" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSimulator" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250" +"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP5" "0x00F00000,0x00FDBFFF, 8, 3,EXT" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24" +"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP6" "0x00FDC000,0x00FEBFFF,16, 3,RAM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100" +"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP7" "0x00FEC000,0x00FFBFFF,16, 1,RAM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000001" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP8" "0x00FFC000,0x00FFDFFF, 8, 3,EXT" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0" +"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0" +"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP9" "0x00FFE000,0x00FFE9FF, 8, 3,EXT" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulatorViewB" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16756480" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0" +"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0" +"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF81E4" 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"1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" +"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000003F48" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0" 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1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Demo/H8S/RTOSDemo/main.c b/Demo/H8S/RTOSDemo/main.c new file mode 100644 index 000000000..97ae2e282 --- /dev/null +++ b/Demo/H8S/RTOSDemo/main.c @@ -0,0 +1,372 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * To check the operation of the memory allocator the check task also + * dynamically creates a task before delaying, and deletes it again when it + * wakes. If memory cannot be allocated for the new task the call to xTaskCreate + * will fail and an error is signalled. The dynamically created task itself + * allocates and frees memory just to give the allocator a bit more exercise. + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application file headers. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" +#include "partest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Baud rate used by the serial port tasks (ComTest tasks). */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +the the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 5 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/* + * The 'Check' task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* + * Start all the tasks then start the scheduler. + */ +int main( void ) +{ + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Start the various standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the 'Check' task. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + /* Should never get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +/* + * Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainCHECK_PERIOD to mainERROR_CHECK_PERIOD so + * the on board LED flash rate will increase. + * + * In addition to the standard tests the memory allocator is tested through + * the dynamic creation and deletion of a task each cycle. Each time the + * task is created memory must be allocated for its stack. When the task is + * deleted this memory is returned to the heap. If the task cannot be created + * then it is likely that the memory allocation failed. In addition the + * dynamically created task allocates and frees memory while it runs. + */ +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +volatile unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Set ulMemCheckTaskRunningCount to a known value so we can check + later that it has changed. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + xCreatedTask = mainNO_TASK; + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Check each set of tasks in turn to see if they have experienced any + * error conditions. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lNoErrorsDiscovered = ( portLONG ) pdTRUE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask task did not increment the counter - it must + have failed. */ + lNoErrorsDiscovered = pdFALSE; + } + + return lNoErrorsDiscovered; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* Reset the count so an error is detected by the + prvCheckOtherTasksAreStillRunning() function. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +/* + * Called by the startup code. Initial processor setup can be placed in this + * function. + */ +void hw_initialise (void) +{ +} + diff --git a/Demo/H8S/RTOSDemo/serial/serial.c b/Demo/H8S/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..fef568826 --- /dev/null +++ b/Demo/H8S/RTOSDemo/serial/serial.c @@ -0,0 +1,260 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. In particular no use is made of the DMA +peripheral. */ + +/* Standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + +/* The queues used to communicate between the task code and the interrupt +service routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Hardware specific constants. */ +#define serTX_INTERRUPT ( ( unsigned portCHAR ) 0x80 ) +#define serRX_INTERRUPT ( ( unsigned portCHAR ) 0x40 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x20 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* Macros to turn on and off the serial port THRE interrupt while leaving the +other register bits in their correct state. The Rx interrupt is always +enabled. */ +#define serTX_INTERRUPT_ON() SCR1 = serTX_INTERRUPT | serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; +#define serTX_INTERRUPT_OFF() SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; + +/* Bit used to switch on the channel 1 serial port in the module stop +register. */ +#define serMSTP6 ( ( unsigned portSHORT ) 0x0040 ) + +/* Interrupt service routines. Note that the Rx and Tx service routines can +cause a context switch and are therefore defined with the saveall attribute in +addition to the interrupt_handler attribute. See the FreeRTOS.org WEB site +documentation for a full explanation.*/ +void vCOM_1_Rx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +void vCOM_1_Tx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +void vCOM_1_Error_ISR( void ) __attribute__ ( ( interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise port 1 for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Create the queues used to communicate between the tasks and the + interrupt service routines. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* No parity, 8 data bits and 1 stop bit is the default so does not require + configuration - setup the remains of the hardware. */ + portENTER_CRITICAL(); + { + /* Turn channel 1 on. */ + MSTPCR &= ~serMSTP6; + + /* Enable the channels and the Rx interrupt. The Tx interrupt is only + enabled when data is being transmitted. */ + SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; + + /* Bit rate settings for 22.1184MHz clock only!. */ + switch( ulWantedBaud ) + { + case 4800 : BRR1 = 143; + break; + case 9600 : BRR1 = 71; + break; + case 19200 : BRR1 = 35; + break; + case 38400 : BRR1 = 17; + break; + case 57600 : BRR1 = 11; + break; + case 115200 : BRR1 = 5; + break; + default : BRR1 = 5; + break; + } + } + portEXIT_CRITICAL(); + + /* Unlike some ports, this driver code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer queue. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn = pdPASS; + + /* Return false if after the block time there is no room on the Tx queue. */ + portENTER_CRITICAL(); + { + /* Send a character to the queue of characters waiting transmission. + The queue is serviced by the Tx ISR. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + /* Could not post onto the queue. */ + xReturn = pdFAIL; + } + else + { + /* The message was posted onto the queue so we turn on the Tx + interrupt to allow the Tx ISR to remove the character from the + queue. */ + serTX_INTERRUPT_ON(); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +void vCOM_1_Rx_ISR( void ) +{ + /* This can cause a context switch so this macro must be the first line + in the function. */ + portENTER_SWITCHING_ISR(); + + /* As this is a switching ISR the local variables must be declared as + static. */ + static portCHAR cRxByte; + static portBASE_TYPE xTaskWokenByPost; + + /* Get the character. */ + cRxByte = RDR1; + + /* Post the character onto the queue of received characters - noting + whether or not this wakes a task. */ + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cRxByte, pdFALSE ); + + /* Clear the interrupt. */ + SSR1 &= ~serRX_INTERRUPT; + + /* This must be the last line in the function. We pass cTaskWokenByPost so + a context switch will occur if the received character woke a task that has + a priority higher than the task we interrupted. */ + portEXIT_SWITCHING_ISR( xTaskWokenByPost ); +} +/*-----------------------------------------------------------*/ + +void vCOM_1_Tx_ISR( void ) +{ + /* This can cause a context switch so this macro must be the first line + in the function. */ + portENTER_SWITCHING_ISR(); + + /* As this is a switching ISR the local variables must be declared as + static. */ + static portCHAR cTxByte; + static signed portBASE_TYPE xTaskWokenByTx; + + /* This variable is static so must be explicitly reinitialised each + time the function executes. */ + xTaskWokenByTx = pdFALSE; + + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? Note whether or not the Tx interrupt has + woken a task. */ + if( xQueueReceiveFromISR( xCharsForTx, &cTxByte, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + TDR1 = cTxByte; + + /* Clear the interrupt. */ + SSR1 &= ~serTX_INTERRUPT; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + serTX_INTERRUPT_OFF(); + } + + /* This must be the last line in the function. We pass cTaskWokenByTx so + a context switch will occur if the Tx'ed character woke a task that has + a priority higher than the task we interrupted. */ + portEXIT_SWITCHING_ISR( xTaskWokenByTx ); +} +/*-----------------------------------------------------------*/ + +/* + * This ISR cannot cause a context switch so requires no special + * considerations. + */ +void vCOM_1_Error_ISR( void ) +{ +volatile unsigned portCHAR ucIn; + + ucIn = SSR1; + SSR1 = 0; +} + diff --git a/Demo/H8S/RTOSDemo/start.asm b/Demo/H8S/RTOSDemo/start.asm new file mode 100644 index 000000000..be99b2108 --- /dev/null +++ b/Demo/H8S/RTOSDemo/start.asm @@ -0,0 +1,115 @@ +;/**************************************************************** +;KPIT Cummins Infosystems Ltd, Pune, India. - 4th September 2003. +; +;This program is distributed in the hope that it will be useful, +;but WITHOUT ANY WARRANTY; without even the implied warranty of +;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE +; +;*****************************************************************/ + + +;********************************************************************* +; File: start.asm +; +; +; desc: +; +; System initialisation routine - entry point for the application. +; The stack pointer is initialised, then the hardware initialisation +; routine called. The static data areas are then initialised, before +; the main function is executed. A simple exit funtion is also +; supplied +; +;********************************************************************* + +#ifdef __H8300H__ + +#ifdef __NORMAL_MODE__ + .h8300hn +#else + .h8300h +#endif + +#endif /*_H8300H_ */ + +#ifdef __H8300S__ + +#ifdef __NORMAL_MODE__ + .h8300sn +#else + .h8300s +#endif + +#endif /* __H8300S__ */ + + .section .text + .global _start +#if DEBUG + .extern _exit +#endif + + .extern _hw_initialise + .extern _main + + .extern _data + .extern _mdata + .extern _edata + .extern _bss + .extern _ebss + .extern _stack + +_start: + ; initialise the SP for non-vectored code + mov.l #_stack,er7 + ; call the hardware initialiser + jsr @_hw_initialise +#ifdef ROMSTART + ; get the boundaries for the .data section initialisation + mov.l #_data,er0 + mov.l #_edata,er1 + mov.l #_mdata,er2 + cmp.l er0,er1 + beq start_1 +start_l: + mov.b @er2,r3l ;get from src + mov.b r3l,@er0 ;place in dest + inc.l #1,er2 ;inc src + inc.l #1,er0 ;inc dest + cmp.l er0,er1 ;dest == edata? + bne start_l +start_1: +#endif //ROMSTART + ; zero out bss + mov.l #_bss,er0 + mov.l #_ebss,er1 + cmp.l er0,er1 + beq start_3 + sub.b r2l,r2l +start_2: + mov.b r2l,@er0 + inc.l #1,er0 + cmp.l er0,er1 + bne start_2 +start_3: +#ifdef CPPAPP + ;Initialize global constructor + jsr @___main +#endif + + ; call the mainline + jsr @_main + + + mov.l er0,er4 + + ;call to exit +#if DEBUG + jsr @_exit +#endif +#if RELEASE + exit: + bra exit +#endif + + + diff --git a/Demo/H8S/RTOSDemo/vects.c b/Demo/H8S/RTOSDemo/vects.c new file mode 100644 index 000000000..f220983a9 --- /dev/null +++ b/Demo/H8S/RTOSDemo/vects.c @@ -0,0 +1,137 @@ +/**************************************************************** +KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +*****************************************************************/ + +void start(void); /* Startup code (in start.asm) */ + +/* + * Manual context switch trap function. + */ +void vPortYield( void ); + +/* + * The RTOS tick ISR. + */ +void vTickISR( void ); + +/* + * Serial port ISR functions. + */ +void vCOM_1_Rx_ISR( void ); +void vCOM_1_Tx_ISR( void ); +void vCOM_1_Error_ISR( void ); + + +typedef void (*fp) (void); +#define VECT_SECT __attribute__ ((section (".vects"))) + +const fp HardwareVectors[] VECT_SECT = { +start, /* vector 0 */ +(fp)(0), /* vector 1 */ +(fp)(0), /* vector 2 */ +(fp)(0), /* vector 3 */ +(fp)(0), /* vector 4 */ +(fp)(0), /* vector 5 */ +(fp)(0), /* vector 6 */ +(fp)(0), /* vector 7 */ +vPortYield, /* vector 8 */ +(fp)(0), /* vector 9 */ +(fp)(0), /* vector 10 */ +(fp)(0), /* vector 11 */ +(fp)(0), /* vector 12 */ +(fp)(0), /* vector 13 */ +(fp)(0), /* vector 14 */ +(fp)(0), /* vector 15 */ +(fp)(0), /* vector 16 */ +(fp)(0), /* vector 17 */ +(fp)(0), /* vector 18 */ +(fp)(0), /* vector 19 */ +(fp)(0), /* vector 20 */ +(fp)(0), /* vector 21 */ +(fp)(0), /* vector 22 */ +(fp)(0), /* vector 23 */ +(fp)(0), /* vector 24 */ +(fp)(0), /* vector 25 */ +(fp)(0), /* vector 26 */ +(fp)(0), /* vector 27 */ +(fp)(0), /* vector 28 */ +(fp)(0), /* vector 29 */ +(fp)(0), /* vector 30 */ +(fp)(0), /* vector 31 */ +(fp)(0), /* vector 32 */ +(fp)(0), /* vector 33 */ +(fp)(0), /* vector 34 */ +(fp)(0), /* vector 35 */ +(fp)(0), /* vector 36 */ +(fp)(0), /* vector 37 */ +(fp)(0), /* vector 38 */ +(fp)(0), /* vector 39 */ +vTickISR, /* vector 40 */ +(fp)(0), /* vector 41 */ +(fp)(0), /* vector 42 */ +(fp)(0), /* vector 43 */ +(fp)(0), /* vector 44 */ +(fp)(0), /* vector 45 */ +(fp)(0), /* vector 46 */ +(fp)(0), /* vector 47 */ +(fp)(0), /* vector 48 */ +(fp)(0), /* vector 49 */ +(fp)(0), /* vector 50 */ +(fp)(0), /* vector 51 */ +(fp)(0), /* vector 52 */ +(fp)(0), /* vector 53 */ +(fp)(0), /* vector 54 */ +(fp)(0), /* vector 55 */ +(fp)(0), /* vector 56 */ +(fp)(0), /* vector 57 */ +(fp)(0), /* vector 58 */ +(fp)(0), /* vector 59 */ +(fp)(0), /* vector 60 */ +(fp)(0), /* vector 61 */ +(fp)(0), /* vector 62 */ +(fp)(0), /* vector 63 */ +(fp)(0), /* vector 64 */ +(fp)(0), /* vector 65 */ +(fp)(0), /* vector 66 */ +(fp)(0), /* vector 67 */ +(fp)(0), /* vector 68 */ +(fp)(0), /* vector 69 */ +(fp)(0), /* vector 70 */ +(fp)(0), /* vector 71 */ +(fp)(0), /* vector 72 */ +(fp)(0), /* vector 73 */ +(fp)(0), /* vector 74 */ +(fp)(0), /* vector 75 */ +(fp)(0), /* vector 76 */ +(fp)(0), /* vector 77 */ +(fp)(0), /* vector 78 */ +(fp)(0), /* vector 79 */ +(fp)(0), /* vector 80 */ +(fp)(0), /* vector 81 */ +(fp)(0), /* vector 82 */ +(fp)(0), /* vector 83 */ +vCOM_1_Error_ISR, /* vector 84 */ +vCOM_1_Rx_ISR, /* vector 85 */ +vCOM_1_Tx_ISR, /* vector 86 */ +(fp)(0), /* vector 87 */ +(fp)(0), /* vector 88 */ +(fp)(0), /* vector 89 */ +(fp)(0), /* vector 90 */ +(fp)(0), /* vector 91 */ +(fp)(0), /* vector 92 */ +(fp)(0), /* vector 93 */ +(fp)(0), /* vector 94 */ +(fp)(0), /* vector 95 */ +(fp)(0), /* vector 96 */ +(fp)(0), /* vector 97 */ +(fp)(0), /* vector 98 */ +(fp)(0), /* vector 99 */ +(fp)(0), /* vector 100 */ +(fp)(0), /* vector 101 */ +(fp)(0), /* vector 102 */ +(fp)(0) /* vector 103 */ +}; diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C new file mode 100644 index 000000000..7acd81842 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C @@ -0,0 +1,145 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 21:10 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 255 = 0FFH +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 24 | PB0_ADDR0_DATA0 +** 1 | 25 | PB1_ADDR1_DATA1 +** 2 | 26 | PB2_ADDR2_DATA2 +** 3 | 27 | PB3_ADDR3_DATA3 +** 4 | 28 | PB4_ADDR4_DATA4 +** 5 | 29 | PB5_ADDR5_DATA5 +** 6 | 30 | PB6_ADDR6_DATA6 +** 7 | 31 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE Byte1. */ + +#include "Byte1.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_GetMsk (bean ByteIO) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ + +byte Byte1_GetMsk(byte Value) +{ + return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ +} + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** Bitnum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) /* Is bit mask correct? */ + if (Value) { /* Is it one to be written? */ + PORTB |= Mask; /* Set appropriate bit on port */ + } + else { /* Is it zero to be written? */ + PORTB &= ~Mask; /* Clear appropriate bit on port */ + } +} + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** Bit - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) { /* Is bit mask correct? */ + PORTB ^= Mask; /* Negate appropriate bit on port */ + } +} + + +/* END Byte1. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H new file mode 100644 index 000000000..028d1e3c1 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H @@ -0,0 +1,111 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 21:10 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 255 = 0FFH +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 24 | PB0_ADDR0_DATA0 +** 1 | 25 | PB1_ADDR1_DATA1 +** 2 | 26 | PB2_ADDR2_DATA2 +** 3 | 27 | PB3_ADDR3_DATA3 +** 4 | 28 | PB4_ADDR4_DATA4 +** 5 | 29 | PB5_ADDR5_DATA5 +** 6 | 30 | PB6_ADDR6_DATA6 +** 7 | 31 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Byte1_H +#define __Byte1_H + +/* MODULE Byte1. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +#include "Cpu.h" + +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value); + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum); + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END Byte1. */ + +#endif /* __Byte1_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C new file mode 100644 index 000000000..e575af48c --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C @@ -0,0 +1,205 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : COM0.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : AsynchroSerial +** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:07 +** Abstract : +** This bean "AsynchroSerial" implements an asynchronous serial +** communication. The bean supports different settings of +** parity, word width, stop-bit and communication speed, +** user can select interrupt or polling handler. +** Communication speed can be changed also in runtime. +** The bean requires one on-chip asynchronous serial channel. +** Settings : +** Serial channel : SCI0 +** +** Protocol +** Init baud rate : 38400baud +** Width : 8 bits +** Stop bits : 1 +** Parity : none +** Breaks : Disabled +** +** Registers +** Input buffer : SCI0DRL [207] +** Output buffer : SCI0DRL [207] +** Control register : SCI0CR1 [202] +** Mode register : SCI0CR2 [203] +** Baud setting reg. : SCI0BD [200] +** Special register : SCI0SR1 [204] +** +** Input interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Output interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Used pins : +** ---------------------------------------------------- +** Function | On package | Name +** ---------------------------------------------------- +** Input | 89 | PS0_RxD0 +** Output | 90 | PS1_TxD0 +** ---------------------------------------------------- +** +** +** Used baud modes : +** ---------------------------------------------------- +** No. | Mode ID | Baud rate +** ---------------------------------------------------- +** 0 | Bm_38400baud | 38400baud +** 1 | Bm_19200baud | 19200baud +** 2 | Bm_9600baud | 9600baud +** 3 | Bm_4800baud | 4800baud +** ---------------------------------------------------- +** Contents : +** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE COM0. */ + +#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */ +#pragma MESSAGE DISABLE C4301 /* INFORMATION C4301: Inline expansion done for function call */ + +#include "COM0.h" +#include "TickTimer.h" +#include "Byte1.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG COM0_DATA /* Data section for this module. */ +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ + + +#define OVERRUN_ERR 1 /* Overrun error flag bit */ +#define FRAMING_ERR 2 /* Framing error flag bit */ +#define PARITY_ERR 4 /* Parity error flag bit */ +#define CHAR_IN_RX 8 /* Char is in RX buffer */ +#define FULL_TX 16 /* Full transmit buffer */ +#define RUNINT_FROM_TX 32 /* Interrupt is in progress */ +#define FULL_RX 64 /* Full receive buffer */ +#define NOISE_ERR 128 /* Noise erorr flag bit */ +#define IDLE_ERR 256 /* Idle character flag bit */ +#define BREAK_ERR 512 /* Break detect */ + +static word SerFlag; /* Flags for serial communication */ + /* Bits: 0 - OverRun error */ + /* 1 - Framing error */ + /* 2 - Parity error */ + /* 3 - Char in RX buffer */ + /* 4 - Full TX buffer */ + /* 5 - Running int from TX */ + /* 6 - Full RX buffer */ + /* 7 - Noise error */ + /* 8 - Idle character */ + /* 9 - Break detected */ + /* 10 - Unused */ +static word PrescHigh; +static byte NumMode; /* Number of selected baud mode */ + + +/* +** =================================================================== +** Method : HWEnDi (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + SCI0CR2_TE = 1; /* Enable transmitter */ + SCI0CR2_RE = 1; /* Enable receiver */ + SCI0CR2_RIE = 1; /* Enable recieve interrupt */ +} + +/* +** =================================================================== +** Method : COM0_SetBaudRateMode (bean AsynchroSerial) +** +** Description : +** This method changes the channel communication speed (baud +** rate). This method can be used only if you specify a list +** of possible period settings at design time (see - Runtime setting - from a list of values). +** Each of these settings constitutes a mode and Processor +** Expert^[TM] assigns them a mode identifier. The prescaler +** and compare values corresponding to each mode are +** calculated at design time. You may switch modes at +** runtime by referring only to a mode identifier. No +** run-time calculations are performed, all the calculations +** are performed at design time. +** Parameters : +** NAME - DESCRIPTION +** Mod - Timing mode to set +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte COM0_SetBaudRateMode(byte Mod) +{ + static const word COM0_PrescHigh[4] = {41,81,163,326}; + + if(Mod >= 4) /* Is mode in baud mode list */ + return ERR_VALUE; /* If no then error */ + NumMode = Mod; /* New baud mode */ + PrescHigh = COM0_PrescHigh[Mod]; /* Prescaler in high speed mode */ + SCI0BD = PrescHigh; /* Set prescaler bits */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : COM0_Init (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void COM0_Init(void) +{ + PrescHigh = 41; /* Precaler in high speed mode */ + SerFlag = 0; /* Reset flags */ + NumMode = 0; /* Number of selected baud mode */ + /* SCI0CR1: LOOPS=0,SCISWAI=1,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ + SCI0CR1 = 64; /* Set the SCI configuration */ + /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ + SCI0SR2 = 0; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ + SCI0SR1; /* Reset interrupt request flags */ + /* SCI0CR2: SCTIE=0,TCIE=0,RIE=0,ILIE=0,TE=0,RE=0,RWU=0,SBK=0 */ + SCI0CR2 = 0; /* Disable error interrupts */ + SCI0BD = PrescHigh; /* Set prescaler bits */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + + +/* END COM0. */ + + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H new file mode 100644 index 000000000..3f0e99a23 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H @@ -0,0 +1,191 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : COM0.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : AsynchroSerial +** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:07 +** Abstract : +** This bean "AsynchroSerial" implements an asynchronous serial +** communication. The bean supports different settings of +** parity, word width, stop-bit and communication speed, +** user can select interrupt or polling handler. +** Communication speed can be changed also in runtime. +** The bean requires one on-chip asynchronous serial channel. +** Settings : +** Serial channel : SCI0 +** +** Protocol +** Init baud rate : 38400baud +** Width : 8 bits +** Stop bits : 1 +** Parity : none +** Breaks : Disabled +** +** Registers +** Input buffer : SCI0DRL [207] +** Output buffer : SCI0DRL [207] +** Control register : SCI0CR1 [202] +** Mode register : SCI0CR2 [203] +** Baud setting reg. : SCI0BD [200] +** Special register : SCI0SR1 [204] +** +** Input interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Output interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Used pins : +** ---------------------------------------------------- +** Function | On package | Name +** ---------------------------------------------------- +** Input | 89 | PS0_RxD0 +** Output | 90 | PS1_TxD0 +** ---------------------------------------------------- +** +** +** Used baud modes : +** ---------------------------------------------------- +** No. | Mode ID | Baud rate +** ---------------------------------------------------- +** 0 | Bm_38400baud | 38400baud +** 1 | Bm_19200baud | 19200baud +** 2 | Bm_9600baud | 9600baud +** 3 | Bm_4800baud | 4800baud +** ---------------------------------------------------- +** Contents : +** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __COM0 +#define __COM0 + +/* MODULE COM0. */ + +#include "Cpu.h" + +#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */ +#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */ +#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */ +#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */ + + + +#ifndef __BWUserType_tItem +#define __BWUserType_tItem + typedef struct { /* Item of the index table for possible baudrates */ + word div; /* divisior */ + byte val; /* values of the prescalers */ + } tItem; +#endif +#ifndef __BWUserType_COM0_TError +#define __BWUserType_COM0_TError +typedef union { + byte err; + struct { + bool OverRun : 1; /* OverRun error flag */ + bool Framing : 1; /* Framing error flag */ + bool Parity : 1; /* Parity error flag */ + bool RxBufOvf : 1; /* Rx buffer full error flag */ + bool Noise : 1; /* Noise error */ + bool Break : 1; /* Break detect */ + bool Idle : 1; /* Idle characted */ + }errName; +} COM0_TError; +#endif +#ifndef __BWUserType_TDirection +#define __BWUserType_TDirection + typedef enum { /* */ + TXD_INPUT, + TXD_OUTPUT + } TDirection; +#endif + +#ifndef __BWUserType_COM0_TComData +#define __BWUserType_COM0_TComData + typedef byte COM0_TComData ; /* User type for communication. Size of this type depends on the communication data witdh. */ +#endif + +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ + +byte COM0_SetBaudRateMode(byte Mod); +/* +** =================================================================== +** Method : COM0_SetBaudRateMode (bean AsynchroSerial) +** +** Description : +** This method changes the channel communication speed (baud +** rate). This method can be used only if you specify a list +** of possible period settings at design time (see - Runtime setting - from a list of values). +** Each of these settings constitutes a mode and Processor +** Expert^[TM] assigns them a mode identifier. The prescaler +** and compare values corresponding to each mode are +** calculated at design time. You may switch modes at +** runtime by referring only to a mode identifier. No +** run-time calculations are performed, all the calculations +** are performed at design time. +** Parameters : +** NAME - DESCRIPTION +** Mod - Timing mode to set +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void COM0_Interrupt(void); +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : COM0_Interrupt (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +void COM0_Init(void); +/* +** =================================================================== +** Method : COM0_Init (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END COM0. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + +#endif /* ifndef __COM0 */ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c b/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c new file mode 100644 index 000000000..7842537ce --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c @@ -0,0 +1,112 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 19:18 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "TickTimer.h" +#include "Byte1.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vCOM0_ISR( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + Cpu_Interrupt, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + vCOM0_ISR, + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C new file mode 100644 index 000000000..a204a0b7c --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C @@ -0,0 +1,198 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE Cpu. */ + +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#define CGM_DELAY 3071UL + + +/* Global variables */ +volatile byte CCR_reg; /* Current CCR reegister */ +byte CpuMode = HIGH_SPEED; /* Current speed mode */ + + +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void) +{ +} + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12DP256_112) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_DisableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12DP256_112) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_EnableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : _EntryPoint (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ +#define INITRG_ADR 0x0011 /* Register map position register */ +#pragma NO_FRAME +#pragma NO_EXIT +void _EntryPoint(void) +{ + /*** ### MC9S12DP256_112 "Cpu" init code ... ***/ + /*** PE initialization code after reset ***/ + /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ + *(byte*)INITRG_ADR = 0; /* Set the register map position */ + asm nop; /* nop instruction */ + INITRM=1; /* Set the RAM map position */ + INITEE=1; /* Set the EEPROM map position */ + /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ + MISC=1; + /* System clock initialization */ + CLKSEL=0; + CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ + PLLCTL_PLLON = 0; /* Disable the PLL */ + SYNR = 24; /* Set the multiplier register */ + REFDV = 15; /* Set the divider register */ + PLLCTL = 192; + PLLCTL_PLLON = 1; /* Enable the PLL */ + while(!CRGFLG_LOCK); /* Wait */ + CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ + /*** End of PE initialization code after reset ***/ + + __asm jmp _Startup; /* Jump to C startup code */ +} + +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_low_level_init(void) +{ + /* Common initialization of the CPU registers */ +/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ + output( TSCR1, input( TSCR1 ) & ~192 | 32 ); +/* TCTL2: OM0=0,OL0=0 */ + output( TCTL2, input( TCTL2 ) & ~3 ); +/* TCTL1: OM7=0,OL7=0 */ + output( TCTL1, input( TCTL1 ) & ~192 ); +/* TIE: C0I=0 */ + output( TIE, input( TIE ) & ~1 ); +/* TTOV: TOV0=0 */ + output( TTOV, input( TTOV ) & ~1 ); +/* TSCR2: TOI=0,TCRE=1 */ + output( TSCR2, input( TSCR2 ) & ~128 | 8 ); +/* TIOS: IOS7=1,IOS0=1 */ + output( TIOS, input( TIOS ) | 129 ); +/* PWMCTL: PSWAI=0,PFRZ=0 */ + output( PWMCTL, input( PWMCTL ) & ~12 ); +/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ + output( PWMSDN, 0 ); +/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */ + output( ICSYS, 0 ); +/* MCCTL: MODMC=1 */ + output( MCCTL, input( MCCTL ) | 64 ); + /* ### MC9S12DP256_112 "Cpu" init code ... */ + /* ### TimerInt "TickTimer" init code ... */ + TickTimer_Init(); + /* ### ByteIO "Byte1" init code ... */ + PORTB = 255; /* Prepare value for output */ + DDRB = 255; /* Set direction to output */ + /* ### Asynchro serial "COM0" init code ... */ + DDRS &= ~1; + PTS |= 2; + DDRS |= 2; + COM0_Init(); + /* Common peripheral initialization - ENABLE */ +/* TSCR1: TEN=1 */ + output( TSCR1, input( TSCR1 ) | 128 ); + INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ + __DI(); /* Disable interrupts */ +} + +/* END Cpu. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H new file mode 100644 index 000000000..2c554db7f --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H @@ -0,0 +1,111 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Cpu +#define __Cpu + +/* Active configuration define symbol */ +#define PEcfg_112pin 1 + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* MODULE Cpu. */ + + +/* Global variables */ +extern volatile byte CCR_reg; /* Current CCR reegister */ +extern byte CpuMode; /* Current speed mode */ + + + + +#define Cpu_DisableInt() __DI() /* Disable interrupts */ +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12DP256_112) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_EnableInt() __EI() /* Enable interrupts */ +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12DP256_112) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +void PE_low_level_init(void); +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +/* END Cpu. */ + +#endif /* ifndef __Cpu */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Events.C b/Demo/HCS12_CodeWarrior_banked/CODE/Events.C new file mode 100644 index 000000000..de1680f54 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Events.C @@ -0,0 +1,153 @@ +/** ################################################################### +** Filename : Events.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE Events */ + + +/*Including used modules for compilling procedure*/ +#include "Cpu.h" +#include "Events.h" +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* +** =================================================================== +** Event : TickTimer_OnInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void TickTimer_OnInterrupt(void) +{ + /* Write your code here ... */ +} + + +/* +** =================================================================== +** Event : COM0_OnError (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when a channel error (not the error +** returned by a given method) occurs. The errors can be +** read using method. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnError(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnRxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a correct character is +** received. This +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnRxChar(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnTxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a character is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnTxChar(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnFullRxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when the input buffer is full. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnFullRxBuf(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnFreeTxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after the last character in output +** buffer is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnFreeTxBuf(void) +{ + /* Write your code here ... */ +} + +/* END Events */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Events.H b/Demo/HCS12_CodeWarrior_banked/CODE/Events.H new file mode 100644 index 000000000..f8f27b947 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Events.H @@ -0,0 +1,130 @@ +/** ################################################################### +** Filename : Events.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Events_H +#define __Events_H +/* MODULE Events */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +void TickTimer_OnInterrupt(void); +/* +** =================================================================== +** Event : TickTimer_OnInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + +void COM0_OnError(void); +/* +** =================================================================== +** Event : COM0_OnError (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when a channel error (not the error +** returned by a given method) occurs. The errors can be +** read using method. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnRxChar(void); +/* +** =================================================================== +** Event : COM0_OnRxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a correct character is +** received. This +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnTxChar(void); +/* +** =================================================================== +** Event : COM0_OnTxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a character is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnFullRxBuf(void); +/* +** =================================================================== +** Event : COM0_OnFullRxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when the input buffer is full. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnFreeTxBuf(void); +/* +** =================================================================== +** Event : COM0_OnFreeTxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after the last character in output +** buffer is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Events */ +#endif /* __Events_H*/ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C new file mode 100644 index 000000000..549a0292f --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C @@ -0,0 +1,559 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* Based on CPU DB MC9S12DP256_112, version 2.87.278 */ +#include "PE_types.h" +#include "IO_Map.h" + +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ +volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */ +volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */ +volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */ +volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */ +volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */ +volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */ +volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ +volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ +volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ +volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */ +volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */ +volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */ +volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */ +volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */ +volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */ +volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */ +volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */ +volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */ +volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */ +volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */ +volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */ +volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */ +volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */ +volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */ +volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */ +volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */ +volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */ +volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */ +volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */ +volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */ +volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */ +volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */ +volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */ +volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */ +volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */ +volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */ +volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */ +volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */ +volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */ +volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */ +volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */ +volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */ +volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */ +volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */ +volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */ +volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */ +volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */ +volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */ +volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */ +volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */ +volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */ +volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */ +volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */ +volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */ +volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */ +volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */ +volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */ +volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */ +volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */ +volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */ +volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */ +volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */ +volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */ +volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */ +volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */ +volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */ +volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */ +volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */ +volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */ +volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */ +volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */ +volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */ +volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */ +volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */ +volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */ +volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */ +volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */ +volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */ +volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */ +volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */ +volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */ +volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */ +volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */ +volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */ +volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */ +volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */ +volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */ +volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */ +volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */ +volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */ +volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */ +volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */ +volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */ +volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */ +volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */ +volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */ +volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */ +volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */ +volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */ +volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */ +volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */ +volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */ +volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */ +volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */ +volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */ +volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */ +volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */ +volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */ +volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */ +volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */ +volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */ +volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */ +volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */ +volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */ +volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */ +volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */ +volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */ +volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */ +volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */ +volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */ +volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */ +volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */ +volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */ +volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */ +volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */ +volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */ +volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */ +volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */ +volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */ +volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */ +volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */ +volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */ +volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */ +volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */ +volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */ +volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */ +volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */ +volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */ +volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */ +volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */ +volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */ +volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */ +volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */ +volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */ +volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */ +volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */ +volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */ +volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */ +volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */ +volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */ +volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */ +volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */ +volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */ +volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */ +volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */ +volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */ +volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */ +volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */ +volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */ +volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */ +volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */ +volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */ +volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */ +volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */ +volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */ +volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */ +volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */ +volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */ +volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */ +volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */ +volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */ +volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */ +volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */ +volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */ +volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */ +volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */ +volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */ +volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */ +volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */ +volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */ +volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */ +volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */ +volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */ +volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */ +volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */ +volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */ +volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */ +volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */ +volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */ +volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */ +volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */ +volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */ +volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */ +volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */ +volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */ +volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */ +volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */ +volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */ +volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */ +volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */ +volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */ +volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */ +volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */ +volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */ +volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */ +volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */ +volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */ +volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */ +volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */ +volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */ +volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */ +volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */ +volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */ +volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */ +volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */ +volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */ +volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */ +volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */ +volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */ +volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */ +volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */ +volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */ +volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */ +volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */ +volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */ +volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */ +volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */ +volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */ +volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */ +volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */ +volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */ +volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */ +volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */ +volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */ +volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */ +volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */ +volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */ +volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */ +volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */ +volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */ +volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */ +volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */ +volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */ +volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */ +volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */ +volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */ +volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */ +volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */ +volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */ +volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */ +volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */ +volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */ +volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */ +volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */ +volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */ +volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */ +volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */ +volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */ +volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */ +volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */ +volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */ +volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */ +volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */ +volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */ +volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */ +volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */ +volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */ +volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */ +volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */ +volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */ +volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */ +volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */ +volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */ +volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */ +volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */ +volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */ +volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */ +volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */ +volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */ +volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */ +volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */ +volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */ +volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */ +volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */ +volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */ +volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */ +volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */ +volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */ +volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */ +volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */ +volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */ +volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */ +volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */ +volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ +volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ +volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register */ +volatile DDRHSTR _DDRH; /* Port H Data Direction Register */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ +volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */ +volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */ +volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */ +volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */ +volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */ +volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */ +volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */ +volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ +volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */ +volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */ +volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */ +volatile EPROTSTR _EPROT; /* EEPROM Protection Register */ +volatile ESTATSTR _ESTAT; /* EEPROM Status Register */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ +volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */ +volatile FPROTSTR _FPROT; /* Flash Protection Register */ +volatile FSECSTR _FSEC; /* Flash Security Register */ +volatile FSTATSTR _FSTAT; /* Flash Status Register */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ +volatile IBADSTR _IBAD; /* IIC Address Register */ +volatile IBCRSTR _IBCR; /* IIC Control Register */ +volatile IBDRSTR _IBDR; /* IIC Data I/O Register */ +volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */ +volatile IBSRSTR _IBSR; /* IIC Status Register */ +volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */ +volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */ +volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register */ +volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */ +volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ +volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ +volatile MODESTR _MODE; /* Mode Register */ +volatile MODRRSTR _MODRR; /* Module Routing Register */ +volatile MTST0STR _MTST0; /* MTST0 */ +volatile MTST1STR _MTST1; /* MTST1 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ +volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ +volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ +volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */ +volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */ +volatile PEARSTR _PEAR; /* Port E Assignment Register */ +volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ +volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ +volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ +volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */ +volatile PORTESTR _PORTE; /* Port E Register */ +volatile PORTKSTR _PORTK; /* Port K Data Register */ +volatile PPAGESTR _PPAGE; /* Page Index Register */ +volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */ +volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ +volatile PTHSTR _PTH; /* Port H I/O Register */ +volatile PTIHSTR _PTIH; /* Port H Input Register */ +volatile PTIJSTR _PTIJ; /* Port J Input Register */ +volatile PTIMSTR _PTIM; /* Port M Input */ +volatile PTIPSTR _PTIP; /* Port P Input */ +volatile PTISSTR _PTIS; /* Port S Input */ +volatile PTITSTR _PTIT; /* Port T Input */ +volatile PTJSTR _PTJ; /* Port J I/O Register */ +volatile PTMSTR _PTM; /* Port M I/O Register */ +volatile PTPSTR _PTP; /* Port P I/O Register */ +volatile PTSSTR _PTS; /* Port S I/O Register */ +volatile PTTSTR _PTT; /* Port T I/O Register */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ +volatile PWMESTR _PWME; /* PWM Enable Register */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ +volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ +volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */ +volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */ +volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */ +volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */ +volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */ +volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */ +volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */ +volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */ +volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */ +volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */ +volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */ +volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */ +volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */ +volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */ +volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */ +volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */ +volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */ +volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */ +volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */ +volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */ +volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */ +volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */ +volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */ +volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */ +volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */ +volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */ +volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ +volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */ +volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ +volatile TIMTSTSTR _TIMTST; /* Timer Test Register */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ +volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */ +volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */ +volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */ +volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */ +volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */ +volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */ +volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */ +volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */ +volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */ +volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */ +volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */ +volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */ +volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */ +volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */ +volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */ +volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */ +volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */ +volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */ +volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */ +volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ +volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */ +volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */ +volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */ +volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */ +volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */ +volatile PORTABSTR _PORTAB; /* Port AB Register */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ +volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ +volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ +volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */ +volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */ +volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ +volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ +volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ +volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ +volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ +volatile TCNTSTR _TCNT; /* Timer Count Register */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H new file mode 100644 index 000000000..678b0b350 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H @@ -0,0 +1,18408 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* Linker pragmas */ +#pragma LINK_INFO DERIVATIVE "MC9S12DP256B" +#pragma LINK_INFO OSCFREQUENCY "16000000" + + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + +/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */ +#ifndef _MC9S12DP256_112_H +#define _MC9S12DP256_112_H + +#include "PE_Types.h" + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ + +/*********************************************/ +/* */ +/* PE I/O map format */ +/* */ +/*********************************************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ + byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ + byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ + byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ + byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ + byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ + byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ + byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ + byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ + byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ + byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ + byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ + byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ + byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ + byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ + word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ + word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ + word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ + word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ + word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ + word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ + word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ + word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ + word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ + word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ + word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ + word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ + word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ + word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ + word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 +#define PORTAB_BIT _PORTAB.MergedBits.grpBIT + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port B Bit 0 */ + word BIT1 :1; /* Data Direction Port B Bit 1 */ + word BIT2 :1; /* Data Direction Port B Bit 2 */ + word BIT3 :1; /* Data Direction Port B Bit 3 */ + word BIT4 :1; /* Data Direction Port B Bit 4 */ + word BIT5 :1; /* Data Direction Port B Bit 5 */ + word BIT6 :1; /* Data Direction Port B Bit 6 */ + word BIT7 :1; /* Data Direction Port B Bit 7 */ + word BIT8 :1; /* Data Direction Port A Bit 8 */ + word BIT9 :1; /* Data Direction Port A Bit 9 */ + word BIT10 :1; /* Data Direction Port A Bit 10 */ + word BIT11 :1; /* Data Direction Port A Bit 11 */ + word BIT12 :1; /* Data Direction Port A Bit 12 */ + word BIT13 :1; /* Data Direction Port A Bit 13 */ + word BIT14 :1; /* Data Direction Port A Bit 14 */ + word BIT15 :1; /* Data Direction Port A Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 +#define DDRAB_BIT _DDRAB.MergedBits.grpBIT + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + struct { + byte BIT15 :1; /* Timer Count Register Bit 15 */ + byte BIT14 :1; /* Timer Count Register Bit 14 */ + byte BIT13 :1; /* Timer Count Register Bit 13 */ + byte BIT12 :1; /* Timer Count Register Bit 12 */ + byte BIT11 :1; /* Timer Count Register Bit 11 */ + byte BIT10 :1; /* Timer Count Register Bit 10 */ + byte BIT9 :1; /* Timer Count Register Bit 9 */ + byte BIT8 :1; /* Timer Count Register Bit 8 */ + } Bits; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 + #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 + #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 + #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 + #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 + #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 + #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 + #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Count Register Bit 0 */ + byte BIT1 :1; /* Timer Count Register Bit 1 */ + byte BIT2 :1; /* Timer Count Register Bit 2 */ + byte BIT3 :1; /* Timer Count Register Bit 3 */ + byte BIT4 :1; /* Timer Count Bit Register 4 */ + byte BIT5 :1; /* Timer Count Bit Register 5 */ + byte BIT6 :1; /* Timer Count Bit Register 6 */ + byte BIT7 :1; /* Timer Count Bit Register 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 + #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 + #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 + #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 + #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 + #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 + #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 + #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 + #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); +#define TCNT _TCNT.Word +#define TCNT_BIT _TCNT.MergedBits.grpBIT + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 + #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 + #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 + #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 + #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 + #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 + #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 + #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 + #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 + #define TC0Hi_BIT TC0Hi_BIT_8 + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 + #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 + #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 + #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 + #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 + #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 + #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 + #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 + #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); +#define TC0 _TC0.Word +#define TC0_BIT _TC0.MergedBits.grpBIT + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 + #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 + #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 + #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 + #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 + #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 + #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 + #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 + #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 + #define TC1Hi_BIT TC1Hi_BIT_8 + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 + #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 + #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 + #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 + #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 + #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 + #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 + #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 + #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); +#define TC1 _TC1.Word +#define TC1_BIT _TC1.MergedBits.grpBIT + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 + #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 + #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 + #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 + #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 + #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 + #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 + #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 + #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 + #define TC2Hi_BIT TC2Hi_BIT_8 + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 + #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 + #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 + #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 + #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 + #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 + #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 + #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 + #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); +#define TC2 _TC2.Word +#define TC2_BIT _TC2.MergedBits.grpBIT + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 + #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 + #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 + #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 + #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 + #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 + #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 + #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 + #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 + #define TC3Hi_BIT TC3Hi_BIT_8 + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 + #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 + #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 + #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 + #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 + #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 + #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 + #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 + #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); +#define TC3 _TC3.Word +#define TC3_BIT _TC3.MergedBits.grpBIT + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 + #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 + #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 + #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 + #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 + #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 + #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 + #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 + #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 + #define TC4Hi_BIT TC4Hi_BIT_8 + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 + #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 + #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 + #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 + #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 + #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 + #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 + #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 + #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); +#define TC4 _TC4.Word +#define TC4_BIT _TC4.MergedBits.grpBIT + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 + #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 + #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 + #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 + #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 + #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 + #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 + #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 + #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 + #define TC5Hi_BIT TC5Hi_BIT_8 + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 + #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 + #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 + #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 + #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 + #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 + #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 + #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 + #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); +#define TC5 _TC5.Word +#define TC5_BIT _TC5.MergedBits.grpBIT + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 + #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 + #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 + #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 + #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 + #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 + #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 + #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 + #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 + #define TC6Hi_BIT TC6Hi_BIT_8 + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 + #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 + #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 + #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 + #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 + #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 + #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 + #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 + #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); +#define TC6 _TC6.Word +#define TC6_BIT _TC6.MergedBits.grpBIT + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 + #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 + #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 + #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 + #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 + #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 + #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 + #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 + #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 + #define TC7Hi_BIT TC7Hi_BIT_8 + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 + #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 + #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 + #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 + #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 + #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 + #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 + #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 + #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); +#define TC7 _TC7.Word +#define TC7_BIT _TC7.MergedBits.grpBIT + + +/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN3STR; + #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte + #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT + + /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN2STR; + #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte + #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PACN32STR; +extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062); +#define PACN32 _PACN32.Word +#define PACN32_BIT _PACN32.MergedBits.grpBIT + + +/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN1STR; + #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte + #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT + + /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN0STR; + #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte + #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PACN10STR; +extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064); +#define PACN10 _PACN10.Word +#define PACN10_BIT _PACN10.MergedBits.grpBIT + + +/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA3HSTR; + #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte + #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0 + #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1 + #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2 + #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3 + #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4 + #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5 + #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6 + #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7 + #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT + + /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA2HSTR; + #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte + #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0 + #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1 + #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2 + #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3 + #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4 + #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5 + #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6 + #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7 + #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PA32HSTR; +extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072); +#define PA32H _PA32H.Word +#define PA32H_BIT0 _PA32H.Bits.BIT0 +#define PA32H_BIT1 _PA32H.Bits.BIT1 +#define PA32H_BIT2 _PA32H.Bits.BIT2 +#define PA32H_BIT3 _PA32H.Bits.BIT3 +#define PA32H_BIT4 _PA32H.Bits.BIT4 +#define PA32H_BIT5 _PA32H.Bits.BIT5 +#define PA32H_BIT6 _PA32H.Bits.BIT6 +#define PA32H_BIT7 _PA32H.Bits.BIT7 +#define PA32H_BIT8 _PA32H.Bits.BIT8 +#define PA32H_BIT9 _PA32H.Bits.BIT9 +#define PA32H_BIT10 _PA32H.Bits.BIT10 +#define PA32H_BIT11 _PA32H.Bits.BIT11 +#define PA32H_BIT12 _PA32H.Bits.BIT12 +#define PA32H_BIT13 _PA32H.Bits.BIT13 +#define PA32H_BIT14 _PA32H.Bits.BIT14 +#define PA32H_BIT15 _PA32H.Bits.BIT15 +#define PA32H_BIT _PA32H.MergedBits.grpBIT + + +/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA1HSTR; + #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte + #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0 + #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1 + #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2 + #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3 + #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4 + #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5 + #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6 + #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7 + #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT + + /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA0HSTR; + #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte + #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0 + #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1 + #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2 + #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3 + #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4 + #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5 + #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6 + #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7 + #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PA10HSTR; +extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074); +#define PA10H _PA10H.Word +#define PA10H_BIT0 _PA10H.Bits.BIT0 +#define PA10H_BIT1 _PA10H.Bits.BIT1 +#define PA10H_BIT2 _PA10H.Bits.BIT2 +#define PA10H_BIT3 _PA10H.Bits.BIT3 +#define PA10H_BIT4 _PA10H.Bits.BIT4 +#define PA10H_BIT5 _PA10H.Bits.BIT5 +#define PA10H_BIT6 _PA10H.Bits.BIT6 +#define PA10H_BIT7 _PA10H.Bits.BIT7 +#define PA10H_BIT8 _PA10H.Bits.BIT8 +#define PA10H_BIT9 _PA10H.Bits.BIT9 +#define PA10H_BIT10 _PA10H.Bits.BIT10 +#define PA10H_BIT11 _PA10H.Bits.BIT11 +#define PA10H_BIT12 _PA10H.Bits.BIT12 +#define PA10H_BIT13 _PA10H.Bits.BIT13 +#define PA10H_BIT14 _PA10H.Bits.BIT14 +#define PA10H_BIT15 _PA10H.Bits.BIT15 +#define PA10H_BIT _PA10H.MergedBits.grpBIT + + +/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Modulus Down-Counter Bit 8 */ + byte BIT9 :1; /* Modulus Down-Counter Bit 9 */ + byte BIT10 :1; /* Modulus Down-Counter Bit 10 */ + byte BIT11 :1; /* Modulus Down-Counter Bit 11 */ + byte BIT12 :1; /* Modulus Down-Counter Bit 12 */ + byte BIT13 :1; /* Modulus Down-Counter Bit 13 */ + byte BIT14 :1; /* Modulus Down-Counter Bit 14 */ + byte BIT15 :1; /* Modulus Down-Counter Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } MCCNThiSTR; + #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte + #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8 + #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9 + #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10 + #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11 + #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12 + #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13 + #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14 + #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15 + #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8 + #define MCCNThi_BIT MCCNThi_BIT_8 + + /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Modulus Down-Counter Bit 0 */ + byte BIT1 :1; /* Modulus Down-Counter Bit 1 */ + byte BIT2 :1; /* Modulus Down-Counter Bit 2 */ + byte BIT3 :1; /* Modulus Down-Counter Bit 3 */ + byte BIT4 :1; /* Modulus Down-Counter Bit 4 */ + byte BIT5 :1; /* Modulus Down-Counter Bit 5 */ + byte BIT6 :1; /* Modulus Down-Counter Bit 6 */ + byte BIT7 :1; /* Modulus Down-Counter Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } MCCNTloSTR; + #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte + #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0 + #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1 + #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2 + #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3 + #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4 + #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5 + #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6 + #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7 + #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} MCCNTSTR; +extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076); +#define MCCNT _MCCNT.Word +#define MCCNT_BIT _MCCNT.MergedBits.grpBIT + + +/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HhiSTR; + #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte + #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8 + #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9 + #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10 + #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11 + #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12 + #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13 + #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14 + #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15 + #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8 + #define TC0Hhi_BIT TC0Hhi_BIT_8 + + /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0HloSTR; + #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte + #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0 + #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1 + #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2 + #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3 + #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4 + #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5 + #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6 + #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7 + #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC0HSTR; +extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078); +#define TC0H _TC0H.Word +#define TC0H_BIT0 _TC0H.Bits.BIT0 +#define TC0H_BIT1 _TC0H.Bits.BIT1 +#define TC0H_BIT2 _TC0H.Bits.BIT2 +#define TC0H_BIT3 _TC0H.Bits.BIT3 +#define TC0H_BIT4 _TC0H.Bits.BIT4 +#define TC0H_BIT5 _TC0H.Bits.BIT5 +#define TC0H_BIT6 _TC0H.Bits.BIT6 +#define TC0H_BIT7 _TC0H.Bits.BIT7 +#define TC0H_BIT8 _TC0H.Bits.BIT8 +#define TC0H_BIT9 _TC0H.Bits.BIT9 +#define TC0H_BIT10 _TC0H.Bits.BIT10 +#define TC0H_BIT11 _TC0H.Bits.BIT11 +#define TC0H_BIT12 _TC0H.Bits.BIT12 +#define TC0H_BIT13 _TC0H.Bits.BIT13 +#define TC0H_BIT14 _TC0H.Bits.BIT14 +#define TC0H_BIT15 _TC0H.Bits.BIT15 +#define TC0H_BIT _TC0H.MergedBits.grpBIT + + +/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HhiSTR; + #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte + #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8 + #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9 + #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10 + #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11 + #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12 + #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13 + #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14 + #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15 + #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8 + #define TC1Hhi_BIT TC1Hhi_BIT_8 + + /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1HloSTR; + #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte + #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0 + #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1 + #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2 + #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3 + #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4 + #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5 + #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6 + #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7 + #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC1HSTR; +extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A); +#define TC1H _TC1H.Word +#define TC1H_BIT0 _TC1H.Bits.BIT0 +#define TC1H_BIT1 _TC1H.Bits.BIT1 +#define TC1H_BIT2 _TC1H.Bits.BIT2 +#define TC1H_BIT3 _TC1H.Bits.BIT3 +#define TC1H_BIT4 _TC1H.Bits.BIT4 +#define TC1H_BIT5 _TC1H.Bits.BIT5 +#define TC1H_BIT6 _TC1H.Bits.BIT6 +#define TC1H_BIT7 _TC1H.Bits.BIT7 +#define TC1H_BIT8 _TC1H.Bits.BIT8 +#define TC1H_BIT9 _TC1H.Bits.BIT9 +#define TC1H_BIT10 _TC1H.Bits.BIT10 +#define TC1H_BIT11 _TC1H.Bits.BIT11 +#define TC1H_BIT12 _TC1H.Bits.BIT12 +#define TC1H_BIT13 _TC1H.Bits.BIT13 +#define TC1H_BIT14 _TC1H.Bits.BIT14 +#define TC1H_BIT15 _TC1H.Bits.BIT15 +#define TC1H_BIT _TC1H.MergedBits.grpBIT + + +/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HhiSTR; + #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte + #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8 + #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9 + #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10 + #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11 + #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12 + #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13 + #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14 + #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15 + #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8 + #define TC2Hhi_BIT TC2Hhi_BIT_8 + + /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2HloSTR; + #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte + #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0 + #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1 + #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2 + #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3 + #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4 + #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5 + #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6 + #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7 + #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC2HSTR; +extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C); +#define TC2H _TC2H.Word +#define TC2H_BIT0 _TC2H.Bits.BIT0 +#define TC2H_BIT1 _TC2H.Bits.BIT1 +#define TC2H_BIT2 _TC2H.Bits.BIT2 +#define TC2H_BIT3 _TC2H.Bits.BIT3 +#define TC2H_BIT4 _TC2H.Bits.BIT4 +#define TC2H_BIT5 _TC2H.Bits.BIT5 +#define TC2H_BIT6 _TC2H.Bits.BIT6 +#define TC2H_BIT7 _TC2H.Bits.BIT7 +#define TC2H_BIT8 _TC2H.Bits.BIT8 +#define TC2H_BIT9 _TC2H.Bits.BIT9 +#define TC2H_BIT10 _TC2H.Bits.BIT10 +#define TC2H_BIT11 _TC2H.Bits.BIT11 +#define TC2H_BIT12 _TC2H.Bits.BIT12 +#define TC2H_BIT13 _TC2H.Bits.BIT13 +#define TC2H_BIT14 _TC2H.Bits.BIT14 +#define TC2H_BIT15 _TC2H.Bits.BIT15 +#define TC2H_BIT _TC2H.MergedBits.grpBIT + + +/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HhiSTR; + #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte + #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8 + #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9 + #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10 + #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11 + #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12 + #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13 + #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14 + #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15 + #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8 + #define TC3Hhi_BIT TC3Hhi_BIT_8 + + /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3HloSTR; + #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte + #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0 + #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1 + #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2 + #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3 + #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4 + #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5 + #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6 + #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7 + #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC3HSTR; +extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E); +#define TC3H _TC3H.Word +#define TC3H_BIT0 _TC3H.Bits.BIT0 +#define TC3H_BIT1 _TC3H.Bits.BIT1 +#define TC3H_BIT2 _TC3H.Bits.BIT2 +#define TC3H_BIT3 _TC3H.Bits.BIT3 +#define TC3H_BIT4 _TC3H.Bits.BIT4 +#define TC3H_BIT5 _TC3H.Bits.BIT5 +#define TC3H_BIT6 _TC3H.Bits.BIT6 +#define TC3H_BIT7 _TC3H.Bits.BIT7 +#define TC3H_BIT8 _TC3H.Bits.BIT8 +#define TC3H_BIT9 _TC3H.Bits.BIT9 +#define TC3H_BIT10 _TC3H.Bits.BIT10 +#define TC3H_BIT11 _TC3H.Bits.BIT11 +#define TC3H_BIT12 _TC3H.Bits.BIT12 +#define TC3H_BIT13 _TC3H.Bits.BIT13 +#define TC3H_BIT14 _TC3H.Bits.BIT14 +#define TC3H_BIT15 _TC3H.Bits.BIT15 +#define TC3H_BIT _TC3H.MergedBits.grpBIT + + +/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD 0 Wait Mode */ + byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD 0 Disable / Power Down */ + } Bits; + } ATD0CTL2STR; + #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte + #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF + #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE + #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE + #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP + #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE + #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI + #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC + #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU + + /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL3STR; + #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte + #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0 + #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1 + #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO + #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C + #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C + #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C + #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C + #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD 0 Wait Mode */ + word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD 0 Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD0CTL23STR; +extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082); +#define ATD0CTL23 _ATD0CTL23.Word +#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0 +#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1 +#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO +#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C +#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C +#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C +#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C +#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF +#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE +#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE +#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP +#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE +#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI +#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC +#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU +#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ + + +/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */ + byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */ + byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */ + byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */ + byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD 0 Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD0CTL4STR; + #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte + #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0 + #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1 + #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2 + #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3 + #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4 + #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0 + #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1 + #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8 + #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS + #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP + + /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATD0CTL5STR; + #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte + #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA + #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB + #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC + #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT + #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN + #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN + #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD 0 Clock Prescaler 0 */ + word PRS1 :1; /* ATD 0 Clock Prescaler 1 */ + word PRS2 :1; /* ATD 0 Clock Prescaler 2 */ + word PRS3 :1; /* ATD 0 Clock Prescaler 3 */ + word PRS4 :1; /* ATD 0 Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD 0 Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD0CTL45STR; +extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084); +#define ATD0CTL45 _ATD0CTL45.Word +#define ATD0CTL45_CA _ATD0CTL45.Bits.CA +#define ATD0CTL45_CB _ATD0CTL45.Bits.CB +#define ATD0CTL45_CC _ATD0CTL45.Bits.CC +#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT +#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN +#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN +#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM +#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0 +#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1 +#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2 +#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3 +#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4 +#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0 +#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1 +#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8 +#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS +#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP + + +/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR0HSTR; + #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte + #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8 + #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9 + #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10 + #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11 + #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12 + #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13 + #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14 + #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15 + #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8 + #define ATD0DR0H_BIT ATD0DR0H_BIT_8 + + /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR0LSTR; + #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte + #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6 + #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7 + #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6 + #define ATD0DR0L_BIT ATD0DR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR0STR; +extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090); +#define ATD0DR0 _ATD0DR0.Word +#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6 +#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7 +#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8 +#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9 +#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10 +#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11 +#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12 +#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13 +#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14 +#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15 +#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6 +#define ATD0DR0_BIT ATD0DR0_BIT_6 + + +/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR1HSTR; + #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte + #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8 + #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9 + #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10 + #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11 + #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12 + #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13 + #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14 + #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15 + #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8 + #define ATD0DR1H_BIT ATD0DR1H_BIT_8 + + /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR1LSTR; + #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte + #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6 + #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7 + #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6 + #define ATD0DR1L_BIT ATD0DR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR1STR; +extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092); +#define ATD0DR1 _ATD0DR1.Word +#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6 +#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7 +#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8 +#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9 +#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10 +#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11 +#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12 +#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13 +#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14 +#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15 +#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6 +#define ATD0DR1_BIT ATD0DR1_BIT_6 + + +/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR2HSTR; + #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte + #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8 + #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9 + #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10 + #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11 + #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12 + #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13 + #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14 + #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15 + #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8 + #define ATD0DR2H_BIT ATD0DR2H_BIT_8 + + /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR2LSTR; + #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte + #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6 + #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7 + #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6 + #define ATD0DR2L_BIT ATD0DR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR2STR; +extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094); +#define ATD0DR2 _ATD0DR2.Word +#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6 +#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7 +#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8 +#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9 +#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10 +#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11 +#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12 +#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13 +#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14 +#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15 +#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6 +#define ATD0DR2_BIT ATD0DR2_BIT_6 + + +/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR3HSTR; + #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte + #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8 + #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9 + #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10 + #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11 + #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12 + #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13 + #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14 + #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15 + #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8 + #define ATD0DR3H_BIT ATD0DR3H_BIT_8 + + /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR3LSTR; + #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte + #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6 + #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7 + #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6 + #define ATD0DR3L_BIT ATD0DR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR3STR; +extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096); +#define ATD0DR3 _ATD0DR3.Word +#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6 +#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7 +#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8 +#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9 +#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10 +#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11 +#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12 +#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13 +#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14 +#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15 +#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6 +#define ATD0DR3_BIT ATD0DR3_BIT_6 + + +/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR4HSTR; + #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte + #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8 + #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9 + #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10 + #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11 + #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12 + #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13 + #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14 + #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15 + #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8 + #define ATD0DR4H_BIT ATD0DR4H_BIT_8 + + /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR4LSTR; + #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte + #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6 + #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7 + #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6 + #define ATD0DR4L_BIT ATD0DR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR4STR; +extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098); +#define ATD0DR4 _ATD0DR4.Word +#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6 +#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7 +#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8 +#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9 +#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10 +#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11 +#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12 +#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13 +#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14 +#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15 +#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6 +#define ATD0DR4_BIT ATD0DR4_BIT_6 + + +/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR5HSTR; + #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte + #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8 + #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9 + #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10 + #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11 + #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12 + #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13 + #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14 + #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15 + #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8 + #define ATD0DR5H_BIT ATD0DR5H_BIT_8 + + /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR5LSTR; + #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte + #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6 + #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7 + #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6 + #define ATD0DR5L_BIT ATD0DR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR5STR; +extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A); +#define ATD0DR5 _ATD0DR5.Word +#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6 +#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7 +#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8 +#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9 +#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10 +#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11 +#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12 +#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13 +#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14 +#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15 +#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6 +#define ATD0DR5_BIT ATD0DR5_BIT_6 + + +/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR6HSTR; + #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte + #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8 + #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9 + #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10 + #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11 + #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12 + #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13 + #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14 + #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15 + #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8 + #define ATD0DR6H_BIT ATD0DR6H_BIT_8 + + /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR6LSTR; + #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte + #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6 + #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7 + #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6 + #define ATD0DR6L_BIT ATD0DR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR6STR; +extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C); +#define ATD0DR6 _ATD0DR6.Word +#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6 +#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7 +#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8 +#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9 +#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10 +#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11 +#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12 +#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13 +#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14 +#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15 +#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6 +#define ATD0DR6_BIT ATD0DR6_BIT_6 + + +/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR7HSTR; + #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte + #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8 + #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9 + #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10 + #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11 + #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12 + #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13 + #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14 + #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15 + #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8 + #define ATD0DR7H_BIT ATD0DR7H_BIT_8 + + /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR7LSTR; + #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte + #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6 + #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7 + #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6 + #define ATD0DR7L_BIT ATD0DR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR7STR; +extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E); +#define ATD0DR7 _ATD0DR7.Word +#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6 +#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7 +#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8 +#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9 +#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10 +#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11 +#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12 +#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13 +#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14 +#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15 +#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6 +#define ATD0DR7_BIT ATD0DR7_BIT_6 + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC); +#define PWMCNT01 _PWMCNT01.Word +#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE); +#define PWMCNT23 _PWMCNT23.Word +#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0); +#define PWMCNT45 _PWMCNT45.Word +#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT + + +/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT6STR; + #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte + #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT + + /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT7STR; + #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte + #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT67STR; +extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2); +#define PWMCNT67 _PWMCNT67.Word +#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4); +#define PWMPER01 _PWMPER01.Word +#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6); +#define PWMPER23 _PWMPER23.Word +#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8); +#define PWMPER45 _PWMPER45.Word +#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT + + +/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER6STR; + #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte + #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT + + /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER7STR; + #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte + #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER67STR; +extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA); +#define PWMPER67 _PWMPER67.Word +#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC); +#define PWMDTY01 _PWMDTY01.Word +#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE); +#define PWMDTY23 _PWMDTY23.Word +#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0); +#define PWMDTY45 _PWMDTY45.Word +#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT + + +/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY6STR; + #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte + #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT + + /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY7STR; + #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte + #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY67STR; +extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2); +#define PWMDTY67 _PWMDTY67.Word +#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT + + +/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI 0 baud rate Bit 8 */ + byte SBR9 :1; /* SCI 0 baud rate Bit 9 */ + byte SBR10 :1; /* SCI 0 baud rate Bit 10 */ + byte SBR11 :1; /* SCI 0 baud rate Bit 11 */ + byte SBR12 :1; /* SCI 0 baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI0BDHSTR; + #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte + #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8 + #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9 + #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10 + #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11 + #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12 + #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8 + #define SCI0BDH_SBR SCI0BDH_SBR_8 + + /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI 0 baud rate Bit 0 */ + byte SBR1 :1; /* SCI 0 baud rate Bit 1 */ + byte SBR2 :1; /* SCI 0 baud rate Bit 2 */ + byte SBR3 :1; /* SCI 0 baud rate Bit 3 */ + byte SBR4 :1; /* SCI 0 baud rate Bit 4 */ + byte SBR5 :1; /* SCI 0 baud rate Bit 5 */ + byte SBR6 :1; /* SCI 0 baud rate Bit 6 */ + byte SBR7 :1; /* SCI 0 baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCI0BDLSTR; + #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte + #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0 + #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1 + #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2 + #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3 + #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4 + #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5 + #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6 + #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7 + #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI 0 baud rate Bit 0 */ + word SBR1 :1; /* SCI 0 baud rate Bit 1 */ + word SBR2 :1; /* SCI 0 baud rate Bit 2 */ + word SBR3 :1; /* SCI 0 baud rate Bit 3 */ + word SBR4 :1; /* SCI 0 baud rate Bit 4 */ + word SBR5 :1; /* SCI 0 baud rate Bit 5 */ + word SBR6 :1; /* SCI 0 baud rate Bit 6 */ + word SBR7 :1; /* SCI 0 baud rate Bit 7 */ + word SBR8 :1; /* SCI 0 baud rate Bit 8 */ + word SBR9 :1; /* SCI 0 baud rate Bit 9 */ + word SBR10 :1; /* SCI 0 baud rate Bit 10 */ + word SBR11 :1; /* SCI 0 baud rate Bit 11 */ + word SBR12 :1; /* SCI 0 baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI0BDSTR; +extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8); +#define SCI0BD _SCI0BD.Word +#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 +#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 +#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 +#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 +#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 +#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 +#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 +#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 +#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 +#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 +#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 +#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 +#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 +#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR + + +/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI 1 baud rate Bit 8 */ + byte SBR9 :1; /* SCI 1 baud rate Bit 9 */ + byte SBR10 :1; /* SCI 1 baud rate Bit 10 */ + byte SBR11 :1; /* SCI 1 baud rate Bit 11 */ + byte SBR12 :1; /* SCI 1 baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI1BDHSTR; + #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte + #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 + #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 + #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 + #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 + #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 + #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 + #define SCI1BDH_SBR SCI1BDH_SBR_8 + + /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI 1 baud rate Bit 0 */ + byte SBR1 :1; /* SCI 1 baud rate Bit 1 */ + byte SBR2 :1; /* SCI 1 baud rate Bit 2 */ + byte SBR3 :1; /* SCI 1 baud rate Bit 3 */ + byte SBR4 :1; /* SCI 1 baud rate Bit 4 */ + byte SBR5 :1; /* SCI 1 baud rate Bit 5 */ + byte SBR6 :1; /* SCI 1 baud rate Bit 6 */ + byte SBR7 :1; /* SCI 1 baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCI1BDLSTR; + #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte + #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 + #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 + #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 + #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 + #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 + #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 + #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 + #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 + #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI 1 baud rate Bit 0 */ + word SBR1 :1; /* SCI 1 baud rate Bit 1 */ + word SBR2 :1; /* SCI 1 baud rate Bit 2 */ + word SBR3 :1; /* SCI 1 baud rate Bit 3 */ + word SBR4 :1; /* SCI 1 baud rate Bit 4 */ + word SBR5 :1; /* SCI 1 baud rate Bit 5 */ + word SBR6 :1; /* SCI 1 baud rate Bit 6 */ + word SBR7 :1; /* SCI 1 baud rate Bit 7 */ + word SBR8 :1; /* SCI 1 baud rate Bit 8 */ + word SBR9 :1; /* SCI 1 baud rate Bit 9 */ + word SBR10 :1; /* SCI 1 baud rate Bit 10 */ + word SBR11 :1; /* SCI 1 baud rate Bit 11 */ + word SBR12 :1; /* SCI 1 baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI1BDSTR; +extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0); +#define SCI1BD _SCI1BD.Word +#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 +#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 +#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 +#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 +#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 +#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 +#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 +#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 +#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 +#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 +#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 +#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 +#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 +#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR + + +/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD 1 Wait Mode */ + byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD 1 Disable / Power Down */ + } Bits; + } ATD1CTL2STR; + #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte + #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF + #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE + #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE + #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP + #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE + #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI + #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC + #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU + + /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL3STR; + #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte + #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0 + #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1 + #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO + #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C + #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C + #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C + #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C + #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD 1 Wait Mode */ + word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD 1 Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD1CTL23STR; +extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122); +#define ATD1CTL23 _ATD1CTL23.Word +#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0 +#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1 +#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO +#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C +#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C +#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C +#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C +#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF +#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE +#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE +#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP +#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE +#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI +#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC +#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU +#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ + + +/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */ + byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */ + byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */ + byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */ + byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD 1 Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD1CTL4STR; + #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte + #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0 + #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1 + #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2 + #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3 + #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4 + #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0 + #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1 + #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8 + #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS + #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP + + /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATD1CTL5STR; + #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte + #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA + #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB + #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC + #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT + #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN + #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN + #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD 1 Clock Prescaler 0 */ + word PRS1 :1; /* ATD 1 Clock Prescaler 1 */ + word PRS2 :1; /* ATD 1 Clock Prescaler 2 */ + word PRS3 :1; /* ATD 1 Clock Prescaler 3 */ + word PRS4 :1; /* ATD 1 Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD 1 Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD1CTL45STR; +extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124); +#define ATD1CTL45 _ATD1CTL45.Word +#define ATD1CTL45_CA _ATD1CTL45.Bits.CA +#define ATD1CTL45_CB _ATD1CTL45.Bits.CB +#define ATD1CTL45_CC _ATD1CTL45.Bits.CC +#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT +#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN +#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN +#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM +#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0 +#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1 +#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2 +#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3 +#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4 +#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0 +#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1 +#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8 +#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS +#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP + + +/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR0HSTR; + #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte + #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8 + #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9 + #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10 + #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11 + #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12 + #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13 + #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14 + #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15 + #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8 + #define ATD1DR0H_BIT ATD1DR0H_BIT_8 + + /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR0LSTR; + #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte + #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6 + #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7 + #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6 + #define ATD1DR0L_BIT ATD1DR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR0STR; +extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130); +#define ATD1DR0 _ATD1DR0.Word +#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6 +#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7 +#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8 +#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9 +#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10 +#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11 +#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12 +#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13 +#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14 +#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15 +#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6 +#define ATD1DR0_BIT ATD1DR0_BIT_6 + + +/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR1HSTR; + #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte + #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8 + #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9 + #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10 + #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11 + #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12 + #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13 + #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14 + #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15 + #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8 + #define ATD1DR1H_BIT ATD1DR1H_BIT_8 + + /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR1LSTR; + #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte + #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6 + #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7 + #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6 + #define ATD1DR1L_BIT ATD1DR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR1STR; +extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132); +#define ATD1DR1 _ATD1DR1.Word +#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6 +#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7 +#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8 +#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9 +#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10 +#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11 +#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12 +#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13 +#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14 +#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15 +#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6 +#define ATD1DR1_BIT ATD1DR1_BIT_6 + + +/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR2HSTR; + #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte + #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8 + #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9 + #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10 + #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11 + #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12 + #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13 + #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14 + #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15 + #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8 + #define ATD1DR2H_BIT ATD1DR2H_BIT_8 + + /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR2LSTR; + #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte + #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6 + #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7 + #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6 + #define ATD1DR2L_BIT ATD1DR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR2STR; +extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134); +#define ATD1DR2 _ATD1DR2.Word +#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6 +#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7 +#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8 +#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9 +#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10 +#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11 +#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12 +#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13 +#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14 +#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15 +#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6 +#define ATD1DR2_BIT ATD1DR2_BIT_6 + + +/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR3HSTR; + #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte + #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8 + #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9 + #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10 + #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11 + #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12 + #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13 + #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14 + #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15 + #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8 + #define ATD1DR3H_BIT ATD1DR3H_BIT_8 + + /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR3LSTR; + #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte + #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6 + #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7 + #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6 + #define ATD1DR3L_BIT ATD1DR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR3STR; +extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136); +#define ATD1DR3 _ATD1DR3.Word +#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6 +#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7 +#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8 +#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9 +#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10 +#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11 +#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12 +#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13 +#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14 +#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15 +#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6 +#define ATD1DR3_BIT ATD1DR3_BIT_6 + + +/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR4HSTR; + #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte + #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8 + #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9 + #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10 + #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11 + #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12 + #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13 + #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14 + #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15 + #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8 + #define ATD1DR4H_BIT ATD1DR4H_BIT_8 + + /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR4LSTR; + #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte + #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6 + #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7 + #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6 + #define ATD1DR4L_BIT ATD1DR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR4STR; +extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138); +#define ATD1DR4 _ATD1DR4.Word +#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6 +#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7 +#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8 +#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9 +#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10 +#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11 +#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12 +#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13 +#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14 +#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15 +#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6 +#define ATD1DR4_BIT ATD1DR4_BIT_6 + + +/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR5HSTR; + #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte + #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8 + #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9 + #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10 + #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11 + #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12 + #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13 + #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14 + #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15 + #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8 + #define ATD1DR5H_BIT ATD1DR5H_BIT_8 + + /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR5LSTR; + #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte + #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6 + #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7 + #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6 + #define ATD1DR5L_BIT ATD1DR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR5STR; +extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A); +#define ATD1DR5 _ATD1DR5.Word +#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6 +#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7 +#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8 +#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9 +#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10 +#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11 +#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12 +#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13 +#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14 +#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15 +#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6 +#define ATD1DR5_BIT ATD1DR5_BIT_6 + + +/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR6HSTR; + #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte + #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8 + #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9 + #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10 + #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11 + #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12 + #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13 + #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14 + #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15 + #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8 + #define ATD1DR6H_BIT ATD1DR6H_BIT_8 + + /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR6LSTR; + #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte + #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6 + #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7 + #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6 + #define ATD1DR6L_BIT ATD1DR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR6STR; +extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C); +#define ATD1DR6 _ATD1DR6.Word +#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6 +#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7 +#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8 +#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9 +#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10 +#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11 +#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12 +#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13 +#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14 +#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15 +#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6 +#define ATD1DR6_BIT ATD1DR6_BIT_6 + + +/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR7HSTR; + #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte + #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8 + #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9 + #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10 + #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11 + #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12 + #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13 + #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14 + #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15 + #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8 + #define ATD1DR7H_BIT ATD1DR7H_BIT_8 + + /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR7LSTR; + #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte + #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6 + #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7 + #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6 + #define ATD1DR7L_BIT ATD1DR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR7STR; +extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E); +#define ATD1DR7 _ATD1DR7.Word +#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6 +#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7 +#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8 +#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9 +#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10 +#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11 +#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12 +#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13 +#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14 +#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15 +#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6 +#define ATD1DR7_BIT ATD1DR7_BIT_6 + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0, XIRQ */ + byte BIT1 :1; /* Port E Bit 1, IRQ */ + byte BIT2 :1; /* Port E Bit 2, R/W */ + byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */ + byte BIT4 :1; /* Port E Bit 4, ECLK */ + byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */ + byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */ + byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 +#define PORTE_BIT _PORTE.MergedBits.grpBIT + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); +#define DDRE _DDRE.Byte +#define DDRE_BIT0 _DDRE.Bits.BIT0 +#define DDRE_BIT1 _DDRE.Bits.BIT1 +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT _DDRE.MergedBits.grpBIT + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + + +/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position REG11 */ + byte REG12 :1; /* Internal register map position REG12 */ + byte REG13 :1; /* Internal register map position REG13 */ + byte REG14 :1; /* Internal register map position REG14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + + +/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + + +/*** MTST0 - MTST0; 0x00000014 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST0 Bit 0 */ + byte BIT1 :1; /* MTST0 Bit 1 */ + byte BIT2 :1; /* MTST0 Bit 2 */ + byte BIT3 :1; /* MTST0 Bit 3 */ + byte BIT4 :1; /* MTST0 Bit 4 */ + byte BIT5 :1; /* MTST0 Bit 5 */ + byte BIT6 :1; /* MTST0 Bit 6 */ + byte BIT7 :1; /* MTST0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST0STR; +extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); +#define MTST0 _MTST0.Byte +#define MTST0_BIT0 _MTST0.Bits.BIT0 +#define MTST0_BIT1 _MTST0.Bits.BIT1 +#define MTST0_BIT2 _MTST0.Bits.BIT2 +#define MTST0_BIT3 _MTST0.Bits.BIT3 +#define MTST0_BIT4 _MTST0.Bits.BIT4 +#define MTST0_BIT5 _MTST0.Bits.BIT5 +#define MTST0_BIT6 _MTST0.Bits.BIT6 +#define MTST0_BIT7 _MTST0.Bits.BIT7 +#define MTST0_BIT _MTST0.MergedBits.grpBIT + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + + +/*** MTST1 - MTST1; 0x00000017 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST1 Bit 0 */ + byte BIT1 :1; /* MTST1 Bit 1 */ + byte BIT2 :1; /* MTST1 Bit 2 */ + byte BIT3 :1; /* MTST1 Bit 3 */ + byte BIT4 :1; /* MTST1 Bit 4 */ + byte BIT5 :1; /* MTST1 Bit 5 */ + byte BIT6 :1; /* MTST1 Bit 6 */ + byte BIT7 :1; /* MTST1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST1STR; +extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); +#define MTST1 _MTST1.Byte +#define MTST1_BIT0 _MTST1.Bits.BIT0 +#define MTST1_BIT1 _MTST1.Bits.BIT1 +#define MTST1_BIT2 _MTST1.Bits.BIT2 +#define MTST1_BIT3 _MTST1.Bits.BIT3 +#define MTST1_BIT4 _MTST1.Bits.BIT4 +#define MTST1_BIT5 _MTST1.Bits.BIT5 +#define MTST1_BIT6 _MTST1.Bits.BIT6 +#define MTST1_BIT7 _MTST1.Bits.BIT7 +#define MTST1_BIT _MTST1.MergedBits.grpBIT + + +/*** PARTIDH - Part ID Register High; 0x0000001A ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Part ID Register Bit 15 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID8 :1; /* Part ID Register Bit 8 */ + } Bits; +} PARTIDHSTR; +extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); +#define PARTIDH _PARTIDH.Byte +#define PARTIDH_ID15 _PARTIDH.Bits.ID15 +#define PARTIDH_ID14 _PARTIDH.Bits.ID14 +#define PARTIDH_ID13 _PARTIDH.Bits.ID13 +#define PARTIDH_ID12 _PARTIDH.Bits.ID12 +#define PARTIDH_ID11 _PARTIDH.Bits.ID11 +#define PARTIDH_ID10 _PARTIDH.Bits.ID10 +#define PARTIDH_ID9 _PARTIDH.Bits.ID9 +#define PARTIDH_ID8 _PARTIDH.Bits.ID8 + + +/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ +typedef union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + struct { + byte grpID :8; + } MergedBits; +} PARTIDLSTR; +extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); +#define PARTIDL _PARTIDL.Byte +#define PARTIDL_ID0 _PARTIDL.Bits.ID0 +#define PARTIDL_ID1 _PARTIDL.Bits.ID1 +#define PARTIDL_ID2 _PARTIDL.Bits.ID2 +#define PARTIDL_ID3 _PARTIDL.Bits.ID3 +#define PARTIDL_ID4 _PARTIDL.Bits.ID4 +#define PARTIDL_ID5 _PARTIDL.Bits.ID5 +#define PARTIDL_ID6 _PARTIDL.Bits.ID6 +#define PARTIDL_ID7 _PARTIDL.Bits.ID7 +#define PARTIDL_ID _PARTIDL.MergedBits.grpID + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 +#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 +#define BKP0H_BIT BKP0H_BIT_8 + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 +#define BKP0L_BIT _BKP0L.MergedBits.grpBIT + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 +#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 +#define BKP1H_BIT BKP1H_BIT_8 + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 +#define BKP1L_BIT _BKP1L.MergedBits.grpBIT + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0 */ + byte BIT1 :1; /* Port K Bit 1 */ + byte BIT2 :1; /* Port K Bit 2 */ + byte BIT3 :1; /* Port K Bit 3 */ + byte BIT4 :1; /* Port K Bit 4 */ + byte BIT5 :1; /* Port K Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte DDK0 :1; /* Port K Data Direction Bit 0 */ + byte DDK1 :1; /* Port K Data Direction Bit 1 */ + byte DDK2 :1; /* Port K Data Direction Bit 2 */ + byte DDK3 :1; /* Port K Data Direction Bit 3 */ + byte DDK4 :1; /* Port K Data Direction Bit 4 */ + byte DDK5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte DDK7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDK :6; + byte :1; + byte grpDDK_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); +#define DDRK _DDRK.Byte +#define DDRK_DDK0 _DDRK.Bits.DDK0 +#define DDRK_DDK1 _DDRK.Bits.DDK1 +#define DDRK_DDK2 _DDRK.Bits.DDK2 +#define DDRK_DDK3 _DDRK.Bits.DDK3 +#define DDRK_DDK4 _DDRK.Bits.DDK4 +#define DDRK_DDK5 _DDRK.Bits.DDK5 +#define DDRK_DDK7 _DDRK.Bits.DDK7 +#define DDRK_DDK _DDRK.MergedBits.grpDDK + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + + +/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ +typedef union { + byte Byte; + struct { + byte TOUT0 :1; /* CRG Test Flags Bit 0 */ + byte TOUT1 :1; /* CRG Test Flags Bit 1 */ + byte TOUT2 :1; /* CRG Test Flags Bit 2 */ + byte TOUT3 :1; /* CRG Test Flags Bit 3 */ + byte TOUT4 :1; /* CRG Test Flags Bit 4 */ + byte TOUT5 :1; /* CRG Test Flags Bit 5 */ + byte TOUT6 :1; /* CRG Test Flags Bit 6 */ + byte TOUT7 :1; /* CRG Test Flags Bit 7 */ + } Bits; + struct { + byte grpTOUT :8; + } MergedBits; +} CTFLGSTR; +extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); +#define CTFLG _CTFLG.Byte +#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 +#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 +#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 +#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 +#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 +#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 +#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 +#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 +#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte :1; + byte :1; + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Crystal Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + + +/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Bit 0 */ + byte BIT1 :1; /* Bit 1 */ + byte BIT2 :1; /* Bit 2 */ + byte BIT3 :1; /* Bit 3 */ + byte BIT4 :1; /* Bit 4 */ + byte BIT5 :1; /* Bit 5 */ + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} FORBYPSTR; +extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D); +#define FORBYP _FORBYP.Byte +#define FORBYP_BIT0 _FORBYP.Bits.BIT0 +#define FORBYP_BIT1 _FORBYP.Bits.BIT1 +#define FORBYP_BIT2 _FORBYP.Bits.BIT2 +#define FORBYP_BIT3 _FORBYP.Bits.BIT3 +#define FORBYP_BIT4 _FORBYP.Bits.BIT4 +#define FORBYP_BIT5 _FORBYP.Bits.BIT5 +#define FORBYP_BIT6 _FORBYP.Bits.BIT6 +#define FORBYP_BIT7 _FORBYP.Bits.BIT7 +#define FORBYP_BIT _FORBYP.MergedBits.grpBIT + + +/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ +typedef union { + byte Byte; + struct { + byte TCTL0 :1; /* CRG Test Control Bit 0 */ + byte TCTL1 :1; /* CRG Test Control Bit 1 */ + byte TCTL2 :1; /* CRG Test Control Bit 2 */ + byte TCTL3 :1; /* CRG Test Control Bit 3 */ + byte TCTL4 :1; /* CRG Test Control Bit 4 */ + byte TCTL5 :1; /* CRG Test Control Bit 5 */ + byte TCTL6 :1; /* CRG Test Control Bit 6 */ + byte TCTL7 :1; /* CRG Test Control Bit 7 */ + } Bits; + struct { + byte grpTCTL :8; + } MergedBits; +} CTCTLSTR; +extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); +#define CTCTL _CTCTL.Byte +#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 +#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 +#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 +#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 +#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 +#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 +#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 +#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 +#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 +#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; + struct { + byte grpIOS :8; + } MergedBits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 +#define TIOS_IOS _TIOS.MergedBits.grpIOS + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; + struct { + byte grpFOC :8; + } MergedBits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 +#define CFORC_FOC _CFORC.MergedBits.grpFOC + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; + struct { + byte grpOC7M :8; + } MergedBits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 +#define OC7M_OC7M _OC7M.MergedBits.grpOC7M + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; + struct { + byte grpOC7D :8; + } MergedBits; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); +#define OC7D _OC7D.Byte +#define OC7D_OC7D _OC7D.MergedBits.grpOC7D + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; + struct { + byte grpTOV :8; + } MergedBits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 +#define TTOV_TOV _TTOV.MergedBits.grpTOV + + +/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + + +/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + + +/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/ +typedef union { + byte Byte; + struct { + byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */ + byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */ + byte MCEN :1; /* Modulus Down-Counter Enable */ + byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */ + byte ICLAT :1; /* Input Capture Force Latch Action */ + byte RDMCL :1; /* Read Modulus Down-Counter Load */ + byte MODMC :1; /* Modulus Mode Enable */ + byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */ + } Bits; + struct { + byte grpMCPR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCCTLSTR; +extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066); +#define MCCTL _MCCTL.Byte +#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0 +#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1 +#define MCCTL_MCEN _MCCTL.Bits.MCEN +#define MCCTL_FLMC _MCCTL.Bits.FLMC +#define MCCTL_ICLAT _MCCTL.Bits.ICLAT +#define MCCTL_RDMCL _MCCTL.Bits.RDMCL +#define MCCTL_MODMC _MCCTL.Bits.MODMC +#define MCCTL_MCZI _MCCTL.Bits.MCZI +#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR + + +/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/ +typedef union { + byte Byte; + struct { + byte POLF0 :1; /* First Input Capture Polarity Status 0 */ + byte POLF1 :1; /* First Input Capture Polarity Status 1 */ + byte POLF2 :1; /* First Input Capture Polarity Status 2 */ + byte POLF3 :1; /* First Input Capture Polarity Status 3 */ + byte :1; + byte :1; + byte :1; + byte MCZF :1; /* Modulus Counter Underflow Flag */ + } Bits; + struct { + byte grpPOLF :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCFLGSTR; +extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067); +#define MCFLG _MCFLG.Byte +#define MCFLG_POLF0 _MCFLG.Bits.POLF0 +#define MCFLG_POLF1 _MCFLG.Bits.POLF1 +#define MCFLG_POLF2 _MCFLG.Bits.POLF2 +#define MCFLG_POLF3 _MCFLG.Bits.POLF3 +#define MCFLG_MCZF _MCFLG.Bits.MCZF +#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF + + +/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/ +typedef union { + byte Byte; + struct { + byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */ + byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */ + byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */ + byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ICPARSTR; +extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068); +#define ICPAR _ICPAR.Byte +#define ICPAR_PA0EN _ICPAR.Bits.PA0EN +#define ICPAR_PA1EN _ICPAR.Bits.PA1EN +#define ICPAR_PA2EN _ICPAR.Bits.PA2EN +#define ICPAR_PA3EN _ICPAR.Bits.PA3EN + + +/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/ +typedef union { + byte Byte; + struct { + byte DLY0 :1; /* Delay Counter Select 0 */ + byte DLY1 :1; /* Delay Counter Select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLY :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLYCTSTR; +extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069); +#define DLYCT _DLYCT.Byte +#define DLYCT_DLY0 _DLYCT.Bits.DLY0 +#define DLYCT_DLY1 _DLYCT.Bits.DLY1 +#define DLYCT_DLY _DLYCT.MergedBits.grpDLY + + +/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/ +typedef union { + byte Byte; + struct { + byte NOVW0 :1; /* No Input Capture Overwrite 0 */ + byte NOVW1 :1; /* No Input Capture Overwrite 1 */ + byte NOVW2 :1; /* No Input Capture Overwrite 2 */ + byte NOVW3 :1; /* No Input Capture Overwrite 3 */ + byte NOVW4 :1; /* No Input Capture Overwrite 4 */ + byte NOVW5 :1; /* No Input Capture Overwrite 5 */ + byte NOVW6 :1; /* No Input Capture Overwrite 6 */ + byte NOVW7 :1; /* No Input Capture Overwrite 7 */ + } Bits; + struct { + byte grpNOVW :8; + } MergedBits; +} ICOVWSTR; +extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A); +#define ICOVW _ICOVW.Byte +#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0 +#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1 +#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2 +#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3 +#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4 +#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5 +#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6 +#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7 +#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW + + +/*** ICSYS - Input Control System Control Register; 0x0000006B ***/ +typedef union { + byte Byte; + struct { + byte LATQ :1; /* Input Control Latch or Queue Mode Enable */ + byte BUFEN :1; /* IC Buffer Enable */ + byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */ + byte TFMOD :1; /* Timer Flag-setting Mode */ + byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */ + byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */ + byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */ + byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */ + } Bits; +} ICSYSSTR; +extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B); +#define ICSYS _ICSYS.Byte +#define ICSYS_LATQ _ICSYS.Bits.LATQ +#define ICSYS_BUFEN _ICSYS.Bits.BUFEN +#define ICSYS_PACMX _ICSYS.Bits.PACMX +#define ICSYS_TFMOD _ICSYS.Bits.TFMOD +#define ICSYS_SH04 _ICSYS.Bits.SH04 +#define ICSYS_SH15 _ICSYS.Bits.SH15 +#define ICSYS_SH26 _ICSYS.Bits.SH26 +#define ICSYS_SH37 _ICSYS.Bits.SH37 + + +/*** TIMTST - Timer Test Register; 0x0000006D ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte TCBYP :1; /* Main Timer Divider Chain Bypass */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIMTSTSTR; +extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D); +#define TIMTST _TIMTST.Byte +#define TIMTST_TCBYP _TIMTST.Bits.TCBYP + + +/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PBEN :1; /* Pulse Accumulator B System Enable */ + byte :1; + } Bits; +} PBCTLSTR; +extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070); +#define PBCTL _PBCTL.Byte +#define PBCTL_PBOVI _PBCTL.Bits.PBOVI +#define PBCTL_PBEN _PBCTL.Bits.PBEN + + +/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PBFLGSTR; +extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071); +#define PBFLG _PBFLG.Byte +#define PBFLG_PBOVF _PBFLG.Bits.PBOVF + + +/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD0STAT0STR; +extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086); +#define ATD0STAT0 _ATD0STAT0.Byte +#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0 +#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1 +#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2 +#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR +#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF +#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF +#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC + + +/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATD0STAT1STR; +extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B); +#define ATD0STAT1 _ATD0STAT1.Byte +#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0 +#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1 +#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2 +#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3 +#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4 +#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5 +#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6 +#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7 +#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF + + +/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ + byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ + byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ + byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ + byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ + byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ + byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ + byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATD0DIENSTR; +extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D); +#define ATD0DIEN _ATD0DIEN.Byte +#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0 +#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1 +#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2 +#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3 +#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4 +#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5 +#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6 +#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7 +#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 +#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 +#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 +#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 +#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 +#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 +#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 +#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 +#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT + + +/*** PWME - PWM Enable Register; 0x000000A0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; + struct { + byte grpPWME :8; + } MergedBits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 +#define PWME_PWME _PWME.MergedBits.grpPWME + + +/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; + struct { + byte grpPPOL :8; + } MergedBits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 +#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL + + +/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; + struct { + byte grpPCLK :8; + } MergedBits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 +#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; + struct { + byte grpCAE :8; + } MergedBits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 +#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE + + +/*** PWMCTL - PWM Control Register; 0x000000A5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + + +/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 +#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT + + +/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 +#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT + + +/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + + +/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI0CR1STR; +extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA); +#define SCI0CR1 _SCI0CR1.Byte +#define SCI0CR1_PT _SCI0CR1.Bits.PT +#define SCI0CR1_PE _SCI0CR1.Bits.PE +#define SCI0CR1_ILT _SCI0CR1.Bits.ILT +#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE +#define SCI0CR1_M _SCI0CR1.Bits.M +#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC +#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI +#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS + + +/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI0CR2STR; +extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB); +#define SCI0CR2 _SCI0CR2.Byte +#define SCI0CR2_SBK _SCI0CR2.Bits.SBK +#define SCI0CR2_RWU _SCI0CR2.Bits.RWU +#define SCI0CR2_RE _SCI0CR2.Bits.RE +#define SCI0CR2_TE _SCI0CR2.Bits.TE +#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE +#define SCI0CR2_RIE _SCI0CR2.Bits.RIE +#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE +#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE + + +/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI0SR1STR; +extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC); +#define SCI0SR1 _SCI0SR1.Byte +#define SCI0SR1_PF _SCI0SR1.Bits.PF +#define SCI0SR1_FE _SCI0SR1.Bits.FE +#define SCI0SR1_NF _SCI0SR1.Bits.NF +#define SCI0SR1_OR _SCI0SR1.Bits.OR +#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE +#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF +#define SCI0SR1_TC _SCI0SR1.Bits.TC +#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE + + +/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI0SR2STR; +extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD); +#define SCI0SR2 _SCI0SR2.Byte +#define SCI0SR2_RAF _SCI0SR2.Bits.RAF +#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR +#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 + + +/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI0DRHSTR; +extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE); +#define SCI0DRH _SCI0DRH.Byte +#define SCI0DRH_T8 _SCI0DRH.Bits.T8 +#define SCI0DRH_R8 _SCI0DRH.Bits.R8 + + +/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI0DRLSTR; +extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF); +#define SCI0DRL _SCI0DRL.Byte +#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 +#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 +#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 +#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 +#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 +#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 +#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 +#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 + + +/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI1CR1STR; +extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2); +#define SCI1CR1 _SCI1CR1.Byte +#define SCI1CR1_PT _SCI1CR1.Bits.PT +#define SCI1CR1_PE _SCI1CR1.Bits.PE +#define SCI1CR1_ILT _SCI1CR1.Bits.ILT +#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE +#define SCI1CR1_M _SCI1CR1.Bits.M +#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC +#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI +#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS + + +/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI1CR2STR; +extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3); +#define SCI1CR2 _SCI1CR2.Byte +#define SCI1CR2_SBK _SCI1CR2.Bits.SBK +#define SCI1CR2_RWU _SCI1CR2.Bits.RWU +#define SCI1CR2_RE _SCI1CR2.Bits.RE +#define SCI1CR2_TE _SCI1CR2.Bits.TE +#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE +#define SCI1CR2_RIE _SCI1CR2.Bits.RIE +#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE +#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE + + +/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI1SR1STR; +extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4); +#define SCI1SR1 _SCI1SR1.Byte +#define SCI1SR1_PF _SCI1SR1.Bits.PF +#define SCI1SR1_FE _SCI1SR1.Bits.FE +#define SCI1SR1_NF _SCI1SR1.Bits.NF +#define SCI1SR1_OR _SCI1SR1.Bits.OR +#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE +#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF +#define SCI1SR1_TC _SCI1SR1.Bits.TC +#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE + + +/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI1SR2STR; +extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5); +#define SCI1SR2 _SCI1SR2.Byte +#define SCI1SR2_RAF _SCI1SR2.Bits.RAF +#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR +#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 + + +/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI1DRHSTR; +extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6); +#define SCI1DRH _SCI1DRH.Byte +#define SCI1DRH_T8 _SCI1DRH.Bits.T8 +#define SCI1DRH_R8 _SCI1DRH.Bits.R8 + + +/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI1DRLSTR; +extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7); +#define SCI1DRL _SCI1DRL.Byte +#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 +#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 +#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 +#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 +#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 +#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 +#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 +#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 + + +/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 0 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 0 Clock Phase Bit */ + byte CPOL :1; /* SPI 0 Clock Polarity Bit */ + byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 0 System Enable Bit */ + byte SPIE :1; /* SPI 0 Interrupt Enable Bit */ + } Bits; +} SPI0CR1STR; +extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8); +#define SPI0CR1 _SPI0CR1.Byte +#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE +#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE +#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA +#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL +#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR +#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE +#define SPI0CR1_SPE _SPI0CR1.Bits.SPE +#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE + + +/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI0CR2STR; +extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9); +#define SPI0CR2 _SPI0CR2.Byte +#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 +#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI +#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE +#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN + + +/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI0BRSTR; +extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA); +#define SPI0BR _SPI0BR.Byte +#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 +#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 +#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 +#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 +#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 +#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 +#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR +#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR + + +/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI0SRSTR; +extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB); +#define SPI0SR _SPI0SR.Byte +#define SPI0SR_MODF _SPI0SR.Bits.MODF +#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF +#define SPI0SR_SPIF _SPI0SR.Bits.SPIF + + +/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI0DRSTR; +extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD); +#define SPI0DR _SPI0DR.Byte +#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT + + +/*** IBAD - IIC Address Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte ADR1 :1; /* Slave Address Bit 1 */ + byte ADR2 :1; /* Slave Address Bit 2 */ + byte ADR3 :1; /* Slave Address Bit 3 */ + byte ADR4 :1; /* Slave Address Bit 4 */ + byte ADR5 :1; /* Slave Address Bit 5 */ + byte ADR6 :1; /* Slave Address Bit 6 */ + byte ADR7 :1; /* Slave Address Bit 7 */ + } Bits; + struct { + byte :1; + byte grpADR_1 :7; + } MergedBits; +} IBADSTR; +extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0); +#define IBAD _IBAD.Byte +#define IBAD_ADR1 _IBAD.Bits.ADR1 +#define IBAD_ADR2 _IBAD.Bits.ADR2 +#define IBAD_ADR3 _IBAD.Bits.ADR3 +#define IBAD_ADR4 _IBAD.Bits.ADR4 +#define IBAD_ADR5 _IBAD.Bits.ADR5 +#define IBAD_ADR6 _IBAD.Bits.ADR6 +#define IBAD_ADR7 _IBAD.Bits.ADR7 +#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1 +#define IBAD_ADR IBAD_ADR_1 + + +/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte IBC0 :1; /* I-Bus Clock Rate 0 */ + byte IBC1 :1; /* I-Bus Clock Rate 1 */ + byte IBC2 :1; /* I-Bus Clock Rate 2 */ + byte IBC3 :1; /* I-Bus Clock Rate 3 */ + byte IBC4 :1; /* I-Bus Clock Rate 4 */ + byte IBC5 :1; /* I-Bus Clock Rate 5 */ + byte IBC6 :1; /* I-Bus Clock Rate 6 */ + byte IBC7 :1; /* I-Bus Clock Rate 7 */ + } Bits; + struct { + byte grpIBC :8; + } MergedBits; +} IBFDSTR; +extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1); +#define IBFD _IBFD.Byte +#define IBFD_IBC0 _IBFD.Bits.IBC0 +#define IBFD_IBC1 _IBFD.Bits.IBC1 +#define IBFD_IBC2 _IBFD.Bits.IBC2 +#define IBFD_IBC3 _IBFD.Bits.IBC3 +#define IBFD_IBC4 _IBFD.Bits.IBC4 +#define IBFD_IBC5 _IBFD.Bits.IBC5 +#define IBFD_IBC6 _IBFD.Bits.IBC6 +#define IBFD_IBC7 _IBFD.Bits.IBC7 +#define IBFD_IBC _IBFD.MergedBits.grpIBC + + +/*** IBCR - IIC Control Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ + byte :1; + byte RSTA :1; /* Repeat Start */ + byte TXAK :1; /* Transmit Acknowledge enable */ + byte TX_RX :1; /* Transmit/Receive mode select bit */ + byte MS_SL :1; /* Master/Slave mode select bit */ + byte IBIE :1; /* I-Bus Interrupt Enable */ + byte IBEN :1; /* I-Bus Enable */ + } Bits; +} IBCRSTR; +extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2); +#define IBCR _IBCR.Byte +#define IBCR_IBSWAI _IBCR.Bits.IBSWAI +#define IBCR_RSTA _IBCR.Bits.RSTA +#define IBCR_TXAK _IBCR.Bits.TXAK +#define IBCR_TX_RX _IBCR.Bits.TX_RX +#define IBCR_MS_SL _IBCR.Bits.MS_SL +#define IBCR_IBIE _IBCR.Bits.IBIE +#define IBCR_IBEN _IBCR.Bits.IBEN + + +/*** IBSR - IIC Status Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte RXAK :1; /* Received Acknowledge */ + byte IBIF :1; /* I-Bus Interrupt */ + byte SRW :1; /* Slave Read/Write */ + byte :1; + byte IBAL :1; /* Arbitration Lost */ + byte IBB :1; /* Bus busy bit */ + byte IAAS :1; /* Addressed as a slave bit */ + byte TCF :1; /* Data transferring bit */ + } Bits; +} IBSRSTR; +extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3); +#define IBSR _IBSR.Byte +#define IBSR_RXAK _IBSR.Bits.RXAK +#define IBSR_IBIF _IBSR.Bits.IBIF +#define IBSR_SRW _IBSR.Bits.SRW +#define IBSR_IBAL _IBSR.Bits.IBAL +#define IBSR_IBB _IBSR.Bits.IBB +#define IBSR_IAAS _IBSR.Bits.IAAS +#define IBSR_TCF _IBSR.Bits.TCF + + +/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* IIC Data Bit 0 */ + byte D1 :1; /* IIC Data Bit 1 */ + byte D2 :1; /* IIC Data Bit 2 */ + byte D3 :1; /* IIC Data Bit 3 */ + byte D4 :1; /* IIC Data Bit 4 */ + byte D5 :1; /* IIC Data Bit 5 */ + byte D6 :1; /* IIC Data Bit 6 */ + byte D7 :1; /* IIC Data Bit 7 */ + } Bits; + struct { + byte grpD :8; + } MergedBits; +} IBDRSTR; +extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4); +#define IBDR _IBDR.Byte +#define IBDR_D0 _IBDR.Bits.D0 +#define IBDR_D1 _IBDR.Bits.D1 +#define IBDR_D2 _IBDR.Bits.D2 +#define IBDR_D3 _IBDR.Bits.D3 +#define IBDR_D4 _IBDR.Bits.D4 +#define IBDR_D5 _IBDR.Bits.D5 +#define IBDR_D6 _IBDR.Bits.D6 +#define IBDR_D7 _IBDR.Bits.D7 +#define IBDR_D _IBDR.MergedBits.grpD + + +/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/ +typedef union { + byte Byte; + struct { + byte WCM :1; /* Wait Clock Mode */ + byte IE :1; /* Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte CLKS :1; /* Clock Select */ + byte IMSG :1; /* Ignore Message */ + } Bits; +} DLCBCR1STR; +extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8); +#define DLCBCR1 _DLCBCR1.Byte +#define DLCBCR1_WCM _DLCBCR1.Bits.WCM +#define DLCBCR1_IE _DLCBCR1.Bits.IE +#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS +#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG + + +/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte I0 :1; /* Interrupt State Vector Bit 0 */ + byte I1 :1; /* Interrupt State Vector Bit 1 */ + byte I2 :1; /* Interrupt State Vector Bit 2 */ + byte I3 :1; /* Interrupt State Vector Bit 3 */ + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpI :4; + byte :1; + byte :1; + } MergedBits; +} DLCBSVRSTR; +extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9); +#define DLCBSVR _DLCBSVR.Byte +#define DLCBSVR_I0 _DLCBSVR.Bits.I0 +#define DLCBSVR_I1 _DLCBSVR.Bits.I1 +#define DLCBSVR_I2 _DLCBSVR.Bits.I2 +#define DLCBSVR_I3 _DLCBSVR.Bits.I3 +#define DLCBSVR_I _DLCBSVR.MergedBits.grpI + + +/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/ +typedef union { + byte Byte; + struct { + byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */ + byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */ + byte TSIFR :1; /* Transmit In-Frame Response Control 2 */ + byte TEOD :1; /* Transmit End of Data */ + byte NBFS :1; /* Normalization Bit Format Select */ + byte RX4XE :1; /* Receive 4X Enable */ + byte DLOOP :1; /* Digital Loopback Mode */ + byte SMRST :1; /* State Machine Reset */ + } Bits; + struct { + byte grpTMIFR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLCBCR2STR; +extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA); +#define DLCBCR2 _DLCBCR2.Byte +#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0 +#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1 +#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR +#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD +#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS +#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE +#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP +#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST +#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR + + +/*** DLCBDR - BDLC Data Register; 0x000000EB ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* Receive/Transmit Data Bit 0 */ + byte D1 :1; /* Receive/Transmit Data Bit 1 */ + byte D2 :1; /* Receive/Transmit Data Bit 2 */ + byte D3 :1; /* Receive/Transmit Data Bit 3 */ + byte D4 :1; /* Receive/Transmit Data Bit 4 */ + byte D5 :1; /* Receive/Transmit Data Bit 5 */ + byte D6 :1; /* Receive/Transmit Data Bit 6 */ + byte D7 :1; /* Receive/Transmit Data Bit 7 */ + } Bits; + struct { + byte grpD :8; + } MergedBits; +} DLCBDRSTR; +extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB); +#define DLCBDR _DLCBDR.Byte +#define DLCBDR_D0 _DLCBDR.Bits.D0 +#define DLCBDR_D1 _DLCBDR.Bits.D1 +#define DLCBDR_D2 _DLCBDR.Bits.D2 +#define DLCBDR_D3 _DLCBDR.Bits.D3 +#define DLCBDR_D4 _DLCBDR.Bits.D4 +#define DLCBDR_D5 _DLCBDR.Bits.D5 +#define DLCBDR_D6 _DLCBDR.Bits.D6 +#define DLCBDR_D7 _DLCBDR.Bits.D7 +#define DLCBDR_D _DLCBDR.MergedBits.grpD + + +/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/ +typedef union { + byte Byte; + struct { + byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */ + byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */ + byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */ + byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */ + byte :1; + byte :1; + byte RXPOL :1; /* Receive Pin Polarity */ + byte :1; + } Bits; + struct { + byte grpBO :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLCBARDSTR; +extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC); +#define DLCBARD _DLCBARD.Byte +#define DLCBARD_BO0 _DLCBARD.Bits.BO0 +#define DLCBARD_BO1 _DLCBARD.Bits.BO1 +#define DLCBARD_BO2 _DLCBARD.Bits.BO2 +#define DLCBARD_BO3 _DLCBARD.Bits.BO3 +#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL +#define DLCBARD_BO _DLCBARD.MergedBits.grpBO + + +/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/ +typedef union { + byte Byte; + struct { + byte R0 :1; /* Rate Select 0 */ + byte R1 :1; /* Rate Select 1 */ + byte R2 :1; /* Rate Select 2 */ + byte R3 :1; /* Rate Select 3 */ + byte R4 :1; /* Rate Select 4 */ + byte R5 :1; /* Rate Select 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpR :6; + byte :1; + byte :1; + } MergedBits; +} DLCBRSRSTR; +extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED); +#define DLCBRSR _DLCBRSR.Byte +#define DLCBRSR_R0 _DLCBRSR.Bits.R0 +#define DLCBRSR_R1 _DLCBRSR.Bits.R1 +#define DLCBRSR_R2 _DLCBRSR.Bits.R2 +#define DLCBRSR_R3 _DLCBRSR.Bits.R3 +#define DLCBRSR_R4 _DLCBRSR.Bits.R4 +#define DLCBRSR_R5 _DLCBRSR.Bits.R5 +#define DLCBRSR_R _DLCBRSR.MergedBits.grpR + + +/*** DLCSCR - BDLC Control Register; 0x000000EE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BDLCE :1; /* BDLC Enable */ + byte :1; + byte :1; + byte :1; + } Bits; +} DLCSCRSTR; +extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE); +#define DLCSCR _DLCSCR.Byte +#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE + + +/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 1 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 1 Clock Phase Bit */ + byte CPOL :1; /* SPI 1 Clock Polarity Bit */ + byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 1 System Enable Bit */ + byte SPIE :1; /* SPI 1 Interrupt Enable Bit */ + } Bits; +} SPI1CR1STR; +extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0); +#define SPI1CR1 _SPI1CR1.Byte +#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE +#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE +#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA +#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL +#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR +#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE +#define SPI1CR1_SPE _SPI1CR1.Bits.SPE +#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE + + +/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI1CR2STR; +extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1); +#define SPI1CR2 _SPI1CR2.Byte +#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0 +#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI +#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE +#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN + + +/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI1BRSTR; +extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2); +#define SPI1BR _SPI1BR.Byte +#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 +#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 +#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 +#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 +#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 +#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 +#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR +#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR + + +/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI1SRSTR; +extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3); +#define SPI1SR _SPI1SR.Byte +#define SPI1SR_MODF _SPI1SR.Bits.MODF +#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF +#define SPI1SR_SPIF _SPI1SR.Bits.SPIF + + +/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI1DRSTR; +extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5); +#define SPI1DR _SPI1DR.Byte +#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT + + +/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 2 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 2 Clock Phase Bit */ + byte CPOL :1; /* SPI 2 Clock Polarity Bit */ + byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 2 System Enable Bit */ + byte SPIE :1; /* SPI 2 Interrupt Enable Bit */ + } Bits; +} SPI2CR1STR; +extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8); +#define SPI2CR1 _SPI2CR1.Byte +#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE +#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE +#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA +#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL +#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR +#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE +#define SPI2CR1_SPE _SPI2CR1.Bits.SPE +#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE + + +/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI2CR2STR; +extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9); +#define SPI2CR2 _SPI2CR2.Byte +#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0 +#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI +#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE +#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN + + +/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI2BRSTR; +extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA); +#define SPI2BR _SPI2BR.Byte +#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 +#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 +#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 +#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 +#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 +#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 +#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR +#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR + + +/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI2SRSTR; +extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB); +#define SPI2SR _SPI2SR.Byte +#define SPI2SR_MODF _SPI2SR.Bits.MODF +#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF +#define SPI2SR_SPIF _SPI2SR.Bits.SPIF + + +/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI2DRSTR; +extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD); +#define SPI2DR _SPI2DR.Byte +#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte NV6 :1; /* Non Volatile flag bit 6 */ + byte KEYEN :1; /* Enable backdoor key to security */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :5; + byte :1; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_NV6 _FSEC.Bits.NV6 +#define FSEC_KEYEN _FSEC.Bits.KEYEN +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_NV FSEC_NV_2 + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + + +/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/ +typedef union { + byte Byte; + struct { + byte EDIV0 :1; /* EEPROM Clock Divider 0 */ + byte EDIV1 :1; /* EEPROM Clock Divider 1 */ + byte EDIV2 :1; /* EEPROM Clock Divider 2 */ + byte EDIV3 :1; /* EEPROM Clock Divider 3 */ + byte EDIV4 :1; /* EEPROM Clock Divider 4 */ + byte EDIV5 :1; /* EEPROM Clock Divider 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte EDIVLD :1; /* EEPROM Clock Divider Loaded */ + } Bits; + struct { + byte grpEDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} ECLKDIVSTR; +extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110); +#define ECLKDIV _ECLKDIV.Byte +#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0 +#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1 +#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2 +#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3 +#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4 +#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5 +#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8 +#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD +#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV + + +/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; +} ECNFGSTR; +extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113); +#define ECNFG _ECNFG.Byte +#define ECNFG_CCIE _ECNFG.Bits.CCIE +#define ECNFG_CBEIE _ECNFG.Bits.CBEIE + + +/*** EPROT - EEPROM Protection Register; 0x00000114 ***/ +typedef union { + byte Byte; + struct { + byte EP0 :1; /* EEPROM Protection address size 0 */ + byte EP1 :1; /* EEPROM Protection address size 1 */ + byte EP2 :1; /* EEPROM Protection address size 2 */ + byte EPDIS :1; /* EEPROM Protection disable */ + byte :1; + byte :1; + byte :1; + byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */ + } Bits; + struct { + byte grpEP :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} EPROTSTR; +extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114); +#define EPROT _EPROT.Byte +#define EPROT_EP0 _EPROT.Bits.EP0 +#define EPROT_EP1 _EPROT.Bits.EP1 +#define EPROT_EP2 _EPROT.Bits.EP2 +#define EPROT_EPDIS _EPROT.Bits.EPDIS +#define EPROT_EPOPEN _EPROT.Bits.EPOPEN +#define EPROT_EP _EPROT.MergedBits.grpEP + + +/*** ESTAT - EEPROM Status Register; 0x00000115 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */ + } Bits; +} ESTATSTR; +extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115); +#define ESTAT _ESTAT.Byte +#define ESTAT_BLANK _ESTAT.Bits.BLANK +#define ESTAT_ACCERR _ESTAT.Bits.ACCERR +#define ESTAT_PVIOL _ESTAT.Bits.PVIOL +#define ESTAT_CCIF _ESTAT.Bits.CCIF +#define ESTAT_CBEIF _ESTAT.Bits.CBEIF + + +/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* EEPROM User Mode Command 0 */ + byte :1; + byte CMDB2 :1; /* EEPROM User Mode Command 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* EEPROM User Mode Command 5 */ + byte CMDB6 :1; /* EEPROM User Mode Command 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} ECMDSTR; +extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116); +#define ECMD _ECMD.Byte +#define ECMD_CMDB0 _ECMD.Bits.CMDB0 +#define ECMD_CMDB2 _ECMD.Bits.CMDB2 +#define ECMD_CMDB5 _ECMD.Bits.CMDB5 +#define ECMD_CMDB6 _ECMD.Bits.CMDB6 +#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5 +#define ECMD_CMDB ECMD_CMDB_5 + + +/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD1STAT0STR; +extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126); +#define ATD1STAT0 _ATD1STAT0.Byte +#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0 +#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1 +#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2 +#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR +#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF +#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF +#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC + + +/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATD1STAT1STR; +extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B); +#define ATD1STAT1 _ATD1STAT1.Byte +#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0 +#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1 +#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2 +#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3 +#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4 +#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5 +#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6 +#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7 +#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF + + +/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ + byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ + byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ + byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ + byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ + byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ + byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ + byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATD1DIENSTR; +extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D); +#define ATD1DIEN _ATD1DIEN.Byte +#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0 +#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1 +#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2 +#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3 +#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4 +#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5 +#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6 +#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7 +#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT + + +/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD1STR; +extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F); +#define PORTAD1 _PORTAD1.Byte +#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0 +#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1 +#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2 +#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3 +#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4 +#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5 +#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6 +#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7 +#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT + + +/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN0CTL0STR; +extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140); +#define CAN0CTL0 _CAN0CTL0.Byte +#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ +#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ +#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE +#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME +#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH +#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI +#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT +#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM + + +/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 0 Clock Source */ + byte CANE :1; /* MSCAN 0 Enable */ + } Bits; +} CAN0CTL1STR; +extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141); +#define CAN0CTL1 _CAN0CTL1.Byte +#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK +#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK +#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM +#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN +#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB +#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC +#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE + + +/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN0BTR0STR; +extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142); +#define CAN0BTR0 _CAN0BTR0.Byte +#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0 +#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1 +#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2 +#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3 +#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4 +#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5 +#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0 +#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1 +#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP +#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW + + +/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN0BTR1STR; +extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143); +#define CAN0BTR1 _CAN0BTR1.Byte +#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10 +#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11 +#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12 +#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13 +#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20 +#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21 +#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22 +#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP +#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10 +#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20 +#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10 + + +/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RFLGSTR; +extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144); +#define CAN0RFLG _CAN0RFLG.Byte +#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF +#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF +#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0 +#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1 +#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0 +#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1 +#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF +#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF +#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT +#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT + + +/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RIERSTR; +extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145); +#define CAN0RIER _CAN0RIER.Byte +#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE +#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE +#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0 +#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1 +#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0 +#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1 +#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE +#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE +#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE +#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE + + +/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TFLGSTR; +extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146); +#define CAN0TFLG _CAN0TFLG.Byte +#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0 +#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1 +#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2 +#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE + + +/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TIERSTR; +extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147); +#define CAN0TIER _CAN0TIER.Byte +#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0 +#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1 +#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2 +#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE + + +/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TARQSTR; +extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148); +#define CAN0TARQ _CAN0TARQ.Byte +#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0 +#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1 +#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2 +#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ + + +/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TAAKSTR; +extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149); +#define CAN0TAAK _CAN0TAAK.Byte +#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0 +#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1 +#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2 +#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK + + +/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TBSELSTR; +extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A); +#define CAN0TBSEL _CAN0TBSEL.Byte +#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0 +#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1 +#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2 +#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX + + +/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN0IDACSTR; +extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B); +#define CAN0IDAC _CAN0IDAC.Byte +#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0 +#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1 +#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2 +#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0 +#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1 +#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT +#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM + + +/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN0RXERRSTR; +extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E); +#define CAN0RXERR _CAN0RXERR.Byte +#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0 +#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1 +#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2 +#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3 +#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4 +#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5 +#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6 +#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7 +#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR + + +/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN0TXERRSTR; +extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F); +#define CAN0TXERR _CAN0TXERR.Byte +#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0 +#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1 +#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2 +#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3 +#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4 +#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5 +#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6 +#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7 +#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR + + +/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR0STR; +extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150); +#define CAN0IDAR0 _CAN0IDAR0.Byte +#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0 +#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1 +#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2 +#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3 +#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4 +#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5 +#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6 +#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7 +#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC + + +/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR1STR; +extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151); +#define CAN0IDAR1 _CAN0IDAR1.Byte +#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0 +#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1 +#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2 +#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3 +#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4 +#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5 +#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6 +#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7 +#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC + + +/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR2STR; +extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152); +#define CAN0IDAR2 _CAN0IDAR2.Byte +#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0 +#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1 +#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2 +#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3 +#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4 +#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5 +#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6 +#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7 +#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC + + +/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR3STR; +extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153); +#define CAN0IDAR3 _CAN0IDAR3.Byte +#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0 +#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1 +#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2 +#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3 +#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4 +#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5 +#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6 +#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7 +#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC + + +/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR0STR; +extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154); +#define CAN0IDMR0 _CAN0IDMR0.Byte +#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0 +#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1 +#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2 +#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3 +#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4 +#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5 +#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6 +#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7 +#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM + + +/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR1STR; +extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155); +#define CAN0IDMR1 _CAN0IDMR1.Byte +#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0 +#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1 +#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2 +#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3 +#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4 +#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5 +#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6 +#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7 +#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM + + +/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR2STR; +extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156); +#define CAN0IDMR2 _CAN0IDMR2.Byte +#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0 +#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1 +#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2 +#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3 +#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4 +#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5 +#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6 +#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7 +#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM + + +/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR3STR; +extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157); +#define CAN0IDMR3 _CAN0IDMR3.Byte +#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0 +#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1 +#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2 +#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3 +#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4 +#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5 +#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6 +#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7 +#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM + + +/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR4STR; +extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158); +#define CAN0IDAR4 _CAN0IDAR4.Byte +#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0 +#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1 +#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2 +#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3 +#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4 +#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5 +#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6 +#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7 +#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC + + +/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR5STR; +extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159); +#define CAN0IDAR5 _CAN0IDAR5.Byte +#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0 +#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1 +#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2 +#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3 +#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4 +#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5 +#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6 +#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7 +#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC + + +/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR6STR; +extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A); +#define CAN0IDAR6 _CAN0IDAR6.Byte +#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0 +#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1 +#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2 +#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3 +#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4 +#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5 +#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6 +#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7 +#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC + + +/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR7STR; +extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B); +#define CAN0IDAR7 _CAN0IDAR7.Byte +#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0 +#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1 +#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2 +#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3 +#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4 +#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5 +#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6 +#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7 +#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC + + +/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR4STR; +extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C); +#define CAN0IDMR4 _CAN0IDMR4.Byte +#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0 +#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1 +#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2 +#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3 +#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4 +#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5 +#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6 +#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7 +#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM + + +/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR5STR; +extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D); +#define CAN0IDMR5 _CAN0IDMR5.Byte +#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0 +#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1 +#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2 +#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3 +#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4 +#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5 +#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6 +#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7 +#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM + + +/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR6STR; +extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E); +#define CAN0IDMR6 _CAN0IDMR6.Byte +#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0 +#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1 +#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2 +#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3 +#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4 +#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5 +#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6 +#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7 +#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM + + +/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR7STR; +extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F); +#define CAN0IDMR7 _CAN0IDMR7.Byte +#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0 +#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1 +#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2 +#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3 +#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4 +#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5 +#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6 +#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7 +#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM + + +/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN0RXIDR0STR; +extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160); +#define CAN0RXIDR0 _CAN0RXIDR0.Byte +#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21 +#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22 +#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23 +#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24 +#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25 +#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26 +#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27 +#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28 +#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21 +#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21 + + +/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0RXIDR1STR; +extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161); +#define CAN0RXIDR1 _CAN0RXIDR1.Byte +#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15 +#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16 +#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17 +#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE +#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR +#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18 +#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19 +#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20 +#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15 +#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18 +#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15 + + +/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN0RXIDR2STR; +extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162); +#define CAN0RXIDR2 _CAN0RXIDR2.Byte +#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7 +#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8 +#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9 +#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10 +#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11 +#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12 +#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13 +#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14 +#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7 +#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7 + + +/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0RXIDR3STR; +extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163); +#define CAN0RXIDR3 _CAN0RXIDR3.Byte +#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR +#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0 +#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1 +#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2 +#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3 +#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4 +#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5 +#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6 +#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID + + +/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR0STR; +extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164); +#define CAN0RXDSR0 _CAN0RXDSR0.Byte +#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0 +#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1 +#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2 +#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3 +#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4 +#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5 +#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6 +#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7 +#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB + + +/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR1STR; +extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165); +#define CAN0RXDSR1 _CAN0RXDSR1.Byte +#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0 +#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1 +#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2 +#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3 +#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4 +#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5 +#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6 +#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7 +#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB + + +/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR2STR; +extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166); +#define CAN0RXDSR2 _CAN0RXDSR2.Byte +#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0 +#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1 +#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2 +#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3 +#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4 +#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5 +#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6 +#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7 +#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB + + +/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR3STR; +extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167); +#define CAN0RXDSR3 _CAN0RXDSR3.Byte +#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0 +#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1 +#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2 +#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3 +#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4 +#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5 +#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6 +#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7 +#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB + + +/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR4STR; +extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168); +#define CAN0RXDSR4 _CAN0RXDSR4.Byte +#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0 +#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1 +#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2 +#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3 +#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4 +#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5 +#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6 +#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7 +#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB + + +/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR5STR; +extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169); +#define CAN0RXDSR5 _CAN0RXDSR5.Byte +#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0 +#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1 +#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2 +#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3 +#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4 +#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5 +#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6 +#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7 +#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB + + +/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR6STR; +extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A); +#define CAN0RXDSR6 _CAN0RXDSR6.Byte +#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0 +#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1 +#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2 +#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3 +#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4 +#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5 +#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6 +#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7 +#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB + + +/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR7STR; +extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B); +#define CAN0RXDSR7 _CAN0RXDSR7.Byte +#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0 +#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1 +#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2 +#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3 +#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4 +#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5 +#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6 +#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7 +#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB + + +/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0RXDLRSTR; +extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C); +#define CAN0RXDLR _CAN0RXDLR.Byte +#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0 +#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1 +#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2 +#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3 +#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC + + +/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN0TXIDR0STR; +extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170); +#define CAN0TXIDR0 _CAN0TXIDR0.Byte +#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21 +#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22 +#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23 +#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24 +#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25 +#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26 +#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27 +#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28 +#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21 +#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21 + + +/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0TXIDR1STR; +extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171); +#define CAN0TXIDR1 _CAN0TXIDR1.Byte +#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15 +#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16 +#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17 +#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE +#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR +#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18 +#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19 +#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20 +#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15 +#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18 +#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15 + + +/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN0TXIDR2STR; +extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172); +#define CAN0TXIDR2 _CAN0TXIDR2.Byte +#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7 +#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8 +#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9 +#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10 +#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11 +#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12 +#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13 +#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14 +#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7 +#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7 + + +/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0TXIDR3STR; +extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173); +#define CAN0TXIDR3 _CAN0TXIDR3.Byte +#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR +#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0 +#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1 +#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2 +#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3 +#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4 +#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5 +#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6 +#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID + + +/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR0STR; +extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174); +#define CAN0TXDSR0 _CAN0TXDSR0.Byte +#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0 +#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1 +#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2 +#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3 +#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4 +#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5 +#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6 +#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7 +#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB + + +/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR1STR; +extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175); +#define CAN0TXDSR1 _CAN0TXDSR1.Byte +#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0 +#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1 +#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2 +#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3 +#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4 +#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5 +#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6 +#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7 +#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB + + +/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR2STR; +extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176); +#define CAN0TXDSR2 _CAN0TXDSR2.Byte +#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0 +#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1 +#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2 +#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3 +#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4 +#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5 +#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6 +#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7 +#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB + + +/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR3STR; +extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177); +#define CAN0TXDSR3 _CAN0TXDSR3.Byte +#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0 +#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1 +#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2 +#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3 +#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4 +#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5 +#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6 +#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7 +#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB + + +/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR4STR; +extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178); +#define CAN0TXDSR4 _CAN0TXDSR4.Byte +#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0 +#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1 +#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2 +#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3 +#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4 +#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5 +#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6 +#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7 +#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB + + +/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR5STR; +extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179); +#define CAN0TXDSR5 _CAN0TXDSR5.Byte +#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0 +#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1 +#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2 +#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3 +#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4 +#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5 +#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6 +#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7 +#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB + + +/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR6STR; +extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A); +#define CAN0TXDSR6 _CAN0TXDSR6.Byte +#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0 +#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1 +#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2 +#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3 +#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4 +#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5 +#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6 +#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7 +#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB + + +/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR7STR; +extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B); +#define CAN0TXDSR7 _CAN0TXDSR7.Byte +#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0 +#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1 +#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2 +#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3 +#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4 +#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5 +#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6 +#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7 +#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB + + +/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TXDLRSTR; +extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C); +#define CAN0TXDLR _CAN0TXDLR.Byte +#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0 +#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1 +#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2 +#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3 +#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC + + +/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN0TXTBPRSTR; +extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F); +#define CAN0TXTBPR _CAN0TXTBPR.Byte +#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0 +#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1 +#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2 +#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3 +#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4 +#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5 +#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6 +#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7 +#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO + + +/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN1CTL0STR; +extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180); +#define CAN1CTL0 _CAN1CTL0.Byte +#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ +#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ +#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE +#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME +#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH +#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI +#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT +#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM + + +/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 1 Clock Source */ + byte CANE :1; /* MSCAN 1 Enable */ + } Bits; +} CAN1CTL1STR; +extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181); +#define CAN1CTL1 _CAN1CTL1.Byte +#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK +#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK +#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM +#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN +#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB +#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC +#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE + + +/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN1BTR0STR; +extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182); +#define CAN1BTR0 _CAN1BTR0.Byte +#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0 +#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1 +#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2 +#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3 +#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4 +#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5 +#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0 +#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1 +#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP +#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW + + +/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN1BTR1STR; +extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183); +#define CAN1BTR1 _CAN1BTR1.Byte +#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10 +#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11 +#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12 +#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13 +#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20 +#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21 +#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22 +#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP +#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10 +#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20 +#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10 + + +/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN1RFLGSTR; +extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184); +#define CAN1RFLG _CAN1RFLG.Byte +#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF +#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF +#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0 +#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1 +#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0 +#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1 +#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF +#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF +#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT +#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT + + +/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN1RIERSTR; +extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185); +#define CAN1RIER _CAN1RIER.Byte +#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE +#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE +#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0 +#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1 +#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0 +#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1 +#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE +#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE +#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE +#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE + + +/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TFLGSTR; +extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186); +#define CAN1TFLG _CAN1TFLG.Byte +#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0 +#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1 +#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2 +#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE + + +/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TIERSTR; +extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187); +#define CAN1TIER _CAN1TIER.Byte +#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0 +#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1 +#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2 +#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE + + +/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TARQSTR; +extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188); +#define CAN1TARQ _CAN1TARQ.Byte +#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0 +#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1 +#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2 +#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ + + +/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TAAKSTR; +extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189); +#define CAN1TAAK _CAN1TAAK.Byte +#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0 +#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1 +#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2 +#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK + + +/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TBSELSTR; +extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A); +#define CAN1TBSEL _CAN1TBSEL.Byte +#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0 +#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1 +#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2 +#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX + + +/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN1IDACSTR; +extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B); +#define CAN1IDAC _CAN1IDAC.Byte +#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0 +#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1 +#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2 +#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0 +#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1 +#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT +#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM + + +/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN1RXERRSTR; +extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E); +#define CAN1RXERR _CAN1RXERR.Byte +#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0 +#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1 +#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2 +#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3 +#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4 +#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5 +#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6 +#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7 +#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR + + +/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN1TXERRSTR; +extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F); +#define CAN1TXERR _CAN1TXERR.Byte +#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0 +#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1 +#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2 +#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3 +#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4 +#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5 +#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6 +#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7 +#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR + + +/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR0STR; +extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190); +#define CAN1IDAR0 _CAN1IDAR0.Byte +#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0 +#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1 +#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2 +#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3 +#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4 +#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5 +#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6 +#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7 +#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC + + +/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR1STR; +extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191); +#define CAN1IDAR1 _CAN1IDAR1.Byte +#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0 +#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1 +#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2 +#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3 +#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4 +#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5 +#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6 +#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7 +#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC + + +/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR2STR; +extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192); +#define CAN1IDAR2 _CAN1IDAR2.Byte +#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0 +#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1 +#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2 +#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3 +#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4 +#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5 +#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6 +#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7 +#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC + + +/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR3STR; +extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193); +#define CAN1IDAR3 _CAN1IDAR3.Byte +#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0 +#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1 +#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2 +#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3 +#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4 +#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5 +#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6 +#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7 +#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC + + +/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR0STR; +extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194); +#define CAN1IDMR0 _CAN1IDMR0.Byte +#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0 +#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1 +#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2 +#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3 +#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4 +#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5 +#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6 +#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7 +#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM + + +/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR1STR; +extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195); +#define CAN1IDMR1 _CAN1IDMR1.Byte +#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0 +#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1 +#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2 +#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3 +#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4 +#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5 +#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6 +#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7 +#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM + + +/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR2STR; +extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196); +#define CAN1IDMR2 _CAN1IDMR2.Byte +#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0 +#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1 +#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2 +#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3 +#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4 +#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5 +#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6 +#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7 +#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM + + +/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR3STR; +extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197); +#define CAN1IDMR3 _CAN1IDMR3.Byte +#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0 +#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1 +#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2 +#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3 +#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4 +#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5 +#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6 +#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7 +#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM + + +/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR4STR; +extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198); +#define CAN1IDAR4 _CAN1IDAR4.Byte +#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0 +#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1 +#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2 +#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3 +#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4 +#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5 +#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6 +#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7 +#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC + + +/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR5STR; +extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199); +#define CAN1IDAR5 _CAN1IDAR5.Byte +#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0 +#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1 +#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2 +#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3 +#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4 +#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5 +#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6 +#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7 +#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC + + +/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR6STR; +extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A); +#define CAN1IDAR6 _CAN1IDAR6.Byte +#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0 +#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1 +#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2 +#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3 +#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4 +#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5 +#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6 +#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7 +#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC + + +/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR7STR; +extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B); +#define CAN1IDAR7 _CAN1IDAR7.Byte +#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0 +#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1 +#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2 +#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3 +#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4 +#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5 +#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6 +#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7 +#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC + + +/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR4STR; +extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C); +#define CAN1IDMR4 _CAN1IDMR4.Byte +#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0 +#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1 +#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2 +#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3 +#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4 +#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5 +#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6 +#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7 +#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM + + +/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR5STR; +extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D); +#define CAN1IDMR5 _CAN1IDMR5.Byte +#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0 +#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1 +#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2 +#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3 +#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4 +#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5 +#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6 +#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7 +#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM + + +/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR6STR; +extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E); +#define CAN1IDMR6 _CAN1IDMR6.Byte +#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0 +#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1 +#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2 +#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3 +#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4 +#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5 +#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6 +#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7 +#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM + + +/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR7STR; +extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F); +#define CAN1IDMR7 _CAN1IDMR7.Byte +#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0 +#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1 +#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2 +#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3 +#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4 +#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5 +#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6 +#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7 +#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM + + +/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN1RXIDR0STR; +extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0); +#define CAN1RXIDR0 _CAN1RXIDR0.Byte +#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21 +#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22 +#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23 +#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24 +#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25 +#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26 +#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27 +#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28 +#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21 +#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21 + + +/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN1RXIDR1STR; +extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1); +#define CAN1RXIDR1 _CAN1RXIDR1.Byte +#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15 +#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16 +#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17 +#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE +#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR +#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18 +#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19 +#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20 +#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15 +#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18 +#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15 + + +/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN1RXIDR2STR; +extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2); +#define CAN1RXIDR2 _CAN1RXIDR2.Byte +#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7 +#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8 +#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9 +#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10 +#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11 +#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12 +#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13 +#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14 +#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7 +#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7 + + +/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN1RXIDR3STR; +extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3); +#define CAN1RXIDR3 _CAN1RXIDR3.Byte +#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR +#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0 +#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1 +#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2 +#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3 +#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4 +#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5 +#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6 +#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID + + +/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR0STR; +extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4); +#define CAN1RXDSR0 _CAN1RXDSR0.Byte +#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0 +#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1 +#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2 +#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3 +#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4 +#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5 +#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6 +#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7 +#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB + + +/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR1STR; +extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5); +#define CAN1RXDSR1 _CAN1RXDSR1.Byte +#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0 +#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1 +#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2 +#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3 +#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4 +#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5 +#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6 +#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7 +#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB + + +/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR2STR; +extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6); +#define CAN1RXDSR2 _CAN1RXDSR2.Byte +#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0 +#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1 +#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2 +#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3 +#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4 +#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5 +#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6 +#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7 +#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB + + +/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR3STR; +extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7); +#define CAN1RXDSR3 _CAN1RXDSR3.Byte +#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0 +#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1 +#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2 +#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3 +#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4 +#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5 +#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6 +#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7 +#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB + + +/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR4STR; +extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8); +#define CAN1RXDSR4 _CAN1RXDSR4.Byte +#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0 +#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1 +#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2 +#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3 +#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4 +#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5 +#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6 +#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7 +#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB + + +/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR5STR; +extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9); +#define CAN1RXDSR5 _CAN1RXDSR5.Byte +#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0 +#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1 +#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2 +#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3 +#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4 +#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5 +#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6 +#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7 +#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB + + +/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR6STR; +extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA); +#define CAN1RXDSR6 _CAN1RXDSR6.Byte +#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0 +#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1 +#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2 +#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3 +#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4 +#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5 +#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6 +#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7 +#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB + + +/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR7STR; +extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB); +#define CAN1RXDSR7 _CAN1RXDSR7.Byte +#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0 +#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1 +#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2 +#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3 +#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4 +#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5 +#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6 +#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7 +#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB + + +/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1RXDLRSTR; +extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC); +#define CAN1RXDLR _CAN1RXDLR.Byte +#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0 +#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1 +#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2 +#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3 +#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC + + +/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN1TXIDR0STR; +extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0); +#define CAN1TXIDR0 _CAN1TXIDR0.Byte +#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21 +#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22 +#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23 +#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24 +#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25 +#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26 +#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27 +#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28 +#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21 +#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21 + + +/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN1TXIDR1STR; +extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1); +#define CAN1TXIDR1 _CAN1TXIDR1.Byte +#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15 +#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16 +#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17 +#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE +#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR +#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18 +#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19 +#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20 +#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15 +#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18 +#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15 + + +/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN1TXIDR2STR; +extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2); +#define CAN1TXIDR2 _CAN1TXIDR2.Byte +#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7 +#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8 +#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9 +#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10 +#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11 +#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12 +#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13 +#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14 +#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7 +#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7 + + +/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN1TXIDR3STR; +extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3); +#define CAN1TXIDR3 _CAN1TXIDR3.Byte +#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR +#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0 +#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1 +#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2 +#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3 +#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4 +#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5 +#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6 +#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID + + +/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR0STR; +extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4); +#define CAN1TXDSR0 _CAN1TXDSR0.Byte +#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0 +#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1 +#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2 +#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3 +#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4 +#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5 +#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6 +#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7 +#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB + + +/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR1STR; +extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5); +#define CAN1TXDSR1 _CAN1TXDSR1.Byte +#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0 +#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1 +#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2 +#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3 +#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4 +#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5 +#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6 +#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7 +#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB + + +/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR2STR; +extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6); +#define CAN1TXDSR2 _CAN1TXDSR2.Byte +#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0 +#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1 +#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2 +#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3 +#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4 +#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5 +#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6 +#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7 +#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB + + +/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR3STR; +extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7); +#define CAN1TXDSR3 _CAN1TXDSR3.Byte +#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0 +#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1 +#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2 +#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3 +#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4 +#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5 +#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6 +#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7 +#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB + + +/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR4STR; +extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8); +#define CAN1TXDSR4 _CAN1TXDSR4.Byte +#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0 +#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1 +#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2 +#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3 +#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4 +#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5 +#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6 +#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7 +#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB + + +/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR5STR; +extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9); +#define CAN1TXDSR5 _CAN1TXDSR5.Byte +#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0 +#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1 +#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2 +#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3 +#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4 +#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5 +#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6 +#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7 +#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB + + +/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR6STR; +extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA); +#define CAN1TXDSR6 _CAN1TXDSR6.Byte +#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0 +#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1 +#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2 +#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3 +#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4 +#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5 +#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6 +#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7 +#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB + + +/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR7STR; +extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB); +#define CAN1TXDSR7 _CAN1TXDSR7.Byte +#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0 +#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1 +#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2 +#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3 +#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4 +#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5 +#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6 +#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7 +#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB + + +/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TXDLRSTR; +extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC); +#define CAN1TXDLR _CAN1TXDLR.Byte +#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0 +#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1 +#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2 +#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3 +#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC + + +/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN1TXTBPRSTR; +extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF); +#define CAN1TXTBPR _CAN1TXTBPR.Byte +#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0 +#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1 +#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2 +#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3 +#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4 +#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5 +#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6 +#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7 +#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO + + +/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN2CTL0STR; +extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0); +#define CAN2CTL0 _CAN2CTL0.Byte +#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ +#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ +#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE +#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME +#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH +#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI +#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT +#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM + + +/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 2 Clock Source */ + byte CANE :1; /* MSCAN 2 Enable */ + } Bits; +} CAN2CTL1STR; +extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1); +#define CAN2CTL1 _CAN2CTL1.Byte +#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK +#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK +#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM +#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN +#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB +#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC +#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE + + +/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN2BTR0STR; +extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2); +#define CAN2BTR0 _CAN2BTR0.Byte +#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0 +#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1 +#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2 +#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3 +#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4 +#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5 +#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0 +#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1 +#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP +#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW + + +/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN2BTR1STR; +extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3); +#define CAN2BTR1 _CAN2BTR1.Byte +#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10 +#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11 +#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12 +#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13 +#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20 +#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21 +#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22 +#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP +#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10 +#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20 +#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10 + + +/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN2RFLGSTR; +extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4); +#define CAN2RFLG _CAN2RFLG.Byte +#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF +#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF +#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0 +#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1 +#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0 +#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1 +#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF +#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF +#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT +#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT + + +/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN2RIERSTR; +extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5); +#define CAN2RIER _CAN2RIER.Byte +#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE +#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE +#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0 +#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1 +#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0 +#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1 +#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE +#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE +#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE +#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE + + +/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TFLGSTR; +extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6); +#define CAN2TFLG _CAN2TFLG.Byte +#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0 +#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1 +#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2 +#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE + + +/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TIERSTR; +extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7); +#define CAN2TIER _CAN2TIER.Byte +#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0 +#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1 +#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2 +#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE + + +/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TARQSTR; +extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8); +#define CAN2TARQ _CAN2TARQ.Byte +#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0 +#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1 +#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2 +#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ + + +/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TAAKSTR; +extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9); +#define CAN2TAAK _CAN2TAAK.Byte +#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0 +#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1 +#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2 +#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK + + +/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TBSELSTR; +extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA); +#define CAN2TBSEL _CAN2TBSEL.Byte +#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0 +#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1 +#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2 +#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX + + +/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN2IDACSTR; +extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB); +#define CAN2IDAC _CAN2IDAC.Byte +#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0 +#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1 +#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2 +#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0 +#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1 +#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT +#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM + + +/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN2RXERRSTR; +extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE); +#define CAN2RXERR _CAN2RXERR.Byte +#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0 +#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1 +#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2 +#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3 +#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4 +#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5 +#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6 +#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7 +#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR + + +/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN2TXERRSTR; +extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF); +#define CAN2TXERR _CAN2TXERR.Byte +#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0 +#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1 +#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2 +#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3 +#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4 +#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5 +#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6 +#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7 +#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR + + +/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR0STR; +extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0); +#define CAN2IDAR0 _CAN2IDAR0.Byte +#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0 +#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1 +#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2 +#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3 +#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4 +#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5 +#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6 +#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7 +#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC + + +/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR1STR; +extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1); +#define CAN2IDAR1 _CAN2IDAR1.Byte +#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0 +#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1 +#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2 +#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3 +#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4 +#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5 +#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6 +#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7 +#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC + + +/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR2STR; +extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2); +#define CAN2IDAR2 _CAN2IDAR2.Byte +#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0 +#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1 +#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2 +#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3 +#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4 +#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5 +#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6 +#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7 +#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC + + +/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR3STR; +extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3); +#define CAN2IDAR3 _CAN2IDAR3.Byte +#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0 +#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1 +#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2 +#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3 +#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4 +#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5 +#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6 +#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7 +#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC + + +/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR0STR; +extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4); +#define CAN2IDMR0 _CAN2IDMR0.Byte +#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0 +#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1 +#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2 +#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3 +#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4 +#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5 +#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6 +#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7 +#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM + + +/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR1STR; +extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5); +#define CAN2IDMR1 _CAN2IDMR1.Byte +#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0 +#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1 +#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2 +#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3 +#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4 +#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5 +#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6 +#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7 +#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM + + +/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR2STR; +extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6); +#define CAN2IDMR2 _CAN2IDMR2.Byte +#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0 +#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1 +#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2 +#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3 +#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4 +#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5 +#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6 +#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7 +#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM + + +/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR3STR; +extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7); +#define CAN2IDMR3 _CAN2IDMR3.Byte +#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0 +#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1 +#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2 +#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3 +#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4 +#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5 +#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6 +#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7 +#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM + + +/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR4STR; +extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8); +#define CAN2IDAR4 _CAN2IDAR4.Byte +#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0 +#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1 +#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2 +#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3 +#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4 +#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5 +#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6 +#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7 +#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC + + +/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR5STR; +extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9); +#define CAN2IDAR5 _CAN2IDAR5.Byte +#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0 +#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1 +#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2 +#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3 +#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4 +#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5 +#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6 +#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7 +#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC + + +/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR6STR; +extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA); +#define CAN2IDAR6 _CAN2IDAR6.Byte +#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0 +#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1 +#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2 +#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3 +#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4 +#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5 +#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6 +#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7 +#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC + + +/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR7STR; +extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB); +#define CAN2IDAR7 _CAN2IDAR7.Byte +#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0 +#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1 +#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2 +#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3 +#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4 +#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5 +#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6 +#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7 +#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC + + +/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR4STR; +extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC); +#define CAN2IDMR4 _CAN2IDMR4.Byte +#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0 +#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1 +#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2 +#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3 +#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4 +#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5 +#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6 +#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7 +#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM + + +/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR5STR; +extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD); +#define CAN2IDMR5 _CAN2IDMR5.Byte +#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0 +#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1 +#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2 +#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3 +#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4 +#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5 +#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6 +#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7 +#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM + + +/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR6STR; +extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE); +#define CAN2IDMR6 _CAN2IDMR6.Byte +#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0 +#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1 +#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2 +#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3 +#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4 +#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5 +#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6 +#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7 +#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM + + +/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR7STR; +extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF); +#define CAN2IDMR7 _CAN2IDMR7.Byte +#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0 +#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1 +#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2 +#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3 +#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4 +#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5 +#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6 +#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7 +#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM + + +/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN2RXIDR0STR; +extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0); +#define CAN2RXIDR0 _CAN2RXIDR0.Byte +#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21 +#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22 +#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23 +#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24 +#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25 +#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26 +#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27 +#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28 +#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21 +#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21 + + +/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN2RXIDR1STR; +extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1); +#define CAN2RXIDR1 _CAN2RXIDR1.Byte +#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15 +#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16 +#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17 +#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE +#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR +#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18 +#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19 +#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20 +#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15 +#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18 +#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15 + + +/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN2RXIDR2STR; +extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2); +#define CAN2RXIDR2 _CAN2RXIDR2.Byte +#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7 +#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8 +#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9 +#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10 +#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11 +#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12 +#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13 +#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14 +#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7 +#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7 + + +/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN2RXIDR3STR; +extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3); +#define CAN2RXIDR3 _CAN2RXIDR3.Byte +#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR +#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0 +#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1 +#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2 +#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3 +#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4 +#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5 +#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6 +#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID + + +/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR0STR; +extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4); +#define CAN2RXDSR0 _CAN2RXDSR0.Byte +#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0 +#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1 +#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2 +#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3 +#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4 +#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5 +#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6 +#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7 +#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB + + +/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR1STR; +extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5); +#define CAN2RXDSR1 _CAN2RXDSR1.Byte +#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0 +#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1 +#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2 +#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3 +#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4 +#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5 +#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6 +#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7 +#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB + + +/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR2STR; +extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6); +#define CAN2RXDSR2 _CAN2RXDSR2.Byte +#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0 +#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1 +#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2 +#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3 +#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4 +#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5 +#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6 +#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7 +#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB + + +/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR3STR; +extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7); +#define CAN2RXDSR3 _CAN2RXDSR3.Byte +#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0 +#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1 +#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2 +#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3 +#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4 +#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5 +#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6 +#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7 +#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB + + +/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR4STR; +extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8); +#define CAN2RXDSR4 _CAN2RXDSR4.Byte +#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0 +#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1 +#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2 +#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3 +#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4 +#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5 +#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6 +#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7 +#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB + + +/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR5STR; +extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9); +#define CAN2RXDSR5 _CAN2RXDSR5.Byte +#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0 +#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1 +#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2 +#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3 +#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4 +#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5 +#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6 +#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7 +#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB + + +/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR6STR; +extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA); +#define CAN2RXDSR6 _CAN2RXDSR6.Byte +#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0 +#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1 +#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2 +#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3 +#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4 +#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5 +#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6 +#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7 +#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB + + +/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR7STR; +extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB); +#define CAN2RXDSR7 _CAN2RXDSR7.Byte +#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0 +#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1 +#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2 +#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3 +#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4 +#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5 +#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6 +#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7 +#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB + + +/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2RXDLRSTR; +extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC); +#define CAN2RXDLR _CAN2RXDLR.Byte +#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0 +#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1 +#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2 +#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3 +#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC + + +/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN2TXIDR0STR; +extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0); +#define CAN2TXIDR0 _CAN2TXIDR0.Byte +#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21 +#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22 +#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23 +#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24 +#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25 +#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26 +#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27 +#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28 +#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21 +#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21 + + +/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN2TXIDR1STR; +extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1); +#define CAN2TXIDR1 _CAN2TXIDR1.Byte +#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15 +#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16 +#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17 +#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE +#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR +#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18 +#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19 +#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20 +#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15 +#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18 +#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15 + + +/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN2TXIDR2STR; +extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2); +#define CAN2TXIDR2 _CAN2TXIDR2.Byte +#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7 +#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8 +#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9 +#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10 +#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11 +#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12 +#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13 +#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14 +#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7 +#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7 + + +/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN2TXIDR3STR; +extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3); +#define CAN2TXIDR3 _CAN2TXIDR3.Byte +#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR +#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0 +#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1 +#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2 +#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3 +#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4 +#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5 +#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6 +#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID + + +/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR0STR; +extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4); +#define CAN2TXDSR0 _CAN2TXDSR0.Byte +#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0 +#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1 +#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2 +#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3 +#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4 +#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5 +#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6 +#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7 +#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB + + +/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR1STR; +extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5); +#define CAN2TXDSR1 _CAN2TXDSR1.Byte +#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0 +#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1 +#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2 +#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3 +#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4 +#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5 +#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6 +#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7 +#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB + + +/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR2STR; +extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6); +#define CAN2TXDSR2 _CAN2TXDSR2.Byte +#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0 +#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1 +#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2 +#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3 +#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4 +#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5 +#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6 +#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7 +#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB + + +/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR3STR; +extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7); +#define CAN2TXDSR3 _CAN2TXDSR3.Byte +#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0 +#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1 +#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2 +#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3 +#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4 +#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5 +#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6 +#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7 +#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB + + +/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR4STR; +extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8); +#define CAN2TXDSR4 _CAN2TXDSR4.Byte +#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0 +#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1 +#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2 +#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3 +#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4 +#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5 +#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6 +#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7 +#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB + + +/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR5STR; +extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9); +#define CAN2TXDSR5 _CAN2TXDSR5.Byte +#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0 +#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1 +#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2 +#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3 +#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4 +#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5 +#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6 +#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7 +#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB + + +/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR6STR; +extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA); +#define CAN2TXDSR6 _CAN2TXDSR6.Byte +#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0 +#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1 +#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2 +#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3 +#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4 +#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5 +#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6 +#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7 +#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB + + +/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR7STR; +extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB); +#define CAN2TXDSR7 _CAN2TXDSR7.Byte +#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0 +#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1 +#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2 +#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3 +#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4 +#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5 +#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6 +#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7 +#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB + + +/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TXDLRSTR; +extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC); +#define CAN2TXDLR _CAN2TXDLR.Byte +#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0 +#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1 +#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2 +#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3 +#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC + + +/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN2TXTBPRSTR; +extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF); +#define CAN2TXTBPR _CAN2TXTBPR.Byte +#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0 +#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1 +#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2 +#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3 +#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4 +#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5 +#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6 +#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7 +#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO + + +/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN3CTL0STR; +extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200); +#define CAN3CTL0 _CAN3CTL0.Byte +#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ +#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ +#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE +#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME +#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH +#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI +#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT +#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM + + +/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 3 Clock Source */ + byte CANE :1; /* MSCAN 3 Enable */ + } Bits; +} CAN3CTL1STR; +extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201); +#define CAN3CTL1 _CAN3CTL1.Byte +#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK +#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK +#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM +#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN +#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB +#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC +#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE + + +/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN3BTR0STR; +extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202); +#define CAN3BTR0 _CAN3BTR0.Byte +#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0 +#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1 +#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2 +#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3 +#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4 +#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5 +#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0 +#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1 +#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP +#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW + + +/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN3BTR1STR; +extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203); +#define CAN3BTR1 _CAN3BTR1.Byte +#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10 +#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11 +#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12 +#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13 +#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20 +#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21 +#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22 +#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP +#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10 +#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20 +#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10 + + +/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN3RFLGSTR; +extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204); +#define CAN3RFLG _CAN3RFLG.Byte +#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF +#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF +#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0 +#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1 +#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0 +#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1 +#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF +#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF +#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT +#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT + + +/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN3RIERSTR; +extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205); +#define CAN3RIER _CAN3RIER.Byte +#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE +#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE +#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0 +#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1 +#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0 +#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1 +#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE +#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE +#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE +#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE + + +/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TFLGSTR; +extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206); +#define CAN3TFLG _CAN3TFLG.Byte +#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0 +#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1 +#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2 +#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE + + +/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TIERSTR; +extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207); +#define CAN3TIER _CAN3TIER.Byte +#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0 +#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1 +#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2 +#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE + + +/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TARQSTR; +extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208); +#define CAN3TARQ _CAN3TARQ.Byte +#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0 +#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1 +#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2 +#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ + + +/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TAAKSTR; +extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209); +#define CAN3TAAK _CAN3TAAK.Byte +#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0 +#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1 +#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2 +#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK + + +/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TBSELSTR; +extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A); +#define CAN3TBSEL _CAN3TBSEL.Byte +#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0 +#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1 +#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2 +#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX + + +/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN3IDACSTR; +extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B); +#define CAN3IDAC _CAN3IDAC.Byte +#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0 +#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1 +#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2 +#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0 +#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1 +#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT +#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM + + +/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN3RXERRSTR; +extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E); +#define CAN3RXERR _CAN3RXERR.Byte +#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0 +#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1 +#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2 +#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3 +#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4 +#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5 +#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6 +#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7 +#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR + + +/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN3TXERRSTR; +extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F); +#define CAN3TXERR _CAN3TXERR.Byte +#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0 +#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1 +#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2 +#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3 +#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4 +#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5 +#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6 +#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7 +#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR + + +/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR0STR; +extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210); +#define CAN3IDAR0 _CAN3IDAR0.Byte +#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0 +#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1 +#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2 +#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3 +#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4 +#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5 +#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6 +#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7 +#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC + + +/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR1STR; +extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211); +#define CAN3IDAR1 _CAN3IDAR1.Byte +#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0 +#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1 +#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2 +#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3 +#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4 +#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5 +#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6 +#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7 +#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC + + +/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR2STR; +extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212); +#define CAN3IDAR2 _CAN3IDAR2.Byte +#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0 +#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1 +#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2 +#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3 +#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4 +#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5 +#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6 +#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7 +#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC + + +/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR3STR; +extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213); +#define CAN3IDAR3 _CAN3IDAR3.Byte +#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0 +#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1 +#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2 +#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3 +#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4 +#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5 +#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6 +#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7 +#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC + + +/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR0STR; +extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214); +#define CAN3IDMR0 _CAN3IDMR0.Byte +#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0 +#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1 +#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2 +#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3 +#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4 +#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5 +#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6 +#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7 +#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM + + +/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR1STR; +extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215); +#define CAN3IDMR1 _CAN3IDMR1.Byte +#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0 +#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1 +#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2 +#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3 +#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4 +#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5 +#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6 +#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7 +#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM + + +/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR2STR; +extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216); +#define CAN3IDMR2 _CAN3IDMR2.Byte +#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0 +#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1 +#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2 +#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3 +#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4 +#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5 +#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6 +#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7 +#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM + + +/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR3STR; +extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217); +#define CAN3IDMR3 _CAN3IDMR3.Byte +#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0 +#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1 +#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2 +#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3 +#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4 +#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5 +#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6 +#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7 +#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM + + +/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR4STR; +extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218); +#define CAN3IDAR4 _CAN3IDAR4.Byte +#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0 +#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1 +#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2 +#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3 +#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4 +#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5 +#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6 +#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7 +#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC + + +/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR5STR; +extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219); +#define CAN3IDAR5 _CAN3IDAR5.Byte +#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0 +#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1 +#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2 +#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3 +#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4 +#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5 +#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6 +#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7 +#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC + + +/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR6STR; +extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A); +#define CAN3IDAR6 _CAN3IDAR6.Byte +#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0 +#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1 +#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2 +#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3 +#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4 +#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5 +#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6 +#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7 +#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC + + +/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR7STR; +extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B); +#define CAN3IDAR7 _CAN3IDAR7.Byte +#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0 +#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1 +#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2 +#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3 +#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4 +#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5 +#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6 +#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7 +#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC + + +/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR4STR; +extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C); +#define CAN3IDMR4 _CAN3IDMR4.Byte +#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0 +#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1 +#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2 +#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3 +#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4 +#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5 +#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6 +#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7 +#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM + + +/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR5STR; +extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D); +#define CAN3IDMR5 _CAN3IDMR5.Byte +#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0 +#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1 +#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2 +#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3 +#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4 +#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5 +#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6 +#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7 +#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM + + +/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR6STR; +extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E); +#define CAN3IDMR6 _CAN3IDMR6.Byte +#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0 +#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1 +#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2 +#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3 +#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4 +#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5 +#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6 +#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7 +#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM + + +/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR7STR; +extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F); +#define CAN3IDMR7 _CAN3IDMR7.Byte +#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0 +#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1 +#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2 +#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3 +#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4 +#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5 +#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6 +#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7 +#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM + + +/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN3RXIDR0STR; +extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220); +#define CAN3RXIDR0 _CAN3RXIDR0.Byte +#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21 +#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22 +#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23 +#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24 +#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25 +#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26 +#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27 +#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28 +#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21 +#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21 + + +/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN3RXIDR1STR; +extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221); +#define CAN3RXIDR1 _CAN3RXIDR1.Byte +#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15 +#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16 +#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17 +#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE +#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR +#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18 +#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19 +#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20 +#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15 +#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18 +#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15 + + +/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN3RXIDR2STR; +extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222); +#define CAN3RXIDR2 _CAN3RXIDR2.Byte +#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7 +#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8 +#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9 +#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10 +#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11 +#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12 +#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13 +#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14 +#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7 +#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7 + + +/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN3RXIDR3STR; +extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223); +#define CAN3RXIDR3 _CAN3RXIDR3.Byte +#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR +#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0 +#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1 +#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2 +#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3 +#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4 +#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5 +#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6 +#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID + + +/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR0STR; +extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224); +#define CAN3RXDSR0 _CAN3RXDSR0.Byte +#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0 +#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1 +#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2 +#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3 +#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4 +#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5 +#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6 +#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7 +#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB + + +/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR1STR; +extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225); +#define CAN3RXDSR1 _CAN3RXDSR1.Byte +#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0 +#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1 +#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2 +#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3 +#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4 +#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5 +#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6 +#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7 +#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB + + +/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR2STR; +extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226); +#define CAN3RXDSR2 _CAN3RXDSR2.Byte +#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0 +#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1 +#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2 +#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3 +#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4 +#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5 +#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6 +#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7 +#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB + + +/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR3STR; +extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227); +#define CAN3RXDSR3 _CAN3RXDSR3.Byte +#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0 +#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1 +#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2 +#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3 +#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4 +#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5 +#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6 +#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7 +#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB + + +/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR4STR; +extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228); +#define CAN3RXDSR4 _CAN3RXDSR4.Byte +#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0 +#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1 +#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2 +#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3 +#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4 +#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5 +#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6 +#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7 +#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB + + +/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR5STR; +extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229); +#define CAN3RXDSR5 _CAN3RXDSR5.Byte +#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0 +#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1 +#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2 +#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3 +#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4 +#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5 +#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6 +#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7 +#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB + + +/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR6STR; +extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A); +#define CAN3RXDSR6 _CAN3RXDSR6.Byte +#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0 +#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1 +#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2 +#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3 +#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4 +#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5 +#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6 +#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7 +#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB + + +/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR7STR; +extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B); +#define CAN3RXDSR7 _CAN3RXDSR7.Byte +#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0 +#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1 +#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2 +#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3 +#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4 +#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5 +#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6 +#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7 +#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB + + +/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3RXDLRSTR; +extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C); +#define CAN3RXDLR _CAN3RXDLR.Byte +#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0 +#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1 +#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2 +#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3 +#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC + + +/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN3TXIDR0STR; +extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230); +#define CAN3TXIDR0 _CAN3TXIDR0.Byte +#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21 +#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22 +#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23 +#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24 +#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25 +#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26 +#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27 +#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28 +#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21 +#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21 + + +/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN3TXIDR1STR; +extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231); +#define CAN3TXIDR1 _CAN3TXIDR1.Byte +#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15 +#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16 +#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17 +#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE +#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR +#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18 +#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19 +#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20 +#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15 +#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18 +#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15 + + +/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN3TXIDR2STR; +extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232); +#define CAN3TXIDR2 _CAN3TXIDR2.Byte +#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7 +#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8 +#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9 +#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10 +#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11 +#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12 +#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13 +#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14 +#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7 +#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7 + + +/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN3TXIDR3STR; +extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233); +#define CAN3TXIDR3 _CAN3TXIDR3.Byte +#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR +#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0 +#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1 +#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2 +#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3 +#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4 +#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5 +#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6 +#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID + + +/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR0STR; +extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234); +#define CAN3TXDSR0 _CAN3TXDSR0.Byte +#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0 +#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1 +#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2 +#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3 +#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4 +#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5 +#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6 +#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7 +#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB + + +/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR1STR; +extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235); +#define CAN3TXDSR1 _CAN3TXDSR1.Byte +#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0 +#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1 +#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2 +#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3 +#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4 +#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5 +#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6 +#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7 +#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB + + +/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR2STR; +extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236); +#define CAN3TXDSR2 _CAN3TXDSR2.Byte +#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0 +#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1 +#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2 +#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3 +#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4 +#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5 +#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6 +#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7 +#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB + + +/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR3STR; +extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237); +#define CAN3TXDSR3 _CAN3TXDSR3.Byte +#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0 +#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1 +#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2 +#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3 +#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4 +#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5 +#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6 +#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7 +#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB + + +/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR4STR; +extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238); +#define CAN3TXDSR4 _CAN3TXDSR4.Byte +#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0 +#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1 +#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2 +#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3 +#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4 +#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5 +#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6 +#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7 +#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB + + +/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR5STR; +extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239); +#define CAN3TXDSR5 _CAN3TXDSR5.Byte +#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0 +#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1 +#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2 +#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3 +#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4 +#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5 +#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6 +#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7 +#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB + + +/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR6STR; +extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A); +#define CAN3TXDSR6 _CAN3TXDSR6.Byte +#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0 +#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1 +#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2 +#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3 +#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4 +#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5 +#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6 +#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7 +#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB + + +/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR7STR; +extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B); +#define CAN3TXDSR7 _CAN3TXDSR7.Byte +#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0 +#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1 +#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2 +#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3 +#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4 +#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5 +#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6 +#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7 +#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB + + +/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TXDLRSTR; +extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C); +#define CAN3TXDLR _CAN3TXDLR.Byte +#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0 +#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1 +#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2 +#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3 +#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC + + +/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN3TXTBPRSTR; +extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F); +#define CAN3TXTBPR _CAN3TXTBPR.Byte +#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0 +#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1 +#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2 +#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3 +#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4 +#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5 +#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6 +#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7 +#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTT :8; + } MergedBits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 +#define PTT_PTT _PTT.MergedBits.grpPTT + + +/*** PTIT - Port T Input; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTIT :8; + } MergedBits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 +#define PTIT_PTIT _PTIT.MergedBits.grpPTIT + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; + struct { + byte grpDDRT :8; + } MergedBits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 +#define DDRT_DDRT _DDRT.MergedBits.grpDDRT + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; + struct { + byte grpRDRT :8; + } MergedBits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 +#define RDRT_RDRT _RDRT.MergedBits.grpRDRT + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; + struct { + byte grpPERT :8; + } MergedBits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 +#define PERT_PERT _PERT.MergedBits.grpPERT + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; + struct { + byte grpPPST :8; + } MergedBits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 +#define PPST_PPST _PPST.MergedBits.grpPPST + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte PTS4 :1; /* Port S Bit 4 */ + byte PTS5 :1; /* Port S Bit 5 */ + byte PTS6 :1; /* Port S Bit 6 */ + byte PTS7 :1; /* Port S Bit 7 */ + } Bits; + struct { + byte grpPTS :8; + } MergedBits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS4 _PTS.Bits.PTS4 +#define PTS_PTS5 _PTS.Bits.PTS5 +#define PTS_PTS6 _PTS.Bits.PTS6 +#define PTS_PTS7 _PTS.Bits.PTS7 +#define PTS_PTS _PTS.MergedBits.grpPTS + + +/*** PTIS - Port S Input; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte PTIS4 :1; /* Port S Bit 4 */ + byte PTIS5 :1; /* Port S Bit 5 */ + byte PTIS6 :1; /* Port S Bit 6 */ + byte PTIS7 :1; /* Port S Bit 7 */ + } Bits; + struct { + byte grpPTIS :8; + } MergedBits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS4 _PTIS.Bits.PTIS4 +#define PTIS_PTIS5 _PTIS.Bits.PTIS5 +#define PTIS_PTIS6 _PTIS.Bits.PTIS6 +#define PTIS_PTIS7 _PTIS.Bits.PTIS7 +#define PTIS_PTIS _PTIS.MergedBits.grpPTIS + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte DDRS4 :1; /* Data Direction Port S Bit 4 */ + byte DDRS5 :1; /* Data Direction Port S Bit 5 */ + byte DDRS6 :1; /* Data Direction Port S Bit 6 */ + byte DDRS7 :1; /* Data Direction Port S Bit 7 */ + } Bits; + struct { + byte grpDDRS :8; + } MergedBits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS4 _DDRS.Bits.DDRS4 +#define DDRS_DDRS5 _DDRS.Bits.DDRS5 +#define DDRS_DDRS6 _DDRS.Bits.DDRS6 +#define DDRS_DDRS7 _DDRS.Bits.DDRS7 +#define DDRS_DDRS _DDRS.MergedBits.grpDDRS + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */ + byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */ + byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */ + byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */ + } Bits; + struct { + byte grpRDRS :8; + } MergedBits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS4 _RDRS.Bits.RDRS4 +#define RDRS_RDRS5 _RDRS.Bits.RDRS5 +#define RDRS_RDRS6 _RDRS.Bits.RDRS6 +#define RDRS_RDRS7 _RDRS.Bits.RDRS7 +#define RDRS_RDRS _RDRS.MergedBits.grpRDRS + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */ + byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */ + byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */ + byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */ + } Bits; + struct { + byte grpPERS :8; + } MergedBits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS4 _PERS.Bits.PERS4 +#define PERS_PERS5 _PERS.Bits.PERS5 +#define PERS_PERS6 _PERS.Bits.PERS6 +#define PERS_PERS7 _PERS.Bits.PERS7 +#define PERS_PERS _PERS.MergedBits.grpPERS + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte PPSS4 :1; /* Pull Select Port S Bit 4 */ + byte PPSS5 :1; /* Pull Select Port S Bit 5 */ + byte PPSS6 :1; /* Pull Select Port S Bit 6 */ + byte PPSS7 :1; /* Pull Select Port S Bit 7 */ + } Bits; + struct { + byte grpPPSS :8; + } MergedBits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS4 _PPSS.Bits.PPSS4 +#define PPSS_PPSS5 _PPSS.Bits.PPSS5 +#define PPSS_PPSS6 _PPSS.Bits.PPSS6 +#define PPSS_PPSS7 _PPSS.Bits.PPSS7 +#define PPSS_PPSS _PPSS.MergedBits.grpPPSS + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */ + byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */ + byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */ + byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */ + } Bits; + struct { + byte grpWOMS :8; + } MergedBits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS4 _WOMS.Bits.WOMS4 +#define WOMS_WOMS5 _WOMS.Bits.WOMS5 +#define WOMS_WOMS6 _WOMS.Bits.WOMS6 +#define WOMS_WOMS7 _WOMS.Bits.WOMS7 +#define WOMS_WOMS _WOMS.MergedBits.grpWOMS + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port T Bit 0 */ + byte PTM1 :1; /* Port T Bit 1 */ + byte PTM2 :1; /* Port T Bit 2 */ + byte PTM3 :1; /* Port T Bit 3 */ + byte PTM4 :1; /* Port T Bit 4 */ + byte PTM5 :1; /* Port T Bit 5 */ + byte PTM6 :1; /* Port T Bit 6 */ + byte PTM7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTM :8; + } MergedBits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM6 _PTM.Bits.PTM6 +#define PTM_PTM7 _PTM.Bits.PTM7 +#define PTM_PTM _PTM.MergedBits.grpPTM + + +/*** PTIM - Port M Input; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte PTIM6 :1; /* Port M Bit 6 */ + byte PTIM7 :1; /* Port M Bit 7 */ + } Bits; + struct { + byte grpPTIM :8; + } MergedBits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM6 _PTIM.Bits.PTIM6 +#define PTIM_PTIM7 _PTIM.Bits.PTIM7 +#define PTIM_PTIM _PTIM.MergedBits.grpPTIM + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte DDRM6 :1; /* Data Direction Port M Bit 6 */ + byte DDRM7 :1; /* Data Direction Port M Bit 7 */ + } Bits; + struct { + byte grpDDRM :8; + } MergedBits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM6 _DDRM.Bits.DDRM6 +#define DDRM_DDRM7 _DDRM.Bits.DDRM7 +#define DDRM_DDRM _DDRM.MergedBits.grpDDRM + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */ + byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */ + } Bits; + struct { + byte grpRDRM :8; + } MergedBits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM6 _RDRM.Bits.RDRM6 +#define RDRM_RDRM7 _RDRM.Bits.RDRM7 +#define RDRM_RDRM _RDRM.MergedBits.grpRDRM + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */ + byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */ + } Bits; + struct { + byte grpPERM :8; + } MergedBits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM6 _PERM.Bits.PERM6 +#define PERM_PERM7 _PERM.Bits.PERM7 +#define PERM_PERM _PERM.MergedBits.grpPERM + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte PPSM6 :1; /* Pull Select Port M Bit 6 */ + byte PPSM7 :1; /* Pull Select Port M Bit 7 */ + } Bits; + struct { + byte grpPPSM :8; + } MergedBits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM6 _PPSM.Bits.PPSM6 +#define PPSM_PPSM7 _PPSM.Bits.PPSM7 +#define PPSM_PPSM _PPSM.MergedBits.grpPPSM + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */ + byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */ + } Bits; + struct { + byte grpWOMM :8; + } MergedBits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM6 _WOMM.Bits.WOMM6 +#define WOMM_WOMM7 _WOMM.Bits.WOMM7 +#define WOMM_WOMM _WOMM.MergedBits.grpWOMM + + +/*** MODRR - Module Routing Register; 0x00000257 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* CAN0 Routing */ + byte MODRR1 :1; /* CAN0 Routing */ + byte MODRR2 :1; /* CAN4 Routing */ + byte MODRR3 :1; /* CAN4 Routing */ + byte MODRR4 :1; /* SPI0 Routing */ + byte MODRR5 :1; /* SPI1 Routing */ + byte MODRR6 :1; /* SPI2 Routing */ + byte :1; + } Bits; + struct { + byte grpMODRR :7; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR5 _MODRR.Bits.MODRR5 +#define MODRR_MODRR6 _MODRR.Bits.MODRR6 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTP :8; + } MergedBits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 +#define PTP_PTP _PTP.MergedBits.grpPTP + + +/*** PTIP - Port P Input; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTIP :8; + } MergedBits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 +#define PTIP_PTIP _PTIP.MergedBits.grpPTIP + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; + struct { + byte grpDDRP :8; + } MergedBits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 +#define DDRP_DDRP _DDRP.MergedBits.grpDDRP + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; + struct { + byte grpRDRP :8; + } MergedBits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 +#define RDRP_RDRP _RDRP.MergedBits.grpRDRP + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPERP :8; + } MergedBits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 +#define PERP_PERP _PERP.MergedBits.grpPERP + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; + struct { + byte grpPPSP :8; + } MergedBits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 +#define PPSP_PPSP _PPSP.MergedBits.grpPPSP + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPIEP :8; + } MergedBits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 +#define PIEP_PIEP _PIEP.MergedBits.grpPIEP + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; + struct { + byte grpPIFP :8; + } MergedBits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 +#define PIFP_PIFP _PIFP.MergedBits.grpPIFP + + +/*** PTH - Port H I/O Register; 0x00000260 ***/ +typedef union { + byte Byte; + struct { + byte PTH0 :1; /* Port H Bit 0 */ + byte PTH1 :1; /* Port H Bit 1 */ + byte PTH2 :1; /* Port H Bit 2 */ + byte PTH3 :1; /* Port H Bit 3 */ + byte PTH4 :1; /* Port H Bit 4 */ + byte PTH5 :1; /* Port H Bit 5 */ + byte PTH6 :1; /* Port H Bit 6 */ + byte PTH7 :1; /* Port H Bit 7 */ + } Bits; + struct { + byte grpPTH :8; + } MergedBits; +} PTHSTR; +extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260); +#define PTH _PTH.Byte +#define PTH_PTH0 _PTH.Bits.PTH0 +#define PTH_PTH1 _PTH.Bits.PTH1 +#define PTH_PTH2 _PTH.Bits.PTH2 +#define PTH_PTH3 _PTH.Bits.PTH3 +#define PTH_PTH4 _PTH.Bits.PTH4 +#define PTH_PTH5 _PTH.Bits.PTH5 +#define PTH_PTH6 _PTH.Bits.PTH6 +#define PTH_PTH7 _PTH.Bits.PTH7 +#define PTH_PTH _PTH.MergedBits.grpPTH + + +/*** PTIH - Port H Input Register; 0x00000261 ***/ +typedef union { + byte Byte; + struct { + byte PTIH0 :1; /* Port H Bit 0 */ + byte PTIH1 :1; /* Port H Bit 1 */ + byte PTIH2 :1; /* Port H Bit 2 */ + byte PTIH3 :1; /* Port H Bit 3 */ + byte PTIH4 :1; /* Port H Bit 4 */ + byte PTIH5 :1; /* Port H Bit 5 */ + byte PTIH6 :1; /* Port H Bit 6 */ + byte PTIH7 :1; /* Port H Bit 7 */ + } Bits; + struct { + byte grpPTIH :8; + } MergedBits; +} PTIHSTR; +extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261); +#define PTIH _PTIH.Byte +#define PTIH_PTIH0 _PTIH.Bits.PTIH0 +#define PTIH_PTIH1 _PTIH.Bits.PTIH1 +#define PTIH_PTIH2 _PTIH.Bits.PTIH2 +#define PTIH_PTIH3 _PTIH.Bits.PTIH3 +#define PTIH_PTIH4 _PTIH.Bits.PTIH4 +#define PTIH_PTIH5 _PTIH.Bits.PTIH5 +#define PTIH_PTIH6 _PTIH.Bits.PTIH6 +#define PTIH_PTIH7 _PTIH.Bits.PTIH7 +#define PTIH_PTIH _PTIH.MergedBits.grpPTIH + + +/*** DDRH - Port H Data Direction Register; 0x00000262 ***/ +typedef union { + byte Byte; + struct { + byte DDRH0 :1; /* Data Direction Port H Bit 0 */ + byte DDRH1 :1; /* Data Direction Port H Bit 1 */ + byte DDRH2 :1; /* Data Direction Port H Bit 2 */ + byte DDRH3 :1; /* Data Direction Port H Bit 3 */ + byte DDRH4 :1; /* Data Direction Port H Bit 4 */ + byte DDRH5 :1; /* Data Direction Port H Bit 5 */ + byte DDRH6 :1; /* Data Direction Port H Bit 6 */ + byte DDRH7 :1; /* Data Direction Port H Bit 7 */ + } Bits; + struct { + byte grpDDRH :8; + } MergedBits; +} DDRHSTR; +extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262); +#define DDRH _DDRH.Byte +#define DDRH_DDRH0 _DDRH.Bits.DDRH0 +#define DDRH_DDRH1 _DDRH.Bits.DDRH1 +#define DDRH_DDRH2 _DDRH.Bits.DDRH2 +#define DDRH_DDRH3 _DDRH.Bits.DDRH3 +#define DDRH_DDRH4 _DDRH.Bits.DDRH4 +#define DDRH_DDRH5 _DDRH.Bits.DDRH5 +#define DDRH_DDRH6 _DDRH.Bits.DDRH6 +#define DDRH_DDRH7 _DDRH.Bits.DDRH7 +#define DDRH_DDRH _DDRH.MergedBits.grpDDRH + + +/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/ +typedef union { + byte Byte; + struct { + byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */ + byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */ + byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */ + byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */ + byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */ + byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */ + byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */ + byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */ + } Bits; + struct { + byte grpRDRH :8; + } MergedBits; +} RDRHSTR; +extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263); +#define RDRH _RDRH.Byte +#define RDRH_RDRH0 _RDRH.Bits.RDRH0 +#define RDRH_RDRH1 _RDRH.Bits.RDRH1 +#define RDRH_RDRH2 _RDRH.Bits.RDRH2 +#define RDRH_RDRH3 _RDRH.Bits.RDRH3 +#define RDRH_RDRH4 _RDRH.Bits.RDRH4 +#define RDRH_RDRH5 _RDRH.Bits.RDRH5 +#define RDRH_RDRH6 _RDRH.Bits.RDRH6 +#define RDRH_RDRH7 _RDRH.Bits.RDRH7 +#define RDRH_RDRH _RDRH.MergedBits.grpRDRH + + +/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/ +typedef union { + byte Byte; + struct { + byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */ + byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */ + byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */ + byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */ + byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */ + byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */ + byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */ + byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */ + } Bits; + struct { + byte grpPERH :8; + } MergedBits; +} PERHSTR; +extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264); +#define PERH _PERH.Byte +#define PERH_PERH0 _PERH.Bits.PERH0 +#define PERH_PERH1 _PERH.Bits.PERH1 +#define PERH_PERH2 _PERH.Bits.PERH2 +#define PERH_PERH3 _PERH.Bits.PERH3 +#define PERH_PERH4 _PERH.Bits.PERH4 +#define PERH_PERH5 _PERH.Bits.PERH5 +#define PERH_PERH6 _PERH.Bits.PERH6 +#define PERH_PERH7 _PERH.Bits.PERH7 +#define PERH_PERH _PERH.MergedBits.grpPERH + + +/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/ +typedef union { + byte Byte; + struct { + byte PPSH0 :1; /* Pull Select Port H Bit 0 */ + byte PPSH1 :1; /* Pull Select Port H Bit 1 */ + byte PPSH2 :1; /* Pull Select Port H Bit 2 */ + byte PPSH3 :1; /* Pull Select Port H Bit 3 */ + byte PPSH4 :1; /* Pull Select Port H Bit 4 */ + byte PPSH5 :1; /* Pull Select Port H Bit 5 */ + byte PPSH6 :1; /* Pull Select Port H Bit 6 */ + byte PPSH7 :1; /* Pull Select Port H Bit 7 */ + } Bits; + struct { + byte grpPPSH :8; + } MergedBits; +} PPSHSTR; +extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265); +#define PPSH _PPSH.Byte +#define PPSH_PPSH0 _PPSH.Bits.PPSH0 +#define PPSH_PPSH1 _PPSH.Bits.PPSH1 +#define PPSH_PPSH2 _PPSH.Bits.PPSH2 +#define PPSH_PPSH3 _PPSH.Bits.PPSH3 +#define PPSH_PPSH4 _PPSH.Bits.PPSH4 +#define PPSH_PPSH5 _PPSH.Bits.PPSH5 +#define PPSH_PPSH6 _PPSH.Bits.PPSH6 +#define PPSH_PPSH7 _PPSH.Bits.PPSH7 +#define PPSH_PPSH _PPSH.MergedBits.grpPPSH + + +/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/ +typedef union { + byte Byte; + struct { + byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */ + byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */ + byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */ + byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */ + byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */ + byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */ + byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */ + byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */ + } Bits; + struct { + byte grpPIEH :8; + } MergedBits; +} PIEHSTR; +extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266); +#define PIEH _PIEH.Byte +#define PIEH_PIEH0 _PIEH.Bits.PIEH0 +#define PIEH_PIEH1 _PIEH.Bits.PIEH1 +#define PIEH_PIEH2 _PIEH.Bits.PIEH2 +#define PIEH_PIEH3 _PIEH.Bits.PIEH3 +#define PIEH_PIEH4 _PIEH.Bits.PIEH4 +#define PIEH_PIEH5 _PIEH.Bits.PIEH5 +#define PIEH_PIEH6 _PIEH.Bits.PIEH6 +#define PIEH_PIEH7 _PIEH.Bits.PIEH7 +#define PIEH_PIEH _PIEH.MergedBits.grpPIEH + + +/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/ +typedef union { + byte Byte; + struct { + byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */ + byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */ + byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */ + byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */ + byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */ + byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */ + byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */ + byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */ + } Bits; + struct { + byte grpPIFH :8; + } MergedBits; +} PIFHSTR; +extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267); +#define PIFH _PIFH.Byte +#define PIFH_PIFH0 _PIFH.Bits.PIFH0 +#define PIFH_PIFH1 _PIFH.Bits.PIFH1 +#define PIFH_PIFH2 _PIFH.Bits.PIFH2 +#define PIFH_PIFH3 _PIFH.Bits.PIFH3 +#define PIFH_PIFH4 _PIFH.Bits.PIFH4 +#define PIFH_PIFH5 _PIFH.Bits.PIFH5 +#define PIFH_PIFH6 _PIFH.Bits.PIFH6 +#define PIFH_PIFH7 _PIFH.Bits.PIFH7 +#define PIFH_PIFH _PIFH.MergedBits.grpPIFH + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte PTJ0 :1; /* Port J Bit 0 */ + byte PTJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); +#define PTJ _PTJ.Byte +#define PTJ_PTJ0 _PTJ.Bits.PTJ0 +#define PTJ_PTJ1 _PTJ.Bits.PTJ1 +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ _PTJ.MergedBits.grpPTJ +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte PTIJ0 :1; /* Port J Bit 0 */ + byte PTIJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTIJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 +#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte DDRJ0 :1; /* Data Direction Port J Bit 0 */ + byte DDRJ1 :1; /* Data Direction Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte grpDDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 +#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */ + byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte grpRDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0 +#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1 +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */ + byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPERJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); +#define PERJ _PERJ.Byte +#define PERJ_PERJ0 _PERJ.Bits.PERJ0 +#define PERJ_PERJ1 _PERJ.Bits.PERJ1 +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ _PERJ.MergedBits.grpPERJ +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + + +/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte PPSJ0 :1; /* Pull Select Port J Bit 0 */ + byte PPSJ1 :1; /* Pull Select Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte grpPPSJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 +#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */ + byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPIEJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0 +#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1 +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */ + byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte grpPIFJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0 +#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1 +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + + +/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN4CTL0STR; +extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280); +#define CAN4CTL0 _CAN4CTL0.Byte +#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ +#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ +#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE +#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME +#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH +#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI +#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT +#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM + + +/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN4 Clock Source */ + byte CANE :1; /* MSCAN4 Enable */ + } Bits; +} CAN4CTL1STR; +extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281); +#define CAN4CTL1 _CAN4CTL1.Byte +#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK +#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK +#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM +#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN +#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB +#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC +#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE + + +/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN4BTR0STR; +extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282); +#define CAN4BTR0 _CAN4BTR0.Byte +#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0 +#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1 +#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2 +#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3 +#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4 +#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5 +#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0 +#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1 +#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP +#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW + + +/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN4BTR1STR; +extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283); +#define CAN4BTR1 _CAN4BTR1.Byte +#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10 +#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11 +#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12 +#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13 +#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20 +#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21 +#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22 +#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP +#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10 +#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20 +#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10 + + +/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RFLGSTR; +extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284); +#define CAN4RFLG _CAN4RFLG.Byte +#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF +#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF +#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0 +#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1 +#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0 +#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1 +#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF +#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF +#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT +#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT + + +/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RIERSTR; +extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285); +#define CAN4RIER _CAN4RIER.Byte +#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE +#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE +#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0 +#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1 +#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0 +#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1 +#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE +#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE +#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE +#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE + + +/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TFLGSTR; +extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286); +#define CAN4TFLG _CAN4TFLG.Byte +#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0 +#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1 +#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2 +#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE + + +/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TIERSTR; +extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287); +#define CAN4TIER _CAN4TIER.Byte +#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0 +#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1 +#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2 +#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE + + +/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TARQSTR; +extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288); +#define CAN4TARQ _CAN4TARQ.Byte +#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0 +#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1 +#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2 +#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ + + +/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TAAKSTR; +extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289); +#define CAN4TAAK _CAN4TAAK.Byte +#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0 +#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1 +#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2 +#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK + + +/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TBSELSTR; +extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A); +#define CAN4TBSEL _CAN4TBSEL.Byte +#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0 +#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1 +#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2 +#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX + + +/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN4IDACSTR; +extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B); +#define CAN4IDAC _CAN4IDAC.Byte +#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0 +#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1 +#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2 +#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0 +#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1 +#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT +#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM + + +/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN4RXERRSTR; +extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E); +#define CAN4RXERR _CAN4RXERR.Byte +#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0 +#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1 +#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2 +#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3 +#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4 +#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5 +#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6 +#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7 +#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR + + +/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN4TXERRSTR; +extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F); +#define CAN4TXERR _CAN4TXERR.Byte +#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0 +#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1 +#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2 +#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3 +#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4 +#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5 +#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6 +#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7 +#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR + + +/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR0STR; +extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290); +#define CAN4IDAR0 _CAN4IDAR0.Byte +#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0 +#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1 +#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2 +#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3 +#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4 +#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5 +#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6 +#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7 +#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC + + +/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR1STR; +extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291); +#define CAN4IDAR1 _CAN4IDAR1.Byte +#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0 +#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1 +#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2 +#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3 +#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4 +#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5 +#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6 +#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7 +#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC + + +/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR2STR; +extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292); +#define CAN4IDAR2 _CAN4IDAR2.Byte +#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0 +#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1 +#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2 +#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3 +#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4 +#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5 +#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6 +#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7 +#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC + + +/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR3STR; +extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293); +#define CAN4IDAR3 _CAN4IDAR3.Byte +#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0 +#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1 +#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2 +#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3 +#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4 +#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5 +#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6 +#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7 +#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC + + +/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR0STR; +extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294); +#define CAN4IDMR0 _CAN4IDMR0.Byte +#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0 +#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1 +#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2 +#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3 +#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4 +#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5 +#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6 +#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7 +#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM + + +/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR1STR; +extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295); +#define CAN4IDMR1 _CAN4IDMR1.Byte +#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0 +#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1 +#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2 +#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3 +#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4 +#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5 +#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6 +#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7 +#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM + + +/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR2STR; +extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296); +#define CAN4IDMR2 _CAN4IDMR2.Byte +#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0 +#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1 +#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2 +#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3 +#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4 +#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5 +#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6 +#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7 +#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM + + +/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR3STR; +extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297); +#define CAN4IDMR3 _CAN4IDMR3.Byte +#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0 +#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1 +#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2 +#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3 +#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4 +#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5 +#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6 +#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7 +#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM + + +/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR4STR; +extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298); +#define CAN4IDAR4 _CAN4IDAR4.Byte +#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0 +#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1 +#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2 +#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3 +#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4 +#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5 +#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6 +#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7 +#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC + + +/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR5STR; +extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299); +#define CAN4IDAR5 _CAN4IDAR5.Byte +#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0 +#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1 +#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2 +#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3 +#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4 +#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5 +#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6 +#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7 +#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC + + +/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR6STR; +extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A); +#define CAN4IDAR6 _CAN4IDAR6.Byte +#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0 +#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1 +#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2 +#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3 +#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4 +#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5 +#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6 +#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7 +#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC + + +/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR7STR; +extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B); +#define CAN4IDAR7 _CAN4IDAR7.Byte +#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0 +#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1 +#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2 +#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3 +#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4 +#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5 +#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6 +#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7 +#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC + + +/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR4STR; +extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C); +#define CAN4IDMR4 _CAN4IDMR4.Byte +#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0 +#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1 +#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2 +#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3 +#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4 +#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5 +#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6 +#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7 +#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM + + +/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR5STR; +extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D); +#define CAN4IDMR5 _CAN4IDMR5.Byte +#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0 +#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1 +#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2 +#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3 +#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4 +#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5 +#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6 +#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7 +#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM + + +/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR6STR; +extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E); +#define CAN4IDMR6 _CAN4IDMR6.Byte +#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0 +#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1 +#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2 +#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3 +#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4 +#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5 +#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6 +#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7 +#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM + + +/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR7STR; +extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F); +#define CAN4IDMR7 _CAN4IDMR7.Byte +#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0 +#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1 +#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2 +#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3 +#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4 +#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5 +#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6 +#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7 +#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM + + +/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN4RXIDR0STR; +extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0); +#define CAN4RXIDR0 _CAN4RXIDR0.Byte +#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21 +#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22 +#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23 +#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24 +#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25 +#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26 +#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27 +#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28 +#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21 +#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21 + + +/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4RXIDR1STR; +extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1); +#define CAN4RXIDR1 _CAN4RXIDR1.Byte +#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15 +#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16 +#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17 +#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE +#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR +#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18 +#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19 +#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20 +#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15 +#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18 +#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15 + + +/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN4RXIDR2STR; +extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2); +#define CAN4RXIDR2 _CAN4RXIDR2.Byte +#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7 +#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8 +#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9 +#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10 +#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11 +#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12 +#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13 +#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14 +#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7 +#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7 + + +/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4RXIDR3STR; +extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3); +#define CAN4RXIDR3 _CAN4RXIDR3.Byte +#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR +#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0 +#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1 +#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2 +#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3 +#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4 +#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5 +#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6 +#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID + + +/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR0STR; +extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4); +#define CAN4RXDSR0 _CAN4RXDSR0.Byte +#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0 +#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1 +#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2 +#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3 +#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4 +#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5 +#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6 +#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7 +#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB + + +/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR1STR; +extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5); +#define CAN4RXDSR1 _CAN4RXDSR1.Byte +#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0 +#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1 +#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2 +#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3 +#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4 +#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5 +#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6 +#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7 +#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB + + +/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR2STR; +extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6); +#define CAN4RXDSR2 _CAN4RXDSR2.Byte +#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0 +#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1 +#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2 +#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3 +#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4 +#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5 +#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6 +#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7 +#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB + + +/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR3STR; +extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7); +#define CAN4RXDSR3 _CAN4RXDSR3.Byte +#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0 +#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1 +#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2 +#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3 +#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4 +#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5 +#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6 +#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7 +#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB + + +/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR4STR; +extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8); +#define CAN4RXDSR4 _CAN4RXDSR4.Byte +#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0 +#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1 +#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2 +#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3 +#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4 +#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5 +#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6 +#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7 +#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB + + +/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR5STR; +extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9); +#define CAN4RXDSR5 _CAN4RXDSR5.Byte +#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0 +#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1 +#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2 +#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3 +#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4 +#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5 +#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6 +#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7 +#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB + + +/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR6STR; +extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA); +#define CAN4RXDSR6 _CAN4RXDSR6.Byte +#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0 +#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1 +#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2 +#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3 +#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4 +#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5 +#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6 +#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7 +#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB + + +/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR7STR; +extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB); +#define CAN4RXDSR7 _CAN4RXDSR7.Byte +#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0 +#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1 +#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2 +#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3 +#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4 +#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5 +#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6 +#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7 +#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB + + +/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4RXDLRSTR; +extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC); +#define CAN4RXDLR _CAN4RXDLR.Byte +#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0 +#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1 +#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2 +#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3 +#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC + + +/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN4TXIDR0STR; +extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0); +#define CAN4TXIDR0 _CAN4TXIDR0.Byte +#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21 +#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22 +#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23 +#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24 +#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25 +#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26 +#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27 +#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28 +#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21 +#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21 + + +/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4TXIDR1STR; +extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1); +#define CAN4TXIDR1 _CAN4TXIDR1.Byte +#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15 +#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16 +#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17 +#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE +#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR +#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18 +#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19 +#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20 +#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15 +#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18 +#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15 + + +/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN4TXIDR2STR; +extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2); +#define CAN4TXIDR2 _CAN4TXIDR2.Byte +#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7 +#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8 +#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9 +#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10 +#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11 +#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12 +#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13 +#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14 +#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7 +#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7 + + +/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4TXIDR3STR; +extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3); +#define CAN4TXIDR3 _CAN4TXIDR3.Byte +#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR +#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0 +#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1 +#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2 +#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3 +#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4 +#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5 +#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6 +#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID + + +/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR0STR; +extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4); +#define CAN4TXDSR0 _CAN4TXDSR0.Byte +#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0 +#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1 +#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2 +#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3 +#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4 +#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5 +#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6 +#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7 +#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB + + +/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR1STR; +extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5); +#define CAN4TXDSR1 _CAN4TXDSR1.Byte +#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0 +#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1 +#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2 +#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3 +#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4 +#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5 +#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6 +#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7 +#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB + + +/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR2STR; +extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6); +#define CAN4TXDSR2 _CAN4TXDSR2.Byte +#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0 +#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1 +#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2 +#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3 +#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4 +#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5 +#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6 +#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7 +#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB + + +/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR3STR; +extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7); +#define CAN4TXDSR3 _CAN4TXDSR3.Byte +#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0 +#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1 +#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2 +#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3 +#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4 +#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5 +#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6 +#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7 +#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB + + +/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR4STR; +extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8); +#define CAN4TXDSR4 _CAN4TXDSR4.Byte +#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0 +#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1 +#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2 +#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3 +#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4 +#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5 +#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6 +#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7 +#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB + + +/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR5STR; +extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9); +#define CAN4TXDSR5 _CAN4TXDSR5.Byte +#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0 +#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1 +#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2 +#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3 +#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4 +#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5 +#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6 +#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7 +#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB + + +/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR6STR; +extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA); +#define CAN4TXDSR6 _CAN4TXDSR6.Byte +#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0 +#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1 +#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2 +#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3 +#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4 +#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5 +#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6 +#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7 +#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB + + +/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR7STR; +extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB); +#define CAN4TXDSR7 _CAN4TXDSR7.Byte +#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0 +#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1 +#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2 +#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3 +#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4 +#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5 +#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6 +#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7 +#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB + + +/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TXDLRSTR; +extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC); +#define CAN4TXDLR _CAN4TXDLR.Byte +#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0 +#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1 +#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2 +#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3 +#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC + + +/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN4TXTBPRSTR; +extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF); +#define CAN4TXTBPR _CAN4TXTBPR.Byte +#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0 +#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1 +#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2 +#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3 +#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4 +#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5 +#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6 +#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7 +#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO + + +/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte UNSEC :1; /* Unsecure */ + byte CLKSW :1; /* Clock switch */ + byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ + byte SDV :1; /* Shift data valid */ + byte ENTAG :1; /* Tagging enable */ + byte BDMACT :1; /* BDM active status */ + byte ENBDM :1; /* Enable BDM */ + } Bits; +} BDMSTSSTR; +extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); +#define BDMSTS _BDMSTS.Byte +#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC +#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW +#define BDMSTS_TRACE _BDMSTS.Bits.TRACE +#define BDMSTS_SDV _BDMSTS.Bits.SDV +#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG +#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT +#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM + + +/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ +typedef union { + byte Byte; + struct { + byte CCR0 :1; /* BDM CCR Holding Bit 0 */ + byte CCR1 :1; /* BDM CCR Holding Bit 1 */ + byte CCR2 :1; /* BDM CCR Holding Bit 2 */ + byte CCR3 :1; /* BDM CCR Holding Bit 3 */ + byte CCR4 :1; /* BDM CCR Holding Bit 4 */ + byte CCR5 :1; /* BDM CCR Holding Bit 5 */ + byte CCR6 :1; /* BDM CCR Holding Bit 6 */ + byte CCR7 :1; /* BDM CCR Holding Bit 7 */ + } Bits; + struct { + byte grpCCR :8; + } MergedBits; +} BDMCCRSTR; +extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); +#define BDMCCR _BDMCCR.Byte +#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 +#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 +#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 +#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 +#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 +#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 +#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 +#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 +#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR + + +/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position */ + byte REG12 :1; /* Internal register map position */ + byte REG13 :1; /* Internal register map position */ + byte REG14 :1; /* Internal register map position */ + byte REG15 :1; /* Internal register map position */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :5; + } MergedBits; +} BDMINRSTR; +extern volatile BDMINRSTR _BDMINR @(0x0000FF07); +#define BDMINR _BDMINR.Byte +#define BDMINR_REG11 _BDMINR.Bits.REG11 +#define BDMINR_REG12 _BDMINR.Bits.REG12 +#define BDMINR_REG13 _BDMINR.Bits.REG13 +#define BDMINR_REG14 _BDMINR.Bits.REG14 +#define BDMINR_REG15 _BDMINR.Bits.REG15 +#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 +#define BDMINR_REG BDMINR_REG_11 + + + /* Watchdog reset macro */ +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ +#endif + +#endif + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h b/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h new file mode 100644 index 000000000..a01bb9a21 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h @@ -0,0 +1,52 @@ +/* ================================================================================================================================= ** +** ================================================================================================================================= ** +** CONFIGURATION FILE FOR PESL LIBRARY ** +** ================================================================================================================================= ** +** ================================================================================================================================= */ + +#define _MC9S12A128_112 1 +#define _MC9S12A128_80 2 +#define _MC9S12A256_112 3 +#define _MC9S12A256_80 4 +#define _MC9S12A64_112 5 +#define _MC9S12A64_80 6 +#define _MC9S12C32_48 7 +#define _MC9S12C32_52 8 +#define _MC9S12C32_80 9 +#define _MC9S12D64_112 10 +#define _MC9S12D64_80 11 +#define _MC9S12DB128_112 12 +#define _MC9S12DG128_112 13 +#define _MC9S12DG128_80 14 +#define _MC9S12DG256_112 15 +#define _MC9S12DJ128_112 16 +#define _MC9S12DJ128_80 17 +#define _MC9S12DJ256_112 18 +#define _MC9S12DJ256_80 19 +#define _MC9S12DJ64_112 20 +#define _MC9S12DJ64_80 21 +#define _MC9S12DP256_112 22 +#define _MC9S12DT128_112 23 +#define _MC9S12DT256_112 24 +#define _MC9S12A32_80 25 +#define _MC9S12D32_80 26 +#define _MC9S12DP512_112 27 +#define _MC9S12A512_112 28 +#define _MC9S12E128_112 29 +#define _MC9S12E128_80 30 +#define _MC9S12E64_112 31 + + +/* Selected target MCU */ + +#define CPUtype _MC9S12DP256_112 + + +/* PESL library */ + +#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ +#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ + +#include "PESLlib.h" + + diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H new file mode 100644 index 000000000..c278f4a88 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H @@ -0,0 +1,50 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Const +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + +/* Constants for detecting running mode */ +#define HIGH_SPEED 0 /* High speed */ +#define LOW_SPEED 1 /* Low speed */ +#define SLOW_SPEED 2 /* Slow speed */ + +/* Reset cause constants */ +#define RSTSRC_POR 1 /* Power-on reset */ +#define RSTSRC_PIN 8 /* External reset bit */ +#define RSTSRC_COP 4 /* COP reset */ +#define RSTSRC_ILOP 2 /* Illegal opcode reset */ +#define RSTSRC_ILAD 16 /* Illegal address reset */ +#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ + +#endif /* _PE_Const_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H new file mode 100644 index 000000000..813974ecc --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Error +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Error" contains internal definitions +** of the error constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0 /* OK */ +#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2 /* Parameter out of range. */ +#define ERR_VALUE 3 /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4 /* Timer overflow. */ +#define ERR_MATH 5 /* Overflow during evaluation. */ +#define ERR_ENABLED 6 /* Device is enabled. */ +#define ERR_DISABLED 7 /* Device is disabled. */ +#define ERR_BUSY 8 /* Device is busy. */ +#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ +#define ERR_RXEMPTY 10 /* No data in receiver. */ +#define ERR_TXFULL 11 /* Transmitter is full. */ +#define ERR_BUSOFF 12 /* Bus not available. */ +#define ERR_OVERRUN 13 /* Overrun error is detected. */ +#define ERR_FRAMING 14 /* Framing error is detected. */ +#define ERR_PARITY 15 /* Parity error is detected. */ +#define ERR_NOISE 16 /* Noise error is detected. */ +#define ERR_IDLE 17 /* Idle error is detectes. */ +#define ERR_FAULT 18 /* Fault error is detected. */ +#define ERR_BREAK 19 /* Break char is received during communication. */ +#define ERR_CRC 20 /* CRC error is detected. */ +#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22 /* Protection error is detected. */ + +#endif __PE_Error_H diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C new file mode 100644 index 000000000..c94f087a6 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C @@ -0,0 +1,205 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE PE_Timer. */ + +#include "PE_Timer.h" + + + +typedef unsigned long UINT32; + +typedef union { + UINT32 val; + struct { + unsigned short hi16,lo16; + } s; +} OP_UINT32; + +typedef struct { + unsigned short dummy; + UINT32 mid; +} M_UINT32; + +typedef struct { + UINT32 hi32, lo32; +} UINT64; + +typedef union { + UINT64 val; + M_UINT32 m; +} OP_UINT64; + +/* +** =================================================================== +** Method : PE_Timer_LngMul (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_Timer_LngMul(dword va1, dword va2, dlong *var) +{ + OP_UINT32 *va = (OP_UINT32*)&va1; + OP_UINT32 *vb = (OP_UINT32*)&va2; + OP_UINT64 *vr = (OP_UINT64*)var; + + vr->val.hi32 = 0UL; + vr->val.lo32 = ((UINT32)va->s.lo16)*((UINT32)vb->s.lo16); + { + OP_UINT32 tmp; + + tmp.val = ((UINT32)va->s.lo16)*((UINT32)vb->s.hi16); + vr->m.mid += (UINT32)tmp.s.lo16; + vr->val.hi32 += (UINT32)tmp.s.hi16; + } + { + OP_UINT32 tmp; + + tmp.val = ((UINT32)va->s.hi16)*((UINT32)vb->s.lo16); + vr->m.mid += (UINT32)tmp.s.lo16; + vr->val.hi32 += (UINT32)tmp.s.hi16; + } + vr->val.hi32 += ((UINT32)va->s.hi16)*((UINT32)vb->s.hi16); +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi1(dword High, dword Low, word *Out) +{ + if ((High == 0) && ((Low >> 24) == 0)) + if ((Low & 0x80) != 0) { + if ((Low >> 8) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 8))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 8); + return FALSE; + } + *Out = (unsigned int)(Low >> 8); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi2 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi2(dword High, dword Low, word *Out) +{ + if (High == 0) + if ((Low & 0x8000) != 0) { + if ((Low >> 16) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 16))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 16); + return FALSE; + } + *Out = (unsigned int)(Low >> 16); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi3 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi3(dword High, dword Low, word *Out) +{ + if ((High >> 8) == 0) + if ((Low & 0x800000) != 0) { + if (((Low >> 24) | (High << 8)) < 0xFFFF) { + *Out = ((unsigned int)((Low >> 24) | (High << 8)))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)((Low >> 24) | (High << 8)); + return FALSE; + } + *Out = (unsigned int)((Low >> 24) | (High << 8)); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi4 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi4(dword High, dword Low, word *Out) +{ + if ((High >> 16) == 0) + if ((Low & 0x80000000) != 0) { + if (High < 0xFFFF) { + *Out = ((unsigned int)High)+1; + return FALSE; + } + } + else { + *Out = (unsigned int)High; + return FALSE; + } + *Out = (unsigned int)High; + return TRUE; +} + + + +/* END PE_Timer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H new file mode 100644 index 000000000..6ba554b94 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H @@ -0,0 +1,97 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +#ifndef __PE_Timer +#define __PE_Timer +/*Include shared modules, which are used for whole project*/ +#include "PE_types.h" +#include "PE_const.h" + +/* MODULE PE_Timer. */ + +void PE_Timer_LngMul(dword va1, dword va2, dlong *var); +/* +** =================================================================== +** Method : PE_Timer_LngMul (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi1(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi2(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi2 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi3(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi3 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi4(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi4 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#endif /* END PE_Timer. */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H new file mode 100644 index 000000000..196279ded --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H @@ -0,0 +1,87 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Types +** Version : Driver 01.04 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Types" contains internal definitions +** of the types. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +#define FALSE 0 +#define TRUE 1 + +/*Types definition*/ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; +typedef void (*tIntFunc)(void); + +/* Motorola types */ +typedef unsigned char VUINT8; +typedef signed char VINT8; +typedef unsigned short int VUINT16; +typedef signed short int VINT16; +typedef unsigned long int VUINT32; + +#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) +#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } + +#define output(P, V) P = (V) +#define input(P) (P) + +#define __DI() { asm sei; } /* Disable global interrupts */ +#define __EI() { asm cli; } /* Enable global interrupts */ +#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ +#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ +/* obsolete definition for backward compatibility */ +#define SaveStatusReg() EnterCritical() +#define RestoreStatusReg() ExitCritical() + + +typedef struct { /* Black&White Image */ + word width; /* Image width */ + word height; /* Image height */ + byte *pixmap; /* Image pixel bitmap */ + word size; /* Image size */ + char *name; /* Image name */ +} TIMAGE; +typedef TIMAGE* PIMAGE ; /* Pointer to image */ + +/* 16-bit register (Motorola format - big endian) */ +typedef union { + word w; + struct { + byte high,low; + } b; +} TWREG; + +#endif /* __PE_Types_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C new file mode 100644 index 000000000..9466aabd3 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C @@ -0,0 +1,67 @@ +/** ################################################################### +** Filename : RTOSDemo.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Version : Driver 01.05 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** Main module. +** Here is to be placed user's code. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE RTOSDemo */ + +/* Including used modules for compilling procedure */ +#include "Cpu.h" +#include "Events.h" +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +extern void vMain( void ); + +void main(void) +{ + /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ + PE_low_level_init(); + /*** End of Processor Expert internal initialization. ***/ + + /*Write your code here*/ + + /* Just jump to the real main(). */ + __asm + { + jmp vMain + } + + + /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ + for(;;); + /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ +} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ + +/* END RTOSDemo */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM new file mode 100644 index 000000000..3cc861ac5 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM @@ -0,0 +1,64 @@ +/* +** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : RTOSDemo.PRM +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:54 +** Abstract : +** This file is used by the linker. It describes files to be linked, +** memory ranges, stack size, etc. For detailed description of the PRM file +** see CodeWarrior documentation. This file is generated by default. +** You can switch off generation by setting the property +** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify +** this file if needed. +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ################################################################### +*/ + +NAMES + +END + +SECTIONS + /* List of all sections specified on the "Build options" tab */ + RAM = READ_WRITE 0x00001000 TO 0x00003FFF; + ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000C511; + ROM_4000 = READ_ONLY 0x00004000 TO 0x00004255; + ROM_PAGE30 = READ_ONLY 0x00308000 TO 0x00308255; + ROM_PAGE31 = READ_ONLY 0x00318000 TO 0x00318255; + ROM_PAGE32 = READ_ONLY 0x00328000 TO 0x00328255; + ROM_PAGE33 = READ_ONLY 0x00338000 TO 0x00338255; + ROM_PAGE34 = READ_ONLY 0x00348000 TO 0x00348255; + ROM_PAGE35 = READ_ONLY 0x00358000 TO 0x00358255; + ROM_PAGE36 = READ_ONLY 0x00368000 TO 0x00368255; + ROM_PAGE37 = READ_ONLY 0x00378000 TO 0x00378255; + ROM_PAGE38 = READ_ONLY 0x00388000 TO 0x00388255; + ROM_PAGE39 = READ_ONLY 0x00398000 TO 0x00398255; + ROM_PAGE3A = READ_ONLY 0x003A8000 TO 0x003A8255; + ROM_PAGE3B = READ_ONLY 0x003B8000 TO 0x003B8255; + ROM_PAGE3C = READ_ONLY 0x003C8000 TO 0x003C8255; + ROM_PAGE3D = READ_ONLY 0x003D8000 TO 0x003D8255; +END + +PLACEMENT + DEFAULT_RAM INTO RAM; + DEFAULT_ROM INTO ROM_PAGE30, ROM_PAGE31, ROM_PAGE32, ROM_PAGE33, ROM_PAGE34, ROM_PAGE35, ROM_PAGE36, +ROM_PAGE37, ROM_PAGE38, ROM_PAGE39, ROM_PAGE3A, ROM_PAGE3B, ROM_PAGE3C, ROM_PAGE3D; + _PRESTART, STARTUP, + ROM_VAR, STRINGS, + NON_BANKED, COPY INTO ROM_C000, ROM_4000; +END + +INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ + +STACKSIZE 0x0080 /* Size of the system stack. Value can be changed on the "Build options" tab */ + diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C new file mode 100644 index 000000000..5e735073e --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C @@ -0,0 +1,393 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : ECT (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-8 +** Clock : 3124000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 320000 ticks +** microseconds : 1000 to 20000 microseconds +** milliseconds : 1 to 20 milliseconds +** seconds (real) : 0.0010000 to 0.0200000 seconds +** Hz : 50 to 1000 Hz +** +** Initialization: +** Timer : Enabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); +** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); +** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); +** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE TickTimer. */ + +#include "Events.h" +#include "TickTimer.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +static word CmpHighVal; /* Compare register value for high speed CPU mode */ + + +/* +** =================================================================== +** Method : SetCV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetCV(word Val) +{ + if (Val == 0) /* If the given value is zero */ + Val = 65535; /* then change it to the maximal one */ + TC0 = Val; /* Store given value to the compare register */ + TC7 = Val; /* Store given value to the modulo register */ +} + +/* +** =================================================================== +** Method : SetPV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetPV(byte Val) +{ + TSCR2_PR = Val; /* Store given value to the prescaler */ +} + +/* +** =================================================================== +** Method : HWEnDi (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + TIE_C0I = 1; /* Enable interrupt */ +} + +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte TickTimer_Enable(void) +{ + HWEnDi(); /* Enable the device */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 16-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 65535 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodTicks16(word Ticks) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if (Ticks < 16000) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 32-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 320000 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodTicks32(dword Ticks) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Ticks > 320000) || (Ticks < 16000)) /* Is the given value out of range? */ + return ERR_RANGE; /* Range error */ + PE_Timer_LngMul(Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodUS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in microseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in microseconds] +** (1000 to 20000 microseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodUS(word Time) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Time > 20000) || (Time < 1000)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Time,52412023,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi3(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodMS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in miliseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in miliseconds] +** (1 to 20 milliseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodMS(word Time) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Time > 20) || (Time < 1)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Time,204734464,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi2(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (50 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetFreqHz(word Freq) +{ + dlong rtval; /* Result of two 32-bit numbers division */ + word rtword; /* Result of 64-bit number division */ + + if ((Freq > 1000) || (Freq < 50)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + rtval[1] = 799744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ + rtval[0] = 0; /* Convert result to the type dlong */ + if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void TickTimer_Init(void) +{ + CmpHighVal = 3124; /* Compare register value for high speed CPU mode */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + SetPV(3); /* Set prescaler register according to the selected high speed CPU mode */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + TickTimer_OnInterrupt(); /* Invoke user event */ +} + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +/* END TickTimer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H new file mode 100644 index 000000000..8ddab4b3b --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H @@ -0,0 +1,276 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : ECT (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-8 +** Clock : 3124000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 320000 ticks +** microseconds : 1000 to 20000 microseconds +** milliseconds : 1 to 20 milliseconds +** seconds (real) : 0.0010000 to 0.0200000 seconds +** Hz : 50 to 1000 Hz +** +** Initialization: +** Timer : Enabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); +** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); +** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); +** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __TickTimer +#define __TickTimer + +/* MODULE TickTimer. */ + +#include "Cpu.h" + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +#define TickTimer_SPT16Min 16000 /* Lower bound of interval for method SetPeriodTicks16 */ +#define TickTimer_SPT16Max 65535 /* Upper bound of interval for method SetPeriodTicks16 */ +#define TickTimer_SPT32Min 16000 /* Lower bound of interval for method SetPeriodTicks32 */ +#define TickTimer_SPT32Max 320000 /* Upper bound of interval for method SetPeriodTicks32 */ +#define TickTimer_SPUSMin 1000 /* Lower bound of interval for method SetPeriodUS */ +#define TickTimer_SPUSMax 20000 /* Upper bound of interval for method SetPeriodUS */ +#define TickTimer_SPMSMin 1 /* Lower bound of interval for method SetPeriodMS */ +#define TickTimer_SPMSMax 20 /* Upper bound of interval for method SetPeriodMS */ +#define TickTimer_SFHzMin 50 /* Lower bound of interval for method SetFreqHz */ +#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ + + +byte TickTimer_Enable(void); +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +byte TickTimer_SetPeriodTicks16(word Ticks); +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 16-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 65535 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodTicks32(dword Ticks); +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 32-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 320000 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodUS(word Time); +/* +** =================================================================== +** Method : TickTimer_SetPeriodUS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in microseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in microseconds] +** (1000 to 20000 microseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodMS(word Time); +/* +** =================================================================== +** Method : TickTimer_SetPeriodMS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in miliseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in miliseconds] +** (1 to 20 milliseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetFreqHz(word Freq); +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (50 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void); +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +void TickTimer_Init(void); +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END TickTimer. */ + +#endif /* ifndef __TickTimer */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c b/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c new file mode 100644 index 000000000..633348f90 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c @@ -0,0 +1,112 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 19:18 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "TickTimer.h" +#include "Byte1.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vCOM0_ISR( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + Cpu_Interrupt, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + vCOM0_ISR, /* Defined in Demo/serial/serial.c */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, /* The RTOS tick. */ + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* RTOS yield software interrupt. */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl b/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl new file mode 100644 index 000000000..3b16d98a4 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig new file mode 100644 index 000000000..8aea029d4 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig @@ -0,0 +1,23 @@ +================================================================= +This file was generated from Processor Expert 03.33 + project "RTOSDemo", 19/06/2005, 15:54 +----------------------------------------------------------------- +There is no signal defined in this project. + Hint: Signals may be defined in the Bean Inspector (advanced or expert view) +================================================================= + +================================================================= + SIGNAL LIST +----------------------------------------------------------------- + SIGNAL NAME => PIN NAME +----------------------------------------------------------------- +================================================================= + + +================================================================= + PIN LIST +----------------------------------------------------------------- + PIN NAME => SIGNAL NAME +----------------------------------------------------------------- +================================================================= + diff --git a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt new file mode 100644 index 000000000..479e92c6c --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt @@ -0,0 +1,43 @@ +============================================================================= +List of methods in project: RTOSDemo + +THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +============================================================================= + +Module "TickTimer" (bean TimerInt) + TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). + TickTimer_SetPeriodTicks16 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] + as a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodTicks32 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] + as a 32-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodUS -This method sets the new period of the generated events. The period is expressed in [microseconds] as + a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodMS -This method sets the new period of the generated events. The period is expressed in [miliseconds] as + a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a + 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + +Module "Byte1" (bean ByteIO) + Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the + value to a memory or a register, this value will be written to the pin after switching to the output mode - + using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. + Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. + +Module "COM0" (bean AsynchroSerial) + COM0_SetBaudRateMode -This method changes the channel communication speed (baud rate). This method can be used only if you + specify a list of possible period settings at design time (see - Runtime setting - from a + list of values). Each of these settings constitutes a mode and Processor Expert^[TM] assigns them a mode + identifier. The prescaler and compare values corresponding to each mode are calculated at design time. You may + switch modes at runtime by referring only to a mode identifier. No run-time calculations are performed, all the + calculations are performed at design time. + +Module "Cpu" (bean MC9S12DP256_112) + Cpu_EnableInt -Enable maskable interrupts + Cpu_DisableInt -Disable maskable interrupts + +============================================================================= diff --git a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h new file mode 100644 index 000000000..d1449e3f5 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h @@ -0,0 +1,92 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include /* common defines and macros */ +#include "TickTimer.h" + +/* This port requires the compiler to generate code for the BANKED memory +model. */ +#define BANKED_MODEL + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10240 ) ) +#define configMAX_TASK_NAME_LEN ( 1 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This parameter is normally required in order to set the RTOS tick timer. +This port is a bit different in that hardware setup uses the code generated by +the Processor Expert, making this definition obsolete. + +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) +*/ + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini b/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini new file mode 100644 index 000000000..628984302 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini @@ -0,0 +1,71 @@ +[Environment Variables] +GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib +LIBPATH={Compiler}lib\HC12c\include +OBJPATH={Project}bin +TEXTPATH={Project}bin +ABSPATH={Project}bin + +[HI-WAVE] +Target=icd12 +Layout=C_layout.hwl +LoadDialogOptions=AUTOERASEANDFLASH +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,54,54,1254,908 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 +AEFWarningDialog=FALSE + +[ICD12] +CMDFILE0=CMDFILE STARTUP ON ".\cmd\p&e_icd_startup.cmd" +CMDFILE1=CMDFILE RESET ON ".\cmd\p&e_icd_reset.cmd" +CMDFILE2=CMDFILE PRELOAD ON ".\cmd\p&e_icd_preload.cmd" +CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\p&e_icd_postload.cmd" +CMDFILE4=CMDFILE VPPON ON ".\cmd\p&e_icd_vppon.cmd" +CMDFILE5=CMDFILE VPPOFF ON ".\cmd\p&e_icd_vppoff.cmd" +CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_ICD_erase_unsecure_hcs12.cmd" +MCUID=0x3C6 +CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2 +BDMClockSpeed=14 +BNKA_MCUID03C6_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 16 0x30 +BNKA_MCUID03C6_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0 +BNKA_MCUID03C6_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0 +HWBPD_MCUID03C6_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF +HWBPD_MCUID03C6_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E +HWBPD_MCUID03C6_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F +HWBPD_MCUID03C6_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0 +HWBPD_MCUID03C6_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0 +BDMAutoSpeed=0 +COMDEVICE=SETCOMM COMPORT USB "USB-PE5014402" +SETCLKSW=1 +DETECTRUNNING=0 +ISRDISABLEDSTEP=0 +SHOWPROT=1 +NV_PARAMETER_FILE=C:\devtools\Metrowerks\CodeWarrior CW12_V3.1\prog\FPP\mcu03C6.fpp +NV_SAVE_WSP=0 +NV_AUTO_ID=1 +DMM_MCUID03C6_MODULE0=Registers 0x0 0x400 1 4 0 2 1 1 +DMM_MCUID03C6_MODULE1=Ram 0x1000 0x3000 2 5 0 3 1 1 +DMM_MCUID03C6_MODULE2=Eeprom 0x0 0x1000 3 5 1 4 1 1 +DMM_MCUID03C6_MODULE3=Banked£memory 0x8000 0x2f4000 100 6 0 6 1 0 +DMM_MCUID03C6_MODULE4=Banked£flash 0x308000 0xf4000 101 6 1 5 1 0 +DMM_MCUID03C6_MODULE5=Unbanked£flash£4000 0x4000 0x4000 102 5 1 5 1 1 +DMM_MCUID03C6_MODULE6=Unbanked£flash£C000 0xc000 0x4000 103 5 1 5 1 1 +HOTPLUGGING=0 +REALTIMEHWBP=0 +NOREADWHILERUNNING=0 +RESYNCONCOPRESET=0 + +[Recent Applications File List] +File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs +File2=E:\Dev\FreeRTOS\Demo\MC9S12DP256_CodeWarrior\bin\P&E_ICD.abs +File3= +File4= +LoadFlags1=4099 +LoadFlags2=4099 +LoadFlags3=0 +LoadFlags4=0 + +[Recent Layout File List] +File1=C_layout.hwl +File2= +File3= +File4= diff --git a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c new file mode 100644 index 000000000..18bf12e1d --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c @@ -0,0 +1,69 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Processor Expert created headers. */ +#include "byte1.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the Processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_PutBit( uxLED, !xValue ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_NegBit( uxLED ); + portEXIT_CRITICAL(); +} + + + diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C new file mode 100644 index 000000000..7840d35f7 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C @@ -0,0 +1,500 @@ +;Please do not modify this file! +;The file contains internal information about the Processor Expert project generation +[Options] +ProjectName=RTOSDemo +ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\ +DestEventsDirectory=CODE\ +DestDriversSubDirectory= +DestDocumentationDirectory=DOC\ +DestCompiledFilesSubDirectory= +DestFpgaSubDirectory= +DestTemporaryDirectory= +[GenFiles] +LinkerFileGenerated=Yes +MakefileGenerated=No +GenSharedModules=5 +Line=PE_Types +Line=PE_Error +Line=PE_Const +Line=IO_Map +Line=PE_Timer +ShrdHeaderAge0=852337107 +ShrdCodeAge0=-1 +ShrdAsemblAge0=-1 +ShrdHeaderAge1=852337107 +ShrdCodeAge1=-1 +ShrdAsemblAge1=-1 +ShrdHeaderAge2=852337107 +ShrdCodeAge2=-1 +ShrdAsemblAge2=-1 +ShrdHeaderAge3=852337107 +ShrdCodeAge3=852337107 +ShrdAsemblAge3=-1 +ShrdHeaderAge4=852395090 +ShrdCodeAge4=852395090 +ShrdAsemblAge4=-1 +GenExtraFiles=2 +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\Vectors.c +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\PESL.h +XtraAge0=852534276 +XtraAge1=852337108 +GenExtraFileType1=4 +GenExtraFileType0=4 +GenEventModules=1 +Line=Events +GenMethodsInEvents=0 +GenAllModules=10 +Line=Byte1 +Line=COM0 +Line=Cpu +Line=Events +Line=IO_Map +Line=PE_Const +Line=PE_Error +Line=PE_Timer +Line=PE_Types +Line=TickTimer +GenExternModules=0 +GenBeanModules=3 +Line=COM0 +Line=Byte1 +Line=TickTimer +SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\DOC\RTOSDemo.sig +DestinationCompiler=MetrowerksHC12CC +ProjectModificationStamp=28 + +[4] +Generated=Yes +GenCompName=Cpu +GenEventModule=Events +HeaderAge=852395091 +CodeAge=852656823 +AsemblAge=-1 +GenNumMethods=10 +SetStopMode=No +SetWaitMode=No +DisableInt=Yes +EnableInt=Yes +GetIntVect=No +SetIntVect=No +GetSpeedMode=No +SetSlowSpeed=No +SetLowSpeed=No +SetHighSpeed=No +GenNumEvents=4 +OnClockMonitorFail_Selected=1 +OnClockMonitorFail_Name=Cpu_OnClockMonitorFail +OnClockMonitorFail_Priority=interrupts disabled +OnIllegalOpcode_Selected=1 +OnIllegalOpcode_Name=Cpu_OnIllegalOpcode +OnIllegalOpcode_Priority=interrupts disabled +OnReset_Selected=1 +OnReset_Name=Cpu_OnReset +OnReset_Priority=interrupts disabled +OnSwINT_Selected=1 +OnSwINT_Name=Cpu_OnSwINT +OnSwINT_Priority=interrupts disabled +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No + +[6] +Generated=Yes +GenCompName=TickTimer +GenEventModule=Events +HeaderAge=852656822 +CodeAge=852656822 +AsemblAge=-1 +GenNumMethods=14 +SetFreqMHz=No +SetFreqkHz=No +SetFreqHz=Yes +SetPeriodReal=No +SetPeriodSec=No +SetPeriodMS=Yes +SetPeriodUS=Yes +SetPeriodTicks32=Yes +SetPeriodTicks16=Yes +SetPeriodMode=No +DisableEvent=No +EnableEvent=No +Disable=No +Enable=Yes +GenNumEvents=3 +BeforeNewSpeed_Selected=1 +BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed +BeforeNewSpeed_Priority=interrupts disabled +AfterNewSpeed_Selected=1 +AfterNewSpeed_Name=TickTimer_AfterNewSpeed +AfterNewSpeed_Priority=interrupts disabled +OnInterrupt_Selected=2 +OnInterrupt_Name=TickTimer_OnInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=19 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=92 +LineEnd=108 +MethodPos1=SetPeriodTicks16 +MethodType=method +ModuleType=Header +LineBeg=109 +LineEnd=134 +MethodPos2=SetPeriodTicks32 +MethodType=method +ModuleType=Header +LineBeg=135 +LineEnd=160 +MethodPos3=SetPeriodUS +MethodType=method +ModuleType=Header +LineBeg=161 +LineEnd=186 +MethodPos4=SetPeriodMS +MethodType=method +ModuleType=Header +LineBeg=187 +LineEnd=212 +MethodPos5=SetFreqHz +MethodType=method +ModuleType=Header +LineBeg=213 +LineEnd=238 +MethodPos6=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=239 +LineEnd=251 +MethodPos7=Init +MethodType=internal_method +ModuleType=Header +LineBeg=252 +LineEnd=262 +MethodPos8=SetCV +MethodType=internal_method +ModuleType=Code +LineBeg=85 +LineEnd=101 +MethodPos9=SetPV +MethodType=internal_method +ModuleType=Code +LineBeg=102 +LineEnd=115 +MethodPos10=HWEnDi +MethodType=internal_method +ModuleType=Code +LineBeg=116 +LineEnd=130 +MethodPos11=Enable +MethodType=method +ModuleType=Code +LineBeg=131 +LineEnd=151 +MethodPos12=SetPeriodTicks16 +MethodType=method +ModuleType=Code +LineBeg=152 +LineEnd=190 +MethodPos13=SetPeriodTicks32 +MethodType=method +ModuleType=Code +LineBeg=191 +LineEnd=229 +MethodPos14=SetPeriodUS +MethodType=method +ModuleType=Code +LineBeg=230 +LineEnd=268 +MethodPos15=SetPeriodMS +MethodType=method +ModuleType=Code +LineBeg=269 +LineEnd=307 +MethodPos16=SetFreqHz +MethodType=method +ModuleType=Code +LineBeg=308 +LineEnd=347 +MethodPos17=Init +MethodType=internal_method +ModuleType=Code +LineBeg=348 +LineEnd=364 +MethodPos18=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=365 +LineEnd=381 + +[7] +Generated=Yes +GenCompName=Byte1 +GenEventModule=Events +HeaderAge=852535625 +CodeAge=852535625 +AsemblAge=-1 +GenNumMethods=9 +NegBit=Yes +ClrBit=No +SetBit=No +PutBit=Yes +GetBit=No +PutVal=No +GetVal=No +SetDir=No +GetDir=No +GenNumEvents=0 +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=5 +MethodPos0=PutBit +MethodType=method +ModuleType=Header +LineBeg=66 +LineEnd=82 +MethodPos1=NegBit +MethodType=method +ModuleType=Header +LineBeg=83 +LineEnd=97 +MethodPos2=GetMsk +MethodType=internal_method +ModuleType=Code +LineBeg=68 +LineEnd=83 +MethodPos3=PutBit +MethodType=method +ModuleType=Code +LineBeg=84 +LineEnd=111 +MethodPos4=NegBit +MethodType=method +ModuleType=Code +LineBeg=112 +LineEnd=133 + +[8] +Generated=Yes +GenCompName=COM0 +GenEventModule=Events +HeaderAge=852719863 +CodeAge=852719863 +AsemblAge=-1 +GenNumMethods=29 +SetDirection=No +Standby=No +LoopMode=No +SetIdle=No +TurnRxOff=No +TurnRxOn=No +SetTxBaudGenerator=No +SetRxBaudGenerator=No +TurnTxOff=No +TurnTxOn=No +SetAttentionMode=No +SetBreak=No +GetBreak=No +GetError=No +SetBaudRateMode=Yes +GetCharsInTxBuf=No +CharsInTxBuf=No +GetCharsInRxBuf=No +CharsInRxBuf=No +ClearTxBuf=No +ClearRxBuf=No +SendBlock=No +RecvBlock=No +SendChar=No +RecvChar=No +DisableEvent=No +EnableEvent=No +Disable=No +Enable=No +GenNumEvents=9 +BeforeNewSpeed_Selected=1 +BeforeNewSpeed_Name=COM0_BeforeNewSpeed +BeforeNewSpeed_Priority=interrupts disabled +AfterNewSpeed_Selected=1 +AfterNewSpeed_Name=COM0_AfterNewSpeed +AfterNewSpeed_Priority=interrupts disabled +OnError_Selected=1 +OnError_Name=COM0_OnError +OnError_Priority=same as interrupt +OnRxChar_Selected=1 +OnRxChar_Name=COM0_OnRxChar +OnRxChar_Priority=same as interrupt +OnTxChar_Selected=1 +OnTxChar_Name=COM0_OnTxChar +OnTxChar_Priority=same as interrupt +OnFullRxBuf_Selected=0 +OnFullRxBuf_Name=COM0_OnFullRxBuf +OnFullRxBuf_Priority=same as interrupt +OnFreeTxBuf_Selected=0 +OnFreeTxBuf_Name=COM0_OnFreeTxBuf +OnFreeTxBuf_Priority=same as interrupt +OnBreak_Selected=0 +OnBreak_Name=COM0_OnBreak +OnBreak_Priority=same as interrupt +OnIdle_Selected=1 +OnIdle_Name=COM0_OnIdle +OnIdle_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=11 +MethodPos0=SetBaudRateMode +MethodType=method +ModuleType=Header +LineBeg=123 +LineEnd=150 +MethodPos1=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=151 +LineEnd=163 +MethodPos2=InterruptCs +MethodType=internal_method +ModuleType=Header +LineBeg=164 +LineEnd=164 +MethodPos3=Init +MethodType=internal_method +ModuleType=Header +LineBeg=165 +LineEnd=175 +MethodPos4=HWEnDi +MethodType=internal_method +ModuleType=Code +LineBeg=115 +LineEnd=130 +MethodPos5=InterruptRx +MethodType=internal_method +ModuleType=Code +LineBeg=131 +LineEnd=157 +MethodPos6=InterruptTx +MethodType=internal_method +ModuleType=Code +LineBeg=158 +LineEnd=175 +MethodPos7=InterruptError +MethodType=internal_method +ModuleType=Code +LineBeg=176 +LineEnd=200 +MethodPos8=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=201 +LineEnd=221 +MethodPos9=SetBaudRateMode +MethodType=method +ModuleType=Code +LineBeg=222 +LineEnd=259 +MethodPos10=Init +MethodType=internal_method +ModuleType=Code +LineBeg=260 +LineEnd=284 + +[UsedSrcFiles] +SrcFile=Drivers\TimerInt.src=779379233 +SrcFile=Drivers\HCS12\TimerInt.drv=790330280 +SrcFile=Drivers\Common\Header.h=788035759 +SrcFile=Drivers\Common\TimerIntAbstract.Inc=697533454 +SrcFile=Drivers\Common\TimerIntSettings.Inc=662077596 +SrcFile=Drivers\HCS12\CreateCodeSection.prg=759717537 +SrcFile=Drivers\Common\TimerIntEnable.Inc=724722488 +SrcFile=Drivers\Common\GeneralMethod.inc=711812818 +SrcFile=Drivers\Common\GeneralParametersNone.inc=711813294 +SrcFile=Drivers\Common\GeneralDamage.inc=711813453 +SrcFile=Drivers\Common\TimerIntSetPeriodTicks16.Inc=724921621 +SrcFile=Drivers\Common\GeneralParameters.inc=711813750 +SrcFile=Drivers\Common\TimerIntSetPeriodTicks32.Inc=724921601 +SrcFile=Drivers\Common\TimerIntSetPeriodUS.Inc=724921676 +SrcFile=Drivers\Common\TimerIntSetPeriodMS.Inc=724921329 +SrcFile=Drivers\Common\TimerIntSetFreqHz.Inc=724921137 +SrcFile=Drivers\HCS12\CreateIntSection.prg=760697835 +SrcFile=Drivers\Common\TimerIntInterrupt.Inc=662077583 +SrcFile=Drivers\Common\GeneralInternal.inc=724263004 +SrcFile=Drivers\Common\Header.End=710308512 +SrcFile=Drivers\Common\TimerIntOnInterrupt.Inc=724722488 +SrcFile=Drivers\Common\GeneralEvent.inc=711816218 +SrcFile=Drivers\Common\GeneralReturnNothing.inc=711816104 +SrcFile=Drivers\Common\Header.C=788035759 +SrcFile=Drivers\HCS12\CreateDataSection.prg=759780817 +SrcFile=Drivers\Common\GeneralInternalGlobal.Inc=724263104 +SrcFile=Drivers\Common\InitReg8.prg=727217490 +SrcFile=Drivers\Common\InitReg8Enable.prg=783766675 +SrcFile=Drivers\ByteIO.src=779379247 +SrcFile=Drivers\HCS12\ByteIO.drv=786325143 +SrcFile=Drivers\Common\ByteIOAbstract.Inc=697533609 +SrcFile=Drivers\Common\ByteIOSettings.Inc=662077581 +SrcFile=Drivers\Common\UsedPins.inc=662077580 +SrcFile=Drivers\Common\ByteIOPutBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralPutBit.inc=724263173 +SrcFile=Drivers\Common\ByteIONegBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralNegBit.inc=724263119 +SrcFile=Drivers\AsynchroSerial.src=779379258 +SrcFile=Drivers\HCS12\AsynchroSerial.drv=790261986 +SrcFile=Drivers\Common\AsynchroSerialAbstract.Inc=697534037 +SrcFile=Drivers\Common\AsynchroSerialSettings.Inc=696025229 +SrcFile=Drivers\Common\UsedAsynchroPins.inc=730763605 +SrcFile=Drivers\Common\UsedBaudModes.inc=662077584 +SrcFile=Drivers\Common\AsynchroSerialSetBaudRateMode.Inc=777215290 +SrcFile=Drivers\Common\DataHeader.Inc=662077594 +SrcFile=Drivers\Common\DataHeader.End=662077594 +SrcFile=Drivers\Common\GenReg8InitInfo.prg=754344225 +SrcFile=Drivers\Common\GenReg8BitsInitInfo.prg=777356856 +SrcFile=Drivers\HCS12\PE_Types.drv=790261986 +SrcFile=Drivers\Common\PE_TypesAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_TypesSettings.Inc=662077595 +SrcFile=Drivers\HCS12\PE_Error.drv=744839008 +SrcFile=Drivers\Common\PE_ErrorAbstract.Inc=662077580 +SrcFile=Drivers\Common\ErrorDefinitions.Inc=781282486 +SrcFile=Drivers\HCS12\PE_Const.drv=744839020 +SrcFile=Drivers\Common\PE_ConstAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_ConstSettings.Inc=662077595 +SrcFile=Drivers\HCS12\IO_Map.drv=790392555 +SrcFile=Drivers\Common\IO_MapAbstract.Inc=662077601 +SrcFile=Drivers\Common\IO_MapSettings.Inc=662077601 +SrcFile=Drivers\HCS12\MC9S12DP256_112h.prg=788297414 +SrcFile=Drivers\HCS12\MC9S12DP256_112c.prg=787841633 +SrcFile=Drivers\HCS12\PE_Timer.drv=764054261 +SrcFile=Drivers\Common\PE_TimerConstants.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerMethods.Inc=662077585 +SrcFile=Drivers\Common\PE_TimerAbstract.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerSettings.Inc=662077581 +SrcFile=Drivers\Common\PE_TimerLngMul.Inc=662077581 +SrcFile=Drivers\Common\PE_TimerLngHi1.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerLngHi2.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerLngHi3.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerLngHi4.Inc=662077594 +SrcFile=Drivers\MC9S12DP256_112.src=746163715 +SrcFile=Drivers\HCS12\MC9S12.drv=788297552 +SrcFile=Drivers\Common\MC9S12Abstract.Inc=786070990 +SrcFile=Drivers\Common\MC9S12Settings.Inc=786070990 +SrcFile=Drivers\Common\MC9S12DisableInt.Inc=786070990 +SrcFile=Drivers\Common\MC9S12EnableInt.Inc=786070990 +SrcFile=Drivers\Common\CommonInitialization.prg=760832797 +SrcFile=Drivers\Common\CommonRegInitialization.prg=785882407 +SrcFile=Drivers\Common\SetRegBits8.prg=775453568 +SrcFile=Drivers\Common\SetReg8.prg=776374479 +SrcFile=Drivers\Common\CommonEnabling.prg=783766630 +SrcFile=Drivers\Common\CommonRegEnabling.prg=785882407 +SrcFile=Drivers\HCS12\PESL.prg=790397020 +SrcFile=Drivers\Event.src=779379228 +SrcFile=Drivers\HCS12\Evnt.drv=763978411 +SrcFile=Drivers\Common\EvntAbstract.Inc=662077596 +SrcFile=Drivers\Common\EvntSettings.inc=662077580 +SrcFile=Drivers\Common\Header.In1=710699431 +SrcFile=Drivers\_PE_ProjectInfo.src=713322570 +SrcFile=Drivers\SW\_PE_ProjectInfo.drv=726426382 + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk new file mode 100644 index 000000000..23b1cd45e --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk @@ -0,0 +1,166 @@ +[Version] +PE_DesktopFileVersion=819 + +[Desktop] +StartupPrj=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\RTOSDemo.pe + +[PE_IDE_PlugIn] + +[CpuExpert] + +[AppPanel] +AllFocusedNode=Cpu:MC9S12DP256BCPV +ConfigurationsInAllExpanded=No +CPUsInAllExpanded=Yes +FPGAsInAllExpanded=No +OperatingSystemInAllExpanded=Yes +BeansInAllExpanded=Yes +TasksInAllExpanded=No +ProgramsInAllExpanded=No +DocumentationInAllExpanded=No +PESLInAllExpanded=No +PESL_moduleInAllExpanded=No +ViewEnabledItemsOnly=No + +[CpuPanel] +Status=hiden +WindowState=NORMAL +Rect=[0|90|593|532] +CpuPanViewMode=Default + +[ErrorPanel] +Status=Visible +WindowState=NORMAL +Rect=[593|976|593|178] + +[ResourceMeter] +Status=hiden +WindowState=NORMAL +Rect=[593|976|593|178] + +[BeanSelector] +Status=Visible +WindowState=NORMAL +Rect=[-4|62|1608|1130] +BF_ForTgtCpuOnly=Yes +BF_LicensedOnly=Yes + +[ObjInspector] +Status=Visible +WindowState=MAXIMAL +Rect=[-4|62|1199|1100] +ColWidth01=263 +ColWidth02=479 +ColWidth11=188 +ColWidth12=317 +ColWidth21=180 +ColWidth22=352 +ColWidth31=255 +ColWidth32=479 +ColWidth41=133 +ColWidth42=266 +ViewItemLevel=2 + +[PrphInspector] +Status=hiden +WindowState=NORMAL +Rect=[-466|400|516|411] +ViewMode=PrphUsageReport +SortRegsByAddr=Yes +GroupRegisters=No +Peripheral= + +[Editor] +Rect=[-4|0|1199|1100] +FontName=Courier New +FontSize=10 +FontBold=No +FontItalic=No +FontScript=1 +ToolBar=Yes +ToolBarPosition=top +SyntaxHighlighting=Yes +NoHorizScrollBar=Yes +ShowLineNumbers=No +PreserveCurPosDuringPaste=No +UseTabChar=No +ModulesInOneWindow=Yes +TabSize=8 +HintDelay=2 +OpenFilesCount=0 +SelFile= +SelLine=-1 +FileHistory=0 + +[CpuStructure] +Rect=[0|0|0|0] + +[StrListEditor] +WindowWidth=450 +WindowHeight=333 + +[Breakpoints] +WindowVisible=No +Rect=[0|0|0|0] +BreakLine1=0 +BreakModule1= + +[Watches] +Rect=[0|0|0|0] +WindowVisible=No +WatchCount=0 +WatchHistoryCount=0 + +[Registers] +Rect=[0|0|100|500] +WindowVisible=No + +[Dump] +WindowVisible=No +Rect=[0|0|0|0] +Address=0 +DataSize=1 +DataType=num +HistoryAddrCount=0 + +[InterruptVectors] +WindowVisible=No +Rect=[0|0|0|0] + +[MemoryMap] +Rect=[422|156|355|480] +DisplayOnlyMemories=No +WindowVisible=No + +[Browser] +Rect=[0|0|0|0] +WindowVisible=No + +[BeanManager] +Rect=[0|0|0|0] +BeanInfoFilter= +DriverFilter= +DriverInfoFilter= +BeanSettingsProjectFilter= + +[Options] +AutosaveWithProject=No +AutosaveBeforeTool=No +NumberOfBackupCopies=0 +AutoSaveDesktop=Yes +AutoOpenPropEdit=Yes +AutoConnectDevice=Yes +SelectTemplate=No +ShowGenProgress=Yes +AutoShowGeneratedSrc=No +AutoShowEventModules=No +ShowMethodCode=No +GenerateUndo=No +CpuBitmapFileName=Config\PE\CPUbckgr.bmp +CpuBitmapTilled=No +ShowProducerLogo=No +AutoStartApplicationCode=No +ShowSourceLinAfterDbgInit=No +RestoreFilesAfterDebug=No + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.mcp b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.mcp new file mode 100644 index 000000000..dc22dc46c Binary files /dev/null and b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.mcp differ diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.pe b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.pe new file mode 100644 index 000000000..f615a497b --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.pe @@ -0,0 +1,4154 @@ +Processor Expert Version 0333 +ProjectModificationStamp=28 + +[Options] +EventsDirectory=CODE\ +DestinationSubDir= +DocumentationDir=DOC\ +CompiledFilesSubDir= +FPGAsubdirectory= +TemporaryDir=%TEMP% +OverwriteEvents=3 +OverwriteBeanDrv=0 +UseExistingModules=Yes +RenamePeripheries=Yes +Autodependency=Yes +ProjectCompNumb=10 +DelUnusedPreviouslyGenFiles=Yes + +[MC9S12DP256_112:Cpu] +CompNumb=4 +CompEnabled=Yes +GenCodeMode=CHECK_n_WRITE +IconName=CPU_CHIP2 +Comment=0 +Template= + +[Properties] +List=Property +[ItemState] +ItemSymbol=DeviceName +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=Cpu +[ItemState] +ItemSymbol=CPU +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=MC9S12DP256BCPV +[ItemState] +ItemSymbol=Xtal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=16 +[ItemState] +ItemSymbol=InitPriority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=interrupts disabled +[ItemState] +ItemSymbol=PLLStopsInWait +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=HC12_ChipSelects +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=MemMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +[ItemState] +ItemSymbol=HC12_INTFLASHON +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HalfFlashEn +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=ExtBusGrp +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ExtBusStretch +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=3 + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=HC12_InternalMapping +ReadOnly=No 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+Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetTxBaudGenerator +[ItemState] +ItemSymbol=CPUCond +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=TurnRxOn +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnRxOn +[ItemState] +ItemSymbol=TurnRxOff +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnRxOff +[ItemState] +ItemSymbol=SetIdle +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetIdle +[ItemState] +ItemSymbol=LoopMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=LoopMode + +[EndOfChilds] +[ItemState] +ItemSymbol=CPUCond1 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Standby +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Standby + +[EndOfChilds] +[ItemState] +ItemSymbol=ESCIMethodsGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=GetArbiterStatus +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetArbiterStatus +[ItemState] +ItemSymbol=ResetArbiterCounter +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ResetArbiterCounter +[ItemState] +ItemSymbol=GetArbiterCounter +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetArbiterCounter +[ItemState] +ItemSymbol=SetFallingEdgesMeasurement +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFallingEdgesMeasurement +[ItemState] +ItemSymbol=SetLowLevelMeasurement +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetLowLevelMeasurement +[ItemState] +ItemSymbol=ClearArbiterFlags +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ClearArbiterFlags +[ItemState] +ItemSymbol=SetArbitrationMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetArbitrationMode +[ItemState] +ItemSymbol=AdjustBaudRate +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=AdjustBaudRate + +[EndOfChilds] +[ItemState] +ItemSymbol=CPU_HCS08_HCS12 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SetDirection +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=SetDirection + +[EndOfChilds] +[ItemState] +ItemSymbol=56800grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ConnectPin +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ConnectPin + +[EndOfChilds] + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=BeforeNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_BeforeNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=AfterNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_AfterNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=OnError +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnError +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnRxChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnRxChar +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnTxChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnTxChar +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnFullRxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnFullRxBuf +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=OnFreeTxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnFreeTxBuf +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=OnBreak +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnBreak +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=CPUCond0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=OnIdle +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnIdle +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=no + +[EndOfChilds] + +[Program] +ProgType=event +ProgNumb=2 +List=Property +EventModule=Events + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg new file mode 100644 index 000000000..f3d72ee0a Binary files /dev/null and b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg differ diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt new file mode 100644 index 000000000..8ab9f814d Binary files /dev/null and b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt differ diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt new file mode 100644 index 000000000..384e9541b Binary files /dev/null and b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt differ diff --git a/Demo/HCS12_CodeWarrior_banked/Simulator.ini b/Demo/HCS12_CodeWarrior_banked/Simulator.ini new file mode 100644 index 000000000..90a0c8e61 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/Simulator.ini @@ -0,0 +1,25 @@ +[Environment Variables] +GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib +LIBPATH={Compiler}lib\HC12c\include +OBJPATH={Project}bin +TEXTPATH={Project}bin +ABSPATH={Project}bin + +[HI-WAVE] +Target=sim +Layout=C_layout.hwl +LoadDialogOptions= AUTOERASEANDFLASH +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,108,108,1308,962 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 + +[Simulator] +CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd" + +[Simulator HC12] +CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd" +CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd" +CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd" +CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd" +HCS12_SUPPORT=1 +FCS=MC9S12DP256B diff --git a/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c b/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c new file mode 100644 index 000000000..df8b0e648 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c @@ -0,0 +1,342 @@ +/***************************************************** + start12.c - standard startup code + The startup code may be optimized to special user requests + ---------------------------------------------------- + Copyright (c) Metrowerks, Basel, Switzerland + All rights reserved + Do not modify! + +Note: ROM libraries are not implemented in this startup code +Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. + To use this feature, please build your application with the ELF object file format. + *****************************************************/ + +#include "hidef.h" +#include "start12.h" + +/* Macros to control how the startup code handles the COP: */ +/* #define _DO_FEED_COP_ : do feed the COP */ +/* #define _DO_ENABLE_COP_: do enable the COP */ +/* #define _DO_DISABLE_COP_: disable the COP */ +/* Without defining any of these, the startup code does NOT handle the COP */ + +#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */ +struct _tagStartup _startupData; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ +#pragma DATA_SEG DEFAULT +#if defined(FAR_DATA) +#include "non_bank.sgm" +/* the init function must be in non banked memory if banked variables are used */ +/* because _SET_PAGE is called, which may change any page register. */ + +#ifdef __cplusplus + extern "C" +#endif +void _SET_PAGE(void); /* the inline assembler needs a prototype */ + /* this is a runtime routine with a special */ + /* calling convention, dont use it in c code! */ +static void Init(void); +static void Fini(void); +#else +#include "default.sgm" +#if defined( __BANKED__) || defined(__LARGE__) +static void __far Init(void); +static void __far Fini(void); +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#endif /* FAR_DATA */ + + +/* define value and bits for Windef Register */ +#ifdef HC812A4 +#define WINDEF (*(volatile unsigned char*) 0x37) +#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) +#define __ENABLE_PPAGE__ 0x40 +#else +#define __ENABLE_PPAGE__ 0x0 +#endif +#if defined(__DPAGE__) +#define __ENABLE_DPAGE__ 0x80 +#else +#define __ENABLE_DPAGE__ 0x0 +#endif +#if defined(__EPAGE__) +#define __ENABLE_EPAGE__ 0x20 +#else +#define __ENABLE_EPAGE__ 0x0 +#endif +#endif /* HC812A4 */ + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ +#define ___INITRM (*(volatile unsigned char *) 0x0010) +#define ___INITRG (*(volatile unsigned char *) 0x0011) +#define ___INITEE (*(volatile unsigned char *) 0x0012) +#endif + +#if defined(_DO_FEED_COP_) +#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm { +#else +#define __FEED_COP_IN_HLI() /* do nothing */ +#endif + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Init(void) +#else +static void Init(void) +#endif + { +/* purpose: 1) zero out RAM-areas where data is allocated */ +/* 2) copy initialization data from ROM to RAM */ +/* 3) call global constructors in C++ */ +/* called from: _Startup, LibInits */ + __asm { +ZeroOut: +#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) + LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer +#else + LDX _startupData.pZeroOut ; *pZeroOut +#endif + LDY _startupData.nofZeroOuts ; nofZeroOuts + BEQ CopyDown ; if nothing to zero out + +NextZeroOut: PSHY ; save nofZeroOuts +#ifdef FAR_DATA + LDAB 1,X+ ; load page of destination address + LDY 2,X+ ; load offset of destination address + __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register +#else /* FAR_DATA */ + LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) +#endif /* FAR_DATA */ + LDD 2,X+ ; byte count +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +NextWord: CLR 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, NextWord ; dec byte count +#else + LSRD ; /2 and save bit 0 in the carry + PSHX + LDX #0 +LoopClrW: STX 2,Y+ ; Word-Clear + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, LoopClrW + PULX + BCC LastClr ; handle last byte + CLR 1,Y+ +LastClr: +#endif + PULY ; restore nofZeroOuts + DEY ; dec nofZeroOuts + BNE NextZeroOut +CopyDown: +#ifdef __ELF_OBJECT_FILE_FORMAT__ + LDX _startupData.toCopyDownBeg ; load address of copy down desc. +#else + LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. +#endif +NextBlock: + LDD 2,X+ ; size of init-data -> D + BEQ funcInits ; end of copy down desc. +#ifdef FAR_DATA + PSHD ; save counter + LDAB 1,X+ ; load destination page + LDY 2,X+ ; destination address + __PIC_JSR(_SET_PAGE) ; sets the destinations page register + PULD ; restore counter +#else /* FAR_DATA */ + LDY 2,X+ ; load destination address +#endif /* FAR_DATA */ + +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + __asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + + +#include "non_bank.sgm" + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +#ifdef __cplusplus + extern "C" +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) + +#if defined(__SET_RESET_VECTOR__) +void __interrupt 0 _Startup(void) { +#else +void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + for(;;) { /* forever: initialize the program; call the root-procedure */ + if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ + } + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ +#endif + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + Init(); /* zero out, copy down, call constructors */ + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* call main() */ + (*_startupData.main)(); + + /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ + /* the HIWARE object file format does not support this */ +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + Fini(); +#endif + + } /* end loop forever */ +} diff --git a/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c b/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c new file mode 100644 index 000000000..80be5c566 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c @@ -0,0 +1,843 @@ +/****************************************************************************** + FILE : datapage.c + PURPOSE : paged data access runtime routines + MACHINE : Motorola 68HC12 (Target) + LANGUAGE : ANSI-C + HISTORY : 21.7.96 first version created +******************************************************************************/ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. + If some of the -Cp options are given an adapted versions which only covers the + needed cases is produced. +*/ + +/* if no compiler option -Cp is given, it is assumed that all possible are given : */ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ +#define PPAGE_ADDR (0x30+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#define REGISTER_BASE 0x0u +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#include "hidef.h" +#include "non_bank.sgm" +#include "runtime.sgm" + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is usually no problem because the page is set again before any other access */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifing the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we dont know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE +#if defined(__EPAGE__) + BLO L_EPAGE ; EPAGE accesses are possible +#else + BLO L_NOPAGE ; no paged memory below accesses +#endif + CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE +#if defined(__PPAGE__) + BHI L_PPAGE ; EPAGE accesses are possible +#else + BHI L_NOPAGE ; no paged memory above accesses +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ; load page register address and clear zero flag + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ; no paged memory below +#endif + CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one pageregister or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ; set page register +L_NOPAGE: + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ; set page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDY 0,Y ; actual load, overwrites address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDY 0,Y ; actual load, overwrites address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDY 0,Y ; actual load, overwrites address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ; save page register + PSHA ; put it onto the stack + STAB 0,X ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,0,X ; restore page register + PULX ; restore X register + RTS +L_NOPAGE: + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ; save page register + PSHA ; put it onto the stack + STAB PAGE_ADDR ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,PAGE_ADDR; restore page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ; save B register + LDAB 0,X ; save page register + MOVB 0,SP, 0,X ; set page register + STAA 0,Y ; store the value passed in A + STAB 0,X ; restore page register + PULB ; restore B register + PULX ; restore X register + RTS +L_NOPAGE: + STAA 0,Y ; store the value passed in A + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ; save A register + LDAB PAGE_ADDR ; save page register + MOVB 0,SP,PAGE_ADDR ; set page register + STAA 0,Y ; store the value passed in A + STAB PAGE_ADDR ; restore page register + PULB ; restore B register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 0,Y ; store the value passed in X + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 1,Y ; store the value passed in X + MOVB 0,SP, 0,Y ; store the value passed in A + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 1,Y ; store the value passed in X + STAA 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + MOVB 0,SP, 0,Y ; store the value passed in A + STX 1,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ; save page register + MOVB 6,SP, 0,X ; set page register + MOVW 2,SP, 0,Y ; store the value passed in X (high word) + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA 0,X ; restore page register + PULD ; restore A register + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ; store the value passed in X (high word) + STD 2,Y ; store the value passed in D (low word) +done: + PULX ; restore X register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ; save D register + LDAA PAGE_ADDR ; save page register + LDAB 4,SP ; load page part of address + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA PAGE_ADDR ; restore page register + PULD ; restore D register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied at 2,SP. The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroied + - all page register still contain the same value + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : return address + 8,SP : counter, > 0 + --------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ; source addr-=1, because loop counter ends at 1 + PSHX ; save source offset + PSHD ; save both pages + DEY ; destination addr-=1, because loop counter ends at 1 + PSHY ; save destination offset + LDX 8,SP ; load counter, assuming counter > 0 + +loop: + LDD 4,SP ; load source offset + LEAY D,X ; calcutate actual source address + LDAB 2,SP ; load source page + __PIC_JSR (_LOAD_FAR_8); load 1 source byte + PSHB ; save value + LDD 0+1,SP ; load destination offset + LEAY D,X ; calcutate acual destination address + PULA ; restore value + LDAB 3,SP ; load destination page + __PIC_JSR (_STORE_FAR_8); store one byte + DEX + BNE loop + LDX 6,SP ; load return address + LEAS 10,SP ; release stack + JMP 0,X ; return + } +#else + asm { + PSHD ; store page registers + TFR X,D + ADDD 4,SP ; calculate source end address + STD 4,SP + PULB ; reload source page + LDAA PAGE_ADDR ; save page register + PSHA +loop: + STAB PAGE_ADDR ; set source page + LDAA 1,X+ ; load value + MOVB 1,SP, PAGE_ADDR ; set destination page + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ; restore old page value and release stack + STAA PAGE_ADDR ; store it into page register + LDX 4,SP+ ; release stack and load return address + JMP 0,X ; return + } +#endif +} + diff --git a/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map b/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map new file mode 100644 index 000000000..ff7f0c498 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map @@ -0,0 +1,3994 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: BANKED +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: BANKED, Lang: ANSI-C +STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +Cpu.C.o Model: BANKED, Lang: ANSI-C +IO_Map.C.o Model: BANKED, Lang: ANSI-C +Vectors.c.o Model: BANKED, Lang: ANSI-C +RTOSDemo.C.o Model: BANKED, Lang: ANSI-C +main.c.o Model: BANKED, Lang: ANSI-C +ParTest.c.o Model: BANKED, Lang: ANSI-C +serial.c.o Model: BANKED, Lang: ANSI-C +tasks.c.o Model: BANKED, Lang: ANSI-C +queue.c.o Model: BANKED, Lang: ANSI-C +list.c.o Model: BANKED, Lang: ANSI-C +heap_2.c.o Model: BANKED, Lang: ANSI-C +flash.c.o Model: BANKED, Lang: ANSI-C +dynamic.c.o Model: BANKED, Lang: ANSI-C +PollQ.c.o Model: BANKED, Lang: ANSI-C +TickTimer.C.o Model: BANKED, Lang: ANSI-C +Byte1.C.o Model: BANKED, Lang: ANSI-C +PE_Timer.C.o Model: BANKED, Lang: ANSI-C +comtest.c.o Model: BANKED, Lang: ANSI-C +COM0.C.o Model: BANKED, Lang: ANSI-C +port.c.o Model: BANKED, Lang: ANSI-C +integer.c.o Model: BANKED, Lang: ANSI-C +BlockQ.c.o Model: BANKED, Lang: ANSI-C +death.c.o Model: BANKED, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC07C and uses 24 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0x30809A (main) + long stackOffset 0x3988 + unsigned nofZeroOut 1 + _Range pZeroOut 0x1000 10505 + _Copy *toCopyDownBeg 0xC3B5 + int nofLibInits 0 + _LibInit *libInits 0xC098 + int nofInitBodies 0 + _Cpp *initBodies 0xC09A + int nofFiniBodies 0 + _Cpp *finiBodies 0xC09A +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x1000 0x1000 RAM +.text 587 R 0x308000 0x30824A ROM_PAGE30 +.init 124 R 0xC000 0xC07B ROM_C000 +.startData 30 R 0xC07C 0xC099 ROM_C000 +.rodata1 183 R 0xC09A 0xC150 ROM_C000 +NON_BANKED 612 R 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0x398000 0x398196 ROM_PAGE39 +ROM_PAGE3A_533 588 R 0x3A8000 0x3A824B ROM_PAGE3A +ROM_PAGE3B_534 292 R 0x3B8000 0x3B8123 ROM_PAGE3B + +Summary of section sizes per section type: +READ_ONLY (R): 1DD4 (dec: 7636) +READ_WRITE (R/W): 2989 (dec: 10633) +NO_INIT (N/I): 241 (dec: 577) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init 308000 29 41 2 .text + _Startup C151 12 18 1 NON_BANKED +- VARIABLES: + _startupData C07C 18 24 6 .startData +MODULE: -- STRING.C.o (ansibi.lib) -- +- PROCEDURES: + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansibi.lib) -- +- PROCEDURES: + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + Cpu_Interrupt C2FF 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRE 9 1 1 0 .abs_section_9 + _DDRH 262 1 1 0 .abs_section_262 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 0 .abs_section_25a + _DDRS 24A 1 1 2 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCSCR EE 1 1 0 .abs_section_ee + _DLYCT 69 1 1 0 .abs_section_69 + _EBICTL E 1 1 0 .abs_section_e + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECMD 116 1 1 0 .abs_section_116 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FORBYP 3D 1 1 0 .abs_section_3d + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _IBAD E0 1 1 0 .abs_section_e0 + _IBCR E2 1 1 0 .abs_section_e2 + _IBDR E4 1 1 0 .abs_section_e4 + _IBFD E1 1 1 0 .abs_section_e1 + _IBSR E3 1 1 0 .abs_section_e3 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICPAR 68 1 1 0 .abs_section_68 + _ICSYS 6B 1 1 1 .abs_section_6b + _INITEE 12 1 1 1 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 257 1 1 0 .abs_section_257 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PEAR A 1 1 0 .abs_section_a + _PERH 264 1 1 0 .abs_section_264 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 0 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEH 266 1 1 0 .abs_section_266 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 0 .abs_section_25e + _PIFH 267 1 1 0 .abs_section_267 + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 0 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTAD1 12F 1 1 0 .abs_section_12f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSH 265 1 1 0 .abs_section_265 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 0 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 1 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 1 .abs_section_c4 + _RDRH 263 1 1 0 .abs_section_263 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0DR DD 1 1 0 .abs_section_dd + _SPI0SR DB 1 1 0 .abs_section_db + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2DR FD 1 1 0 .abs_section_fd + _SPI2SR FB 1 1 0 .abs_section_fb + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 3 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIMTST 6D 1 1 0 .abs_section_6d + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _DDRAB 2 2 2 1 .abs_section_2 + _MCCNT 76 2 2 0 .abs_section_76 + _PA10H 74 2 2 0 .abs_section_74 + _PA32H 72 2 2 0 .abs_section_72 + _PACN10 64 2 2 0 .abs_section_64 + _PACN32 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 6 .abs_section_0 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _TC0 50 2 2 2 .abs_section_50 + _TC0H 78 2 2 0 .abs_section_78 + _TC1 52 2 2 0 .abs_section_52 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2 54 2 2 0 .abs_section_54 + _TC2H 7C 2 2 0 .abs_section_7c + _TC3 56 2 2 0 .abs_section_56 + _TC3H 7E 2 2 0 .abs_section_7e + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 2 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main 30809A 9 9 0 .text +- VARIABLES: +MODULE: -- main.c.o -- +- PROCEDURES: + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 39 57 3 .text + prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text + vApplicationIdleHook 30817E 70 112 2 .text +- VARIABLES: + STRING.Check.1 C09A 6 6 1 .rodata1 + xLocalError 1001 1 1 2 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestSetLED 3081EE 23 35 4 .text + vParTestToggleLED 308211 14 20 10 .text +- VARIABLES: +MODULE: -- serial.c.o -- +- PROCEDURES: + xSerialPortInitMinimal 308225 26 38 2 .text + xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 + xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 + vCOM0_ISR C300 59 89 1 NON_BANKED +- VARIABLES: + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 + vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 + vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 + uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 + vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 + vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 + vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 + xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 + prvIdleTask 338189 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 + prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 +- VARIABLES: + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 + xQueueSend 34811A D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 + xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 + prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise 358203 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 + vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 + vListInsert 368000 55 85 8 ROM_PAGE36_529 + vListRemove 368055 23 35 32 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- heap_2.c.o -- +- PROCEDURES: + pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 + vPortFree 368139 3B 59 10 ROM_PAGE36_529 +- VARIABLES: + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 + vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 +- VARIABLES: + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + uxFlashTaskNumber 38AA 1 1 2 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 + vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 +- VARIABLES: + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + usCheckVariable 38AB 2 2 3 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xSuspendedTestQueue 38EC 2 2 3 .common +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 + vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 +- VARIABLES: + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE + TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE + TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE +- VARIABLES: + CmpHighVal 38F2 2 2 2 TickTimer_DATA +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_PutBit 3B819F 21 33 2 Byte1_CODE + Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE +- VARIABLES: + Byte1_Table 38F4 8 8 2 Byte1_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 +- VARIABLES: +MODULE: -- comtest.c.o -- +- PROCEDURES: + vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 + vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 + vComRxTask 398000 7B 123 3 ROM_PAGE39_532 + xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 +- VARIABLES: + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + xPort 38C9 2 2 3 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss +MODULE: -- COM0.C.o -- +- PROCEDURES: + COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE + COM0_Init 3B81ED 25 37 2 COM0_CODE +- VARIABLES: + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 + xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 + xBankedStartScheduler C359 1A 26 1 NON_BANKED + vPortYield C373 1D 29 1 NON_BANKED + vPortTickInterrupt C390 25 37 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 1000 1 1 101 .data +MODULE: -- integer.c.o -- +- PROCEDURES: + vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 +- VARIABLES: + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + xTaskCheck 38CD 1 1 3 .bss +MODULE: -- BlockQ.c.o -- +- PROCEDURES: + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 +- VARIABLES: + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + sBlockingConsumerCount 38CE 6 6 4 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss +MODULE: -- death.c.o -- +- PROCEDURES: + vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 + vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 +- VARIABLES: + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 59 0 + STRING.C.o (ansibi.lib) 0 113 0 + rtshc12.c.o (ansibi.lib) 0 412 0 + Cpu.C.o 0 125 0 + IO_Map.C.o 577 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 9 0 + main.c.o 1 331 6 + ParTest.c.o 0 55 0 + serial.c.o 4 170 0 + tasks.c.o 151 1758 5 + queue.c.o 0 943 0 + list.c.o 0 196 0 + heap_2.c.o 10253 252 0 + flash.c.o 1 137 5 + dynamic.c.o 28 593 39 + PollQ.c.o 4 268 16 + TickTimer.C.o 2 123 0 + Byte1.C.o 8 53 0 + PE_Timer.C.o 0 74 0 + comtest.c.o 4 292 12 + COM0.C.o 13 62 0 + port.c.o 1 145 0 + integer.c.o 1 218 8 + BlockQ.c.o 24 539 48 + death.c.o 10 341 44 + other 128 30 27 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init memcpy memset strncpy main vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED + vParTestToggleLED xSerialPortInitMinimal +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted + uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority + xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 + pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList + pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd + uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 + xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount + sBlockingProducerCount sLastBlockingConsumerCount.7 + sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart + usLastCreationCount.6 uxTasksRunningNow.7 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 + STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 + STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 + STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 +SECTION: "NON_BANKED" + _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS + Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt +SECTION: ".common" + xSuspendedTestQueue xCreatedTask1 xCreatedTask2 +SECTION: "TickTimer_CODE" + TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "Byte1_CODE" + Byte1_PutBit Byte1_NegBit +SECTION: "COM0_CODE" + COM0_SetBaudRateMode COM0_Init +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_17f" + _CAN0TXTBPR +SECTION: ".abs_section_182" + _CAN1BTR0 +SECTION: ".abs_section_183" + _CAN1BTR1 +SECTION: ".abs_section_180" + _CAN1CTL0 +SECTION: ".abs_section_181" + _CAN1CTL1 +SECTION: ".abs_section_18b" + _CAN1IDAC +SECTION: ".abs_section_190" + _CAN1IDAR0 +SECTION: ".abs_section_191" + _CAN1IDAR1 +SECTION: ".abs_section_192" + _CAN1IDAR2 +SECTION: ".abs_section_193" + _CAN1IDAR3 +SECTION: ".abs_section_198" + _CAN1IDAR4 +SECTION: ".abs_section_199" + _CAN1IDAR5 +SECTION: ".abs_section_19a" + _CAN1IDAR6 +SECTION: ".abs_section_19b" + _CAN1IDAR7 +SECTION: ".abs_section_194" + _CAN1IDMR0 +SECTION: ".abs_section_195" + _CAN1IDMR1 +SECTION: ".abs_section_196" + _CAN1IDMR2 +SECTION: ".abs_section_197" + _CAN1IDMR3 +SECTION: ".abs_section_19c" + _CAN1IDMR4 +SECTION: ".abs_section_19d" + _CAN1IDMR5 +SECTION: ".abs_section_19e" + _CAN1IDMR6 +SECTION: ".abs_section_19f" + _CAN1IDMR7 +SECTION: ".abs_section_184" + _CAN1RFLG +SECTION: ".abs_section_185" + _CAN1RIER +SECTION: ".abs_section_1ac" + _CAN1RXDLR +SECTION: ".abs_section_1a4" + _CAN1RXDSR0 +SECTION: ".abs_section_1a5" + _CAN1RXDSR1 +SECTION: ".abs_section_1a6" + _CAN1RXDSR2 +SECTION: ".abs_section_1a7" + _CAN1RXDSR3 +SECTION: ".abs_section_1a8" + _CAN1RXDSR4 +SECTION: ".abs_section_1a9" + _CAN1RXDSR5 +SECTION: ".abs_section_1aa" + _CAN1RXDSR6 +SECTION: ".abs_section_1ab" + _CAN1RXDSR7 +SECTION: ".abs_section_18e" + _CAN1RXERR +SECTION: ".abs_section_1a0" + _CAN1RXIDR0 +SECTION: ".abs_section_1a1" + _CAN1RXIDR1 +SECTION: ".abs_section_1a2" + _CAN1RXIDR2 +SECTION: ".abs_section_1a3" + _CAN1RXIDR3 +SECTION: ".abs_section_189" + _CAN1TAAK +SECTION: ".abs_section_188" + _CAN1TARQ +SECTION: ".abs_section_18a" + _CAN1TBSEL +SECTION: ".abs_section_186" + _CAN1TFLG +SECTION: ".abs_section_187" + _CAN1TIER +SECTION: ".abs_section_1bc" + _CAN1TXDLR +SECTION: ".abs_section_1b4" + _CAN1TXDSR0 +SECTION: ".abs_section_1b5" + _CAN1TXDSR1 +SECTION: ".abs_section_1b6" + _CAN1TXDSR2 +SECTION: ".abs_section_1b7" + _CAN1TXDSR3 +SECTION: ".abs_section_1b8" + _CAN1TXDSR4 +SECTION: ".abs_section_1b9" + _CAN1TXDSR5 +SECTION: ".abs_section_1ba" + _CAN1TXDSR6 +SECTION: ".abs_section_1bb" + _CAN1TXDSR7 +SECTION: ".abs_section_18f" + _CAN1TXERR +SECTION: ".abs_section_1b0" + _CAN1TXIDR0 +SECTION: ".abs_section_1b1" + _CAN1TXIDR1 +SECTION: ".abs_section_1b2" + _CAN1TXIDR2 +SECTION: ".abs_section_1b3" + _CAN1TXIDR3 +SECTION: ".abs_section_1bf" + _CAN1TXTBPR +SECTION: ".abs_section_1c2" + _CAN2BTR0 +SECTION: ".abs_section_1c3" + _CAN2BTR1 +SECTION: ".abs_section_1c0" + _CAN2CTL0 +SECTION: ".abs_section_1c1" + _CAN2CTL1 +SECTION: ".abs_section_1cb" + _CAN2IDAC +SECTION: ".abs_section_1d0" + _CAN2IDAR0 +SECTION: ".abs_section_1d1" + _CAN2IDAR1 +SECTION: ".abs_section_1d2" + _CAN2IDAR2 +SECTION: ".abs_section_1d3" + _CAN2IDAR3 +SECTION: ".abs_section_1d8" + _CAN2IDAR4 +SECTION: ".abs_section_1d9" + _CAN2IDAR5 +SECTION: ".abs_section_1da" + _CAN2IDAR6 +SECTION: ".abs_section_1db" + _CAN2IDAR7 +SECTION: ".abs_section_1d4" + _CAN2IDMR0 +SECTION: ".abs_section_1d5" + _CAN2IDMR1 +SECTION: ".abs_section_1d6" + _CAN2IDMR2 +SECTION: ".abs_section_1d7" + _CAN2IDMR3 +SECTION: ".abs_section_1dc" + _CAN2IDMR4 +SECTION: ".abs_section_1dd" + _CAN2IDMR5 +SECTION: ".abs_section_1de" + _CAN2IDMR6 +SECTION: ".abs_section_1df" + _CAN2IDMR7 +SECTION: ".abs_section_1c4" + _CAN2RFLG +SECTION: ".abs_section_1c5" + _CAN2RIER +SECTION: ".abs_section_1ec" + _CAN2RXDLR +SECTION: ".abs_section_1e4" + _CAN2RXDSR0 +SECTION: ".abs_section_1e5" + _CAN2RXDSR1 +SECTION: ".abs_section_1e6" + _CAN2RXDSR2 +SECTION: ".abs_section_1e7" + _CAN2RXDSR3 +SECTION: ".abs_section_1e8" + _CAN2RXDSR4 +SECTION: ".abs_section_1e9" + _CAN2RXDSR5 +SECTION: ".abs_section_1ea" + _CAN2RXDSR6 +SECTION: ".abs_section_1eb" + _CAN2RXDSR7 +SECTION: ".abs_section_1ce" + _CAN2RXERR +SECTION: ".abs_section_1e0" + _CAN2RXIDR0 +SECTION: ".abs_section_1e1" + _CAN2RXIDR1 +SECTION: ".abs_section_1e2" + _CAN2RXIDR2 +SECTION: ".abs_section_1e3" + _CAN2RXIDR3 +SECTION: ".abs_section_1c9" + _CAN2TAAK +SECTION: ".abs_section_1c8" + _CAN2TARQ +SECTION: ".abs_section_1ca" + _CAN2TBSEL +SECTION: ".abs_section_1c6" + _CAN2TFLG +SECTION: ".abs_section_1c7" + _CAN2TIER +SECTION: ".abs_section_1fc" + _CAN2TXDLR +SECTION: ".abs_section_1f4" + _CAN2TXDSR0 +SECTION: ".abs_section_1f5" + _CAN2TXDSR1 +SECTION: ".abs_section_1f6" + _CAN2TXDSR2 +SECTION: ".abs_section_1f7" + _CAN2TXDSR3 +SECTION: ".abs_section_1f8" + _CAN2TXDSR4 +SECTION: ".abs_section_1f9" + _CAN2TXDSR5 +SECTION: ".abs_section_1fa" + _CAN2TXDSR6 +SECTION: ".abs_section_1fb" + _CAN2TXDSR7 +SECTION: ".abs_section_1cf" + _CAN2TXERR +SECTION: ".abs_section_1f0" + _CAN2TXIDR0 +SECTION: ".abs_section_1f1" + _CAN2TXIDR1 +SECTION: ".abs_section_1f2" + _CAN2TXIDR2 +SECTION: ".abs_section_1f3" + _CAN2TXIDR3 +SECTION: ".abs_section_1ff" + _CAN2TXTBPR +SECTION: ".abs_section_202" + _CAN3BTR0 +SECTION: ".abs_section_203" + _CAN3BTR1 +SECTION: ".abs_section_200" + _CAN3CTL0 +SECTION: ".abs_section_201" + _CAN3CTL1 +SECTION: ".abs_section_20b" + _CAN3IDAC +SECTION: ".abs_section_210" + _CAN3IDAR0 +SECTION: ".abs_section_211" + _CAN3IDAR1 +SECTION: ".abs_section_212" + _CAN3IDAR2 +SECTION: ".abs_section_213" + _CAN3IDAR3 +SECTION: ".abs_section_218" + _CAN3IDAR4 +SECTION: ".abs_section_219" + _CAN3IDAR5 +SECTION: ".abs_section_21a" + _CAN3IDAR6 +SECTION: ".abs_section_21b" + _CAN3IDAR7 +SECTION: ".abs_section_214" + _CAN3IDMR0 +SECTION: ".abs_section_215" + _CAN3IDMR1 +SECTION: ".abs_section_216" + _CAN3IDMR2 +SECTION: ".abs_section_217" + _CAN3IDMR3 +SECTION: ".abs_section_21c" + _CAN3IDMR4 +SECTION: ".abs_section_21d" + _CAN3IDMR5 +SECTION: ".abs_section_21e" + _CAN3IDMR6 +SECTION: ".abs_section_21f" + _CAN3IDMR7 +SECTION: ".abs_section_204" + _CAN3RFLG +SECTION: ".abs_section_205" + _CAN3RIER +SECTION: ".abs_section_22c" + _CAN3RXDLR +SECTION: ".abs_section_224" + _CAN3RXDSR0 +SECTION: ".abs_section_225" + _CAN3RXDSR1 +SECTION: ".abs_section_226" + _CAN3RXDSR2 +SECTION: ".abs_section_227" + _CAN3RXDSR3 +SECTION: ".abs_section_228" + _CAN3RXDSR4 +SECTION: ".abs_section_229" + _CAN3RXDSR5 +SECTION: ".abs_section_22a" + _CAN3RXDSR6 +SECTION: ".abs_section_22b" + _CAN3RXDSR7 +SECTION: ".abs_section_20e" + _CAN3RXERR +SECTION: ".abs_section_220" + _CAN3RXIDR0 +SECTION: ".abs_section_221" + _CAN3RXIDR1 +SECTION: ".abs_section_222" + _CAN3RXIDR2 +SECTION: ".abs_section_223" + _CAN3RXIDR3 +SECTION: ".abs_section_209" + _CAN3TAAK +SECTION: ".abs_section_208" + _CAN3TARQ +SECTION: ".abs_section_20a" + _CAN3TBSEL +SECTION: ".abs_section_206" + _CAN3TFLG +SECTION: ".abs_section_207" + _CAN3TIER +SECTION: ".abs_section_23c" + _CAN3TXDLR +SECTION: ".abs_section_234" + _CAN3TXDSR0 +SECTION: ".abs_section_235" + _CAN3TXDSR1 +SECTION: ".abs_section_236" + _CAN3TXDSR2 +SECTION: ".abs_section_237" + _CAN3TXDSR3 +SECTION: ".abs_section_238" + _CAN3TXDSR4 +SECTION: ".abs_section_239" + _CAN3TXDSR5 +SECTION: ".abs_section_23a" + _CAN3TXDSR6 +SECTION: ".abs_section_23b" + _CAN3TXDSR7 +SECTION: ".abs_section_20f" + _CAN3TXERR +SECTION: ".abs_section_230" + _CAN3TXIDR0 +SECTION: ".abs_section_231" + _CAN3TXIDR1 +SECTION: ".abs_section_232" + _CAN3TXIDR2 +SECTION: ".abs_section_233" + _CAN3TXIDR3 +SECTION: ".abs_section_23f" + _CAN3TXTBPR +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2bf" + _CAN4TXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_ec" + _DLCBARD +SECTION: ".abs_section_e8" + _DLCBCR1 +SECTION: ".abs_section_ea" + _DLCBCR2 +SECTION: ".abs_section_eb" + _DLCBDR +SECTION: ".abs_section_ed" + _DLCBRSR +SECTION: ".abs_section_e9" + _DLCBSVR +SECTION: ".abs_section_ee" + _DLCSCR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_3d" + _FORBYP +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_6d" + _TIMTST +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + CmpHighVal +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "COM0_DATA" + COM0_PrescHigh.1 SerFlag PrescHigh NumMode +SECTION: "ROM_PAGE31_524" + xSerialGetChar xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil + vTaskDelay uxTaskPriorityGet +SECTION: "ROM_PAGE32_525" + vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler + vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks +SECTION: "ROM_PAGE33_526" + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists +SECTION: "ROM_PAGE34_527" + prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB + xQueueCreate xQueueSend xQueueSendFromISR +SECTION: "ROM_PAGE35_528" + xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue + prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem + vListInsertEnd +SECTION: "ROM_PAGE36_529" + vListInsert vListRemove pvPortMalloc vPortFree vStartLEDFlashTasks + vLEDFlashTask +SECTION: "ROM_PAGE37_530" + vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask + vCounterControlTask vQueueSendWhenSuspendedTask + vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning +SECTION: "ROM_PAGE38_531" + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning PE_Timer_LngHi1 vAltStartComTestTasks + vComTxTask +SECTION: "ROM_PAGE39_532" + vComRxTask xAreComTestTasksStillRunning pxPortInitialiseStack + xPortStartScheduler vStartIntegerMathTasks vCompeteingIntMathTask + xAreIntegerMathsTaskStillRunning +SECTION: "ROM_PAGE3A_533" + vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer + xAreBlockingQueuesStillRunning vCreateSuicidalTasks +SECTION: "ROM_PAGE3B_534" + vSuicidalTask vCreateTasks xIsCreateTaskStillRunning + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 6 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 1 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _FORBYP 3D 1 1 0 .abs_section_3d + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 3 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 2 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 2 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 1 .abs_section_6b + _TIMTST 6D 1 1 0 .abs_section_6d + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 1 .abs_section_c4 + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCSCR EE 1 1 0 .abs_section_ee + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 1 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 2 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + uxCriticalNesting 1000 1 1 101 .data + xLocalError 1001 1 1 2 .bss + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss + uxFlashTaskNumber 38AA 1 1 2 .bss + usCheckVariable 38AB 2 2 3 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss + xPort 38C9 2 2 3 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss + xTaskCheck 38CD 1 1 3 .bss + sBlockingConsumerCount 38CE 6 6 4 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xSuspendedTestQueue 38EC 2 2 3 .common + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + CmpHighVal 38F2 2 2 2 TickTimer_DATA + Byte1_Table 38F4 8 8 2 Byte1_DATA + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + STRING.Check.1 C09A 6 6 1 .rodata1 + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + _Startup C151 12 18 1 NON_BANKED + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED + Cpu_Interrupt C2FF 1 1 60 NON_BANKED + vCOM0_ISR C300 59 89 1 NON_BANKED + xBankedStartScheduler C359 1A 26 1 NON_BANKED + vPortYield C373 1D 29 1 NON_BANKED + vPortTickInterrupt C390 25 37 1 NON_BANKED + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + Init 308000 29 41 2 .text + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text + main 30809A 9 9 0 .text + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 39 57 3 .text + prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text + vApplicationIdleHook 30817E 70 112 2 .text + vParTestSetLED 3081EE 23 35 4 .text + vParTestToggleLED 308211 14 20 10 .text + xSerialPortInitMinimal 308225 26 38 2 .text + xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 + xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 + xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 + vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 + vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 + uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 + vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 + vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 + vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 + xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 + prvIdleTask 338189 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 + prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 + xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 + xQueueSend 34811A D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 + xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 + prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 + vListInitialise 358203 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 + vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 + vListInsert 368000 55 85 8 ROM_PAGE36_529 + vListRemove 368055 23 35 32 ROM_PAGE36_529 + pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 + vPortFree 368139 3B 59 10 ROM_PAGE36_529 + vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 + vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 + vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 + vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 + vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 + PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 + vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 + vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 + vComRxTask 398000 7B 123 3 ROM_PAGE39_532 + xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 + pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 + xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 + vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 + vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 + vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 + TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE + TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE + TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE + Byte1_PutBit 3B819F 21 33 2 Byte1_CODE + Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE + COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE + COM0_Init 3B81ED 25 37 2 COM0_CODE + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansibi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansibi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS + _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +serial.c.o: + vSerialClose +tasks.c.o: + vTaskEndScheduler +queue.c.o: + vQueueDelete +TickTimer.C.o: + TickTimer_Interrupt SetCV SetPV HWEnDi TickTimer_SetPeriodTicks16 + TickTimer_SetPeriodTicks32 TickTimer_SetPeriodUS TickTimer_SetPeriodMS +Byte1.C.o: + Byte1_GetMsk +PE_Timer.C.o: + PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 +COM0.C.o: + HWEnDi +port.c.o: + vPortEndScheduler prvSetupTimerInterrupt +NOT USED VARIABLES +STRING.C.o (ansibi.lib): + STRING..1 next.2 +rtshc12.c.o (ansibi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg +heap_2.c.o: + heapSTRUCT_SIZE +death.c.o: + uxMaxNumberOfExtraTasksRunning + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xC3B5 ---- SIZE 4 --- +Filling bytes inserted + 00011000 +------- ROM-ADDRESS: 0xC3B9 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xC3BA ---- SIZE 4 --- +Filling bytes inserted + 001038F4 +------- ROM-ADDRESS: 0xC3BE ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xC3C6 ---- SIZE 1 --- +Filling bytes inserted + 00 +------- ROM-ADDRESS: 0xC3C7 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- +Name of initialized Object : COM0_PrescHigh.1:1 + 29005100A3 0146 +------- ROM-ADDRESS: 0xC3CE ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR + _REFDV _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB + _DDRAB _DDRS _PTS COM0_Init _INTCR +_Startup USES _startupData Init +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR + _SCI0CR2 xCharsForTx xQueueReceiveFromISR +xBankedStartScheduler USES TickTimer_SetFreqHz TickTimer_Enable + pxCurrentTCB uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt + vPortYield _EntryPoint +Init USES _startupData +main USES PE_low_level_init vMain +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks + vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks + STRING.Check.1 xTaskCreate vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning + xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning + xIsCreateTaskStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vParTestSetLED USES uxCriticalNesting Byte1_PutBit +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx + COM0_SetBaudRateMode +xSerialGetChar USES xRxedChars xQueueReceive +xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove + xTasksWaitingTermination vListInsertEnd uxTasksDeleted +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 + xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList + vListInitialise +prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll + xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove + uxCurrentNumberOfTasks prvDeleteTCB +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +prvDeleteTCB USES vPortFree +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap + xStart xEnd xTaskResumeAll +vPortFree USES vTaskSuspendAll xStart xTaskResumeAll +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +PE_Timer_LngHi1 USES _LCMP +vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask + STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 +vComTxTask USES xPort xSerialPutChar uxBaseLED + vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay +vComRxTask USES xPort xSerialGetChar uxBaseLED + vParTestToggleLED vParTestSetLED uxRxLoops +xAreComTestTasksStillRunning USES uxRxLoops +xPortStartScheduler USES xBankedStartScheduler +vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 + xTaskCheck xTaskCreate +vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting +xAreIntegerMathsTaskStillRunning USES xTaskCheck +vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate + sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer + STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer + STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc +vBlockingQueueProducer USES xQueueSend +vBlockingQueueConsumer USES xQueueReceive +xAreBlockingQueuesStillRunning USES sLastBlockingConsumerCount.7 + sBlockingProducerCount sLastBlockingProducerCount.8 + sBlockingConsumerCount +vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 + xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart +vSuicidalTask USES _LMUL vTaskDelay vTaskDelete +vCreateTasks USES vPortFree vTaskDelay vSuicidalTask + STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 + STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 + usCreationCount vCreateTasks +xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount + uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart +TickTimer_Enable USES _TFLG1 _TIE +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal _TC0 _TC7 +TickTimer_Init USES CmpHighVal _TC0 _TC7 _TSCR2 _TFLG1 _TIE +Byte1_PutBit USES Byte1_Table _PORTAB +Byte1_NegBit USES Byte1_Table _PORTAB +COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD +COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 + _SCI0SR1 _SCI0CR2 _SCI0BD + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- COM0_Init + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vAltStartComTestTasks + | | | + | | +- xSerialPortInitMinimal + | | | | + | | | +- xQueueCreate (see above) + | | | | + | | | +- COM0_SetBaudRateMode + | | | + | | +- vComTxTask + | | | | + | | | +- xSerialPutChar + | | | | | + | | | | +- xQueueSend (see above) + | | | | + | | | +- vParTestToggleLED (see above) + | | | | + | | | +- vParTestSetLED + | | | | | + | | | | +- Byte1_PutBit + | | | | + | | | +- xTaskGetTickCount (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vComRxTask + | | | + | | +- xSerialGetChar + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | | + | | +- vParTestSetLED (see above) + | | + | +- vStartBlockingQueueTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vBlockingQueueConsumer + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vBlockingQueueProducer + | | | | + | | | +- xQueueSend (see above) + | | | + | | +- pvPortMalloc (see above) + | | + | +- vStartIntegerMathTasks + | | | + | | +- vCompeteingIntMathTask + | | | | + | | | +- _LNEG + | | | | + | | | +- _LDIVS + | | | | | + | | | | +- _NEG_P + | | | | | + | | | | +- _lDivMod + | | | | + | | | +- _LCMP_P (see above) + | | | + | | +- xTaskCreate (see above) + | | + | +- vCreateSuicidalTasks + | | | + | | +- pvPortMalloc (see above) + | | | + | | +- vCreateTasks + | | | | + | | | +- vPortFree (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vSuicidalTask + | | | | | + | | | | +- _LMUL + | | | | | + | | | | +- vTaskDelay (see above) + | | | | | + | | | | +- vTaskDelete + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- xTaskCreate (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- uxTaskGetNumberOfTasks + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | | + | | | +- xAreComTestTasksStillRunning + | | | | + | | | +- xAreIntegerMathsTaskStillRunning + | | | | + | | | +- xAreBlockingQueuesStillRunning + | | | | + | | | +- xIsCreateTaskStillRunning + | | | | + | | | +- uxTaskGetNumberOfTasks (see above) + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- prvDeleteTCB + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG (see above) + | | | + | | +- _LDIVS (see above) + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | + | | +- _LCMP (see above) + | | + | +- TickTimer_Enable + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vCOM0_ISR + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- xQueueReceiveFromISR + | | + | +- memcpy (see above) + | | + | +- xTaskRemoveFromEventList (see above) + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 18 +Total size of all blocks to be downloaded: 7636 + diff --git a/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map b/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map new file mode 100644 index 000000000..6c7e3b7e4 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map @@ -0,0 +1,4026 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\Simulator.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: BANKED +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: BANKED, Lang: ANSI-C +STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +Cpu.C.o Model: BANKED, Lang: ANSI-C +IO_Map.C.o Model: BANKED, Lang: ANSI-C +Vectors.c.o Model: BANKED, Lang: ANSI-C +RTOSDemo.C.o Model: BANKED, Lang: ANSI-C +main.c.o Model: BANKED, Lang: ANSI-C +ParTest.c.o Model: BANKED, Lang: ANSI-C +serial.c.o Model: BANKED, Lang: ANSI-C +tasks.c.o Model: BANKED, Lang: ANSI-C +queue.c.o Model: BANKED, Lang: ANSI-C +list.c.o Model: BANKED, Lang: ANSI-C +heap_2.c.o Model: BANKED, Lang: ANSI-C +TickTimer.C.o Model: BANKED, Lang: ANSI-C +PE_Timer.C.o Model: BANKED, Lang: ANSI-C +Byte1.C.o Model: BANKED, Lang: ANSI-C +flash.c.o Model: BANKED, Lang: ANSI-C +dynamic.c.o Model: BANKED, Lang: ANSI-C +PollQ.c.o Model: BANKED, Lang: ANSI-C +comtest.c.o Model: BANKED, Lang: ANSI-C +COM0.C.o Model: BANKED, Lang: ANSI-C +port.c.o Model: BANKED, Lang: ANSI-C +integer.c.o Model: BANKED, Lang: ANSI-C +BlockQ.c.o Model: BANKED, Lang: ANSI-C +death.c.o Model: BANKED, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC07C and uses 24 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0x30809A (main) + long stackOffset 0x3988 + unsigned nofZeroOut 1 + _Range pZeroOut 0x1000 10505 + _Copy *toCopyDownBeg 0xC3AE + int nofLibInits 0 + _LibInit *libInits 0xC098 + int nofInitBodies 0 + _Cpp *initBodies 0xC09A + int nofFiniBodies 0 + _Cpp *finiBodies 0xC09A +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment 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N/I 0x52 0x53 .absSeg512 +.abs_section_7a 2 N/I 0x7A 0x7B .absSeg513 +.abs_section_54 2 N/I 0x54 0x55 .absSeg514 +.abs_section_7c 2 N/I 0x7C 0x7D .absSeg515 +.abs_section_56 2 N/I 0x56 0x57 .absSeg516 +.abs_section_7e 2 N/I 0x7E 0x7F .absSeg517 +.abs_section_58 2 N/I 0x58 0x59 .absSeg518 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg519 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg520 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg521 +.abs_section_44 2 N/I 0x44 0x45 .absSeg522 +.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg523 +.bss 10475 R/W 0x1001 0x38EB RAM +.common 6 R/W 0x38EC 0x38F1 RAM +TickTimer_CODE 143 R 0x3B811C 0x3B81AA ROM_PAGE3B +Byte1_CODE 61 R 0x3B81AB 0x3B81E7 ROM_PAGE3B +COM0_CODE 67 R 0x3B81E8 0x3B822A ROM_PAGE3B +TickTimer_DATA 2 R/W 0x38F2 0x38F3 RAM +Byte1_DATA 8 R/W 0x38F4 0x38FB RAM +COM0_DATA 13 R/W 0x38FC 0x3908 RAM +.stack 128 R/W 0x3909 0x3988 RAM +ROM_PAGE31_524 552 R 0x318000 0x318227 ROM_PAGE31 +ROM_PAGE32_525 552 R 0x328000 0x328227 ROM_PAGE32 +ROM_PAGE33_526 564 R 0x338000 0x338233 ROM_PAGE33 +ROM_PAGE34_527 579 R 0x348000 0x348242 ROM_PAGE34 +ROM_PAGE35_528 589 R 0x358000 0x35824C ROM_PAGE35 +ROM_PAGE36_529 555 R 0x368000 0x36822A ROM_PAGE36 +ROM_PAGE37_530 578 R 0x378000 0x378241 ROM_PAGE37 +ROM_PAGE38_531 558 R 0x388000 0x38822D ROM_PAGE38 +ROM_PAGE39_532 288 R 0x398000 0x39811F ROM_PAGE39 +ROM_PAGE3A_533 574 R 0x3A8000 0x3A823D ROM_PAGE3A +ROM_PAGE3B_534 284 R 0x3B8000 0x3B811B ROM_PAGE3B + +Summary of section sizes per section type: +READ_ONLY (R): 1DD3 (dec: 7635) +READ_WRITE (R/W): 2989 (dec: 10633) +NO_INIT (N/I): 241 (dec: 577) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init 308000 29 41 2 .text + _Startup C151 12 18 1 NON_BANKED +- VARIABLES: + _startupData C07C 18 24 6 .startData +MODULE: -- STRING.C.o (ansibi.lib) -- +- PROCEDURES: + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansibi.lib) -- +- PROCEDURES: + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + Cpu_Interrupt C2FF 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRE 9 1 1 0 .abs_section_9 + _DDRH 262 1 1 0 .abs_section_262 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 0 .abs_section_25a + _DDRS 24A 1 1 2 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCSCR EE 1 1 0 .abs_section_ee + _DLYCT 69 1 1 0 .abs_section_69 + _EBICTL E 1 1 0 .abs_section_e + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECMD 116 1 1 0 .abs_section_116 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FORBYP 3D 1 1 0 .abs_section_3d + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _IBAD E0 1 1 0 .abs_section_e0 + _IBCR E2 1 1 0 .abs_section_e2 + _IBDR E4 1 1 0 .abs_section_e4 + _IBFD E1 1 1 0 .abs_section_e1 + _IBSR E3 1 1 0 .abs_section_e3 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICPAR 68 1 1 0 .abs_section_68 + _ICSYS 6B 1 1 1 .abs_section_6b + _INITEE 12 1 1 1 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 257 1 1 0 .abs_section_257 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PEAR A 1 1 0 .abs_section_a + _PERH 264 1 1 0 .abs_section_264 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 0 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEH 266 1 1 0 .abs_section_266 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 0 .abs_section_25e + _PIFH 267 1 1 0 .abs_section_267 + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 0 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTAD1 12F 1 1 0 .abs_section_12f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSH 265 1 1 0 .abs_section_265 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 0 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 1 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 1 .abs_section_c4 + _RDRH 263 1 1 0 .abs_section_263 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0DR DD 1 1 0 .abs_section_dd + _SPI0SR DB 1 1 0 .abs_section_db + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2DR FD 1 1 0 .abs_section_fd + _SPI2SR FB 1 1 0 .abs_section_fb + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 2 .abs_section_4c + _TIMTST 6D 1 1 0 .abs_section_6d + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _DDRAB 2 2 2 1 .abs_section_2 + _MCCNT 76 2 2 0 .abs_section_76 + _PA10H 74 2 2 0 .abs_section_74 + _PA32H 72 2 2 0 .abs_section_72 + _PACN10 64 2 2 0 .abs_section_64 + _PACN32 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 6 .abs_section_0 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _TC0 50 2 2 1 .abs_section_50 + _TC0H 78 2 2 0 .abs_section_78 + _TC1 52 2 2 0 .abs_section_52 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2 54 2 2 0 .abs_section_54 + _TC2H 7C 2 2 0 .abs_section_7c + _TC3 56 2 2 0 .abs_section_56 + _TC3H 7E 2 2 0 .abs_section_7e + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main 30809A 9 9 0 .text +- VARIABLES: +MODULE: -- main.c.o -- +- PROCEDURES: + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 33 51 3 .text + prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text + vApplicationIdleHook 308171 70 112 2 .text +- VARIABLES: + STRING.Check.1 C09A 6 6 1 .rodata1 + xLocalError 1001 1 1 2 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestSetLED 3081E1 22 34 4 .text + vParTestToggleLED 308203 14 20 10 .text +- VARIABLES: +MODULE: -- serial.c.o -- +- PROCEDURES: + xSerialPortInitMinimal 308217 24 36 2 .text + xSerialGetChar 30823B 17 23 2 .text + xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 + vCOM0_ISR C300 59 89 1 NON_BANKED +- VARIABLES: + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 + vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 + vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 + uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 + vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 + vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 + vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 + xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 + prvIdleTask 338192 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 + prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 +- VARIABLES: + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 + xQueueSend 348119 D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 + xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 + prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 + vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 + vListInsert 368000 5A 90 8 ROM_PAGE36_529 + vListRemove 36805A 23 35 32 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- heap_2.c.o -- +- PROCEDURES: + pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 + vPortFree 368133 34 52 10 ROM_PAGE36_529 +- VARIABLES: + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV 3B811C F 15 4 TickTimer_CODE + SetPV 3B812B C 12 2 TickTimer_CODE + HWEnDi 3B8137 8 8 4 TickTimer_CODE + TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE + TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE + TickTimer_Init 3B8196 15 21 2 TickTimer_CODE +- VARIABLES: + CmpHighVal 38F2 2 2 2 TickTimer_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE + Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE + Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE +- VARIABLES: + Byte1_Table 38F4 8 8 1 Byte1_DATA +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 + vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 +- VARIABLES: + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + uxFlashTaskNumber 38AA 1 1 2 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 + vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 +- VARIABLES: + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + usCheckVariable 38AB 2 2 4 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xSuspendedTestQueue 38EC 2 2 3 .common +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 + vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 +- VARIABLES: + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss +MODULE: -- comtest.c.o -- +- PROCEDURES: + vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 + vComTxTask 38815E 51 81 3 ROM_PAGE38_531 + vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 + xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 +- VARIABLES: + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + xPort 38C9 2 2 2 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss +MODULE: -- COM0.C.o -- +- PROCEDURES: + HWEnDi 3B81E8 A 10 2 COM0_CODE + COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE + COM0_Init 3B820B 20 32 2 COM0_CODE +- VARIABLES: + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 + prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 + xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 + xBankedStartScheduler C359 13 19 1 NON_BANKED + vPortYield C36C 1D 29 1 NON_BANKED + vPortTickInterrupt C389 25 37 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 1000 1 1 101 .data +MODULE: -- integer.c.o -- +- PROCEDURES: + vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 +- VARIABLES: + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + xTaskCheck 38CD 1 1 3 .bss +MODULE: -- BlockQ.c.o -- +- PROCEDURES: + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 +- VARIABLES: + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + sBlockingConsumerCount 38CE 6 6 5 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss +MODULE: -- death.c.o -- +- PROCEDURES: + vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 + vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 +- VARIABLES: + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 59 0 + STRING.C.o (ansibi.lib) 0 113 0 + rtshc12.c.o (ansibi.lib) 0 412 0 + Cpu.C.o 0 125 0 + IO_Map.C.o 577 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 9 0 + main.c.o 1 318 6 + ParTest.c.o 0 54 0 + serial.c.o 4 177 0 + tasks.c.o 151 1796 5 + queue.c.o 0 933 0 + list.c.o 0 203 0 + heap_2.c.o 10253 234 0 + TickTimer.C.o 2 143 0 + PE_Timer.C.o 0 67 0 + Byte1.C.o 8 61 0 + flash.c.o 1 129 5 + dynamic.c.o 28 578 39 + PollQ.c.o 4 273 16 + comtest.c.o 4 285 12 + COM0.C.o 13 67 0 + port.c.o 1 150 0 + integer.c.o 1 223 8 + BlockQ.c.o 24 523 48 + death.c.o 10 335 44 + other 128 30 27 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init memcpy memset strncpy main vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED + vParTestToggleLED xSerialPortInitMinimal xSerialGetChar +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted + uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority + xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 + pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList + pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd + uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 + xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount + sBlockingProducerCount sLastBlockingConsumerCount.7 + sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart + usLastCreationCount.6 uxTasksRunningNow.7 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 + STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 + STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 + STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 +SECTION: "NON_BANKED" + _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS + Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt +SECTION: ".common" + xSuspendedTestQueue xCreatedTask1 xCreatedTask2 +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_PutBit Byte1_NegBit +SECTION: "COM0_CODE" + HWEnDi COM0_SetBaudRateMode COM0_Init +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_17f" + _CAN0TXTBPR +SECTION: ".abs_section_182" + _CAN1BTR0 +SECTION: ".abs_section_183" + _CAN1BTR1 +SECTION: ".abs_section_180" + _CAN1CTL0 +SECTION: ".abs_section_181" + _CAN1CTL1 +SECTION: ".abs_section_18b" + _CAN1IDAC +SECTION: ".abs_section_190" + _CAN1IDAR0 +SECTION: ".abs_section_191" + _CAN1IDAR1 +SECTION: ".abs_section_192" + _CAN1IDAR2 +SECTION: ".abs_section_193" + _CAN1IDAR3 +SECTION: ".abs_section_198" + _CAN1IDAR4 +SECTION: ".abs_section_199" + _CAN1IDAR5 +SECTION: ".abs_section_19a" + _CAN1IDAR6 +SECTION: ".abs_section_19b" + _CAN1IDAR7 +SECTION: ".abs_section_194" + _CAN1IDMR0 +SECTION: ".abs_section_195" + _CAN1IDMR1 +SECTION: ".abs_section_196" + _CAN1IDMR2 +SECTION: ".abs_section_197" + _CAN1IDMR3 +SECTION: ".abs_section_19c" + _CAN1IDMR4 +SECTION: ".abs_section_19d" + _CAN1IDMR5 +SECTION: ".abs_section_19e" + _CAN1IDMR6 +SECTION: ".abs_section_19f" + _CAN1IDMR7 +SECTION: ".abs_section_184" + _CAN1RFLG +SECTION: ".abs_section_185" + _CAN1RIER +SECTION: ".abs_section_1ac" + _CAN1RXDLR +SECTION: ".abs_section_1a4" + _CAN1RXDSR0 +SECTION: ".abs_section_1a5" + _CAN1RXDSR1 +SECTION: ".abs_section_1a6" + _CAN1RXDSR2 +SECTION: ".abs_section_1a7" + _CAN1RXDSR3 +SECTION: ".abs_section_1a8" + _CAN1RXDSR4 +SECTION: ".abs_section_1a9" + _CAN1RXDSR5 +SECTION: ".abs_section_1aa" + _CAN1RXDSR6 +SECTION: ".abs_section_1ab" + _CAN1RXDSR7 +SECTION: ".abs_section_18e" + _CAN1RXERR +SECTION: ".abs_section_1a0" + _CAN1RXIDR0 +SECTION: ".abs_section_1a1" + _CAN1RXIDR1 +SECTION: ".abs_section_1a2" + _CAN1RXIDR2 +SECTION: ".abs_section_1a3" + _CAN1RXIDR3 +SECTION: ".abs_section_189" + _CAN1TAAK +SECTION: ".abs_section_188" + _CAN1TARQ +SECTION: ".abs_section_18a" + _CAN1TBSEL +SECTION: ".abs_section_186" + _CAN1TFLG +SECTION: ".abs_section_187" + _CAN1TIER +SECTION: ".abs_section_1bc" + _CAN1TXDLR +SECTION: ".abs_section_1b4" + _CAN1TXDSR0 +SECTION: ".abs_section_1b5" + _CAN1TXDSR1 +SECTION: ".abs_section_1b6" + _CAN1TXDSR2 +SECTION: ".abs_section_1b7" + _CAN1TXDSR3 +SECTION: ".abs_section_1b8" + _CAN1TXDSR4 +SECTION: ".abs_section_1b9" + _CAN1TXDSR5 +SECTION: ".abs_section_1ba" + _CAN1TXDSR6 +SECTION: ".abs_section_1bb" + _CAN1TXDSR7 +SECTION: ".abs_section_18f" + _CAN1TXERR +SECTION: ".abs_section_1b0" + _CAN1TXIDR0 +SECTION: ".abs_section_1b1" + _CAN1TXIDR1 +SECTION: ".abs_section_1b2" + _CAN1TXIDR2 +SECTION: ".abs_section_1b3" + _CAN1TXIDR3 +SECTION: ".abs_section_1bf" + _CAN1TXTBPR +SECTION: ".abs_section_1c2" + _CAN2BTR0 +SECTION: ".abs_section_1c3" + _CAN2BTR1 +SECTION: ".abs_section_1c0" + _CAN2CTL0 +SECTION: ".abs_section_1c1" + _CAN2CTL1 +SECTION: ".abs_section_1cb" + _CAN2IDAC +SECTION: ".abs_section_1d0" + _CAN2IDAR0 +SECTION: ".abs_section_1d1" + _CAN2IDAR1 +SECTION: ".abs_section_1d2" + _CAN2IDAR2 +SECTION: ".abs_section_1d3" + _CAN2IDAR3 +SECTION: ".abs_section_1d8" + _CAN2IDAR4 +SECTION: ".abs_section_1d9" + _CAN2IDAR5 +SECTION: ".abs_section_1da" + _CAN2IDAR6 +SECTION: ".abs_section_1db" + _CAN2IDAR7 +SECTION: ".abs_section_1d4" + _CAN2IDMR0 +SECTION: ".abs_section_1d5" + _CAN2IDMR1 +SECTION: ".abs_section_1d6" + _CAN2IDMR2 +SECTION: ".abs_section_1d7" + _CAN2IDMR3 +SECTION: ".abs_section_1dc" + _CAN2IDMR4 +SECTION: ".abs_section_1dd" + _CAN2IDMR5 +SECTION: ".abs_section_1de" + _CAN2IDMR6 +SECTION: ".abs_section_1df" + _CAN2IDMR7 +SECTION: ".abs_section_1c4" + _CAN2RFLG +SECTION: ".abs_section_1c5" + _CAN2RIER +SECTION: ".abs_section_1ec" + _CAN2RXDLR +SECTION: ".abs_section_1e4" + _CAN2RXDSR0 +SECTION: ".abs_section_1e5" + _CAN2RXDSR1 +SECTION: ".abs_section_1e6" + _CAN2RXDSR2 +SECTION: ".abs_section_1e7" + _CAN2RXDSR3 +SECTION: ".abs_section_1e8" + _CAN2RXDSR4 +SECTION: ".abs_section_1e9" + _CAN2RXDSR5 +SECTION: ".abs_section_1ea" + _CAN2RXDSR6 +SECTION: ".abs_section_1eb" + _CAN2RXDSR7 +SECTION: ".abs_section_1ce" + _CAN2RXERR +SECTION: ".abs_section_1e0" + _CAN2RXIDR0 +SECTION: ".abs_section_1e1" + _CAN2RXIDR1 +SECTION: ".abs_section_1e2" + _CAN2RXIDR2 +SECTION: ".abs_section_1e3" + _CAN2RXIDR3 +SECTION: ".abs_section_1c9" + _CAN2TAAK +SECTION: ".abs_section_1c8" + _CAN2TARQ +SECTION: ".abs_section_1ca" + _CAN2TBSEL +SECTION: ".abs_section_1c6" + _CAN2TFLG +SECTION: ".abs_section_1c7" + _CAN2TIER +SECTION: ".abs_section_1fc" + _CAN2TXDLR +SECTION: ".abs_section_1f4" + _CAN2TXDSR0 +SECTION: ".abs_section_1f5" + _CAN2TXDSR1 +SECTION: ".abs_section_1f6" + _CAN2TXDSR2 +SECTION: ".abs_section_1f7" + _CAN2TXDSR3 +SECTION: ".abs_section_1f8" + _CAN2TXDSR4 +SECTION: ".abs_section_1f9" + _CAN2TXDSR5 +SECTION: ".abs_section_1fa" + _CAN2TXDSR6 +SECTION: ".abs_section_1fb" + _CAN2TXDSR7 +SECTION: ".abs_section_1cf" + _CAN2TXERR +SECTION: ".abs_section_1f0" + _CAN2TXIDR0 +SECTION: ".abs_section_1f1" + _CAN2TXIDR1 +SECTION: ".abs_section_1f2" + _CAN2TXIDR2 +SECTION: ".abs_section_1f3" + _CAN2TXIDR3 +SECTION: ".abs_section_1ff" + _CAN2TXTBPR +SECTION: ".abs_section_202" + _CAN3BTR0 +SECTION: ".abs_section_203" + _CAN3BTR1 +SECTION: ".abs_section_200" + _CAN3CTL0 +SECTION: ".abs_section_201" + _CAN3CTL1 +SECTION: ".abs_section_20b" + _CAN3IDAC +SECTION: ".abs_section_210" + _CAN3IDAR0 +SECTION: ".abs_section_211" + _CAN3IDAR1 +SECTION: ".abs_section_212" + _CAN3IDAR2 +SECTION: ".abs_section_213" + _CAN3IDAR3 +SECTION: ".abs_section_218" + _CAN3IDAR4 +SECTION: ".abs_section_219" + _CAN3IDAR5 +SECTION: ".abs_section_21a" + _CAN3IDAR6 +SECTION: ".abs_section_21b" + _CAN3IDAR7 +SECTION: ".abs_section_214" + _CAN3IDMR0 +SECTION: ".abs_section_215" + _CAN3IDMR1 +SECTION: ".abs_section_216" + _CAN3IDMR2 +SECTION: ".abs_section_217" + _CAN3IDMR3 +SECTION: ".abs_section_21c" + _CAN3IDMR4 +SECTION: ".abs_section_21d" + _CAN3IDMR5 +SECTION: ".abs_section_21e" + _CAN3IDMR6 +SECTION: ".abs_section_21f" + _CAN3IDMR7 +SECTION: ".abs_section_204" + _CAN3RFLG +SECTION: ".abs_section_205" + _CAN3RIER +SECTION: ".abs_section_22c" + _CAN3RXDLR +SECTION: ".abs_section_224" + _CAN3RXDSR0 +SECTION: ".abs_section_225" + _CAN3RXDSR1 +SECTION: ".abs_section_226" + _CAN3RXDSR2 +SECTION: ".abs_section_227" + _CAN3RXDSR3 +SECTION: ".abs_section_228" + _CAN3RXDSR4 +SECTION: ".abs_section_229" + _CAN3RXDSR5 +SECTION: ".abs_section_22a" + _CAN3RXDSR6 +SECTION: ".abs_section_22b" + _CAN3RXDSR7 +SECTION: ".abs_section_20e" + _CAN3RXERR +SECTION: ".abs_section_220" + _CAN3RXIDR0 +SECTION: ".abs_section_221" + _CAN3RXIDR1 +SECTION: ".abs_section_222" + _CAN3RXIDR2 +SECTION: ".abs_section_223" + _CAN3RXIDR3 +SECTION: ".abs_section_209" + _CAN3TAAK +SECTION: ".abs_section_208" + _CAN3TARQ +SECTION: ".abs_section_20a" + _CAN3TBSEL +SECTION: ".abs_section_206" + _CAN3TFLG +SECTION: ".abs_section_207" + _CAN3TIER +SECTION: ".abs_section_23c" + _CAN3TXDLR +SECTION: ".abs_section_234" + _CAN3TXDSR0 +SECTION: ".abs_section_235" + _CAN3TXDSR1 +SECTION: ".abs_section_236" + _CAN3TXDSR2 +SECTION: ".abs_section_237" + _CAN3TXDSR3 +SECTION: ".abs_section_238" + _CAN3TXDSR4 +SECTION: ".abs_section_239" + _CAN3TXDSR5 +SECTION: ".abs_section_23a" + _CAN3TXDSR6 +SECTION: ".abs_section_23b" + _CAN3TXDSR7 +SECTION: ".abs_section_20f" + _CAN3TXERR +SECTION: ".abs_section_230" + _CAN3TXIDR0 +SECTION: ".abs_section_231" + _CAN3TXIDR1 +SECTION: ".abs_section_232" + _CAN3TXIDR2 +SECTION: ".abs_section_233" + _CAN3TXIDR3 +SECTION: ".abs_section_23f" + _CAN3TXTBPR +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2bf" + _CAN4TXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_ec" + _DLCBARD +SECTION: ".abs_section_e8" + _DLCBCR1 +SECTION: ".abs_section_ea" + _DLCBCR2 +SECTION: ".abs_section_eb" + _DLCBDR +SECTION: ".abs_section_ed" + _DLCBRSR +SECTION: ".abs_section_e9" + _DLCBSVR +SECTION: ".abs_section_ee" + _DLCSCR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_3d" + _FORBYP +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_6d" + _TIMTST +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + CmpHighVal +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "COM0_DATA" + COM0_PrescHigh.1 SerFlag PrescHigh NumMode +SECTION: "ROM_PAGE31_524" + xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil vTaskDelay + uxTaskPriorityGet +SECTION: "ROM_PAGE32_525" + vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler + vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks +SECTION: "ROM_PAGE33_526" + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists +SECTION: "ROM_PAGE34_527" + prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB + xQueueCreate xQueueSend xQueueSendFromISR +SECTION: "ROM_PAGE35_528" + xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue + prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem + vListInsertEnd +SECTION: "ROM_PAGE36_529" + vListInsert vListRemove pvPortMalloc vPortFree PE_Timer_LngHi1 + vStartLEDFlashTasks vLEDFlashTask +SECTION: "ROM_PAGE37_530" + vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask + vCounterControlTask vQueueSendWhenSuspendedTask + vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning +SECTION: "ROM_PAGE38_531" + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vAltStartComTestTasks vComTxTask vComRxTask + xAreComTestTasksStillRunning +SECTION: "ROM_PAGE39_532" + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartIntegerMathTasks vCompeteingIntMathTask + xAreIntegerMathsTaskStillRunning +SECTION: "ROM_PAGE3A_533" + vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer + xAreBlockingQueuesStillRunning vCreateSuicidalTasks +SECTION: "ROM_PAGE3B_534" + vSuicidalTask vCreateTasks xIsCreateTaskStillRunning + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 6 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 1 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _FORBYP 3D 1 1 0 .abs_section_3d + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 2 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 1 .abs_section_6b + _TIMTST 6D 1 1 0 .abs_section_6d + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 1 .abs_section_c4 + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCSCR EE 1 1 0 .abs_section_ee + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 1 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 2 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + uxCriticalNesting 1000 1 1 101 .data + xLocalError 1001 1 1 2 .bss + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss + uxFlashTaskNumber 38AA 1 1 2 .bss + usCheckVariable 38AB 2 2 4 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss + xPort 38C9 2 2 2 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss + xTaskCheck 38CD 1 1 3 .bss + sBlockingConsumerCount 38CE 6 6 5 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xSuspendedTestQueue 38EC 2 2 3 .common + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + CmpHighVal 38F2 2 2 2 TickTimer_DATA + Byte1_Table 38F4 8 8 1 Byte1_DATA + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + STRING.Check.1 C09A 6 6 1 .rodata1 + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + _Startup C151 12 18 1 NON_BANKED + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED + Cpu_Interrupt C2FF 1 1 60 NON_BANKED + vCOM0_ISR C300 59 89 1 NON_BANKED + xBankedStartScheduler C359 13 19 1 NON_BANKED + vPortYield C36C 1D 29 1 NON_BANKED + vPortTickInterrupt C389 25 37 1 NON_BANKED + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + Init 308000 29 41 2 .text + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text + main 30809A 9 9 0 .text + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 33 51 3 .text + prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text + vApplicationIdleHook 308171 70 112 2 .text + vParTestSetLED 3081E1 22 34 4 .text + vParTestToggleLED 308203 14 20 10 .text + xSerialPortInitMinimal 308217 24 36 2 .text + xSerialGetChar 30823B 17 23 2 .text + xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 + xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 + vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 + vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 + uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 + vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 + vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 + vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 + xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 + prvIdleTask 338192 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 + prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 + xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 + xQueueSend 348119 D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 + xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 + prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 + vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 + vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 + vListInsert 368000 5A 90 8 ROM_PAGE36_529 + vListRemove 36805A 23 35 32 ROM_PAGE36_529 + pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 + vPortFree 368133 34 52 10 ROM_PAGE36_529 + PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 + vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 + vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 + vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 + vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 + vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 + vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 + vComTxTask 38815E 51 81 3 ROM_PAGE38_531 + vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 + xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 + pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 + prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 + xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 + vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 + vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 + vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 + SetCV 3B811C F 15 4 TickTimer_CODE + SetPV 3B812B C 12 2 TickTimer_CODE + HWEnDi 3B8137 8 8 4 TickTimer_CODE + TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE + TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE + TickTimer_Init 3B8196 15 21 2 TickTimer_CODE + Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE + Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE + Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE + HWEnDi 3B81E8 A 10 2 COM0_CODE + COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE + COM0_Init 3B820B 20 32 2 COM0_CODE + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansibi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansibi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS + _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +serial.c.o: + vSerialClose +tasks.c.o: + vTaskEndScheduler +queue.c.o: + vQueueDelete +TickTimer.C.o: + TickTimer_Interrupt TickTimer_SetPeriodTicks16 TickTimer_SetPeriodTicks32 + TickTimer_SetPeriodUS TickTimer_SetPeriodMS +PE_Timer.C.o: + PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 +port.c.o: + vPortEndScheduler +NOT USED VARIABLES +STRING.C.o (ansibi.lib): + STRING..1 next.2 +rtshc12.c.o (ansibi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg +heap_2.c.o: + heapSTRUCT_SIZE +death.c.o: + uxMaxNumberOfExtraTasksRunning + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xC3AE ---- SIZE 4 --- +Filling bytes inserted + 00011000 +------- ROM-ADDRESS: 0xC3B2 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xC3B3 ---- SIZE 4 --- +Filling bytes inserted + 001038F4 +------- ROM-ADDRESS: 0xC3B7 ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xC3BF ---- SIZE 1 --- +Filling bytes inserted + 00 +------- ROM-ADDRESS: 0xC3C0 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- +Name of initialized Object : COM0_PrescHigh.1:1 + 29005100A3 0146 +------- ROM-ADDRESS: 0xC3C7 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR + _REFDV _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB + _DDRAB _DDRS _PTS COM0_Init _INTCR +_Startup USES _startupData Init +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR + _SCI0CR2 xCharsForTx xQueueReceiveFromISR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt + vPortYield _EntryPoint +Init USES _startupData +main USES PE_low_level_init vMain +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks + vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks + STRING.Check.1 xTaskCreate vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning + xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning + xIsCreateTaskStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vParTestSetLED USES uxCriticalNesting Byte1_PutBit +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx + COM0_SetBaudRateMode +xSerialGetChar USES xRxedChars xQueueReceive +xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove + xTasksWaitingTermination vListInsertEnd uxTasksDeleted +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 + xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList + vListInitialise +prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll + xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove + uxCurrentNumberOfTasks prvDeleteTCB +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +prvDeleteTCB USES vPortFree +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap + xStart xEnd xTaskResumeAll +vPortFree USES vTaskSuspendAll xStart xTaskResumeAll +PE_Timer_LngHi1 USES _LCMP +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask + STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 +vComTxTask USES xPort xSerialPutChar uxBaseLED + vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay +vComRxTask USES uxBaseLED vParTestToggleLED vParTestSetLED + uxRxLoops xPort xSerialGetChar +xAreComTestTasksStillRunning USES uxRxLoops +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 + xTaskCheck xTaskCreate +vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting +xAreIntegerMathsTaskStillRunning USES xTaskCheck +vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate + sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer + STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer + STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc +vBlockingQueueProducer USES xQueueSend +vBlockingQueueConsumer USES xQueueReceive +xAreBlockingQueuesStillRunning USES sBlockingConsumerCount + sLastBlockingConsumerCount.7 sBlockingProducerCount + sLastBlockingProducerCount.8 +vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 + xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart +vSuicidalTask USES _LMUL vTaskDelay vTaskDelete +vCreateTasks USES vPortFree vTaskDelay vSuicidalTask + STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 + STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 + usCreationCount vCreateTasks +xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount + uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES _TFLG1 _TIE +TickTimer_Enable USES HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal SetCV SetPV HWEnDi +Byte1_GetMsk USES Byte1_Table +Byte1_PutBit USES Byte1_GetMsk _PORTAB +Byte1_NegBit USES Byte1_GetMsk _PORTAB +HWEnDi USES _SCI0CR2 +COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD +COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 + _SCI0SR1 _SCI0CR2 _SCI0BD HWEnDi + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | | + | | | +- SetCV + | | | | + | | | +- SetPV + | | | | + | | | +- HWEnDi + | | | + | | +- COM0_Init + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vAltStartComTestTasks + | | | + | | +- xSerialPortInitMinimal + | | | | + | | | +- xQueueCreate (see above) + | | | | + | | | +- COM0_SetBaudRateMode + | | | + | | +- vComTxTask + | | | | + | | | +- xSerialPutChar + | | | | | + | | | | +- xQueueSend (see above) + | | | | + | | | +- vParTestToggleLED (see above) + | | | | + | | | +- vParTestSetLED + | | | | | + | | | | +- Byte1_PutBit + | | | | | + | | | | +- Byte1_GetMsk (see above) + | | | | + | | | +- xTaskGetTickCount (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vComRxTask + | | | + | | +- vParTestToggleLED (see above) + | | | + | | +- vParTestSetLED (see above) + | | | + | | +- xSerialGetChar + | | | + | | +- xQueueReceive (see above) + | | + | +- vStartBlockingQueueTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vBlockingQueueConsumer + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vBlockingQueueProducer + | | | | + | | | +- xQueueSend (see above) + | | | + | | +- pvPortMalloc (see above) + | | + | +- vStartIntegerMathTasks + | | | + | | +- vCompeteingIntMathTask + | | | | + | | | +- _LNEG + | | | | + | | | +- _LDIVS + | | | | | + | | | | +- _NEG_P + | | | | | + | | | | +- _lDivMod + | | | | + | | | +- _LCMP_P (see above) + | | | + | | +- xTaskCreate (see above) + | | + | +- vCreateSuicidalTasks + | | | + | | +- pvPortMalloc (see above) + | | | + | | +- vCreateTasks + | | | | + | | | +- vPortFree (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vSuicidalTask + | | | | | + | | | | +- _LMUL + | | | | | + | | | | +- vTaskDelay (see above) + | | | | | + | | | | +- vTaskDelete + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- xTaskCreate (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- uxTaskGetNumberOfTasks + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | | + | | | +- xAreComTestTasksStillRunning + | | | | + | | | +- xAreIntegerMathsTaskStillRunning + | | | | + | | | +- xAreBlockingQueuesStillRunning + | | | | + | | | +- xIsCreateTaskStillRunning + | | | | + | | | +- uxTaskGetNumberOfTasks (see above) + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- prvDeleteTCB + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG (see above) + | | | + | | +- _LDIVS (see above) + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vCOM0_ISR + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- xQueueReceiveFromISR + | | + | +- memcpy (see above) + | | + | +- xTaskRemoveFromEventList (see above) + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 19 +Total size of all blocks to be downloaded: 7635 + diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd new file mode 100644 index 000000000..eecca9d13 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd @@ -0,0 +1,66 @@ +// HCS12 Core erasing + unsecuring command file: +// These commands mass erase the chip then program the security byte to 0xFE (unsecured state). + +// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers: + +// An average programming clock of 175 kHz is chosen. + +// If the oscillator frequency is less than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ". + +// If the oscillator frequency is higher than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)". + +// Datasheet proposed values: +// +// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal) +// +// 16 MHz $49 +// 8 MHz $27 +// 4 MHz $13 +// 2 MHz $9 +// 1 MHz $4 + +define CLKDIV 0x49 + +FLASH MEMUNMAP // do not interact with regular flash programming monitor + +//mass erase flash +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x103 0 // FCFNG select block 0 +wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +ww 0x108 0xD000 // write to FADDR address register +ww 0x10A 0x0000 // write to FDATA data register +wb 0x106 0x41 // write MASS ERASE command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +//mass erase eeprom +wb 0x110 CLKDIV // set ECLKDV clock divider +wb 0x114 0xFF // EPROT all protection disabled +wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register +ww 0x118 0x0400 // write to EADDR eeprom address register +ww 0x11A 0x0000 // write to EDATA eeprom data register +wb 0x116 0x41 // write MASS ERASE command in ECMD register +wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command +wait 20 // wait for command to complete + +reset + +//reprogram Security byte to Unsecure state +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x103 0 // FCFNG select block 0 +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state +wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +reset + +FLASH MEMMAP // restore regular flash programming monitor +undef CLKDIV // undefine variable + diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd new file mode 100644 index 000000000..52e399a61 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd @@ -0,0 +1 @@ +// After programming the flash, the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd new file mode 100644 index 000000000..048a6d94d --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd @@ -0,0 +1 @@ +// Before programming the flash, the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/main.c b/Demo/HCS12_CodeWarrior_banked/main.c new file mode 100644 index 000000000..ac463e406 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/main.c @@ -0,0 +1,291 @@ + +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * + * vMain() is effectively the demo application entry point. It is called by + * the main() function generated by the Processor Expert application. + * + * vMain() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * This file also includes the functionality implemented within the + * standard demo application file integer.c. This is done to demonstrate the + * use of an idle hook. See the documentation within integer.c for the + * rationale of the integer task functionality. + * */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "flash.h" +#include "PollQ.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" +#include "BlockQ.h" +#include "integer.h" +#include "death.h" + + +/*----------------------------------------------------------- + Definitions. +-----------------------------------------------------------*/ + +/* Priorities assigned to demo application tasks. */ +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +then the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 7 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The constants used in the idle task calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + + +/* Baud rate used by the serial port tasks (ComTest tasks). +IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the +Processor Expert is used to set the baud rate. As configured in the FreeRTOS +download this value must be one of the following: + +0 to configure for 38400 baud. +1 to configure for 19200 baud. +2 to configure for 9600 baud. +3 to configure for 4800 baud. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/*----------------------------------------------------------- + Local functions prototypes. +-----------------------------------------------------------*/ + +/* + * The 'Check' task function. See the explanation at the top of the file. + */ +static void vErrorChecks( void* pvParameters ); + +/* + * The idle task hook - in which the integer task is implemented. See the + * explanation at the top of the file. + */ +void vApplicationIdleHook( void ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + + +/*----------------------------------------------------------- + Local variables. +-----------------------------------------------------------*/ + +/* A few tasks are defined within this file. This flag is used to indicate +their status. If an error is detected in one of the locally defined tasks then +this flag is set to pdTRUE. */ +portBASE_TYPE xLocalError = pdFALSE; + + +/*-----------------------------------------------------------*/ + +/* + * This is called from the main() function generated by the Processor Expert. + */ +void vMain( void ) +{ + /* Start some of the standard demo tasks. */ + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the locally defined tasks. There is also a task implemented as + the idle hook. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Must be the last demo created. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* All the tasks have been created - start the scheduler. */ + vTaskStartScheduler(); + + /* Should not reach here! */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the demo application tasks are executing without + error. If an error is found the delay period is shortened - this + has the effect of increasing the flash rate of the 'check' task + LED. */ + if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + /* Toggle the LED each cycle round. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xAllTasksPassed = pdPASS; + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + /* Also check the status flag for the tasks defined within this function. */ + if( xLocalError != pdFALSE ) + { + xAllTasksPassed = pdFAIL; + } + + return xAllTasksPassed; +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +/* This variable is effectively set to a constant so it is made volatile to +ensure the compiler does not just get rid of it. */ +volatile portLONG lValue; + + /* Keep performing a calculation and checking the result against a constant. */ + + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* Did we perform the calculation correctly with no corruption? */ + if( lValue != intgEXPECTED_ANSWER ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif +} +/*-----------------------------------------------------------*/ + + + diff --git a/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl b/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl new file mode 100644 index 000000000..639ffdef3 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl @@ -0,0 +1,223 @@ +/* logical s-record file */ +OPENFILE "%ABS_FILE%.s19" +format=motorola +busWidth=1 +origin=0 +len=0x1000000 +destination=0 +SRECORD=Sx +SENDBYTE 1 "%ABS_FILE%" +CLOSE + +/* physical s-record file */ +OPENFILE "%ABS_FILE%.phy" +format = motorola +busWidth = 1 +len = 0x4000 + +origin = 0x008000 +destination = 0x000000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x004000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x028000 +destination = 0x008000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x038000 +destination = 0x00C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x048000 +destination = 0x010000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x058000 +destination = 0x014000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x068000 +destination = 0x018000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x078000 +destination = 0x01C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x088000 +destination = 0x020000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x098000 +destination = 0x024000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0A8000 +destination = 0x028000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0B8000 +destination = 0x02C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0C8000 +destination = 0x030000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0D8000 +destination = 0x034000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0E8000 +destination = 0x038000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0F8000 +destination = 0x03C000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x108000 +destination = 0x040000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x044000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x128000 +destination = 0x048000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x138000 +destination = 0x04C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x148000 +destination = 0x050000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x158000 +destination = 0x054000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x168000 +destination = 0x058000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x178000 +destination = 0x05C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x188000 +destination = 0x060000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x198000 +destination = 0x064000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x1A8000 +destination = 0x068000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x1B8000 +destination = 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"%ABS_FILE%" +origin = 0x398000 +destination = 0x0E4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3A8000 +destination = 0x0E8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3B8000 +destination = 0x0EC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3C8000 +destination = 0x0F0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3D8000 +destination = 0x0F4000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x3E8000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x004000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x3F8000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x00C000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +CLOSE + diff --git a/Demo/HCS12_CodeWarrior_banked/readme.txt b/Demo/HCS12_CodeWarrior_banked/readme.txt new file mode 100644 index 000000000..2e954115f --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/readme.txt @@ -0,0 +1,121 @@ +//------------------------------------------------------------------------ +// Readme.txt +//------------------------------------------------------------------------ +This project stationery is designed to get you up and running +quickly with CodeWarrior for MC9S12DP256B. +It is set up for the selected CPU and target connection, +but can be easily modified. + +Sample code for the following language(s) is at your disposal: +- C + +The wizard has prepared CodeWarrior target(s) with the connection methods of +your choice: +- Simulator: + This interface/target is prepared to use the FCS (Full Chip Simulation). + +- P&E ICD12: + This enables to debug with the P&E ICD12 target interface. + The P&E ICD12 target interface allows to debug using the + BDM connector with P&E BDM Multilink or Cable12 hardware. + The BDM Multilink and Cable12 connect to the host parallel port. + Please consult your hardware documentation for additional details. + + +Additional connections can be chosen in the simulator/debugger, +use the menu Component > Set Target. + +//------------------------------------------------------------------------ +// Processor Expert +//------------------------------------------------------------------------ +This project is prepared to be designed with Processor Expert. +The project has an additional 'tab' named 'Processor Expert' where you +can configure the CPU and its beans. +The CPU selected is inserted into the Processor Expert project panel, in +the Debug and Release configurations. +Change of the configuration is possible by the mouse double-click on it. +All the installed Embedded Beans are accessible in the Bean Selector +window, grouped into folders according to their function. The mouse +double-click on selected Embedded Bean in the Bean Selector window adds +the Bean to the project. The mouse double-click on the Bean icon in the +Project panel opens the Bean Inspector window, which is used to set the +Bean properties. Source code is generated after selecting the +(Code Design 'Project_name.mcp') menu command from the CodeWarrior main +window (Processor Expert > Code design 'Project_name.mcp'). +Use the bean methods and events to write your code in the main module +'Project_name'.c and the event module Events.c. + +For more help please read Processor Expert help: + (Processor Expert > Help > 'Topic'). + +The following folders are used in CodeWarrior project window for +ProcessorExpert: +- User modules: contains your sources. The main module 'Project_name'.c + and event module Events.c are located here after the Processor Expert + code generation. +- Prm: Linker parameter file used for linking. Note that the file used + for the linker is specified in the Linker Preference Panel. To open + the Preference Panel, please press or open the + (Edit > 'Current Build Target Name' Settings...) menu item in the + CodeWarrior main window menu, while the project window is opened). + After Processor Expert code generation 'Project_name'.prm file + will be placed here. You can switch off the .prm file generation in + Processor Expert if you want (in the CPU bean, Build Options) +- Generated code: this folder appears after the Processor Expert code + generation and contains generated code from Processor Expert. +- Doc: other files generated from the Processor Expert (documentation) + +//------------------------------------------------------------------------ +// Getting Started +//------------------------------------------------------------------------ +To build/debug your project, use the menu Project > Debug or press F5. +This will open the simulator/debugger. +Press again F5 in the debugger (or menu Run > Start/Continue) to start +the application. The menu Run > Halt or F6 stops the application. +In the debugger menu Component > Open you can load additional components. + +//------------------------------------------------------------------------ +// Project structure +//------------------------------------------------------------------------ +The project generated contains various files/folders: +- readme.txt: this file +- Sources: folder with the application source code +- Startup Code: C/C++ startup code +- Prm: + - burner.bbl file to generate S-Records +- Linker Map: the .map file generated by the linker +- Libraries: needed library files (ANSI, derivative header/implementation files) +- Debugger Project File: contains a .ini file for the debugger for each + connection +- Debugger Cmd Files: contains sub-folders for each connection with command + files + +//------------------------------------------------------------------------ +// Adding your own code +//------------------------------------------------------------------------ +Once everything is working as expected, you can begin adding your own code +to the project. Keep in mind that we provide this as an example of how to +get up and running quickly with CodeWarrior. There are certainly other +ways to handle interrupts and set up your linker command file. Feel free +to modify any of the source files provided. + +//------------------------------------------------------------------------ +// Simulator/Debugger: Additional components +//------------------------------------------------------------------------ +In the simulator/debugger, you can load additional components. Try the menu +Component > Open. + +//------------------------------------------------------------------------ +// Additional documentation +//------------------------------------------------------------------------ +Check out the online documentation provided. Use in CodeWarrior IDE the +menu Help > Online Manuals. + +//------------------------------------------------------------------------ +// Contacting Metrowerks +//------------------------------------------------------------------------ +For bug reports, technical questions, and suggestions, please use the +forms installed in the Release_Notes folder and send them to: +USA: support@metrowerks.com +EUROPE: support_europe@metrowerks.com +ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/Demo/HCS12_CodeWarrior_banked/serial/serial.c new file mode 100644 index 000000000..73f855423 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_banked/serial/serial.c @@ -0,0 +1,177 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. */ + +/* Processor Expert generated includes. */ +#include "com0.h" + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + +/* The queues used to communicate between the task code and the interrupt +service routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Interrupt identification bits. */ +#define serOVERRUN_INTERRUPT ( 0x08 ) +#define serRX_INTERRUPT ( 0x20 ) +#define serTX_INTERRUPT ( 0x80 ) + +/*-----------------------------------------------------------*/ + + +/* + * Initialise port for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Hardware setup is performed by the Processor Expert generated code. + This function just creates the queues used to communicate between the + interrupt code and the task code - then sets the required baud rate. */ + + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + COM0_SetBaudRateMode( ( portCHAR ) ulWantedBaud ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer queue. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SCI0CR2_SCTIE = 1;; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + +/* + * Interrupt service routine for the serial port. Must be in non-banked + * memory. + */ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +__interrupt void vCOM0_ISR( void ) +{ +volatile unsigned portCHAR ucByte, ucStatus; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* What caused the interrupt? */ + ucStatus = SCI0SR1; + + if( ucStatus & serOVERRUN_INTERRUPT ) + { + /* The interrupt was caused by an overrun. Clear the error by reading + the data register. */ + ucByte = SCI0DRL; + } + + if( ucStatus & serRX_INTERRUPT ) + { + /* The interrupt was caused by a character being received. + Read the received byte. */ + ucByte = SCI0DRL; + + /* Post the character onto the queue of received characters - noting + whether or not this wakes a task. */ + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); + } + + if( ( ucStatus & serTX_INTERRUPT ) && ( SCI0CR2_SCTIE ) ) + { + /* The interrupt was caused by a character being transmitted. */ + if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE ) + { + /* Clear the SCRF bit. */ + SCI0DRL = ucByte; + } + else + { + /* Disable transmit interrupt */ + SCI0CR2_SCTIE = 0; + } + } + + if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) ) + { + portYIELD(); + } +} + +#pragma CODE_SEG DEFAULT + diff --git a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C new file mode 100644 index 000000000..cb2e67ac5 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C @@ -0,0 +1,117 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : ButtonInterrupt.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ExtInt +** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/05/2005, 19:02 +** Abstract : +** This bean "ExtInt" implements an external +** interrupt, its control methods and interrupt/event +** handling procedure. +** The bean uses one pin which generates interrupt on +** selected edge. +** Settings : +** Interrupt name : INT_PortP +** User handling procedure : ButtonInterrupt_OnInterrupt +** +** Used pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 4 | PP0_PWM0_KWP0 +** ---------------------------------------------------- +** +** Port name : P +** +** Bit number (in port) : 0 +** Bit mask of the port : 1 +** +** Signal edge/level : falling +** Priority : 1 +** Pull option : up +** Initial state : Disabled +** +** Edge register : PPSP [605] +** Priority register : HPRIO [31] +** Enable register : PIEP [606] +** Request register : PIFP [607] +** +** Port data register : PTP [600] +** Port control register : DDRP [602] +** Contents : +** Enable - void ButtonInterrupt_Enable(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE ButtonInterrupt. */ + +#include "ButtonInterrupt.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG ButtonInterrupt_DATA /* Data section for this module. */ +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : ButtonInterrupt_Enable (bean ExtInt) +** +** Description : +** Enable the bean - the external events are accepted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void ButtonInterrupt_Enable(void) +{ + PIFP = 1; /* Clear flag */ + PIEP_PIEP0 = 1; /* Enable interrupt */ +} + +/* +** =================================================================== +** Method : ButtonInterrupt_Interrupt (bean ExtInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void ButtonInterrupt_Interrupt(void) +{ + PIFP = 1; /* Clear flag */ + ButtonInterrupt_OnInterrupt(); +} + +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +/* END ButtonInterrupt. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H new file mode 100644 index 000000000..c23f5160b --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H @@ -0,0 +1,109 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : ButtonInterrupt.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ExtInt +** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/05/2005, 19:02 +** Abstract : +** This bean "ExtInt" implements an external +** interrupt, its control methods and interrupt/event +** handling procedure. +** The bean uses one pin which generates interrupt on +** selected edge. +** Settings : +** Interrupt name : INT_PortP +** User handling procedure : ButtonInterrupt_OnInterrupt +** +** Used pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 4 | PP0_PWM0_KWP0 +** ---------------------------------------------------- +** +** Port name : P +** +** Bit number (in port) : 0 +** Bit mask of the port : 1 +** +** Signal edge/level : falling +** Priority : 1 +** Pull option : up +** Initial state : Disabled +** +** Edge register : PPSP [605] +** Priority register : HPRIO [31] +** Enable register : PIEP [606] +** Request register : PIFP [607] +** +** Port data register : PTP [600] +** Port control register : DDRP [602] +** Contents : +** Enable - void ButtonInterrupt_Enable(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __ButtonInterrupt_H +#define __ButtonInterrupt_H + +/* MODULE ButtonInterrupt. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +void ButtonInterrupt_Enable(void); +/* +** =================================================================== +** Method : ButtonInterrupt_Enable (bean ExtInt) +** +** Description : +** Enable the bean - the external events are accepted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void ButtonInterrupt_Interrupt(void); +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : ButtonInterrupt_Interrupt (bean ExtInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END ButtonInterrupt. */ + +#endif /* __ButtonInterrupt_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C new file mode 100644 index 000000000..5a5dc9b50 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C @@ -0,0 +1,144 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:49 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 0 = 000H +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 16 | PB0_ADDR0_DATA0 +** 1 | 17 | PB1_ADDR1_DATA1 +** 2 | 18 | PB2_ADDR2_DATA2 +** 3 | 19 | PB3_ADDR3_DATA3 +** 4 | 20 | PB4_ADDR4_DATA4 +** 5 | 21 | PB5_ADDR5_DATA5 +** 6 | 22 | PB6_ADDR6_DATA6 +** 7 | 23 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE Byte1. */ + +#include "Byte1.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_GetMsk (bean ByteIO) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ + +byte Byte1_GetMsk(byte Value) +{ + return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ +} + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** Bitnum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) /* Is bit mask correct? */ + if (Value) { /* Is it one to be written? */ + PORTB |= Mask; /* Set appropriate bit on port */ + } + else { /* Is it zero to be written? */ + PORTB &= ~Mask; /* Clear appropriate bit on port */ + } +} + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** Bit - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) { /* Is bit mask correct? */ + PORTB ^= Mask; /* Negate appropriate bit on port */ + } +} + + +/* END Byte1. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H new file mode 100644 index 000000000..c33dd528f --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H @@ -0,0 +1,110 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:49 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 0 = 000H +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 16 | PB0_ADDR0_DATA0 +** 1 | 17 | PB1_ADDR1_DATA1 +** 2 | 18 | PB2_ADDR2_DATA2 +** 3 | 19 | PB3_ADDR3_DATA3 +** 4 | 20 | PB4_ADDR4_DATA4 +** 5 | 21 | PB5_ADDR5_DATA5 +** 6 | 22 | PB6_ADDR6_DATA6 +** 7 | 23 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Byte1_H +#define __Byte1_H + +/* MODULE Byte1. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +#include "Cpu.h" + +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value); + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum); + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END Byte1. */ + +#endif /* __Byte1_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c b/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c new file mode 100644 index 000000000..38854b315 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c @@ -0,0 +1,115 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 18:22 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vButtonPush( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + vButtonPush, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + Cpu_Interrupt, /* 43 Default (unused) interrupt */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C new file mode 100644 index 000000000..970d653b8 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C @@ -0,0 +1,233 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 18:00 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE Cpu. */ + +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#define CGM_DELAY 3071UL + + +/* Global variables */ +volatile byte CCR_reg; /* Current CCR reegister */ +byte CpuMode = HIGH_SPEED; /* Current speed mode */ + + +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void) +{ +} + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12C32_80) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_DisableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12C32_80) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_EnableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_SetStopMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Stop mode. For more information +** about the stop mode see documentation of this CPU. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_SetStopMode(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_SetWaitMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Wait mode. For more information +** about the wait mode see documentation of this CPU. +** Release from Watch mode: Reset or interrupt +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_SetWaitMode(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : _EntryPoint (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ +#define INITRG_ADR 0x0011 /* Register map position register */ +#pragma NO_FRAME +#pragma NO_EXIT +void _EntryPoint(void) +{ + /*** ### MC9S12C32_80 "Cpu" init code ... ***/ + /*** PE initialization code after reset ***/ + /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ + *(byte*)INITRG_ADR = 0; /* Set the register map position */ + asm nop; /* nop instruction */ + INITRM=8; /* Set the RAM map position */ + /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ + MISC=1; + /* System clock initialization */ + CLKSEL=0; + CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ + PLLCTL_PLLON = 0; /* Disable the PLL */ + SYNR = 23; /* Set the multiplier register */ + REFDV = 15; /* Set the divider register */ + PLLCTL = 192; + PLLCTL_PLLON = 1; /* Enable the PLL */ + while(!CRGFLG_LOCK); /* Wait */ + CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ + /*** End of PE initialization code after reset ***/ + + __asm jmp _Startup; /* Jump to C startup code */ +} + +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_low_level_init(void) +{ + /* Common initialization of the CPU registers */ +/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ + output( TSCR1, input( TSCR1 ) & ~192 | 32 ); +/* TCTL2: OM0=0,OL0=0 */ + output( TCTL2, input( TCTL2 ) & ~3 ); +/* TCTL1: OM7=0,OL7=0 */ + output( TCTL1, input( TCTL1 ) & ~192 ); +/* TIE: C0I=0 */ + output( TIE, input( TIE ) & ~1 ); +/* TTOV: TOV0=0 */ + output( TTOV, input( TTOV ) & ~1 ); +/* TSCR2: TOI=0,TCRE=1 */ + output( TSCR2, input( TSCR2 ) & ~128 | 8 ); +/* TIOS: IOS7=1,IOS0=1 */ + output( TIOS, input( TIOS ) | 129 ); +/* PPSP: PPSP0=0 */ + output( PPSP, input( PPSP ) & ~1 ); +/* PERP: PERP0=1 */ + output( PERP, input( PERP ) | 1 ); +/* DDRP: DDRP0=0 */ + output( DDRP, input( DDRP ) & ~1 ); +/* PWMCTL: PSWAI=0,PFRZ=0 */ + output( PWMCTL, input( PWMCTL ) & ~12 ); +/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ + output( PWMSDN, 0 ); + /* ### MC9S12C32_80 "Cpu" init code ... */ + /* ### ByteIO "Byte1" init code ... */ + PORTB = 0; /* Prepare value for output */ + DDRB = 255; /* Set direction to output */ + /* ### TimerInt "TickTimer" init code ... */ + TickTimer_Init(); + /* ### External interrupt "ButtonInterrupt" init code ... */ + PIEP_PIEP0 = 0; /* Disable interrupt */ + /* Common peripheral initialization - ENABLE */ +/* TSCR1: TEN=1 */ + output( TSCR1, input( TSCR1 ) | 128 ); + INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ + __DI(); /* Disable interrupts */ +} + +/* END Cpu. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H new file mode 100644 index 000000000..a08230e92 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H @@ -0,0 +1,140 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Cpu +#define __Cpu + +/* Active configuration define symbol */ +#define PEcfg_80pin 1 + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* MODULE Cpu. */ + + +/* Global variables */ +extern volatile byte CCR_reg; /* Current CCR reegister */ +extern byte CpuMode; /* Current speed mode */ + + +#define Cpu_SetStopMode() __asm("STOP") /* Set STOP mode */ +/* +** =================================================================== +** Method : Cpu_SetStopMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Stop mode. For more information +** about the stop mode see documentation of this CPU. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_SetWaitMode() __asm("WAIT") /* Set WAIT mode */ +/* +** =================================================================== +** Method : Cpu_SetWaitMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Wait mode. For more information +** about the wait mode see documentation of this CPU. +** Release from Watch mode: Reset or interrupt +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + + +#define Cpu_DisableInt() __DI() /* Disable interrupts */ +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12C32_80) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_EnableInt() __EI() /* Enable interrupts */ +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12C32_80) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +void PE_low_level_init(void); +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +/* END Cpu. */ + +#endif /* ifndef __Cpu */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Events.C b/Demo/HCS12_CodeWarrior_small/CODE/Events.C new file mode 100644 index 000000000..6a3f6079a --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Events.C @@ -0,0 +1,87 @@ +/** ################################################################### +** Filename : Events.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** vTaskTickInterrupt - void vTaskTickInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE Events */ + + +/*Including used modules for compilling procedure*/ +#include "Cpu.h" +#include "Events.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* +** =================================================================== +** Event : vTaskTickInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void vTaskTickInterrupt(void) +{ + /* Write your code here ... */ +} + + +/* +** =================================================================== +** Event : ButtonInterrupt_OnInterrupt (module Events) +** +** From bean : ButtonInterrupt [ExtInt] +** Description : +** This event is called when the active signal edge/level +** occurs. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void ButtonInterrupt_OnInterrupt(void) +{ + /* place your ButtonInterrupt interrupt procedure body here */ +} + + +/* END Events */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Events.H b/Demo/HCS12_CodeWarrior_small/CODE/Events.H new file mode 100644 index 000000000..23f2c45b4 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Events.H @@ -0,0 +1,74 @@ +/** ################################################################### +** Filename : Events.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** vTaskTickInterrupt - void vTaskTickInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Events_H +#define __Events_H +/* MODULE Events */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +void vTaskTickInterrupt(void); +/* +** =================================================================== +** Event : vTaskTickInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + +void ButtonInterrupt_OnInterrupt(void); +/* +** =================================================================== +** Event : ButtonInterrupt_OnInterrupt (module Events) +** +** From bean : ButtonInterrupt [ExtInt] +** Description : +** This event is called when the active signal edge/level +** occurs. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* END Events */ +#endif /* __Events_H*/ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C new file mode 100644 index 000000000..ad23df3b1 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C @@ -0,0 +1,260 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* Based on CPU DB MC9S12C32_80, version 2.87.264 */ +#include "PE_types.h" +#include "IO_Map.h" + +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ +volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */ +volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */ +volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */ +volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ +volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ +volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ +volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */ +volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */ +volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */ +volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */ +volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */ +volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */ +volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */ +volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */ +volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */ +volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */ +volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */ +volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */ +volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */ +volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */ +volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */ +volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */ +volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */ +volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */ +volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */ +volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */ +volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */ +volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */ +volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */ +volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */ +volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */ +volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */ +volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */ +volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */ +volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */ +volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */ +volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */ +volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */ +volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */ +volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */ +volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */ +volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */ +volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */ +volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */ +volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */ +volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */ +volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */ +volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */ +volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */ +volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */ +volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */ +volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */ +volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */ +volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */ +volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */ +volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */ +volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */ +volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */ +volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */ +volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */ +volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */ +volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */ +volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ +volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ +volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ +volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ +volatile FPROTSTR _FPROT; /* Flash Protection Register */ +volatile FSECSTR _FSEC; /* Flash Security Register */ +volatile FSTATSTR _FSTAT; /* Flash Status Register */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ +volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ +volatile MODESTR _MODE; /* Mode Register */ +volatile MODRRSTR _MODRR; /* Module Routing Register */ +volatile MTST0STR _MTST0; /* MTST0 */ +volatile MTST1STR _MTST1; /* MTST1 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ +volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ +volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ +volatile PEARSTR _PEAR; /* Port E Assignment Register */ +volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ +volatile PORTESTR _PORTE; /* Port E Register */ +volatile PORTKSTR _PORTK; /* Port K Data Register */ +volatile PPAGESTR _PPAGE; /* Page Index Register */ +volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */ +volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ +volatile PTADSTR _PTAD; /* Port AD I/O Register */ +volatile PTIADSTR _PTIAD; /* Port AD Input Register */ +volatile PTIJSTR _PTIJ; /* Port J Input Register */ +volatile PTIMSTR _PTIM; /* Port M Input */ +volatile PTIPSTR _PTIP; /* Port P Input */ +volatile PTISSTR _PTIS; /* Port S Input */ +volatile PTITSTR _PTIT; /* Port T Input */ +volatile PTJSTR _PTJ; /* Port J I/O Register */ +volatile PTMSTR _PTM; /* Port M I/O Register */ +volatile PTPSTR _PTP; /* Port P I/O Register */ +volatile PTSSTR _PTS; /* Port S I/O Register */ +volatile PTTSTR _PTT; /* Port T I/O Register */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ +volatile PWMESTR _PWME; /* PWM Enable Register */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ +volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ +volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */ +volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */ +volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */ +volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */ +volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */ +volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */ +volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */ +volatile SPICR1STR _SPICR1; /* SPI Control Register */ +volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */ +volatile SPIDRSTR _SPIDR; /* SPI Data Register */ +volatile SPISRSTR _SPISR; /* SPI Status Register */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ +volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */ +volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ +volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */ +volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */ +volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */ +volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */ +volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */ +volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */ +volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */ +volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */ +volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */ +volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ +volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */ +volatile PORTABSTR _PORTAB; /* Port AB Register */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ +volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ +volatile TCNTSTR _TCNT; /* Timer Count Register */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H new file mode 100644 index 000000000..2ff2281a1 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H @@ -0,0 +1,8072 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* Linker pragmas */ +#pragma LINK_INFO DERIVATIVE "MC9S12C32" +#pragma LINK_INFO OSCFREQUENCY "16000000" + + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + +/* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */ +#ifndef _MC9S12C32_80_H +#define _MC9S12C32_80_H + +#include "PE_Types.h" + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ + +/*********************************************/ +/* */ +/* PE I/O map format */ +/* */ +/*********************************************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit 0 */ + byte BIT1 :1; /* Port A Bit 1 */ + byte BIT2 :1; /* Port A Bit 2 */ + byte BIT3 :1; /* Port A Bit 3 */ + byte BIT4 :1; /* Port A Bit 4 */ + byte BIT5 :1; /* Port A Bit 5 */ + byte BIT6 :1; /* Port A Bit 6 */ + byte BIT7 :1; /* Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0 */ + byte BIT1 :1; /* Port B Bit 1 */ + byte BIT2 :1; /* Port B Bit 2 */ + byte BIT3 :1; /* Port B Bit 3 */ + byte BIT4 :1; /* Port B Bit 4 */ + byte BIT5 :1; /* Port B Bit 5 */ + byte BIT6 :1; /* Port B Bit 6 */ + byte BIT7 :1; /* Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port AB Bit 0 */ + word BIT1 :1; /* Port AB Bit 1 */ + word BIT2 :1; /* Port AB Bit 2 */ + word BIT3 :1; /* Port AB Bit 3 */ + word BIT4 :1; /* Port AB Bit 4 */ + word BIT5 :1; /* Port AB Bit 5 */ + word BIT6 :1; /* Port AB Bit 6 */ + word BIT7 :1; /* Port AB Bit 7 */ + word BIT8 :1; /* Port AB Bit 8 */ + word BIT9 :1; /* Port AB Bit 9 */ + word BIT10 :1; /* Port AB Bit 10 */ + word BIT11 :1; /* Port AB Bit 11 */ + word BIT12 :1; /* Port AB Bit 12 */ + word BIT13 :1; /* Port AB Bit 13 */ + word BIT14 :1; /* Port AB Bit 14 */ + word BIT15 :1; /* Port AB Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 +#define PORTAB_BIT _PORTAB.MergedBits.grpBIT + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port B Bit 0 */ + word BIT1 :1; /* Data Direction Port B Bit 1 */ + word BIT2 :1; /* Data Direction Port B Bit 2 */ + word BIT3 :1; /* Data Direction Port B Bit 3 */ + word BIT4 :1; /* Data Direction Port B Bit 4 */ + word BIT5 :1; /* Data Direction Port B Bit 5 */ + word BIT6 :1; /* Data Direction Port B Bit 6 */ + word BIT7 :1; /* Data Direction Port B Bit 7 */ + word BIT8 :1; /* Data Direction Port A Bit 8 */ + word BIT9 :1; /* Data Direction Port A Bit 9 */ + word BIT10 :1; /* Data Direction Port A Bit 10 */ + word BIT11 :1; /* Data Direction Port A Bit 11 */ + word BIT12 :1; /* Data Direction Port A Bit 12 */ + word BIT13 :1; /* Data Direction Port A Bit 13 */ + word BIT14 :1; /* Data Direction Port A Bit 14 */ + word BIT15 :1; /* Data Direction Port A Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 +#define DDRAB_BIT _DDRAB.MergedBits.grpBIT + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + struct { + byte BIT15 :1; /* Timer Count Register Bit 15 */ + byte BIT14 :1; /* Timer Count Register Bit 14 */ + byte BIT13 :1; /* Timer Count Register Bit 13 */ + byte BIT12 :1; /* Timer Count Register Bit 12 */ + byte BIT11 :1; /* Timer Count Register Bit 11 */ + byte BIT10 :1; /* Timer Count Register Bit 10 */ + byte BIT9 :1; /* Timer Count Register Bit 9 */ + byte BIT8 :1; /* Timer Count Register Bit 8 */ + } Bits; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 + #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 + #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 + #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 + #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 + #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 + #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 + #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Count Register Bit 0 */ + byte BIT1 :1; /* Timer Count Register Bit 1 */ + byte BIT2 :1; /* Timer Count Register Bit 2 */ + byte BIT3 :1; /* Timer Count Register Bit 3 */ + byte BIT4 :1; /* Timer Count Bit Register 4 */ + byte BIT5 :1; /* Timer Count Bit Register 5 */ + byte BIT6 :1; /* Timer Count Bit Register 6 */ + byte BIT7 :1; /* Timer Count Bit Register 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 + #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 + #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 + #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 + #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 + #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 + #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 + #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 + #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); +#define TCNT _TCNT.Word +#define TCNT_BIT _TCNT.MergedBits.grpBIT + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 + #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 + #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 + #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 + #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 + #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 + #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 + #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 + #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 + #define TC0Hi_BIT TC0Hi_BIT_8 + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 + #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 + #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 + #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 + #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 + #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 + #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 + #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 + #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); +#define TC0 _TC0.Word +#define TC0_BIT _TC0.MergedBits.grpBIT + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 + #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 + #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 + #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 + #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 + #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 + #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 + #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 + #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 + #define TC1Hi_BIT TC1Hi_BIT_8 + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 + #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 + #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 + #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 + #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 + #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 + #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 + #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 + #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); +#define TC1 _TC1.Word +#define TC1_BIT _TC1.MergedBits.grpBIT + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 + #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 + #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 + #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 + #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 + #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 + #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 + #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 + #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 + #define TC2Hi_BIT TC2Hi_BIT_8 + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 + #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 + #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 + #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 + #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 + #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 + #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 + #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 + #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); +#define TC2 _TC2.Word +#define TC2_BIT _TC2.MergedBits.grpBIT + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 + #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 + #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 + #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 + #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 + #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 + #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 + #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 + #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 + #define TC3Hi_BIT TC3Hi_BIT_8 + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 + #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 + #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 + #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 + #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 + #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 + #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 + #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 + #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); +#define TC3 _TC3.Word +#define TC3_BIT _TC3.MergedBits.grpBIT + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 + #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 + #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 + #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 + #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 + #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 + #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 + #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 + #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 + #define TC4Hi_BIT TC4Hi_BIT_8 + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 + #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 + #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 + #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 + #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 + #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 + #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 + #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 + #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); +#define TC4 _TC4.Word +#define TC4_BIT _TC4.MergedBits.grpBIT + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 + #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 + #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 + #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 + #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 + #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 + #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 + #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 + #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 + #define TC5Hi_BIT TC5Hi_BIT_8 + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 + #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 + #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 + #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 + #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 + #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 + #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 + #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 + #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); +#define TC5 _TC5.Word +#define TC5_BIT _TC5.MergedBits.grpBIT + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 + #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 + #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 + #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 + #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 + #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 + #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 + #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 + #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 + #define TC6Hi_BIT TC6Hi_BIT_8 + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 + #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 + #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 + #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 + #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 + #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 + #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 + #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 + #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); +#define TC6 _TC6.Word +#define TC6_BIT _TC6.MergedBits.grpBIT + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 + #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 + #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 + #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 + #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 + #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 + #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 + #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 + #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 + #define TC7Hi_BIT TC7Hi_BIT_8 + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 + #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 + #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 + #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 + #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 + #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 + #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 + #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 + #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); +#define TC7 _TC7.Word +#define TC7_BIT _TC7.MergedBits.grpBIT + + +/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/ +typedef union { + word Word; + struct { + word grpBIT :16; + } MergedBits; +} PACNTSTR; +extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062); +#define PACNT _PACNT.Word +#define PACNT_BIT _PACNT.MergedBits.grpBIT + + +/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATDCTL2STR; + #define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte + #define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF + #define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE + #define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE + #define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP + #define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE + #define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI + #define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC + #define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU + + /*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATDCTL3STR; + #define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte + #define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0 + #define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1 + #define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO + #define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C + #define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C + #define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C + #define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C + #define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATDCTL23STR; +extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082); +#define ATDCTL23 _ATDCTL23.Word +#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0 +#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1 +#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO +#define ATDCTL23_S1C _ATDCTL23.Bits.S1C +#define ATDCTL23_S2C _ATDCTL23.Bits.S2C +#define ATDCTL23_S4C _ATDCTL23.Bits.S4C +#define ATDCTL23_S8C _ATDCTL23.Bits.S8C +#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF +#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE +#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE +#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP +#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE +#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI +#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC +#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU +#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ + + +/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* A/D Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATDCTL4STR; + #define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte + #define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0 + #define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1 + #define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2 + #define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3 + #define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4 + #define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0 + #define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1 + #define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8 + #define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS + #define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP + + /*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATDCTL5STR; + #define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte + #define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA + #define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB + #define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC + #define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT + #define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN + #define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN + #define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* A/D Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATDCTL45STR; +extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084); +#define ATDCTL45 _ATDCTL45.Word +#define ATDCTL45_CA _ATDCTL45.Bits.CA +#define ATDCTL45_CB _ATDCTL45.Bits.CB +#define ATDCTL45_CC _ATDCTL45.Bits.CC +#define ATDCTL45_MULT _ATDCTL45.Bits.MULT +#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN +#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN +#define ATDCTL45_DJM _ATDCTL45.Bits.DJM +#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0 +#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1 +#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2 +#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3 +#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4 +#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0 +#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1 +#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8 +#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS +#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP + + +/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR0HSTR; + #define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte + #define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8 + #define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9 + #define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10 + #define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11 + #define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12 + #define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13 + #define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14 + #define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15 + #define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8 + #define ATDDR0H_BIT ATDDR0H_BIT_8 + + /*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR0LSTR; + #define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte + #define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6 + #define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7 + #define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6 + #define ATDDR0L_BIT ATDDR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR0STR; +extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090); +#define ATDDR0 _ATDDR0.Word +#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6 +#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7 +#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8 +#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9 +#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10 +#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11 +#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12 +#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13 +#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14 +#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15 +#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6 +#define ATDDR0_BIT ATDDR0_BIT_6 + + +/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR1HSTR; + #define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte + #define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8 + #define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9 + #define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10 + #define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11 + #define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12 + #define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13 + #define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14 + #define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15 + #define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8 + #define ATDDR1H_BIT ATDDR1H_BIT_8 + + /*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR1LSTR; + #define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte + #define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6 + #define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7 + #define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6 + #define ATDDR1L_BIT ATDDR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR1STR; +extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092); +#define ATDDR1 _ATDDR1.Word +#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6 +#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7 +#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8 +#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9 +#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10 +#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11 +#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12 +#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13 +#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14 +#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15 +#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6 +#define ATDDR1_BIT ATDDR1_BIT_6 + + +/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR2HSTR; + #define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte + #define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8 + #define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9 + #define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10 + #define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11 + #define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12 + #define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13 + #define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14 + #define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15 + #define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8 + #define ATDDR2H_BIT ATDDR2H_BIT_8 + + /*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR2LSTR; + #define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte + #define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6 + #define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7 + #define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6 + #define ATDDR2L_BIT ATDDR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR2STR; +extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094); +#define ATDDR2 _ATDDR2.Word +#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6 +#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7 +#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8 +#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9 +#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10 +#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11 +#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12 +#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13 +#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14 +#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15 +#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6 +#define ATDDR2_BIT ATDDR2_BIT_6 + + +/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR3HSTR; + #define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte + #define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8 + #define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9 + #define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10 + #define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11 + #define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12 + #define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13 + #define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14 + #define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15 + #define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8 + #define ATDDR3H_BIT ATDDR3H_BIT_8 + + /*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR3LSTR; + #define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte + #define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6 + #define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7 + #define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6 + #define ATDDR3L_BIT ATDDR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR3STR; +extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096); +#define ATDDR3 _ATDDR3.Word +#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6 +#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7 +#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8 +#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9 +#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10 +#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11 +#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12 +#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13 +#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14 +#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15 +#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6 +#define ATDDR3_BIT ATDDR3_BIT_6 + + +/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR4HSTR; + #define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte + #define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8 + #define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9 + #define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10 + #define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11 + #define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12 + #define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13 + #define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14 + #define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15 + #define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8 + #define ATDDR4H_BIT ATDDR4H_BIT_8 + + /*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR4LSTR; + #define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte + #define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6 + #define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7 + #define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6 + #define ATDDR4L_BIT ATDDR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR4STR; +extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098); +#define ATDDR4 _ATDDR4.Word +#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6 +#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7 +#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8 +#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9 +#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10 +#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11 +#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12 +#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13 +#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14 +#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15 +#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6 +#define ATDDR4_BIT ATDDR4_BIT_6 + + +/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR5HSTR; + #define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte + #define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8 + #define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9 + #define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10 + #define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11 + #define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12 + #define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13 + #define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14 + #define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15 + #define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8 + #define ATDDR5H_BIT ATDDR5H_BIT_8 + + /*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR5LSTR; + #define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte + #define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6 + #define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7 + #define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6 + #define ATDDR5L_BIT ATDDR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR5STR; +extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A); +#define ATDDR5 _ATDDR5.Word +#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6 +#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7 +#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8 +#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9 +#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10 +#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11 +#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12 +#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13 +#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14 +#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15 +#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6 +#define ATDDR5_BIT ATDDR5_BIT_6 + + +/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR6HSTR; + #define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte + #define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8 + #define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9 + #define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10 + #define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11 + #define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12 + #define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13 + #define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14 + #define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15 + #define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8 + #define ATDDR6H_BIT ATDDR6H_BIT_8 + + /*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR6LSTR; + #define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte + #define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6 + #define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7 + #define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6 + #define ATDDR6L_BIT ATDDR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR6STR; +extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C); +#define ATDDR6 _ATDDR6.Word +#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6 +#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7 +#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8 +#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9 +#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10 +#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11 +#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12 +#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13 +#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14 +#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15 +#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6 +#define ATDDR6_BIT ATDDR6_BIT_6 + + +/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR7HSTR; + #define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte + #define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8 + #define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9 + #define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10 + #define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11 + #define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12 + #define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13 + #define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14 + #define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15 + #define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8 + #define ATDDR7H_BIT ATDDR7H_BIT_8 + + /*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR7LSTR; + #define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte + #define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6 + #define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7 + #define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6 + #define ATDDR7L_BIT ATDDR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR7STR; +extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E); +#define ATDDR7 _ATDDR7.Word +#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6 +#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7 +#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8 +#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9 +#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10 +#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11 +#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12 +#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13 +#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14 +#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15 +#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6 +#define ATDDR7_BIT ATDDR7_BIT_6 + + +/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI baud rate Bit 8 */ + byte SBR9 :1; /* SCI baud rate Bit 9 */ + byte SBR10 :1; /* SCI baud rate Bit 10 */ + byte SBR11 :1; /* SCI baud rate Bit 11 */ + byte SBR12 :1; /* SCI baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCIBDHSTR; + #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte + #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8 + #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9 + #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10 + #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11 + #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12 + #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8 + #define SCIBDH_SBR SCIBDH_SBR_8 + + /*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI baud rate Bit 0 */ + byte SBR1 :1; /* SCI baud rate Bit 1 */ + byte SBR2 :1; /* SCI baud rate Bit 2 */ + byte SBR3 :1; /* SCI baud rate Bit 3 */ + byte SBR4 :1; /* SCI baud rate Bit 4 */ + byte SBR5 :1; /* SCI baud rate Bit 5 */ + byte SBR6 :1; /* SCI baud rate Bit 6 */ + byte SBR7 :1; /* SCI baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCIBDLSTR; + #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte + #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0 + #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1 + #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2 + #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3 + #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4 + #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5 + #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6 + #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7 + #define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI baud rate Bit 0 */ + word SBR1 :1; /* SCI baud rate Bit 1 */ + word SBR2 :1; /* SCI baud rate Bit 2 */ + word SBR3 :1; /* SCI baud rate Bit 3 */ + word SBR4 :1; /* SCI baud rate Bit 4 */ + word SBR5 :1; /* SCI baud rate Bit 5 */ + word SBR6 :1; /* SCI baud rate Bit 6 */ + word SBR7 :1; /* SCI baud rate Bit 7 */ + word SBR8 :1; /* SCI baud rate Bit 8 */ + word SBR9 :1; /* SCI baud rate Bit 9 */ + word SBR10 :1; /* SCI baud rate Bit 10 */ + word SBR11 :1; /* SCI baud rate Bit 11 */ + word SBR12 :1; /* SCI baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCIBDSTR; +extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8); +#define SCIBD _SCIBD.Word +#define SCIBD_SBR0 _SCIBD.Bits.SBR0 +#define SCIBD_SBR1 _SCIBD.Bits.SBR1 +#define SCIBD_SBR2 _SCIBD.Bits.SBR2 +#define SCIBD_SBR3 _SCIBD.Bits.SBR3 +#define SCIBD_SBR4 _SCIBD.Bits.SBR4 +#define SCIBD_SBR5 _SCIBD.Bits.SBR5 +#define SCIBD_SBR6 _SCIBD.Bits.SBR6 +#define SCIBD_SBR7 _SCIBD.Bits.SBR7 +#define SCIBD_SBR8 _SCIBD.Bits.SBR8 +#define SCIBD_SBR9 _SCIBD.Bits.SBR9 +#define SCIBD_SBR10 _SCIBD.Bits.SBR10 +#define SCIBD_SBR11 _SCIBD.Bits.SBR11 +#define SCIBD_SBR12 _SCIBD.Bits.SBR12 +#define SCIBD_SBR _SCIBD.MergedBits.grpSBR + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC); +#define PWMCNT01 _PWMCNT01.Word +#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE); +#define PWMCNT23 _PWMCNT23.Word +#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0); +#define PWMCNT45 _PWMCNT45.Word +#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2); +#define PWMPER01 _PWMPER01.Word +#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4); +#define PWMPER23 _PWMPER23.Word +#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6); +#define PWMPER45 _PWMPER45.Word +#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8); +#define PWMDTY01 _PWMDTY01.Word +#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA); +#define PWMDTY23 _PWMDTY23.Word +#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC); +#define PWMDTY45 _PWMDTY45.Word +#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0 */ + byte BIT1 :1; /* Port E Bit 1 */ + byte BIT2 :1; /* Port E Bit 2 */ + byte BIT3 :1; /* Port E Bit 3 */ + byte BIT4 :1; /* Port E Bit 4 */ + byte BIT5 :1; /* Port E Bit 5 */ + byte BIT6 :1; /* Port E Bit 6 */ + byte BIT7 :1; /* Port E Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 +#define PORTE_BIT _PORTE.MergedBits.grpBIT + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte grpBIT_2 :6; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); +#define DDRE _DDRE.Byte +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2 +#define DDRE_BIT DDRE_BIT_2 + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + + +/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position REG11 */ + byte REG12 :1; /* Internal register map position REG12 */ + byte REG13 :1; /* Internal register map position REG13 */ + byte REG14 :1; /* Internal register map position REG14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + + +/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + + +/*** MTST0 - MTST0; 0x00000014 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST0 Bit 0 */ + byte BIT1 :1; /* MTST0 Bit 1 */ + byte BIT2 :1; /* MTST0 Bit 2 */ + byte BIT3 :1; /* MTST0 Bit 3 */ + byte BIT4 :1; /* MTST0 Bit 4 */ + byte BIT5 :1; /* MTST0 Bit 5 */ + byte BIT6 :1; /* MTST0 Bit 6 */ + byte BIT7 :1; /* MTST0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST0STR; +extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); +#define MTST0 _MTST0.Byte +#define MTST0_BIT0 _MTST0.Bits.BIT0 +#define MTST0_BIT1 _MTST0.Bits.BIT1 +#define MTST0_BIT2 _MTST0.Bits.BIT2 +#define MTST0_BIT3 _MTST0.Bits.BIT3 +#define MTST0_BIT4 _MTST0.Bits.BIT4 +#define MTST0_BIT5 _MTST0.Bits.BIT5 +#define MTST0_BIT6 _MTST0.Bits.BIT6 +#define MTST0_BIT7 _MTST0.Bits.BIT7 +#define MTST0_BIT _MTST0.MergedBits.grpBIT + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + + +/*** MTST1 - MTST1; 0x00000017 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST1 Bit 0 */ + byte BIT1 :1; /* MTST1 Bit 1 */ + byte BIT2 :1; /* MTST1 Bit 2 */ + byte BIT3 :1; /* MTST1 Bit 3 */ + byte BIT4 :1; /* MTST1 Bit 4 */ + byte BIT5 :1; /* MTST1 Bit 5 */ + byte BIT6 :1; /* MTST1 Bit 6 */ + byte BIT7 :1; /* MTST1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST1STR; +extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); +#define MTST1 _MTST1.Byte +#define MTST1_BIT0 _MTST1.Bits.BIT0 +#define MTST1_BIT1 _MTST1.Bits.BIT1 +#define MTST1_BIT2 _MTST1.Bits.BIT2 +#define MTST1_BIT3 _MTST1.Bits.BIT3 +#define MTST1_BIT4 _MTST1.Bits.BIT4 +#define MTST1_BIT5 _MTST1.Bits.BIT5 +#define MTST1_BIT6 _MTST1.Bits.BIT6 +#define MTST1_BIT7 _MTST1.Bits.BIT7 +#define MTST1_BIT _MTST1.MergedBits.grpBIT + + +/*** PARTIDH - Part ID Register High; 0x0000001A ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Part ID Register Bit 15 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID8 :1; /* Part ID Register Bit 8 */ + } Bits; +} PARTIDHSTR; +extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); +#define PARTIDH _PARTIDH.Byte +#define PARTIDH_ID15 _PARTIDH.Bits.ID15 +#define PARTIDH_ID14 _PARTIDH.Bits.ID14 +#define PARTIDH_ID13 _PARTIDH.Bits.ID13 +#define PARTIDH_ID12 _PARTIDH.Bits.ID12 +#define PARTIDH_ID11 _PARTIDH.Bits.ID11 +#define PARTIDH_ID10 _PARTIDH.Bits.ID10 +#define PARTIDH_ID9 _PARTIDH.Bits.ID9 +#define PARTIDH_ID8 _PARTIDH.Bits.ID8 + + +/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ +typedef union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + struct { + byte grpID :8; + } MergedBits; +} PARTIDLSTR; +extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); +#define PARTIDL _PARTIDL.Byte +#define PARTIDL_ID0 _PARTIDL.Bits.ID0 +#define PARTIDL_ID1 _PARTIDL.Bits.ID1 +#define PARTIDL_ID2 _PARTIDL.Bits.ID2 +#define PARTIDL_ID3 _PARTIDL.Bits.ID3 +#define PARTIDL_ID4 _PARTIDL.Bits.ID4 +#define PARTIDL_ID5 _PARTIDL.Bits.ID5 +#define PARTIDL_ID6 _PARTIDL.Bits.ID6 +#define PARTIDL_ID7 _PARTIDL.Bits.ID7 +#define PARTIDL_ID _PARTIDL.MergedBits.grpID + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 +#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 +#define BKP0H_BIT BKP0H_BIT_8 + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 +#define BKP0L_BIT _BKP0L.MergedBits.grpBIT + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 +#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 +#define BKP1H_BIT BKP1H_BIT_8 + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 +#define BKP1L_BIT _BKP1L.MergedBits.grpBIT + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0, XAB14 */ + byte BIT1 :1; /* Port K Bit 1, XAB15 */ + byte BIT2 :1; /* Port K Bit 2, XAB16 */ + byte BIT3 :1; /* Port K Bit 3, XAB17 */ + byte BIT4 :1; /* Port K Bit 4, XAB18 */ + byte BIT5 :1; /* Port K Bit 5, XAB19 */ + byte BIT6 :1; /* Port K Bit 6 */ + byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT6 _PORTK.Bits.BIT6 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte DDK0 :1; /* Port K Data Direction Bit 0 */ + byte DDK1 :1; /* Port K Data Direction Bit 1 */ + byte DDK2 :1; /* Port K Data Direction Bit 2 */ + byte DDK3 :1; /* Port K Data Direction Bit 3 */ + byte DDK4 :1; /* Port K Data Direction Bit 4 */ + byte DDK5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte DDK7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDK :6; + byte :1; + byte grpDDK_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); +#define DDRK _DDRK.Byte +#define DDRK_DDK0 _DDRK.Bits.DDK0 +#define DDRK_DDK1 _DDRK.Bits.DDK1 +#define DDRK_DDK2 _DDRK.Bits.DDK2 +#define DDRK_DDK3 _DDRK.Bits.DDK3 +#define DDRK_DDK4 _DDRK.Bits.DDK4 +#define DDRK_DDK5 _DDRK.Bits.DDK5 +#define DDRK_DDK7 _DDRK.Bits.DDK7 +#define DDRK_DDK _DDRK.MergedBits.grpDDK + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + + +/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ +typedef union { + byte Byte; + struct { + byte TOUT0 :1; /* CRG Test Flags Bit 0 */ + byte TOUT1 :1; /* CRG Test Flags Bit 1 */ + byte TOUT2 :1; /* CRG Test Flags Bit 2 */ + byte TOUT3 :1; /* CRG Test Flags Bit 3 */ + byte TOUT4 :1; /* CRG Test Flags Bit 4 */ + byte TOUT5 :1; /* CRG Test Flags Bit 5 */ + byte TOUT6 :1; /* CRG Test Flags Bit 6 */ + byte TOUT7 :1; /* CRG Test Flags Bit 7 */ + } Bits; + struct { + byte grpTOUT :8; + } MergedBits; +} CTFLGSTR; +extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); +#define CTFLG _CTFLG.Byte +#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 +#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 +#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 +#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 +#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 +#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 +#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 +#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 +#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte :1; + byte :1; + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Crystal Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + + +/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ +typedef union { + byte Byte; + struct { + byte TCTL0 :1; /* CRG Test Control Bit 0 */ + byte TCTL1 :1; /* CRG Test Control Bit 1 */ + byte TCTL2 :1; /* CRG Test Control Bit 2 */ + byte TCTL3 :1; /* CRG Test Control Bit 3 */ + byte TCTL4 :1; /* CRG Test Control Bit 4 */ + byte TCTL5 :1; /* CRG Test Control Bit 5 */ + byte TCTL6 :1; /* CRG Test Control Bit 6 */ + byte TCTL7 :1; /* CRG Test Control Bit 7 */ + } Bits; + struct { + byte grpTCTL :8; + } MergedBits; +} CTCTLSTR; +extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); +#define CTCTL _CTCTL.Byte +#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 +#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 +#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 +#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 +#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 +#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 +#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 +#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 +#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 +#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; + struct { + byte grpIOS :8; + } MergedBits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 +#define TIOS_IOS _TIOS.MergedBits.grpIOS + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; + struct { + byte grpFOC :8; + } MergedBits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 +#define CFORC_FOC _CFORC.MergedBits.grpFOC + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; + struct { + byte grpOC7M :8; + } MergedBits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 +#define OC7M_OC7M _OC7M.MergedBits.grpOC7M + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; + struct { + byte OC7D0 :1; /* Output Compare 7 Bit 0 */ + byte OC7D1 :1; /* Output Compare 7 Bit 1 */ + byte OC7D2 :1; /* Output Compare 7 Bit 2 */ + byte OC7D3 :1; /* Output Compare 7 Bit 3 */ + byte OC7D4 :1; /* Output Compare 7 Bit 4 */ + byte OC7D5 :1; /* Output Compare 7 Bit 5 */ + byte OC7D6 :1; /* Output Compare 7 Bit 6 */ + byte OC7D7 :1; /* Output Compare 7 Bit 7 */ + } Bits; + struct { + byte grpOC7D :8; + } MergedBits; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); +#define OC7D _OC7D.Byte +#define OC7D_OC7D0 _OC7D.Bits.OC7D0 +#define OC7D_OC7D1 _OC7D.Bits.OC7D1 +#define OC7D_OC7D2 _OC7D.Bits.OC7D2 +#define OC7D_OC7D3 _OC7D.Bits.OC7D3 +#define OC7D_OC7D4 _OC7D.Bits.OC7D4 +#define OC7D_OC7D5 _OC7D.Bits.OC7D5 +#define OC7D_OC7D6 _OC7D.Bits.OC7D6 +#define OC7D_OC7D7 _OC7D.Bits.OC7D7 +#define OC7D_OC7D _OC7D.MergedBits.grpOC7D + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; + struct { + byte grpTOV :8; + } MergedBits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 +#define TTOV_TOV _TTOV.MergedBits.grpTOV + + +/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + + +/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + + +/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATDSTAT0STR; +extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086); +#define ATDSTAT0 _ATDSTAT0.Byte +#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0 +#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1 +#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2 +#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR +#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF +#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF +#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC + + +/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATDSTAT1STR; +extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B); +#define ATDSTAT1 _ATDSTAT1.Byte +#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0 +#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1 +#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2 +#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3 +#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4 +#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5 +#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6 +#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7 +#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF + + +/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable digital input buffer */ + byte BIT1 :1; /* Disable/Enable digital input buffer */ + byte BIT2 :1; /* Disable/Enable digital input buffer */ + byte BIT3 :1; /* Disable/Enable digital input buffer */ + byte BIT4 :1; /* Disable/Enable digital input buffer */ + byte BIT5 :1; /* Disable/Enable digital input buffer */ + byte BIT6 :1; /* Disable/Enable digital input buffer */ + byte BIT7 :1; /* Disable/Enable digital input buffer */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATDDIENSTR; +extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D); +#define ATDDIEN _ATDDIEN.Byte +#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0 +#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1 +#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2 +#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3 +#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4 +#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5 +#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6 +#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7 +#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 +#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 +#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 +#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 +#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 +#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 +#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 +#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 +#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT + + +/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCICR1STR; +extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA); +#define SCICR1 _SCICR1.Byte +#define SCICR1_PT _SCICR1.Bits.PT +#define SCICR1_PE _SCICR1.Bits.PE +#define SCICR1_ILT _SCICR1.Bits.ILT +#define SCICR1_WAKE _SCICR1.Bits.WAKE +#define SCICR1_M _SCICR1.Bits.M +#define SCICR1_RSRC _SCICR1.Bits.RSRC +#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI +#define SCICR1_LOOPS _SCICR1.Bits.LOOPS + + +/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCICR2STR; +extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB); +#define SCICR2 _SCICR2.Byte +#define SCICR2_SBK _SCICR2.Bits.SBK +#define SCICR2_RWU _SCICR2.Bits.RWU +#define SCICR2_RE _SCICR2.Bits.RE +#define SCICR2_TE _SCICR2.Bits.TE +#define SCICR2_ILIE _SCICR2.Bits.ILIE +#define SCICR2_RIE _SCICR2.Bits.RIE +#define SCICR2_TCIE _SCICR2.Bits.TCIE +#define SCICR2_SCTIE _SCICR2.Bits.SCTIE + + +/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCISR1STR; +extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC); +#define SCISR1 _SCISR1.Byte +#define SCISR1_PF _SCISR1.Bits.PF +#define SCISR1_FE _SCISR1.Bits.FE +#define SCISR1_NF _SCISR1.Bits.NF +#define SCISR1_OR _SCISR1.Bits.OR +#define SCISR1_IDLE _SCISR1.Bits.IDLE +#define SCISR1_RDRF _SCISR1.Bits.RDRF +#define SCISR1_TC _SCISR1.Bits.TC +#define SCISR1_TDRE _SCISR1.Bits.TDRE + + +/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCISR2STR; +extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD); +#define SCISR2 _SCISR2.Byte +#define SCISR2_RAF _SCISR2.Bits.RAF +#define SCISR2_TXDIR _SCISR2.Bits.TXDIR +#define SCISR2_BRK13 _SCISR2.Bits.BRK13 + + +/*** SCIDRH - SCI Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCIDRHSTR; +extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE); +#define SCIDRH _SCIDRH.Byte +#define SCIDRH_T8 _SCIDRH.Bits.T8 +#define SCIDRH_R8 _SCIDRH.Bits.R8 + + +/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCIDRLSTR; +extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF); +#define SCIDRL _SCIDRL.Byte +#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0 +#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1 +#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2 +#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3 +#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4 +#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5 +#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6 +#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7 + + +/*** SPICR1 - SPI Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPICR1STR; +extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8); +#define SPICR1 _SPICR1.Byte +#define SPICR1_LSBFE _SPICR1.Bits.LSBFE +#define SPICR1_SSOE _SPICR1.Bits.SSOE +#define SPICR1_CPHA _SPICR1.Bits.CPHA +#define SPICR1_CPOL _SPICR1.Bits.CPOL +#define SPICR1_MSTR _SPICR1.Bits.MSTR +#define SPICR1_SPTIE _SPICR1.Bits.SPTIE +#define SPICR1_SPE _SPICR1.Bits.SPE +#define SPICR1_SPIE _SPICR1.Bits.SPIE + + +/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPICR2STR; +extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9); +#define SPICR2 _SPICR2.Byte +#define SPICR2_SPC0 _SPICR2.Bits.SPC0 +#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI +#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE +#define SPICR2_MODFEN _SPICR2.Bits.MODFEN + + +/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPIBRSTR; +extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA); +#define SPIBR _SPIBR.Byte +#define SPIBR_SPR0 _SPIBR.Bits.SPR0 +#define SPIBR_SPR1 _SPIBR.Bits.SPR1 +#define SPIBR_SPR2 _SPIBR.Bits.SPR2 +#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0 +#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1 +#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2 +#define SPIBR_SPR _SPIBR.MergedBits.grpSPR +#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR + + +/*** SPISR - SPI Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPISRSTR; +extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB); +#define SPISR _SPISR.Byte +#define SPISR_MODF _SPISR.Bits.MODF +#define SPISR_SPTEF _SPISR.Bits.SPTEF +#define SPISR_SPIF _SPISR.Bits.SPIF + + +/*** SPIDR - SPI Data Register; 0x000000DD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPIDRSTR; +extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD); +#define SPIDR _SPIDR.Byte +#define SPIDR_BIT _SPIDR.MergedBits.grpBIT + + +/*** PWME - PWM Enable Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; + struct { + byte grpPWME :8; + } MergedBits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 +#define PWME_PWME _PWME.MergedBits.grpPWME + + +/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; + struct { + byte grpPPOL :8; + } MergedBits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 +#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL + + +/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; + struct { + byte grpPCLK :8; + } MergedBits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 +#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; + struct { + byte grpCAE :8; + } MergedBits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 +#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE + + +/*** PWMCTL - PWM Control Register; 0x000000E5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + + +/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 +#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT + + +/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 +#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT + + +/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte NV6 :1; /* Non Volatile flag bit 6 */ + byte KEYEN :1; /* Enable backdoor key to security */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :5; + byte :1; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_NV6 _FSEC.Bits.NV6 +#define FSEC_KEYEN _FSEC.Bits.KEYEN +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_NV FSEC_NV_2 + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + + +/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CANCTL0STR; +extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140); +#define CANCTL0 _CANCTL0.Byte +#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ +#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ +#define CANCTL0_WUPE _CANCTL0.Bits.WUPE +#define CANCTL0_TIME _CANCTL0.Bits.TIME +#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH +#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI +#define CANCTL0_RXACT _CANCTL0.Bits.RXACT +#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM + + +/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN Clock Source */ + byte CANE :1; /* MSCAN Enable */ + } Bits; +} CANCTL1STR; +extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141); +#define CANCTL1 _CANCTL1.Byte +#define CANCTL1_INITAK _CANCTL1.Bits.INITAK +#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK +#define CANCTL1_WUPM _CANCTL1.Bits.WUPM +#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN +#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB +#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC +#define CANCTL1_CANE _CANCTL1.Bits.CANE + + +/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CANBTR0STR; +extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142); +#define CANBTR0 _CANBTR0.Byte +#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0 +#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1 +#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2 +#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3 +#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4 +#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5 +#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0 +#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1 +#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP +#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW + + +/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CANBTR1STR; +extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143); +#define CANBTR1 _CANBTR1.Byte +#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10 +#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11 +#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12 +#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13 +#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20 +#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21 +#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22 +#define CANBTR1_SAMP _CANBTR1.Bits.SAMP +#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10 +#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20 +#define CANBTR1_TSEG CANBTR1_TSEG_10 + + +/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CANRFLGSTR; +extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144); +#define CANRFLG _CANRFLG.Byte +#define CANRFLG_RXF _CANRFLG.Bits.RXF +#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF +#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0 +#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1 +#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0 +#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1 +#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF +#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF +#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT +#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT + + +/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CANRIERSTR; +extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145); +#define CANRIER _CANRIER.Byte +#define CANRIER_RXFIE _CANRIER.Bits.RXFIE +#define CANRIER_OVRIE _CANRIER.Bits.OVRIE +#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0 +#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1 +#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0 +#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1 +#define CANRIER_CSCIE _CANRIER.Bits.CSCIE +#define CANRIER_WUPIE _CANRIER.Bits.WUPIE +#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE +#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE + + +/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTFLGSTR; +extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146); +#define CANTFLG _CANTFLG.Byte +#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0 +#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1 +#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2 +#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE + + +/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTIERSTR; +extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147); +#define CANTIER _CANTIER.Byte +#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0 +#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1 +#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2 +#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE + + +/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTARQSTR; +extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148); +#define CANTARQ _CANTARQ.Byte +#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0 +#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1 +#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2 +#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ + + +/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTAAKSTR; +extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149); +#define CANTAAK _CANTAAK.Byte +#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0 +#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1 +#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2 +#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK + + +/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTBSELSTR; +extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A); +#define CANTBSEL _CANTBSEL.Byte +#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0 +#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1 +#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2 +#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX + + +/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CANIDACSTR; +extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B); +#define CANIDAC _CANIDAC.Byte +#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0 +#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1 +#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2 +#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0 +#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1 +#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT +#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM + + +/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CANRXERRSTR; +extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E); +#define CANRXERR _CANRXERR.Byte +#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0 +#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1 +#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2 +#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3 +#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4 +#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5 +#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6 +#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7 +#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR + + +/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CANTXERRSTR; +extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F); +#define CANTXERR _CANTXERR.Byte +#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0 +#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1 +#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2 +#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3 +#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4 +#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5 +#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6 +#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7 +#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR + + +/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR0STR; +extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150); +#define CANIDAR0 _CANIDAR0.Byte +#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0 +#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1 +#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2 +#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3 +#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4 +#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5 +#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6 +#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7 +#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC + + +/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR1STR; +extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151); +#define CANIDAR1 _CANIDAR1.Byte +#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0 +#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1 +#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2 +#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3 +#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4 +#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5 +#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6 +#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7 +#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC + + +/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR2STR; +extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152); +#define CANIDAR2 _CANIDAR2.Byte +#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0 +#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1 +#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2 +#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3 +#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4 +#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5 +#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6 +#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7 +#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC + + +/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR3STR; +extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153); +#define CANIDAR3 _CANIDAR3.Byte +#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0 +#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1 +#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2 +#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3 +#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4 +#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5 +#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6 +#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7 +#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC + + +/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR0STR; +extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154); +#define CANIDMR0 _CANIDMR0.Byte +#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0 +#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1 +#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2 +#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3 +#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4 +#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5 +#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6 +#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7 +#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM + + +/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR1STR; +extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155); +#define CANIDMR1 _CANIDMR1.Byte +#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0 +#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1 +#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2 +#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3 +#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4 +#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5 +#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6 +#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7 +#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM + + +/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR2STR; +extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156); +#define CANIDMR2 _CANIDMR2.Byte +#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0 +#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1 +#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2 +#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3 +#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4 +#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5 +#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6 +#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7 +#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM + + +/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR3STR; +extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157); +#define CANIDMR3 _CANIDMR3.Byte +#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0 +#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1 +#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2 +#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3 +#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4 +#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5 +#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6 +#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7 +#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM + + +/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR4STR; +extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158); +#define CANIDAR4 _CANIDAR4.Byte +#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0 +#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1 +#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2 +#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3 +#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4 +#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5 +#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6 +#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7 +#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC + + +/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR5STR; +extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159); +#define CANIDAR5 _CANIDAR5.Byte +#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0 +#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1 +#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2 +#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3 +#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4 +#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5 +#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6 +#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7 +#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC + + +/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR6STR; +extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A); +#define CANIDAR6 _CANIDAR6.Byte +#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0 +#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1 +#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2 +#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3 +#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4 +#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5 +#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6 +#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7 +#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC + + +/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR7STR; +extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B); +#define CANIDAR7 _CANIDAR7.Byte +#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0 +#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1 +#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2 +#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3 +#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4 +#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5 +#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6 +#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7 +#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC + + +/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR4STR; +extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C); +#define CANIDMR4 _CANIDMR4.Byte +#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0 +#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1 +#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2 +#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3 +#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4 +#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5 +#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6 +#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7 +#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM + + +/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR5STR; +extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D); +#define CANIDMR5 _CANIDMR5.Byte +#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0 +#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1 +#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2 +#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3 +#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4 +#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5 +#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6 +#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7 +#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM + + +/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR6STR; +extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E); +#define CANIDMR6 _CANIDMR6.Byte +#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0 +#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1 +#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2 +#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3 +#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4 +#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5 +#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6 +#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7 +#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM + + +/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR7STR; +extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F); +#define CANIDMR7 _CANIDMR7.Byte +#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0 +#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1 +#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2 +#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3 +#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4 +#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5 +#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6 +#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7 +#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM + + +/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CANRXIDR0STR; +extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160); +#define CANRXIDR0 _CANRXIDR0.Byte +#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21 +#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22 +#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23 +#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24 +#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25 +#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26 +#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27 +#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28 +#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21 +#define CANRXIDR0_ID CANRXIDR0_ID_21 + + +/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CANRXIDR1STR; +extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161); +#define CANRXIDR1 _CANRXIDR1.Byte +#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15 +#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16 +#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17 +#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE +#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR +#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18 +#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19 +#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20 +#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15 +#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18 +#define CANRXIDR1_ID CANRXIDR1_ID_15 + + +/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CANRXIDR2STR; +extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162); +#define CANRXIDR2 _CANRXIDR2.Byte +#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7 +#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8 +#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9 +#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10 +#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11 +#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12 +#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13 +#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14 +#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7 +#define CANRXIDR2_ID CANRXIDR2_ID_7 + + +/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CANRXIDR3STR; +extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163); +#define CANRXIDR3 _CANRXIDR3.Byte +#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR +#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0 +#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1 +#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2 +#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3 +#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4 +#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5 +#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6 +#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID + + +/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR0STR; +extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164); +#define CANRXDSR0 _CANRXDSR0.Byte +#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0 +#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1 +#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2 +#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3 +#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4 +#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5 +#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6 +#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7 +#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB + + +/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR1STR; +extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165); +#define CANRXDSR1 _CANRXDSR1.Byte +#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0 +#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1 +#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2 +#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3 +#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4 +#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5 +#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6 +#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7 +#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB + + +/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR2STR; +extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166); +#define CANRXDSR2 _CANRXDSR2.Byte +#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0 +#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1 +#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2 +#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3 +#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4 +#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5 +#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6 +#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7 +#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB + + +/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR3STR; +extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167); +#define CANRXDSR3 _CANRXDSR3.Byte +#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0 +#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1 +#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2 +#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3 +#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4 +#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5 +#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6 +#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7 +#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB + + +/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR4STR; +extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168); +#define CANRXDSR4 _CANRXDSR4.Byte +#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0 +#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1 +#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2 +#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3 +#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4 +#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5 +#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6 +#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7 +#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB + + +/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR5STR; +extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169); +#define CANRXDSR5 _CANRXDSR5.Byte +#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0 +#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1 +#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2 +#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3 +#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4 +#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5 +#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6 +#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7 +#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB + + +/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR6STR; +extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A); +#define CANRXDSR6 _CANRXDSR6.Byte +#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0 +#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1 +#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2 +#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3 +#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4 +#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5 +#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6 +#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7 +#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB + + +/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR7STR; +extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B); +#define CANRXDSR7 _CANRXDSR7.Byte +#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0 +#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1 +#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2 +#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3 +#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4 +#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5 +#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6 +#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7 +#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB + + +/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANRXDLRSTR; +extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C); +#define CANRXDLR _CANRXDLR.Byte +#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0 +#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1 +#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2 +#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3 +#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC + + +/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CANTXIDR0STR; +extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170); +#define CANTXIDR0 _CANTXIDR0.Byte +#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21 +#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22 +#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23 +#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24 +#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25 +#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26 +#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27 +#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28 +#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21 +#define CANTXIDR0_ID CANTXIDR0_ID_21 + + +/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CANTXIDR1STR; +extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171); +#define CANTXIDR1 _CANTXIDR1.Byte +#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15 +#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16 +#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17 +#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE +#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR +#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18 +#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19 +#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20 +#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15 +#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18 +#define CANTXIDR1_ID CANTXIDR1_ID_15 + + +/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CANTXIDR2STR; +extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172); +#define CANTXIDR2 _CANTXIDR2.Byte +#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7 +#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8 +#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9 +#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10 +#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11 +#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12 +#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13 +#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14 +#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7 +#define CANTXIDR2_ID CANTXIDR2_ID_7 + + +/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CANTXIDR3STR; +extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173); +#define CANTXIDR3 _CANTXIDR3.Byte +#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR +#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0 +#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1 +#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2 +#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3 +#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4 +#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5 +#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6 +#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID + + +/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR0STR; +extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174); +#define CANTXDSR0 _CANTXDSR0.Byte +#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0 +#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1 +#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2 +#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3 +#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4 +#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5 +#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6 +#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7 +#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB + + +/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR1STR; +extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175); +#define CANTXDSR1 _CANTXDSR1.Byte +#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0 +#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1 +#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2 +#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3 +#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4 +#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5 +#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6 +#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7 +#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB + + +/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR2STR; +extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176); +#define CANTXDSR2 _CANTXDSR2.Byte +#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0 +#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1 +#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2 +#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3 +#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4 +#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5 +#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6 +#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7 +#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB + + +/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR3STR; +extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177); +#define CANTXDSR3 _CANTXDSR3.Byte +#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0 +#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1 +#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2 +#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3 +#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4 +#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5 +#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6 +#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7 +#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB + + +/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR4STR; +extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178); +#define CANTXDSR4 _CANTXDSR4.Byte +#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0 +#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1 +#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2 +#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3 +#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4 +#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5 +#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6 +#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7 +#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB + + +/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR5STR; +extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179); +#define CANTXDSR5 _CANTXDSR5.Byte +#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0 +#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1 +#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2 +#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3 +#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4 +#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5 +#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6 +#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7 +#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB + + +/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR6STR; +extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A); +#define CANTXDSR6 _CANTXDSR6.Byte +#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0 +#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1 +#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2 +#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3 +#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4 +#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5 +#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6 +#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7 +#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB + + +/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR7STR; +extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B); +#define CANTXDSR7 _CANTXDSR7.Byte +#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0 +#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1 +#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2 +#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3 +#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4 +#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5 +#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6 +#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7 +#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB + + +/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTXDLRSTR; +extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C); +#define CANTXDLR _CANTXDLR.Byte +#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0 +#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1 +#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2 +#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3 +#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC + + +/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CANTXTBPRSTR; +extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F); +#define CANTXTBPR _CANTXTBPR.Byte +#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0 +#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1 +#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2 +#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3 +#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4 +#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5 +#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6 +#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7 +#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTT :8; + } MergedBits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 +#define PTT_PTT _PTT.MergedBits.grpPTT + + +/*** PTIT - Port T Input; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTIT :8; + } MergedBits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 +#define PTIT_PTIT _PTIT.MergedBits.grpPTIT + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; + struct { + byte grpDDRT :8; + } MergedBits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 +#define DDRT_DDRT _DDRT.MergedBits.grpDDRT + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; + struct { + byte grpRDRT :8; + } MergedBits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 +#define RDRT_RDRT _RDRT.MergedBits.grpRDRT + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; + struct { + byte grpPERT :8; + } MergedBits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 +#define PERT_PERT _PERT.MergedBits.grpPERT + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; + struct { + byte grpPPST :8; + } MergedBits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 +#define PPST_PPST _PPST.MergedBits.grpPPST + + +/*** MODRR - Module Routing Register; 0x00000247 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* Module Routing Bit 0 */ + byte MODRR1 :1; /* Module Routing Bit 1 */ + byte MODRR2 :1; /* Module Routing Bit 2 */ + byte MODRR3 :1; /* Module Routing Bit 3 */ + byte MODRR4 :1; /* Module Routing Bit 4 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpMODRR :5; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS _PTS.MergedBits.grpPTS + + +/*** PTIS - Port S Input; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS _PTIS.MergedBits.grpPTIS + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS _DDRS.MergedBits.grpDDRS + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpRDRS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS _RDRS.MergedBits.grpRDRS + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS _PERS.MergedBits.grpPERS + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS _PPSS.MergedBits.grpPPSS + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS _WOMS.MergedBits.grpWOMS + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port T Bit 0 */ + byte PTM1 :1; /* Port T Bit 1 */ + byte PTM2 :1; /* Port T Bit 2 */ + byte PTM3 :1; /* Port T Bit 3 */ + byte PTM4 :1; /* Port T Bit 4 */ + byte PTM5 :1; /* Port T Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPTM :6; + byte :1; + byte :1; + } MergedBits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM _PTM.MergedBits.grpPTM + + +/*** PTIM - Port M Input; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIM :6; + byte :1; + byte :1; + } MergedBits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM _PTIM.MergedBits.grpPTIM + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRM :6; + byte :1; + byte :1; + } MergedBits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM _DDRM.MergedBits.grpDDRM + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpRDRM :6; + byte :1; + byte :1; + } MergedBits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM _RDRM.MergedBits.grpRDRM + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPERM :6; + byte :1; + byte :1; + } MergedBits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM _PERM.MergedBits.grpPERM + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSM :6; + byte :1; + byte :1; + } MergedBits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM _PPSM.MergedBits.grpPPSM + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMM :6; + byte :1; + byte :1; + } MergedBits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM _WOMM.MergedBits.grpWOMM + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTP :8; + } MergedBits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 +#define PTP_PTP _PTP.MergedBits.grpPTP + + +/*** PTIP - Port P Input; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTIP :8; + } MergedBits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 +#define PTIP_PTIP _PTIP.MergedBits.grpPTIP + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; + struct { + byte grpDDRP :8; + } MergedBits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 +#define DDRP_DDRP _DDRP.MergedBits.grpDDRP + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; + struct { + byte grpRDRP :8; + } MergedBits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 +#define RDRP_RDRP _RDRP.MergedBits.grpRDRP + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPERP :8; + } MergedBits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 +#define PERP_PERP _PERP.MergedBits.grpPERP + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; + struct { + byte grpPPSP :8; + } MergedBits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 +#define PPSP_PPSP _PPSP.MergedBits.grpPPSP + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPIEP :8; + } MergedBits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 +#define PIEP_PIEP _PIEP.MergedBits.grpPIEP + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; + struct { + byte grpPIFP :8; + } MergedBits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 +#define PIFP_PIFP _PIFP.MergedBits.grpPIFP + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); +#define PTJ _PTJ.Byte +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); +#define PERJ _PERJ.Byte +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + + +/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + + +/*** PTAD - Port AD I/O Register; 0x00000270 ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* Port AD Bit 0 */ + byte PTAD1 :1; /* Port AD Bit 1 */ + byte PTAD2 :1; /* Port AD Bit 2 */ + byte PTAD3 :1; /* Port AD Bit 3 */ + byte PTAD4 :1; /* Port AD Bit 4 */ + byte PTAD5 :1; /* Port AD Bit 5 */ + byte PTAD6 :1; /* Port AD Bit 6 */ + byte PTAD7 :1; /* Port AD Bit 7 */ + } Bits; + struct { + byte grpPTAD :8; + } MergedBits; +} PTADSTR; +extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270); +#define PTAD _PTAD.Byte +#define PTAD_PTAD0 _PTAD.Bits.PTAD0 +#define PTAD_PTAD1 _PTAD.Bits.PTAD1 +#define PTAD_PTAD2 _PTAD.Bits.PTAD2 +#define PTAD_PTAD3 _PTAD.Bits.PTAD3 +#define PTAD_PTAD4 _PTAD.Bits.PTAD4 +#define PTAD_PTAD5 _PTAD.Bits.PTAD5 +#define PTAD_PTAD6 _PTAD.Bits.PTAD6 +#define PTAD_PTAD7 _PTAD.Bits.PTAD7 +#define PTAD_PTAD _PTAD.MergedBits.grpPTAD + + +/*** PTIAD - Port AD Input Register; 0x00000271 ***/ +typedef union { + byte Byte; + struct { + byte PTIAD0 :1; /* Port AD Bit 0 */ + byte PTIAD1 :1; /* Port AD Bit 1 */ + byte PTIAD2 :1; /* Port AD Bit 2 */ + byte PTIAD3 :1; /* Port AD Bit 3 */ + byte PTIAD4 :1; /* Port AD Bit 4 */ + byte PTIAD5 :1; /* Port AD Bit 5 */ + byte PTIAD6 :1; /* Port AD Bit 6 */ + byte PTIAD7 :1; /* Port AD Bit 7 */ + } Bits; + struct { + byte grpPTIAD :8; + } MergedBits; +} PTIADSTR; +extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271); +#define PTIAD _PTIAD.Byte +#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0 +#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1 +#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2 +#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3 +#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4 +#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5 +#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6 +#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7 +#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD + + +/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/ +typedef union { + byte Byte; + struct { + byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */ + byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */ + byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */ + byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */ + byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */ + byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */ + byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */ + byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDRAD :8; + } MergedBits; +} DDRADSTR; +extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272); +#define DDRAD _DDRAD.Byte +#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0 +#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1 +#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2 +#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3 +#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4 +#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5 +#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6 +#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7 +#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD + + +/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/ +typedef union { + byte Byte; + struct { + byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */ + byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */ + byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */ + byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */ + byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */ + byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */ + byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */ + byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */ + } Bits; + struct { + byte grpRDRAD :8; + } MergedBits; +} RDRADSTR; +extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273); +#define RDRAD _RDRAD.Byte +#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0 +#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1 +#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2 +#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3 +#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4 +#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5 +#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6 +#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7 +#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD + + +/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/ +typedef union { + byte Byte; + struct { + byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */ + byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */ + byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */ + byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */ + byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */ + byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */ + byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */ + byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */ + } Bits; + struct { + byte grpPERAD :8; + } MergedBits; +} PERADSTR; +extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274); +#define PERAD _PERAD.Byte +#define PERAD_PERAD0 _PERAD.Bits.PERAD0 +#define PERAD_PERAD1 _PERAD.Bits.PERAD1 +#define PERAD_PERAD2 _PERAD.Bits.PERAD2 +#define PERAD_PERAD3 _PERAD.Bits.PERAD3 +#define PERAD_PERAD4 _PERAD.Bits.PERAD4 +#define PERAD_PERAD5 _PERAD.Bits.PERAD5 +#define PERAD_PERAD6 _PERAD.Bits.PERAD6 +#define PERAD_PERAD7 _PERAD.Bits.PERAD7 +#define PERAD_PERAD _PERAD.MergedBits.grpPERAD + + +/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/ +typedef union { + byte Byte; + struct { + byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */ + byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */ + byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */ + byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */ + byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */ + byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */ + byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */ + byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */ + } Bits; + struct { + byte grpPPSAD :8; + } MergedBits; +} PPSADSTR; +extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275); +#define PPSAD _PPSAD.Byte +#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0 +#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1 +#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2 +#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3 +#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4 +#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5 +#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6 +#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7 +#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD + + +/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte UNSEC :1; /* Unsecure */ + byte CLKSW :1; /* Clock switch */ + byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ + byte SDV :1; /* Shift data valid */ + byte ENTAG :1; /* Tagging enable */ + byte BDMACT :1; /* BDM active status */ + byte ENBDM :1; /* Enable BDM */ + } Bits; +} BDMSTSSTR; +extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); +#define BDMSTS _BDMSTS.Byte +#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC +#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW +#define BDMSTS_TRACE _BDMSTS.Bits.TRACE +#define BDMSTS_SDV _BDMSTS.Bits.SDV +#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG +#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT +#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM + + +/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ +typedef union { + byte Byte; + struct { + byte CCR0 :1; /* BDM CCR Holding Bit 0 */ + byte CCR1 :1; /* BDM CCR Holding Bit 1 */ + byte CCR2 :1; /* BDM CCR Holding Bit 2 */ + byte CCR3 :1; /* BDM CCR Holding Bit 3 */ + byte CCR4 :1; /* BDM CCR Holding Bit 4 */ + byte CCR5 :1; /* BDM CCR Holding Bit 5 */ + byte CCR6 :1; /* BDM CCR Holding Bit 6 */ + byte CCR7 :1; /* BDM CCR Holding Bit 7 */ + } Bits; + struct { + byte grpCCR :8; + } MergedBits; +} BDMCCRSTR; +extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); +#define BDMCCR _BDMCCR.Byte +#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 +#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 +#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 +#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 +#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 +#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 +#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 +#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 +#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR + + +/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position */ + byte REG12 :1; /* Internal register map position */ + byte REG13 :1; /* Internal register map position */ + byte REG14 :1; /* Internal register map position */ + byte REG15 :1; /* Internal register map position */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :5; + } MergedBits; +} BDMINRSTR; +extern volatile BDMINRSTR _BDMINR @(0x0000FF07); +#define BDMINR _BDMINR.Byte +#define BDMINR_REG11 _BDMINR.Bits.REG11 +#define BDMINR_REG12 _BDMINR.Bits.REG12 +#define BDMINR_REG13 _BDMINR.Bits.REG13 +#define BDMINR_REG14 _BDMINR.Bits.REG14 +#define BDMINR_REG15 _BDMINR.Bits.REG15 +#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 +#define BDMINR_REG BDMINR_REG_11 + + + /* Watchdog reset macro */ +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ +#endif + +#endif + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PESL.h b/Demo/HCS12_CodeWarrior_small/CODE/PESL.h new file mode 100644 index 000000000..9f79f6868 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PESL.h @@ -0,0 +1,52 @@ +/* ================================================================================================================================= ** +** ================================================================================================================================= ** +** CONFIGURATION FILE FOR PESL LIBRARY ** +** ================================================================================================================================= ** +** ================================================================================================================================= */ + +#define _MC9S12A128_112 1 +#define _MC9S12A128_80 2 +#define _MC9S12A256_112 3 +#define _MC9S12A256_80 4 +#define _MC9S12A64_112 5 +#define _MC9S12A64_80 6 +#define _MC9S12C32_48 7 +#define _MC9S12C32_52 8 +#define _MC9S12C32_80 9 +#define _MC9S12D64_112 10 +#define _MC9S12D64_80 11 +#define _MC9S12DB128_112 12 +#define _MC9S12DG128_112 13 +#define _MC9S12DG128_80 14 +#define _MC9S12DG256_112 15 +#define _MC9S12DJ128_112 16 +#define _MC9S12DJ128_80 17 +#define _MC9S12DJ256_112 18 +#define _MC9S12DJ256_80 19 +#define _MC9S12DJ64_112 20 +#define _MC9S12DJ64_80 21 +#define _MC9S12DP256_112 22 +#define _MC9S12DT128_112 23 +#define _MC9S12DT256_112 24 +#define _MC9S12A32_80 25 +#define _MC9S12D32_80 26 +#define _MC9S12DP512_112 27 +#define _MC9S12A512_112 28 +#define _MC9S12E128_112 29 +#define _MC9S12E128_80 30 +#define _MC9S12E64_112 31 + + +/* Selected target MCU */ + +#define CPUtype _MC9S12C32_80 + + +/* PESL library */ + +#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ +#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ + +#include "PESLlib.h" + + diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H new file mode 100644 index 000000000..2f0b2f1ca --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H @@ -0,0 +1,50 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Const +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + +/* Constants for detecting running mode */ +#define HIGH_SPEED 0 /* High speed */ +#define LOW_SPEED 1 /* Low speed */ +#define SLOW_SPEED 2 /* Slow speed */ + +/* Reset cause constants */ +#define RSTSRC_POR 1 /* Power-on reset */ +#define RSTSRC_PIN 8 /* External reset bit */ +#define RSTSRC_COP 4 /* COP reset */ +#define RSTSRC_ILOP 2 /* Illegal opcode reset */ +#define RSTSRC_ILAD 16 /* Illegal address reset */ +#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ + +#endif /* _PE_Const_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H new file mode 100644 index 000000000..2025f4e0a --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Error +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Error" contains internal definitions +** of the error constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0 /* OK */ +#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2 /* Parameter out of range. */ +#define ERR_VALUE 3 /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4 /* Timer overflow. */ +#define ERR_MATH 5 /* Overflow during evaluation. */ +#define ERR_ENABLED 6 /* Device is enabled. */ +#define ERR_DISABLED 7 /* Device is disabled. */ +#define ERR_BUSY 8 /* Device is busy. */ +#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ +#define ERR_RXEMPTY 10 /* No data in receiver. */ +#define ERR_TXFULL 11 /* Transmitter is full. */ +#define ERR_BUSOFF 12 /* Bus not available. */ +#define ERR_OVERRUN 13 /* Overrun error is detected. */ +#define ERR_FRAMING 14 /* Framing error is detected. */ +#define ERR_PARITY 15 /* Parity error is detected. */ +#define ERR_NOISE 16 /* Noise error is detected. */ +#define ERR_IDLE 17 /* Idle error is detectes. */ +#define ERR_FAULT 18 /* Fault error is detected. */ +#define ERR_BREAK 19 /* Break char is received during communication. */ +#define ERR_CRC 20 /* CRC error is detected. */ +#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22 /* Protection error is detected. */ + +#endif __PE_Error_H diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C new file mode 100644 index 000000000..3618734f6 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C @@ -0,0 +1,69 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:44 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE PE_Timer. */ + +#include "PE_Timer.h" + + +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi1(dword High, dword Low, word *Out) +{ + if ((High == 0) && ((Low >> 24) == 0)) + if ((Low & 0x80) != 0) { + if ((Low >> 8) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 8))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 8); + return FALSE; + } + *Out = (unsigned int)(Low >> 8); + return TRUE; +} + + + +/* END PE_Timer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H new file mode 100644 index 000000000..1ec107559 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:44 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +#ifndef __PE_Timer +#define __PE_Timer +/*Include shared modules, which are used for whole project*/ +#include "PE_types.h" +#include "PE_const.h" + +/* MODULE PE_Timer. */ + +bool PE_Timer_LngHi1(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#endif /* END PE_Timer. */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H new file mode 100644 index 000000000..42c849ebd --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H @@ -0,0 +1,87 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Types +** Version : Driver 01.04 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Types" contains internal definitions +** of the types. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +#define FALSE 0 +#define TRUE 1 + +/*Types definition*/ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; +typedef void (*tIntFunc)(void); + +/* Motorola types */ +typedef unsigned char VUINT8; +typedef signed char VINT8; +typedef unsigned short int VUINT16; +typedef signed short int VINT16; +typedef unsigned long int VUINT32; + +#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) +#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } + +#define output(P, V) P = (V) +#define input(P) (P) + +#define __DI() { asm sei; } /* Disable global interrupts */ +#define __EI() { asm cli; } /* Enable global interrupts */ +#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ +#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ +/* obsolete definition for backward compatibility */ +#define SaveStatusReg() EnterCritical() +#define RestoreStatusReg() ExitCritical() + + +typedef struct { /* Black&White Image */ + word width; /* Image width */ + word height; /* Image height */ + byte *pixmap; /* Image pixel bitmap */ + word size; /* Image size */ + char *name; /* Image name */ +} TIMAGE; +typedef TIMAGE* PIMAGE ; /* Pointer to image */ + +/* 16-bit register (Motorola format - big endian) */ +typedef union { + word w; + struct { + byte high,low; + } b; +} TWREG; + +#endif /* __PE_Types_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C new file mode 100644 index 000000000..95899d4ea --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C @@ -0,0 +1,66 @@ +/** ################################################################### +** Filename : RTOSDemo.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Version : Driver 01.05 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** Main module. +** Here is to be placed user's code. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE RTOSDemo */ + +/* Including used modules for compilling procedure */ +#include "Cpu.h" +#include "Events.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +extern void vMain( void ); + +void main(void) +{ + /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ + PE_low_level_init(); + /*** End of Processor Expert internal initialization. ***/ + + /*Write your code here*/ + + /* Just jump to the real main(). */ + __asm + { + jmp vMain + } + + /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ + for(;;); + /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ +} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ + +/* END RTOSDemo */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM new file mode 100644 index 000000000..cfa3147fd --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM @@ -0,0 +1,48 @@ +/* +** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : RTOSDemo.PRM +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 18:00 +** Abstract : +** This file is used by the linker. It describes files to be linked, +** memory ranges, stack size, etc. For detailed description of the PRM file +** see CodeWarrior documentation. This file is generated by default. +** You can switch off generation by setting the property +** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify +** this file if needed. +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ################################################################### +*/ + +NAMES + +END + +SECTIONS + /* List of all sections specified on the "Build options" tab */ + RAM = READ_WRITE 0x00000800 TO 0x00000FFF; + ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000FF7F; + ROM_4000 = READ_ONLY 0x00004000 TO 0x00007FFF; +END + +PLACEMENT + DEFAULT_RAM INTO RAM; + _PRESTART, STARTUP, + ROM_VAR, STRINGS, + NON_BANKED, DEFAULT_ROM, COPY INTO ROM_C000, ROM_4000; +END + +INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ + +STACKSIZE 0x0030 /* Size of the system stack. Value can be changed on the "Build options" tab */ + diff --git a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C new file mode 100644 index 000000000..d00bb65cc --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C @@ -0,0 +1,243 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 17:53 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : TIM (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-4 +** Clock : 5999000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 160000 ticks +** microseconds : 1000 to 10000 microseconds +** milliseconds : 1 to 10 milliseconds +** seconds (real) : 0.0010000 to 0.0100000 seconds +** Hz : 100 to 1000 Hz +** +** Initialization: +** Timer : Disabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE TickTimer. */ + +#include "Events.h" +#include "TickTimer.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +static bool EnUser; /* Enable/Disable device by user */ +static word CmpHighVal; /* Compare register value for high speed CPU mode */ + + +/* +** =================================================================== +** Method : SetCV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetCV(word Val) +{ + if (Val == 0) /* If the given value is zero */ + Val = 65535; /* then change it to the maximal one */ + TC0 = Val; /* Store given value to the compare register */ + TC7 = Val; /* Store given value to the modulo register */ +} + +/* +** =================================================================== +** Method : SetPV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetPV(byte Val) +{ + TSCR2_PR = Val; /* Store given value to the prescaler */ +} + +/* +** =================================================================== +** Method : HWEnDi (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + if (EnUser) { /* Enable device? */ + TFLG1 = 1; /* Reset interrupt request flag */ + TIE_C0I = 1; /* Enable interrupt */ + } + else { /* Disable device? */ + TIE_C0I = 0; /* Disable interrupt */ + } +} + +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte TickTimer_Enable(void) +{ + if (!EnUser) { /* Is the device disabled by user? */ + EnUser = TRUE; /* If yes then set the flag "device enabled" */ + HWEnDi(); /* Enable the device */ + } + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (100 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetFreqHz(word Freq) +{ + dlong rtval; /* Result of two 32-bit numbers division */ + word rtword; /* Result of 64-bit number division */ + + if ((Freq > 1000) || (Freq < 100)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + rtval[1] = 1535744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ + rtval[0] = 0; /* Convert result to the type dlong */ + if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void TickTimer_Init(void) +{ + CmpHighVal = 5999; /* Compare register value for high speed CPU mode */ + EnUser = FALSE; /* Disable device */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + SetPV(2); /* Set prescaler register according to the selected high speed CPU mode */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + vTaskTickInterrupt(); /* Invoke user event */ +} + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +/* END TickTimer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H new file mode 100644 index 000000000..f0818fd9e --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H @@ -0,0 +1,160 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 17:53 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : TIM (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-4 +** Clock : 5999000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 160000 ticks +** microseconds : 1000 to 10000 microseconds +** milliseconds : 1 to 10 milliseconds +** seconds (real) : 0.0010000 to 0.0100000 seconds +** Hz : 100 to 1000 Hz +** +** Initialization: +** Timer : Disabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __TickTimer +#define __TickTimer + +/* MODULE TickTimer. */ + +#include "Cpu.h" + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +#define TickTimer_SFHzMin 100 /* Lower bound of interval for method SetFreqHz */ +#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ + + +byte TickTimer_Enable(void); +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +byte TickTimer_SetFreqHz(word Freq); +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (100 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void); +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +void TickTimer_Init(void); +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END TickTimer. */ + +#endif /* ifndef __TickTimer */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c b/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c new file mode 100644 index 000000000..38854b315 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c @@ -0,0 +1,115 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 18:22 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vButtonPush( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + vButtonPush, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + Cpu_Interrupt, /* 43 Default (unused) interrupt */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/C_Layout.hwl b/Demo/HCS12_CodeWarrior_small/C_Layout.hwl new file mode 100644 index 000000000..3b16d98a4 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig new file mode 100644 index 000000000..7931aed92 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig @@ -0,0 +1,23 @@ +================================================================= +This file was generated from Processor Expert 03.33 + project "RTOSDemo", 18/06/2005, 18:00 +----------------------------------------------------------------- +There is no signal defined in this project. + Hint: Signals may be defined in the Bean Inspector (advanced or expert view) +================================================================= + +================================================================= + SIGNAL LIST +----------------------------------------------------------------- + SIGNAL NAME => PIN NAME +----------------------------------------------------------------- +================================================================= + + +================================================================= + PIN LIST +----------------------------------------------------------------- + PIN NAME => SIGNAL NAME +----------------------------------------------------------------- +================================================================= + diff --git a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt new file mode 100644 index 000000000..7bfe268c6 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt @@ -0,0 +1,32 @@ +============================================================================= +List of methods in project: RTOSDemo + +THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +============================================================================= + +Module "Byte1" (bean ByteIO) + Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the + value to a memory or a register, this value will be written to the pin after switching to the output mode - + using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. + Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. + +Module "TickTimer" (bean TimerInt) + TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). + TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a + 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + +Module "ButtonInterrupt" (bean ExtInt) + ButtonInterrupt_Enable -Enable the bean - the external events are accepted. + +Module "Cpu" (bean MC9S12C32_80) + Cpu_EnableInt -Enable maskable interrupts + Cpu_DisableInt -Disable maskable interrupts + Cpu_SetWaitMode -Set low power mode - Wait mode. +For more information about the wait mode see documentation of this CPU. + +Release from Wait mode: Reset or interrupt + Cpu_SetStopMode -Set low power mode - Stop mode. +For more information about the stop mode see documentation of this CPU. + +============================================================================= diff --git a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h new file mode 100644 index 000000000..775cd2f3f --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include /* common defines and macros */ +#include "TickTimer.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2048 - 256 ) ) +#define configMAX_TASK_NAME_LEN ( 1 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This parameter is normally required in order to set the RTOS tick timer. +This port is a bit different in that hardware setup uses the code generated by +the Processor Expert, making this definition obsolete. + +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 ) +*/ + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c new file mode 100644 index 000000000..18bf12e1d --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c @@ -0,0 +1,69 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Processor Expert created headers. */ +#include "byte1.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the Processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_PutBit( uxLED, !xValue ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_NegBit( uxLED ); + portEXIT_CRITICAL(); +} + + + diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C b/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C new file mode 100644 index 000000000..f25c6b4af --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C @@ -0,0 +1,368 @@ +;Please do not modify this file! +;The file contains internal information about the Processor Expert project generation +[Options] +ProjectName=RTOSDemo +ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\ +DestEventsDirectory=CODE\ +DestDriversSubDirectory= +DestDocumentationDirectory=DOC\ +DestCompiledFilesSubDirectory= +DestFpgaSubDirectory= +DestTemporaryDirectory= +[GenFiles] +LinkerFileGenerated=Yes +MakefileGenerated=No +GenSharedModules=5 +Line=PE_Types +Line=PE_Error +Line=PE_Const +Line=IO_Map +Line=PE_Timer +ShrdHeaderAge0=850024804 +ShrdCodeAge0=-1 +ShrdAsemblAge0=-1 +ShrdHeaderAge1=850024804 +ShrdCodeAge1=-1 +ShrdAsemblAge1=-1 +ShrdHeaderAge2=850024804 +ShrdCodeAge2=-1 +ShrdAsemblAge2=-1 +ShrdHeaderAge3=850024804 +ShrdCodeAge3=850024804 +ShrdAsemblAge3=-1 +ShrdHeaderAge4=850478475 +ShrdCodeAge4=850478475 +ShrdAsemblAge4=-1 +GenExtraFiles=2 +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\Vectors.c +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\PESL.h +XtraAge0=852660312 +XtraAge1=850024804 +GenExtraFileType1=4 +GenExtraFileType0=4 +GenEventModules=1 +Line=Events +GenMethodsInEvents=0 +GenAllModules=10 +Line=ButtonInterrupt +Line=Byte1 +Line=Cpu +Line=Events +Line=IO_Map +Line=PE_Const +Line=PE_Error +Line=PE_Timer +Line=PE_Types +Line=TickTimer +GenExternModules=0 +GenBeanModules=3 +Line=ButtonInterrupt +Line=TickTimer +Line=Byte1 +SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\DOC\RTOSDemo.sig +DestinationCompiler=MetrowerksHC12CC +ProjectModificationStamp=23 + +[18] +Generated=Yes +GenCompName=Cpu +GenEventModule=Events +HeaderAge=850478231 +CodeAge=852660246 +AsemblAge=-1 +GenNumMethods=10 +SetStopMode=Yes +SetWaitMode=Yes +DisableInt=Yes +EnableInt=Yes +GetIntVect=No +SetIntVect=No +GetSpeedMode=No +SetSlowSpeed=No +SetLowSpeed=No +SetHighSpeed=No +GenNumEvents=4 +OnClockMonitorFail_Selected=1 +OnClockMonitorFail_Name=Cpu_OnClockMonitorFail +OnClockMonitorFail_Priority=interrupts disabled +OnIllegalOpcode_Selected=1 +OnIllegalOpcode_Name=Cpu_OnIllegalOpcode +OnIllegalOpcode_Priority=interrupts disabled +OnReset_Selected=1 +OnReset_Name=Cpu_OnReset +OnReset_Priority=interrupts disabled +OnSwINT_Selected=1 +OnSwINT_Name=Cpu_OnSwINT +OnSwINT_Priority=interrupts disabled +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No + +[22] +Generated=Yes +GenCompName=Byte1 +GenEventModule=Events +HeaderAge=850026034 +CodeAge=850026034 +AsemblAge=-1 +GenNumMethods=9 +NegBit=Yes +ClrBit=No +SetBit=No +PutBit=Yes +GetBit=No +PutVal=No +GetVal=No +SetDir=No +GetDir=No +GenNumEvents=0 +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=5 +MethodPos0=PutBit +MethodType=method +ModuleType=Header +LineBeg=65 +LineEnd=81 +MethodPos1=NegBit +MethodType=method +ModuleType=Header +LineBeg=82 +LineEnd=96 +MethodPos2=GetMsk +MethodType=internal_method +ModuleType=Code +LineBeg=67 +LineEnd=82 +MethodPos3=PutBit +MethodType=method +ModuleType=Code +LineBeg=83 +LineEnd=110 +MethodPos4=NegBit +MethodType=method +ModuleType=Code +LineBeg=111 +LineEnd=132 + +[25] +Generated=Yes +GenCompName=TickTimer +GenEventModule=Events +HeaderAge=852659892 +CodeAge=852659892 +AsemblAge=-1 +GenNumMethods=14 +SetFreqMHz=No +SetFreqkHz=No +SetFreqHz=Yes +SetPeriodReal=No +SetPeriodSec=No +SetPeriodMS=No +SetPeriodUS=No +SetPeriodTicks32=No +SetPeriodTicks16=No +SetPeriodMode=No +DisableEvent=No +EnableEvent=No +Disable=No +Enable=Yes +GenNumEvents=3 +BeforeNewSpeed_Selected=1 +BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed +BeforeNewSpeed_Priority=interrupts disabled +AfterNewSpeed_Selected=1 +AfterNewSpeed_Name=TickTimer_AfterNewSpeed +AfterNewSpeed_Priority=interrupts disabled +OnInterrupt_Selected=2 +OnInterrupt_Name=vTaskTickInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=11 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=80 +LineEnd=96 +MethodPos1=SetFreqHz +MethodType=method +ModuleType=Header +LineBeg=97 +LineEnd=122 +MethodPos2=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=123 +LineEnd=135 +MethodPos3=Init +MethodType=internal_method +ModuleType=Header +LineBeg=136 +LineEnd=146 +MethodPos4=SetCV +MethodType=internal_method +ModuleType=Code +LineBeg=82 +LineEnd=98 +MethodPos5=SetPV +MethodType=internal_method +ModuleType=Code +LineBeg=99 +LineEnd=112 +MethodPos6=HWEnDi +MethodType=internal_method +ModuleType=Code +LineBeg=113 +LineEnd=132 +MethodPos7=Enable +MethodType=method +ModuleType=Code +LineBeg=133 +LineEnd=156 +MethodPos8=SetFreqHz +MethodType=method +ModuleType=Code +LineBeg=157 +LineEnd=196 +MethodPos9=Init +MethodType=internal_method +ModuleType=Code +LineBeg=197 +LineEnd=214 +MethodPos10=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=215 +LineEnd=231 + +[26] +Generated=Yes +GenCompName=ButtonInterrupt +GenEventModule=Events +HeaderAge=850630744 +CodeAge=850630744 +AsemblAge=-1 +GenNumMethods=4 +SetEdge=No +GetVal=No +Disable=No +Enable=Yes +GenNumEvents=1 +OnInterrupt_Selected=2 +OnInterrupt_Name=ButtonInterrupt_OnInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=4 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=71 +LineEnd=82 +MethodPos1=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=83 +LineEnd=95 +MethodPos2=Enable +MethodType=method +ModuleType=Code +LineBeg=73 +LineEnd=88 +MethodPos3=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=89 +LineEnd=105 + +[UsedSrcFiles] +SrcFile=Drivers\ByteIO.src=779379247 +SrcFile=Drivers\HCS12\ByteIO.drv=786325143 +SrcFile=Drivers\Common\Header.h=788035759 +SrcFile=Drivers\Common\ByteIOAbstract.Inc=697533609 +SrcFile=Drivers\Common\ByteIOSettings.Inc=662077581 +SrcFile=Drivers\Common\UsedPins.inc=662077580 +SrcFile=Drivers\HCS12\CreateCodeSection.prg=759717537 +SrcFile=Drivers\Common\ByteIOPutBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralPutBit.inc=724263173 +SrcFile=Drivers\Common\GeneralMethod.inc=711812818 +SrcFile=Drivers\Common\GeneralParameters.inc=711813750 +SrcFile=Drivers\Common\GeneralReturnNothing.inc=711816104 +SrcFile=Drivers\Common\GeneralDamage.inc=711813453 +SrcFile=Drivers\Common\ByteIONegBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralNegBit.inc=724263119 +SrcFile=Drivers\Common\Header.End=710308512 +SrcFile=Drivers\Common\Header.c=788035759 +SrcFile=Drivers\HCS12\CreateDataSection.prg=759780817 +SrcFile=Drivers\Common\GeneralInternal.Inc=724263004 +SrcFile=Drivers\TimerInt.src=779379233 +SrcFile=Drivers\HCS12\TimerInt.drv=790330280 +SrcFile=Drivers\Common\TimerIntAbstract.Inc=697533454 +SrcFile=Drivers\Common\TimerIntSettings.Inc=662077596 +SrcFile=Drivers\Common\TimerIntEnable.Inc=724722488 +SrcFile=Drivers\Common\GeneralParametersNone.inc=711813294 +SrcFile=Drivers\Common\TimerIntSetFreqHz.Inc=724921137 +SrcFile=Drivers\HCS12\CreateIntSection.prg=760697835 +SrcFile=Drivers\Common\TimerIntInterrupt.Inc=662077583 +SrcFile=Drivers\Common\TimerIntOnInterrupt.Inc=724722488 +SrcFile=Drivers\Common\GeneralEvent.inc=711816218 +SrcFile=Drivers\Common\GeneralInternalGlobal.Inc=724263104 +SrcFile=Drivers\Common\InitReg8.prg=727217490 +SrcFile=Drivers\Common\InitReg8Enable.prg=783766675 +SrcFile=Drivers\ExtInt.src=779379242 +SrcFile=Drivers\HCS12\ExternalInterrupt.drv=786325143 +SrcFile=Drivers\Common\ExternalInterruptAbstract.Inc=697533660 +SrcFile=Drivers\Common\ExternalInterruptSettings.Inc=662077582 +SrcFile=Drivers\Common\UsedPin.inc=662077580 +SrcFile=Drivers\Common\ExternalInterruptEnable.Inc=724459205 +SrcFile=Drivers\Common\ExternalInterruptOnInterrupt.inc=724459205 +SrcFile=Drivers\HCS12\PE_Types.drv=790261986 +SrcFile=Drivers\Common\PE_TypesAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_TypesSettings.Inc=662077595 +SrcFile=Drivers\HCS12\PE_Error.drv=744839008 +SrcFile=Drivers\Common\PE_ErrorAbstract.Inc=662077580 +SrcFile=Drivers\Common\ErrorDefinitions.Inc=781282486 +SrcFile=Drivers\HCS12\PE_Const.drv=744839020 +SrcFile=Drivers\Common\PE_ConstAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_ConstSettings.Inc=662077595 +SrcFile=Drivers\HCS12\IO_Map.drv=790392555 +SrcFile=Drivers\Common\IO_MapAbstract.Inc=662077601 +SrcFile=Drivers\Common\IO_MapSettings.Inc=662077601 +SrcFile=Drivers\HCS12\MC9S12C32_80h.prg=788297413 +SrcFile=Drivers\HCS12\MC9S12C32_80c.prg=787968924 +SrcFile=Drivers\HCS12\PE_Timer.drv=764054261 +SrcFile=Drivers\Common\PE_TimerConstants.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerMethods.Inc=662077585 +SrcFile=Drivers\Common\PE_TimerAbstract.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerSettings.Inc=662077581 +SrcFile=Drivers\Common\PE_TimerLngHi1.Inc=662077594 +SrcFile=Drivers\MC9S12C32_80.src=783110234 +SrcFile=Drivers\HCS12\MC9S12.drv=788297552 +SrcFile=Drivers\Common\MC9S12Abstract.Inc=786070990 +SrcFile=Drivers\Common\MC9S12Settings.Inc=786070990 +SrcFile=Drivers\Common\MC9S12SetStopMode.Inc=786070990 +SrcFile=Drivers\Common\MC9S12SetWaitMode.Inc=786070990 +SrcFile=Drivers\Common\MC9S12DisableInt.Inc=786070990 +SrcFile=Drivers\Common\MC9S12EnableInt.Inc=786070990 +SrcFile=Drivers\Common\GenReg8InitInfo.prg=754344225 +SrcFile=Drivers\Common\GenReg8BitsInitInfo.prg=777356856 +SrcFile=Drivers\Common\CommonInitialization.prg=760832797 +SrcFile=Drivers\Common\CommonRegInitialization.prg=785882407 +SrcFile=Drivers\Common\SetRegBits8.prg=775453568 +SrcFile=Drivers\Common\SetReg8.prg=776374479 +SrcFile=Drivers\Common\CommonEnabling.prg=783766630 +SrcFile=Drivers\Common\CommonRegEnabling.prg=785882407 +SrcFile=Drivers\HCS12\PESL.prg=790397020 +SrcFile=Drivers\Event.src=779379228 +SrcFile=Drivers\HCS12\Evnt.drv=763978411 +SrcFile=Drivers\Common\EvntAbstract.Inc=662077596 +SrcFile=Drivers\Common\EvntSettings.inc=662077580 +SrcFile=Drivers\Common\Header.In1=710699431 +SrcFile=Drivers\_PE_ProjectInfo.src=713322570 +SrcFile=Drivers\SW\_PE_ProjectInfo.drv=726426382 + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk b/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk new file mode 100644 index 000000000..14b46d97a --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk @@ -0,0 +1,166 @@ +[Version] +PE_DesktopFileVersion=819 + +[Desktop] +StartupPrj=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\RTOSDemo.pe + +[PE_IDE_PlugIn] + +[CpuExpert] + +[AppPanel] +AllFocusedNode=Cpu:MC9S12C32CFU +ConfigurationsInAllExpanded=Yes +CPUsInAllExpanded=Yes +FPGAsInAllExpanded=No +OperatingSystemInAllExpanded=Yes +BeansInAllExpanded=Yes +TasksInAllExpanded=No +ProgramsInAllExpanded=No +DocumentationInAllExpanded=No +PESLInAllExpanded=No +PESL_moduleInAllExpanded=No +ViewEnabledItemsOnly=No + +[CpuPanel] +Status=hiden +WindowState=NORMAL +Rect=[-568|282|617|532] +CpuPanViewMode=Default + +[ErrorPanel] +Status=hiden +WindowState=NORMAL +Rect=[4|94|1608|1130] + +[ResourceMeter] +Status=hiden +WindowState=NORMAL +Rect=[49|1168|617|178] + +[BeanSelector] +Status=Visible +WindowState=NORMAL +Rect=[-4|62|1608|1130] +BF_ForTgtCpuOnly=Yes +BF_LicensedOnly=Yes + +[ObjInspector] +Status=Visible +WindowState=MAXIMAL +Rect=[-4|62|1199|1100] +ColWidth01=263 +ColWidth02=479 +ColWidth11=188 +ColWidth12=317 +ColWidth21=180 +ColWidth22=352 +ColWidth31=255 +ColWidth32=479 +ColWidth41=133 +ColWidth42=266 +ViewItemLevel=2 + +[PrphInspector] +Status=hiden +WindowState=NORMAL +Rect=[-466|400|516|411] +ViewMode=PrphUsageReport +SortRegsByAddr=Yes +GroupRegisters=No +Peripheral= + +[Editor] +Rect=[-4|0|1199|1100] +FontName=Courier New +FontSize=10 +FontBold=No +FontItalic=No +FontScript=1 +ToolBar=Yes +ToolBarPosition=top +SyntaxHighlighting=Yes +NoHorizScrollBar=Yes +ShowLineNumbers=No +PreserveCurPosDuringPaste=No +UseTabChar=No +ModulesInOneWindow=Yes +TabSize=8 +HintDelay=2 +OpenFilesCount=0 +SelFile= +SelLine=-1 +FileHistory=0 + +[CpuStructure] +Rect=[0|0|0|0] + +[StrListEditor] +WindowWidth=450 +WindowHeight=333 + +[Breakpoints] +WindowVisible=No +Rect=[0|0|0|0] +BreakLine1=0 +BreakModule1= + +[Watches] +Rect=[0|0|0|0] +WindowVisible=No +WatchCount=0 +WatchHistoryCount=0 + +[Registers] +Rect=[0|0|100|500] +WindowVisible=No + +[Dump] +WindowVisible=No +Rect=[0|0|0|0] +Address=0 +DataSize=1 +DataType=num +HistoryAddrCount=0 + +[InterruptVectors] +WindowVisible=No +Rect=[0|0|0|0] + +[MemoryMap] +Rect=[422|156|355|480] +DisplayOnlyMemories=No +WindowVisible=No + +[Browser] +Rect=[0|0|0|0] +WindowVisible=No + +[BeanManager] +Rect=[0|0|0|0] +BeanInfoFilter= +DriverFilter= +DriverInfoFilter= +BeanSettingsProjectFilter= + +[Options] +AutosaveWithProject=No +AutosaveBeforeTool=No +NumberOfBackupCopies=0 +AutoSaveDesktop=Yes +AutoOpenPropEdit=Yes +AutoConnectDevice=Yes +SelectTemplate=No +ShowGenProgress=Yes +AutoShowGeneratedSrc=No +AutoShowEventModules=No +ShowMethodCode=No +GenerateUndo=No +CpuBitmapFileName=Config\PE\CPUbckgr.bmp +CpuBitmapTilled=No +ShowProducerLogo=No +AutoStartApplicationCode=No +ShowSourceLinAfterDbgInit=No +RestoreFilesAfterDebug=No + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp b/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp new file mode 100644 index 000000000..14c456857 Binary files /dev/null and b/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe b/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe new file mode 100644 index 000000000..54386559d --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe @@ -0,0 +1,2387 @@ +Processor Expert Version 0333 +ProjectModificationStamp=23 + +[Options] +EventsDirectory=CODE\ +DestinationSubDir= +DocumentationDir=DOC\ +CompiledFilesSubDir= +FPGAsubdirectory= +TemporaryDir=%TEMP% +OverwriteEvents=3 +OverwriteBeanDrv=0 +UseExistingModules=Yes +RenamePeripheries=Yes +Autodependency=Yes +ProjectCompNumb=27 +DelUnusedPreviouslyGenFiles=Yes + +[MC9S12C32_80:Cpu] +CompNumb=18 +CompEnabled=Yes +GenCodeMode=CHECK_n_WRITE +IconName=CPU_CHIP2 +Comment=0 +Template= + +[Properties] +List=Property +[ItemState] +ItemSymbol=DeviceName +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=Cpu +[ItemState] +ItemSymbol=CPU +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=MC9S12C32CFU +[ItemState] +ItemSymbol=Xtal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=16 +[ItemState] +ItemSymbol=InitPriority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=interrupts disabled +[ItemState] +ItemSymbol=PLLStopsInWait +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=HC12_ChipSelects +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=MemMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +[ItemState] +ItemSymbol=HC12_INTFLASHON +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HalfFlashEn +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=ExtBusGrp +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ExtBusStretch +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=3 + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=HC12_InternalMapping +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HC12_INITRG +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +[ItemState] +ItemSymbol=HC12_INITRM +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +TypeSpecNameState=typeHCS12_RAMMapping2kRAM +Index=1 + +[EndOfChilds] +[ItemState] +ItemSymbol=Intperiphgrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PWMmoduleGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PWMStopsInWait +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PWMStopsInFreeze +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PWMEmergency +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PWMEmergencyInputLevel +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +[ItemState] +ItemSymbol=PWMEmergencyShutLevel +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=ECTmoduleGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ECTStopsInWait +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=ECTStopsInFreeze +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=IOmoduleGrp0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PortAGrp0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PAreduceddrive +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=PortBGrp0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PBreduceddrive +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=PortEGrp0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PEreduceddrive +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=PortTGrp0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PTreduceddriveBit0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PTreduceddriveBit1 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PTreduceddriveBit2 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PTreduceddriveBit3 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PTreduceddriveBit4 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=PTreduceddriveBit5 +ReadOnly=No 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+UsrMethodName=GetVal +[ItemState] +ItemSymbol=PutVal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=PutVal +[ItemState] +ItemSymbol=GetBit +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetBit +[ItemState] +ItemSymbol=PutBit +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=PutBit +[ItemState] +ItemSymbol=SetBit +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetBit +[ItemState] +ItemSymbol=ClrBit +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ClrBit +[ItemState] +ItemSymbol=NegBit +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=NegBit + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events + +[TimerInt:TickTimer] +CompNumb=25 +CompEnabled=Yes +GenCodeMode=CHECK_n_WRITE +IconName=TMRCNTR +Comment=0 +Template= + +[Properties] +List=Property +[ItemState] +ItemSymbol=DeviceName +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=TickTimer +[ItemState] +ItemSymbol=_Cmp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=TC0 +SharedPrphMode=No +[ItemState] +ItemSymbol=Tmr +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=TIM +SharedPrphMode=No +[ItemState] +ItemSymbol=IntService +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=CmpInt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=INT_TC0 +SharedPrphMode=No +[ItemState] +ItemSymbol=CmpInitPriority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=medium priority +[ItemState] +ItemSymbol=COP8_grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ScndReloadGrp +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ScndTmr +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=EXPERT +Value= +SharedPrphMode=No +[ItemState] +ItemSymbol=ScndIntr +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +SharedPrphMode=No + +[EndOfChilds] + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=COP8grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=COP8TimerSpeedBase +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +TypeSpecNameState=typeCOP8_TimerPrescalerDefault +Index=0 + +[EndOfChilds] +[ItemState] +ItemSymbol=InitPrescaler +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InternPrescaler +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem + +[EndOfChilds] +Value=Auto selected prescaler +[ItemState] +ItemSymbol=InternCompare +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem + +[EndOfChilds] +Value=Auto selected prescaler + +[EndOfChilds] +Value=Auto selected prescaler +[ItemState] +ItemSymbol=_Tmg +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=1000 Hz +RuntimeSetting=1 +InitValue=1000 Hz +Precision=5 +PrecInProc=Yes +LowLimit=100 Hz +HighLimit=1000 Hz +List=0 +UnitText=Hz +[ItemState] +ItemSymbol=SameValuesInAllModes +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=EntireTimer +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +[ItemState] +ItemSymbol=_InitGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InitEnable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=InitEnableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=_SpeedGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HighSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=LowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=SlowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=MirrorECTmoduleGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem + +[EndOfChilds] + +[Methods] +List=Method +[ItemState] +ItemSymbol=Enable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=Enable +[ItemState] +ItemSymbol=Disable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Disable +[ItemState] +ItemSymbol=EnableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=EnableEvent +[ItemState] +ItemSymbol=DisableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=DisableEvent +[ItemState] +ItemSymbol=SetPeriodMode +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=never +UsrMethodName=SetPeriodMode +[ItemState] +ItemSymbol=SetPeriodTicks16 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodTicks16 +[ItemState] +ItemSymbol=SetPeriodTicks32 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodTicks32 +[ItemState] +ItemSymbol=SetPeriodUS +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodUS +[ItemState] +ItemSymbol=SetPeriodMS +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodMS +[ItemState] +ItemSymbol=SetPeriodSec +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetPeriodSec +[ItemState] +ItemSymbol=SetPeriodReal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetPeriodReal +[ItemState] +ItemSymbol=SetFreqHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=SetFreqHz +[ItemState] +ItemSymbol=SetFreqkHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFreqkHz +[ItemState] +ItemSymbol=SetFreqMHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFreqMHz + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=BeforeNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=TickTimer_BeforeNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=AfterNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=TickTimer_AfterNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=OnInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=vTaskTickInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=always + +[ExtInt:ButtonInterrupt] +CompNumb=26 +CompEnabled=Yes +GenCodeMode=CHECK_n_WRITE +IconName=EXTINT +Comment=0 +Template= + +[Properties] +List=Property +[ItemState] +ItemSymbol=DeviceName +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=ButtonInterrupt +[ItemState] +ItemSymbol=_Pin +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=PP0_PWM0_KWP0 +SharedPrphMode=No +[ItemState] +ItemSymbol=PinSignal +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +[ItemState] +ItemSymbol=PullMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +TypeSpecNameState=typePULL +Index=1 +[ItemState] +ItemSymbol=InitEdge +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=2 +[ItemState] +ItemSymbol=HCS08grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Invert +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=Int +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=INT_PortP +SharedPrphMode=No +[ItemState] +ItemSymbol=InitPriority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=medium priority +[ItemState] +ItemSymbol=JBJGcond +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PTE4Int +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SHpin +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value= +SharedPrphMode=No +[ItemState] +ItemSymbol=SHPinSignal +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +[ItemState] +ItemSymbol=SHPullMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +TypeSpecNameState=typePULL +Index=5 + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=_InitGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InitEnable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] + +[Methods] +List=Method +[ItemState] +ItemSymbol=Enable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=Enable +[ItemState] +ItemSymbol=Disable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Disable +[ItemState] +ItemSymbol=GetVal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetVal +[ItemState] +ItemSymbol=SetEdge +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetEdge +[ItemState] +ItemSymbol=56800grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ConnectPin +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ConnectPin + +[EndOfChilds] + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=OnInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=ButtonInterrupt_OnInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=always +[ItemState] +ItemSymbol=CPUCondJBJG +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=OnTriggerInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=ButtonInterrupt_OnTriggerInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=interrupts disabled + +[EndOfChilds] +LastSelection=No +LastUserSel=never + +[EndOfChilds] + +[Program] +ProgType=event +ProgNumb=2 +List=Property +EventModule=Events + +[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg new file mode 100644 index 000000000..34ba6fcbe Binary files /dev/null and b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt new file mode 100644 index 000000000..908534209 Binary files /dev/null and b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt new file mode 100644 index 000000000..f3e53147f Binary files /dev/null and b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt differ diff --git a/Demo/HCS12_CodeWarrior_small/Simulator.ini b/Demo/HCS12_CodeWarrior_small/Simulator.ini new file mode 100644 index 000000000..bf14c5590 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/Simulator.ini @@ -0,0 +1,41 @@ +[Environment Variables] +GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib +LIBPATH={Compiler}lib\HC12c\include +OBJPATH={Project}bin +TEXTPATH={Project}bin +ABSPATH={Project}bin + +[HI-WAVE] +Target=sim +Layout=C_layout.hwl +LoadDialogOptions= +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,243,243,1443,1097 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 + +[Simulator] +CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd" + +[Simulator HC12] +CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd" +CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd" +CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd" +CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd" +HCS12_SUPPORT=1 +FCS=MC9S12C32 + +[Recent Applications File List] +File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\Simulator.abs +File2= +File3= +File4= +LoadFlags1=4099 +LoadFlags2=0 +LoadFlags3=0 +LoadFlags4=0 + +[Recent Layout File List] +File1=C_layout.hwl +File2= +File3= +File4= diff --git a/Demo/HCS12_CodeWarrior_small/SofTec.ini b/Demo/HCS12_CodeWarrior_small/SofTec.ini new file mode 100644 index 000000000..88e349622 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/SofTec.ini @@ -0,0 +1,50 @@ +[Environment Variables] +GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib +LIBPATH={Compiler}lib\HC12c\include +OBJPATH={Project}bin +TEXTPATH={Project}bin +ABSPATH={Project}bin + +[HI-WAVE] +Target=gdi +Layout=C_layout.hwl +LoadDialogOptions=AUTOERASEANDFLASH +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,216,216,1416,1070 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 + +[GDI] +COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL "SofTec_BDM12.dll" + +[SofTec_Microsystems_GdiHCS12] +Hardware=PK-HCS12C32 +DeviceName=MC9S12C32 +Settings=- + +[inDART-HCS12_GDI_SETTINGS] +CMDFILE0=CMDFILE STARTUP ON ".\cmd\SofTec_startup.cmd" +CMDFILE1=CMDFILE RESET ON ".\cmd\SofTec_reset.cmd" +CMDFILE2=CMDFILE PRELOAD ON ".\cmd\SofTec_preload.cmd" +CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\SofTec_postload.cmd" +BNKA_MCUID03E1_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 2 0x3E +BNKA_MCUID03E1_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0 +BNKA_MCUID03E1_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0 +DBG_S12_0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON +DBG_S12_1=DBG USER12 0x0 0x0 0x0 0x0 +DBG_S12_2=DBG PREDEFINED SELECT 0 END STOP 0x0 DATAMATCH_HIGH NORMAL + +[Recent Applications File List] +File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\SofTec.abs +File2= +File3= +File4= +LoadFlags1=4099 +LoadFlags2=0 +LoadFlags3=0 +LoadFlags4=0 + +[Recent Layout File List] +File1=C_layout.hwl +File2= +File3= +File4= diff --git a/Demo/HCS12_CodeWarrior_small/Sources/Start12.c b/Demo/HCS12_CodeWarrior_small/Sources/Start12.c new file mode 100644 index 000000000..df8b0e648 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/Sources/Start12.c @@ -0,0 +1,342 @@ +/***************************************************** + start12.c - standard startup code + The startup code may be optimized to special user requests + ---------------------------------------------------- + Copyright (c) Metrowerks, Basel, Switzerland + All rights reserved + Do not modify! + +Note: ROM libraries are not implemented in this startup code +Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. + To use this feature, please build your application with the ELF object file format. + *****************************************************/ + +#include "hidef.h" +#include "start12.h" + +/* Macros to control how the startup code handles the COP: */ +/* #define _DO_FEED_COP_ : do feed the COP */ +/* #define _DO_ENABLE_COP_: do enable the COP */ +/* #define _DO_DISABLE_COP_: disable the COP */ +/* Without defining any of these, the startup code does NOT handle the COP */ + +#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */ +struct _tagStartup _startupData; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ +#pragma DATA_SEG DEFAULT +#if defined(FAR_DATA) +#include "non_bank.sgm" +/* the init function must be in non banked memory if banked variables are used */ +/* because _SET_PAGE is called, which may change any page register. */ + +#ifdef __cplusplus + extern "C" +#endif +void _SET_PAGE(void); /* the inline assembler needs a prototype */ + /* this is a runtime routine with a special */ + /* calling convention, dont use it in c code! */ +static void Init(void); +static void Fini(void); +#else +#include "default.sgm" +#if defined( __BANKED__) || defined(__LARGE__) +static void __far Init(void); +static void __far Fini(void); +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#endif /* FAR_DATA */ + + +/* define value and bits for Windef Register */ +#ifdef HC812A4 +#define WINDEF (*(volatile unsigned char*) 0x37) +#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) +#define __ENABLE_PPAGE__ 0x40 +#else +#define __ENABLE_PPAGE__ 0x0 +#endif +#if defined(__DPAGE__) +#define __ENABLE_DPAGE__ 0x80 +#else +#define __ENABLE_DPAGE__ 0x0 +#endif +#if defined(__EPAGE__) +#define __ENABLE_EPAGE__ 0x20 +#else +#define __ENABLE_EPAGE__ 0x0 +#endif +#endif /* HC812A4 */ + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ +#define ___INITRM (*(volatile unsigned char *) 0x0010) +#define ___INITRG (*(volatile unsigned char *) 0x0011) +#define ___INITEE (*(volatile unsigned char *) 0x0012) +#endif + +#if defined(_DO_FEED_COP_) +#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm { +#else +#define __FEED_COP_IN_HLI() /* do nothing */ +#endif + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Init(void) +#else +static void Init(void) +#endif + { +/* purpose: 1) zero out RAM-areas where data is allocated */ +/* 2) copy initialization data from ROM to RAM */ +/* 3) call global constructors in C++ */ +/* called from: _Startup, LibInits */ + __asm { +ZeroOut: +#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) + LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer +#else + LDX _startupData.pZeroOut ; *pZeroOut +#endif + LDY _startupData.nofZeroOuts ; nofZeroOuts + BEQ CopyDown ; if nothing to zero out + +NextZeroOut: PSHY ; save nofZeroOuts +#ifdef FAR_DATA + LDAB 1,X+ ; load page of destination address + LDY 2,X+ ; load offset of destination address + __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register +#else /* FAR_DATA */ + LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) +#endif /* FAR_DATA */ + LDD 2,X+ ; byte count +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +NextWord: CLR 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, NextWord ; dec byte count +#else + LSRD ; /2 and save bit 0 in the carry + PSHX + LDX #0 +LoopClrW: STX 2,Y+ ; Word-Clear + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, LoopClrW + PULX + BCC LastClr ; handle last byte + CLR 1,Y+ +LastClr: +#endif + PULY ; restore nofZeroOuts + DEY ; dec nofZeroOuts + BNE NextZeroOut +CopyDown: +#ifdef __ELF_OBJECT_FILE_FORMAT__ + LDX _startupData.toCopyDownBeg ; load address of copy down desc. +#else + LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. +#endif +NextBlock: + LDD 2,X+ ; size of init-data -> D + BEQ funcInits ; end of copy down desc. +#ifdef FAR_DATA + PSHD ; save counter + LDAB 1,X+ ; load destination page + LDY 2,X+ ; destination address + __PIC_JSR(_SET_PAGE) ; sets the destinations page register + PULD ; restore counter +#else /* FAR_DATA */ + LDY 2,X+ ; load destination address +#endif /* FAR_DATA */ + +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + __asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + + +#include "non_bank.sgm" + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +#ifdef __cplusplus + extern "C" +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) + +#if defined(__SET_RESET_VECTOR__) +void __interrupt 0 _Startup(void) { +#else +void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + for(;;) { /* forever: initialize the program; call the root-procedure */ + if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ + } + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ +#endif + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + Init(); /* zero out, copy down, call constructors */ + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* call main() */ + (*_startupData.main)(); + + /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ + /* the HIWARE object file format does not support this */ +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + Fini(); +#endif + + } /* end loop forever */ +} diff --git a/Demo/HCS12_CodeWarrior_small/Sources/datapage.c b/Demo/HCS12_CodeWarrior_small/Sources/datapage.c new file mode 100644 index 000000000..80be5c566 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/Sources/datapage.c @@ -0,0 +1,843 @@ +/****************************************************************************** + FILE : datapage.c + PURPOSE : paged data access runtime routines + MACHINE : Motorola 68HC12 (Target) + LANGUAGE : ANSI-C + HISTORY : 21.7.96 first version created +******************************************************************************/ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. + If some of the -Cp options are given an adapted versions which only covers the + needed cases is produced. +*/ + +/* if no compiler option -Cp is given, it is assumed that all possible are given : */ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ +#define PPAGE_ADDR (0x30+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#define REGISTER_BASE 0x0u +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#include "hidef.h" +#include "non_bank.sgm" +#include "runtime.sgm" + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is usually no problem because the page is set again before any other access */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifing the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we dont know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE +#if defined(__EPAGE__) + BLO L_EPAGE ; EPAGE accesses are possible +#else + BLO L_NOPAGE ; no paged memory below accesses +#endif + CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE +#if defined(__PPAGE__) + BHI L_PPAGE ; EPAGE accesses are possible +#else + BHI L_NOPAGE ; no paged memory above accesses +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ; load page register address and clear zero flag + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ; no paged memory below +#endif + CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one pageregister or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ; set page register +L_NOPAGE: + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ; set page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDY 0,Y ; actual load, overwrites address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDY 0,Y ; actual load, overwrites address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDY 0,Y ; actual load, overwrites address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ; save page register + PSHA ; put it onto the stack + STAB 0,X ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,0,X ; restore page register + PULX ; restore X register + RTS +L_NOPAGE: + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ; save page register + PSHA ; put it onto the stack + STAB PAGE_ADDR ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,PAGE_ADDR; restore page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ; save B register + LDAB 0,X ; save page register + MOVB 0,SP, 0,X ; set page register + STAA 0,Y ; store the value passed in A + STAB 0,X ; restore page register + PULB ; restore B register + PULX ; restore X register + RTS +L_NOPAGE: + STAA 0,Y ; store the value passed in A + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ; save A register + LDAB PAGE_ADDR ; save page register + MOVB 0,SP,PAGE_ADDR ; set page register + STAA 0,Y ; store the value passed in A + STAB PAGE_ADDR ; restore page register + PULB ; restore B register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 0,Y ; store the value passed in X + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 1,Y ; store the value passed in X + MOVB 0,SP, 0,Y ; store the value passed in A + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 1,Y ; store the value passed in X + STAA 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + MOVB 0,SP, 0,Y ; store the value passed in A + STX 1,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ; save page register + MOVB 6,SP, 0,X ; set page register + MOVW 2,SP, 0,Y ; store the value passed in X (high word) + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA 0,X ; restore page register + PULD ; restore A register + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ; store the value passed in X (high word) + STD 2,Y ; store the value passed in D (low word) +done: + PULX ; restore X register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ; save D register + LDAA PAGE_ADDR ; save page register + LDAB 4,SP ; load page part of address + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA PAGE_ADDR ; restore page register + PULD ; restore D register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied at 2,SP. The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroied + - all page register still contain the same value + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : return address + 8,SP : counter, > 0 + --------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ; source addr-=1, because loop counter ends at 1 + PSHX ; save source offset + PSHD ; save both pages + DEY ; destination addr-=1, because loop counter ends at 1 + PSHY ; save destination offset + LDX 8,SP ; load counter, assuming counter > 0 + +loop: + LDD 4,SP ; load source offset + LEAY D,X ; calcutate actual source address + LDAB 2,SP ; load source page + __PIC_JSR (_LOAD_FAR_8); load 1 source byte + PSHB ; save value + LDD 0+1,SP ; load destination offset + LEAY D,X ; calcutate acual destination address + PULA ; restore value + LDAB 3,SP ; load destination page + __PIC_JSR (_STORE_FAR_8); store one byte + DEX + BNE loop + LDX 6,SP ; load return address + LEAS 10,SP ; release stack + JMP 0,X ; return + } +#else + asm { + PSHD ; store page registers + TFR X,D + ADDD 4,SP ; calculate source end address + STD 4,SP + PULB ; reload source page + LDAA PAGE_ADDR ; save page register + PSHA +loop: + STAB PAGE_ADDR ; set source page + LDAA 1,X+ ; load value + MOVB 1,SP, PAGE_ADDR ; set destination page + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ; restore old page value and release stack + STAA PAGE_ADDR ; store it into page register + LDX 4,SP+ ; release stack and load return address + JMP 0,X ; return + } +#endif +} + diff --git a/Demo/HCS12_CodeWarrior_small/bin/Simulator.map b/Demo/HCS12_CodeWarrior_small/bin/Simulator.map new file mode 100644 index 000000000..64c54c7eb --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/bin/Simulator.map @@ -0,0 +1,2175 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\Simulator.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: SMALL +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: SMALL, Lang: ANSI-C +STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +Cpu.C.o Model: SMALL, Lang: ANSI-C +Byte1.C.o Model: SMALL, Lang: ANSI-C +IO_Map.C.o Model: SMALL, Lang: ANSI-C +Vectors.c.o Model: SMALL, Lang: ANSI-C +RTOSDemo.C.o Model: SMALL, Lang: ANSI-C +tasks.c.o Model: SMALL, Lang: ANSI-C +queue.c.o Model: SMALL, Lang: ANSI-C +list.c.o Model: SMALL, Lang: ANSI-C +port.c.o Model: SMALL, Lang: ANSI-C +flash.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +heap_1.c.o Model: SMALL, Lang: ANSI-C +TickTimer.C.o Model: SMALL, Lang: ANSI-C +PE_Timer.C.o Model: SMALL, Lang: ANSI-C +ParTest.c.o Model: SMALL, Lang: ANSI-C +PollQ.c.o Model: SMALL, Lang: ANSI-C +dynamic.c.o Model: SMALL, Lang: ANSI-C +ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC076 and uses 23 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0xC1FD (main) + long stackOffset 0xFED + unsigned nofZeroOut 1 + _Range pZeroOut 0x800 1982 + _Copy *toCopyDownBeg 0xD3CF + int nofLibInits 0 + _LibInit *libInits 0xC091 + int nofInitBodies 0 + _Cpp *initBodies 0xC093 + int nofFiniBodies 0 + _Cpp *finiBodies 0xC093 +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x800 0x800 RAM +.init 118 R 0xC000 0xC075 ROM_C000 +.startData 29 R 0xC076 0xC092 ROM_C000 +.rodata1 78 R 0xC093 0xC0E0 ROM_C000 +NON_BANKED 114 R 0xC0E1 0xC152 ROM_C000 +.text 4164 R 0xC153 0xD196 ROM_C000 +.copy 19 R 0xD3CF 0xD3E1 ROM_C000 +.abs_section_3f 1 N/I 0x3F 0x3F .absSeg0 +.abs_section_8d 1 N/I 0x8D 0x8D .absSeg1 +.abs_section_86 1 N/I 0x86 0x86 .absSeg2 +.abs_section_8b 1 N/I 0x8B 0x8B .absSeg3 +.abs_section_ff06 1 N/I 0xFF06 0xFF06 .absSeg4 +.abs_section_ff07 1 N/I 0xFF07 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+Byte1_CODE 28 R 0xD30C 0xD327 ROM_C000 +TickTimer_CODE 157 R 0xD328 0xD3C4 ROM_C000 +ButtonInterrupt_CODE 10 R 0xD3C5 0xD3CE ROM_C000 +Byte1_DATA 8 R/W 0xFB3 0xFBA RAM +TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM +.stack 48 R/W 0xFBE 0xFED RAM + +Summary of section sizes per section type: +READ_ONLY (R): 1462 (dec: 5218) +READ_WRITE (R/W): 7EE (dec: 2030) +NO_INIT (N/I): 100 (dec: 256) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text +- VARIABLES: + _startupData C076 17 23 6 .startData +MODULE: -- STRING.C.o (ansisi.lib) -- +- PROCEDURES: + memcpy C18C 26 38 3 .text + memset C1B2 1E 30 1 .text + strncpy C1D0 2D 45 1 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LCMP D197 19 25 2 RUNTIME + _LCMP_P D1B0 15 21 2 RUNTIME + _LNEG D1C5 D 13 1 RUNTIME + _LINC D1D2 5 5 4 RUNTIME + _lDivMod D1D7 E3 227 3 RUNTIME + _LDIVU D2BA E 14 1 RUNTIME + _NEG_P D2C8 F 15 4 RUNTIME + _LDIVS D2D7 35 53 1 RUNTIME +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + Cpu_Interrupt C0E1 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk D30C D 13 1 Byte1_CODE + Byte1_NegBit D319 F 15 1 Byte1_CODE +- VARIABLES: + Byte1_Table FB3 8 8 1 Byte1_DATA +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATDDIEN 8D 1 1 0 .abs_section_8d + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRAD 272 1 1 0 .abs_section_272 + _DDRE 9 1 1 0 .abs_section_9 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 1 .abs_section_25a + _DDRS 24A 1 1 0 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _EBICTL E 1 1 0 .abs_section_e + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _INITEE 12 1 1 0 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 247 1 1 0 .abs_section_247 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PEAR A 1 1 0 .abs_section_a + _PERAD 274 1 1 0 .abs_section_274 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 1 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 2 .abs_section_25e + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 2 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSAD 275 1 1 0 .abs_section_275 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 1 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 0 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMSDN FE 1 1 1 .abs_section_fe + _RDRAD 273 1 1 0 .abs_section_273 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SPIBR DA 1 1 0 .abs_section_da + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIDR DD 1 1 0 .abs_section_dd + _SPISR DB 1 1 0 .abs_section_db + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _DDRAB 2 2 2 1 .abs_section_2 + _PACNT 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 3 .abs_section_0 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _SCIBD C8 2 2 0 .abs_section_c8 + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main C1FD 8 8 0 .text +- VARIABLES: +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate C205 CE 206 11 .text + vTaskDelayUntil C2D3 74 116 3 .text + vTaskDelay C347 46 70 4 .text + uxTaskPriorityGet C38D 26 38 1 .text + vTaskPrioritySet C3B3 69 105 2 .text + vTaskSuspend C41C 44 68 3 .text + vTaskResume C460 59 89 3 .text + vTaskStartScheduler C4B9 30 48 1 .text + vTaskSuspendAll C4E9 13 19 11 .text + xTaskResumeAll C4FC 9F 159 13 .text + xTaskGetTickCount C59B 17 23 2 .text + vTaskIncrementTick C5B2 81 129 2 .text + vTaskSwitchContext C633 5B 91 3 .text + vTaskPlaceOnEventList C68E 41 65 2 .text + xTaskRemoveFromEventList C6CF 6C 108 3 .text + prvIdleTask C73B 10 16 1 .text + prvInitialiseTCBVariables C74B 4C 76 1 .text + prvInitialiseTaskLists C797 3C 60 1 .text + prvCheckTasksWaitingTermination C7D3 1 1 1 .text + prvAllocateTCBAndStack C7D4 33 51 1 .text +- VARIABLES: + STRING.IDLE.2 C093 5 5 1 .rodata1 + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate C807 77 119 3 .text + xQueueSend C87E CA 202 3 .text + xQueueSendFromISR C948 54 84 1 .text + xQueueReceive C99C C4 196 4 .text + uxQueueMessagesWaiting CA60 1B 27 1 .text + prvUnlockQueue CA7B 6F 111 4 .text + prvIsQueueEmpty CAEA 21 33 1 .text + prvIsQueueFull CB0B 24 36 1 .text +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise CB2F 1F 31 7 .text + vListInitialiseItem CB4E 7 7 3 .text + vListInsertEnd CB55 27 39 7 .text + vListInsert CB7C 5A 90 4 .text + vListRemove CBD6 23 35 13 .text +- VARIABLES: +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack CBF9 2B 43 1 .text + prvSetupTimerInterrupt CC24 9 9 1 .text + xPortStartScheduler CC2D 4 4 1 .text + xBankedStartScheduler C0E2 F 15 1 NON_BANKED + vPortYield C0F1 16 22 1 NON_BANKED + vPortTickInterrupt C107 1D 29 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 800 1 1 91 .data +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks CC31 26 38 1 .text + vLEDFlashTask CC57 52 82 1 .text +- VARIABLES: + STRING.LEDx.1 C098 5 5 1 .rodata1 + uxFlashTaskNumber 888 1 1 2 .bss +MODULE: -- main.c.o -- +- PROCEDURES: + vMain CCA9 42 66 1 .text + vErrorChecks CCEB 2F 47 1 .text + prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text + vApplicationIdleHook CD3D 73 115 1 .text + vButtonTask CDB0 4F 79 1 .text + vButtonPush C124 2F 47 1 NON_BANKED +- VARIABLES: + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss +MODULE: -- heap_1.c.o -- +- PROCEDURES: + pvPortMalloc CDFF 30 48 4 .text + vPortFree CE2F 1 1 2 .text +- VARIABLES: + xNextFreeByte 88D 2 2 5 .bss + xHeap 88F 704 1796 1 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV D328 F 15 2 TickTimer_CODE + SetPV D337 C 12 1 TickTimer_CODE + HWEnDi D343 11 17 2 TickTimer_CODE + TickTimer_Enable D354 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE + TickTimer_Init D3B1 14 20 1 TickTimer_CODE +- VARIABLES: + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 CE30 43 67 1 .text +- VARIABLES: +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestToggleLED CE73 13 19 4 .text +- VARIABLES: +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks CE86 40 64 1 .text + vPolledQueueProducer CEC6 4D 77 1 .text + vPolledQueueConsumer CF13 59 89 1 .text + xArePollingQueuesStillRunning CF6C 1D 29 1 .text +- VARIABLES: + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks CF89 7C 124 1 .text + vLimitedIncrementTask D005 21 33 1 .text + vContinuousIncrementTask D026 30 48 1 .text + vCounterControlTask D056 98 152 3 .text + vQueueSendWhenSuspendedTask D0EE 34 52 1 .text + vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text + xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text +- VARIABLES: + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + usCheckVariable F97 2 2 4 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common +MODULE: -- ButtonInterrupt.C.o -- +- PROCEDURES: + ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE +- VARIABLES: + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 57 0 + STRING.C.o (ansisi.lib) 0 113 0 + rtshc12.c.o (ansisi.lib) 0 373 0 + Cpu.C.o 0 119 0 + Byte1.C.o 8 28 0 + IO_Map.C.o 256 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 8 0 + tasks.c.o 135 1538 5 + queue.c.o 0 808 0 + list.c.o 0 202 0 + port.c.o 1 122 0 + flash.c.o 1 120 5 + main.c.o 4 389 13 + heap_1.c.o 1798 49 0 + TickTimer.C.o 3 157 0 + PE_Timer.C.o 0 67 0 + ParTest.c.o 0 19 0 + PollQ.c.o 4 259 16 + dynamic.c.o 28 526 39 + ButtonInterrupt.C.o 0 10 0 + other 48 29 19 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init _Startup memcpy memset strncpy main xTaskCreate vTaskDelayUntil + vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume + vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack + xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive + uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull + vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask + pvPortMalloc vPortFree PE_Timer_LngHi1 vParTestToggleLED + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vStartDynamicPriorityTasks + vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask + vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask + xAreDynamicPriorityTasksStillRunning +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority + uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks + uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 + pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList + xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue + xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount + xPolledQueue.1 usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 + STRING.SUSP_TX.4 STRING.SUSP_RX.5 +SECTION: "NON_BANKED" + Cpu_Interrupt xBankedStartScheduler vPortYield vPortTickInterrupt + vButtonPush +SECTION: "RUNTIME" + _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS +SECTION: ".common" + xSuspendedTestQueue +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_NegBit +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "ButtonInterrupt_CODE" + ButtonInterrupt_Enable +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATDDIEN +SECTION: ".abs_section_86" + _ATDSTAT0 +SECTION: ".abs_section_8b" + _ATDSTAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CANBTR0 +SECTION: ".abs_section_143" + _CANBTR1 +SECTION: ".abs_section_140" + _CANCTL0 +SECTION: ".abs_section_141" + _CANCTL1 +SECTION: ".abs_section_14b" + _CANIDAC +SECTION: ".abs_section_150" + _CANIDAR0 +SECTION: ".abs_section_151" + _CANIDAR1 +SECTION: ".abs_section_152" + _CANIDAR2 +SECTION: ".abs_section_153" + _CANIDAR3 +SECTION: ".abs_section_158" + _CANIDAR4 +SECTION: ".abs_section_159" + _CANIDAR5 +SECTION: ".abs_section_15a" + _CANIDAR6 +SECTION: ".abs_section_15b" + _CANIDAR7 +SECTION: ".abs_section_154" + _CANIDMR0 +SECTION: ".abs_section_155" + _CANIDMR1 +SECTION: ".abs_section_156" + _CANIDMR2 +SECTION: ".abs_section_157" + _CANIDMR3 +SECTION: ".abs_section_15c" + _CANIDMR4 +SECTION: ".abs_section_15d" + _CANIDMR5 +SECTION: ".abs_section_15e" + _CANIDMR6 +SECTION: ".abs_section_15f" + _CANIDMR7 +SECTION: ".abs_section_144" + _CANRFLG +SECTION: ".abs_section_145" + _CANRIER +SECTION: ".abs_section_16c" + _CANRXDLR +SECTION: ".abs_section_164" + _CANRXDSR0 +SECTION: ".abs_section_165" + _CANRXDSR1 +SECTION: ".abs_section_166" + _CANRXDSR2 +SECTION: ".abs_section_167" + _CANRXDSR3 +SECTION: ".abs_section_168" + _CANRXDSR4 +SECTION: ".abs_section_169" + _CANRXDSR5 +SECTION: ".abs_section_16a" + _CANRXDSR6 +SECTION: ".abs_section_16b" + _CANRXDSR7 +SECTION: ".abs_section_14e" + _CANRXERR +SECTION: ".abs_section_160" + _CANRXIDR0 +SECTION: ".abs_section_161" + _CANRXIDR1 +SECTION: ".abs_section_162" + _CANRXIDR2 +SECTION: ".abs_section_163" + _CANRXIDR3 +SECTION: ".abs_section_149" + _CANTAAK +SECTION: ".abs_section_148" + _CANTARQ +SECTION: ".abs_section_14a" + _CANTBSEL +SECTION: ".abs_section_146" + _CANTFLG +SECTION: ".abs_section_147" + _CANTIER +SECTION: ".abs_section_17c" + _CANTXDLR +SECTION: ".abs_section_174" + _CANTXDSR0 +SECTION: ".abs_section_175" + _CANTXDSR1 +SECTION: ".abs_section_176" + _CANTXDSR2 +SECTION: ".abs_section_177" + _CANTXDSR3 +SECTION: ".abs_section_178" + _CANTXDSR4 +SECTION: ".abs_section_179" + _CANTXDSR5 +SECTION: ".abs_section_17a" + _CANTXDSR6 +SECTION: ".abs_section_17b" + _CANTXDSR7 +SECTION: ".abs_section_14f" + _CANTXERR +SECTION: ".abs_section_170" + _CANTXIDR0 +SECTION: ".abs_section_171" + _CANTXIDR1 +SECTION: ".abs_section_172" + _CANTXIDR2 +SECTION: ".abs_section_173" + _CANTXIDR3 +SECTION: ".abs_section_17f" + _CANTXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_272" + _DDRAD +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_247" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_274" + _PERAD +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_275" + _PPSAD +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_270" + _PTAD +SECTION: ".abs_section_271" + _PTIAD +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_e4" + _PWMCAE +SECTION: ".abs_section_e2" + _PWMCLK +SECTION: ".abs_section_e5" + _PWMCTL +SECTION: ".abs_section_e0" + _PWME +SECTION: ".abs_section_e1" + _PWMPOL +SECTION: ".abs_section_e3" + _PWMPRCLK +SECTION: ".abs_section_e8" + _PWMSCLA +SECTION: ".abs_section_e9" + _PWMSCLB +SECTION: ".abs_section_fe" + _PWMSDN +SECTION: ".abs_section_273" + _RDRAD +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCICR1 +SECTION: ".abs_section_cb" + _SCICR2 +SECTION: ".abs_section_ce" + _SCIDRH +SECTION: ".abs_section_cf" + _SCIDRL +SECTION: ".abs_section_cc" + _SCISR1 +SECTION: ".abs_section_cd" + _SCISR2 +SECTION: ".abs_section_da" + _SPIBR +SECTION: ".abs_section_d8" + _SPICR1 +SECTION: ".abs_section_d9" + _SPICR2 +SECTION: ".abs_section_dd" + _SPIDR +SECTION: ".abs_section_db" + _SPISR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATDCTL23 +SECTION: ".abs_section_84" + _ATDCTL45 +SECTION: ".abs_section_90" + _ATDDR0 +SECTION: ".abs_section_92" + _ATDDR1 +SECTION: ".abs_section_94" + _ATDDR2 +SECTION: ".abs_section_96" + _ATDDR3 +SECTION: ".abs_section_98" + _ATDDR4 +SECTION: ".abs_section_9a" + _ATDDR5 +SECTION: ".abs_section_9c" + _ATDDR6 +SECTION: ".abs_section_9e" + _ATDDR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_62" + _PACNT +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ec" + _PWMCNT01 +SECTION: ".abs_section_ee" + _PWMCNT23 +SECTION: ".abs_section_f0" + _PWMCNT45 +SECTION: ".abs_section_f8" + _PWMDTY01 +SECTION: ".abs_section_fa" + _PWMDTY23 +SECTION: ".abs_section_fc" + _PWMDTY45 +SECTION: ".abs_section_f2" + _PWMPER01 +SECTION: ".abs_section_f4" + _PWMPER23 +SECTION: ".abs_section_f6" + _PWMPER45 +SECTION: ".abs_section_c8" + _SCIBD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + EnUser CmpHighVal + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACNT 62 2 2 0 .abs_section_62 + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _ATDDIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _SCIBD C8 2 2 0 .abs_section_c8 + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIBR DA 1 1 0 .abs_section_da + _SPISR DB 1 1 0 .abs_section_db + _SPIDR DD 1 1 0 .abs_section_dd + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMSDN FE 1 1 1 .abs_section_fe + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _MODRR 247 1 1 0 .abs_section_247 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 1 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 1 .abs_section_25c + _PPSP 25D 1 1 1 .abs_section_25d + _PIEP 25E 1 1 2 .abs_section_25e + _PIFP 25F 1 1 2 .abs_section_25f + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _DDRAD 272 1 1 0 .abs_section_272 + _RDRAD 273 1 1 0 .abs_section_273 + _PERAD 274 1 1 0 .abs_section_274 + _PPSAD 275 1 1 0 .abs_section_275 + uxCriticalNesting 800 1 1 91 .data + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss + uxFlashTaskNumber 888 1 1 2 .bss + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss + xNextFreeByte 88D 2 2 5 .bss + xHeap 88F 704 1796 1 .bss + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss + usCheckVariable F97 2 2 4 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common + Byte1_Table FB3 8 8 1 Byte1_DATA + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + STRING.IDLE.2 C093 5 5 1 .rodata1 + STRING.LEDx.1 C098 5 5 1 .rodata1 + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + Cpu_Interrupt C0E1 1 1 60 NON_BANKED + xBankedStartScheduler C0E2 F 15 1 NON_BANKED + vPortYield C0F1 16 22 1 NON_BANKED + vPortTickInterrupt C107 1D 29 1 NON_BANKED + vButtonPush C124 2F 47 1 NON_BANKED + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text + memcpy C18C 26 38 3 .text + memset C1B2 1E 30 1 .text + strncpy C1D0 2D 45 1 .text + main C1FD 8 8 0 .text + xTaskCreate C205 CE 206 11 .text + vTaskDelayUntil C2D3 74 116 3 .text + vTaskDelay C347 46 70 4 .text + uxTaskPriorityGet C38D 26 38 1 .text + vTaskPrioritySet C3B3 69 105 2 .text + vTaskSuspend C41C 44 68 3 .text + vTaskResume C460 59 89 3 .text + vTaskStartScheduler C4B9 30 48 1 .text + vTaskSuspendAll C4E9 13 19 11 .text + xTaskResumeAll C4FC 9F 159 13 .text + xTaskGetTickCount C59B 17 23 2 .text + vTaskIncrementTick C5B2 81 129 2 .text + vTaskSwitchContext C633 5B 91 3 .text + vTaskPlaceOnEventList C68E 41 65 2 .text + xTaskRemoveFromEventList C6CF 6C 108 3 .text + prvIdleTask C73B 10 16 1 .text + prvInitialiseTCBVariables C74B 4C 76 1 .text + prvInitialiseTaskLists C797 3C 60 1 .text + prvCheckTasksWaitingTermination C7D3 1 1 1 .text + prvAllocateTCBAndStack C7D4 33 51 1 .text + xQueueCreate C807 77 119 3 .text + xQueueSend C87E CA 202 3 .text + xQueueSendFromISR C948 54 84 1 .text + xQueueReceive C99C C4 196 4 .text + uxQueueMessagesWaiting CA60 1B 27 1 .text + prvUnlockQueue CA7B 6F 111 4 .text + prvIsQueueEmpty CAEA 21 33 1 .text + prvIsQueueFull CB0B 24 36 1 .text + vListInitialise CB2F 1F 31 7 .text + vListInitialiseItem CB4E 7 7 3 .text + vListInsertEnd CB55 27 39 7 .text + vListInsert CB7C 5A 90 4 .text + vListRemove CBD6 23 35 13 .text + pxPortInitialiseStack CBF9 2B 43 1 .text + prvSetupTimerInterrupt CC24 9 9 1 .text + xPortStartScheduler CC2D 4 4 1 .text + vStartLEDFlashTasks CC31 26 38 1 .text + vLEDFlashTask CC57 52 82 1 .text + vMain CCA9 42 66 1 .text + vErrorChecks CCEB 2F 47 1 .text + prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text + vApplicationIdleHook CD3D 73 115 1 .text + vButtonTask CDB0 4F 79 1 .text + pvPortMalloc CDFF 30 48 4 .text + vPortFree CE2F 1 1 2 .text + PE_Timer_LngHi1 CE30 43 67 1 .text + vParTestToggleLED CE73 13 19 4 .text + vStartPolledQueueTasks CE86 40 64 1 .text + vPolledQueueProducer CEC6 4D 77 1 .text + vPolledQueueConsumer CF13 59 89 1 .text + xArePollingQueuesStillRunning CF6C 1D 29 1 .text + vStartDynamicPriorityTasks CF89 7C 124 1 .text + vLimitedIncrementTask D005 21 33 1 .text + vContinuousIncrementTask D026 30 48 1 .text + vCounterControlTask D056 98 152 3 .text + vQueueSendWhenSuspendedTask D0EE 34 52 1 .text + vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text + xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text + _LCMP D197 19 25 2 RUNTIME + _LCMP_P D1B0 15 21 2 RUNTIME + _LNEG D1C5 D 13 1 RUNTIME + _LINC D1D2 5 5 4 RUNTIME + _lDivMod D1D7 E3 227 3 RUNTIME + _LDIVU D2BA E 14 1 RUNTIME + _NEG_P D2C8 F 15 4 RUNTIME + _LDIVS D2D7 35 53 1 RUNTIME + Byte1_GetMsk D30C D 13 1 Byte1_CODE + Byte1_NegBit D319 F 15 1 Byte1_CODE + SetCV D328 F 15 2 TickTimer_CODE + SetPV D337 C 12 1 TickTimer_CODE + HWEnDi D343 11 17 2 TickTimer_CODE + TickTimer_Enable D354 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE + TickTimer_Init D3B1 14 20 1 TickTimer_CODE + ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansisi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU + _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +Byte1.C.o: + Byte1_PutBit +tasks.c.o: + vTaskEndScheduler uxTaskGetNumberOfTasks +queue.c.o: + xQueueReceiveFromISR vQueueDelete +port.c.o: + vPortEndScheduler +heap_1.c.o: + vPortInitialiseBlocks +TickTimer.C.o: + TickTimer_Interrupt +ParTest.c.o: + vParTestSetLED +ButtonInterrupt.C.o: + ButtonInterrupt_Interrupt +NOT USED VARIABLES +STRING.C.o (ansisi.lib): + STRING..1 next.2 +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xD3CF ---- SIZE 4 --- +Filling bytes inserted + 00010800 +------- ROM-ADDRESS: 0xD3D3 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xD3D4 ---- SIZE 4 --- +Filling bytes inserted + 00080FB3 +------- ROM-ADDRESS: 0xD3D8 ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xD3E0 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV + _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB + TickTimer_Init _PIEP _INTCR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +vButtonPush USES uxValToSend.3 _PIFP xButtonQueue + xQueueSendFromISR uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +Init USES _startupData +_Startup USES _startupData Init +main USES PE_low_level_init vMain +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise + xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate + vButtonTask STRING.Button.2 vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vButtonTask USES xQueueCreate xButtonQueue + ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError + vParTestToggleLED +pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap + xTaskResumeAll +PE_Timer_LngHi1 USES _LCMP +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +Byte1_GetMsk USES Byte1_Table +Byte1_NegBit USES Byte1_GetMsk _PORTAB +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES EnUser _TFLG1 _TIE +TickTimer_Enable USES EnUser HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi +ButtonInterrupt_Enable USES _PIFP _PIEP +_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt + vPortYield _EntryPoint + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- SetCV + | | | + | | +- SetPV + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vButtonTask + | | | + | | +- xQueueCreate (see above) + | | | + | | +- ButtonInterrupt_Enable + | | | + | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG + | | | + | | +- _LDIVS + | | | | + | | | +- _NEG_P + | | | | + | | | +- _lDivMod + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vButtonPush + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- vTaskSwitchContext + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext (see above) + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 9 +Total size of all blocks to be downloaded: 5218 + diff --git a/Demo/HCS12_CodeWarrior_small/bin/SofTec.map b/Demo/HCS12_CodeWarrior_small/bin/SofTec.map new file mode 100644 index 000000000..d221a8792 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/bin/SofTec.map @@ -0,0 +1,2175 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\SofTec.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: SMALL +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: SMALL, Lang: ANSI-C +STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +tasks.c.o Model: SMALL, Lang: ANSI-C +queue.c.o Model: SMALL, Lang: ANSI-C +list.c.o Model: SMALL, Lang: ANSI-C +port.c.o Model: SMALL, Lang: ANSI-C +flash.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +heap_1.c.o Model: SMALL, Lang: ANSI-C +ParTest.c.o Model: SMALL, Lang: ANSI-C +Cpu.C.o Model: SMALL, Lang: ANSI-C +Byte1.C.o Model: SMALL, Lang: ANSI-C +TickTimer.C.o Model: SMALL, Lang: ANSI-C +IO_Map.C.o Model: SMALL, Lang: ANSI-C +PE_Timer.C.o Model: SMALL, Lang: ANSI-C +Vectors.c.o Model: SMALL, Lang: ANSI-C +RTOSDemo.C.o Model: SMALL, Lang: ANSI-C +PollQ.c.o Model: SMALL, Lang: ANSI-C +dynamic.c.o Model: SMALL, Lang: ANSI-C +ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC076 and uses 23 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0xCE77 (main) + long stackOffset 0xFED + unsigned nofZeroOut 1 + _Range pZeroOut 0x800 1982 + _Copy *toCopyDownBeg 0xD3C4 + int nofLibInits 0 + _LibInit *libInits 0xC091 + int nofInitBodies 0 + _Cpp *initBodies 0xC093 + int nofFiniBodies 0 + _Cpp *finiBodies 0xC093 +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x800 0x800 RAM +.init 118 R 0xC000 0xC075 ROM_C000 +.startData 29 R 0xC076 0xC092 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.absSeg218 +.abs_section_58 2 N/I 0x58 0x59 .absSeg219 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg220 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg221 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg222 +.abs_section_44 2 N/I 0x44 0x45 .absSeg223 +.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg224 +.bss 1968 R/W 0x801 0xFB0 RAM +RUNTIME 373 R 0xD199 0xD30D ROM_C000 +.common 2 R/W 0xFB1 0xFB2 RAM +TickTimer_CODE 149 R 0xD30E 0xD3A2 ROM_C000 +ButtonInterrupt_CODE 10 R 0xD3A3 0xD3AC ROM_C000 +Byte1_CODE 23 R 0xD3AD 0xD3C3 ROM_C000 +Byte1_DATA 8 R/W 0xFB3 0xFBA RAM +TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM +.stack 48 R/W 0xFBE 0xFED RAM + +Summary of section sizes per section type: +READ_ONLY (R): 1457 (dec: 5207) +READ_WRITE (R/W): 7EE (dec: 2030) +NO_INIT (N/I): 100 (dec: 256) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text +- VARIABLES: + _startupData C076 17 23 6 .startData +MODULE: -- STRING.C.o (ansisi.lib) -- +- PROCEDURES: + _memcpy_8bitCount C18C 1C 28 3 .text + memset C1A8 1E 30 1 .text + strncpy C1C6 2D 45 1 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LCMP D199 19 25 2 RUNTIME + _LCMP_P D1B2 15 21 2 RUNTIME + _LNEG D1C7 D 13 1 RUNTIME + _LINC D1D4 5 5 4 RUNTIME + _lDivMod D1D9 E3 227 3 RUNTIME + _LDIVU D2BC E 14 1 RUNTIME + _NEG_P D2CA F 15 4 RUNTIME + _LDIVS D2D9 35 53 1 RUNTIME +- VARIABLES: +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate C1F3 CE 206 11 .text + vTaskDelayUntil C2C1 74 116 3 .text + vTaskDelay C335 46 70 4 .text + uxTaskPriorityGet C37B 26 38 1 .text + vTaskPrioritySet C3A1 69 105 2 .text + vTaskSuspend C40A 44 68 3 .text + vTaskResume C44E 59 89 3 .text + vTaskStartScheduler C4A7 30 48 1 .text + vTaskSuspendAll C4D7 13 19 11 .text + xTaskResumeAll C4EA 9F 159 13 .text + xTaskGetTickCount C589 17 23 2 .text + vTaskIncrementTick C5A0 81 129 2 .text + vTaskSwitchContext C621 5B 91 3 .text + vTaskPlaceOnEventList C67C 3E 62 2 .text + xTaskRemoveFromEventList C6BA 65 101 3 .text + prvIdleTask C71F 10 16 1 .text + prvInitialiseTCBVariables C72F 4A 74 1 .text + prvInitialiseTaskLists C779 37 55 1 .text + prvCheckTasksWaitingTermination C7B0 1 1 1 .text + prvAllocateTCBAndStack C7B1 39 57 1 .text +- VARIABLES: + STRING.IDLE.2 C093 5 5 1 .rodata1 + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate C7EA 76 118 3 .text + xQueueSend C860 C9 201 3 .text + xQueueSendFromISR C929 58 88 1 .text + xQueueReceive C981 C3 195 4 .text + uxQueueMessagesWaiting CA44 1B 27 1 .text + prvUnlockQueue CA5F 6F 111 4 .text + prvIsQueueEmpty CACE 21 33 1 .text + prvIsQueueFull CAEF 24 36 1 .text +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise CB13 1F 31 7 .text + vListInitialiseItem CB32 7 7 3 .text + vListInsertEnd CB39 25 37 7 .text + vListInsert CB5E 54 84 4 .text + vListRemove CBB2 23 35 13 .text +- VARIABLES: +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack CBD5 2B 43 1 .text + prvSetupTimerInterrupt CC00 9 9 1 .text + xPortStartScheduler CC09 4 4 1 .text + xBankedStartScheduler C0E1 F 15 1 NON_BANKED + vPortYield C0F0 16 22 1 NON_BANKED + vPortTickInterrupt C106 1D 29 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 800 1 1 91 .data +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks CC0D 2E 46 1 .text + vLEDFlashTask CC3B 52 82 1 .text +- VARIABLES: + STRING.LEDx.1 C098 5 5 1 .rodata1 + uxFlashTaskNumber 888 1 1 2 .bss +MODULE: -- main.c.o -- +- PROCEDURES: + vMain CC8D 42 66 1 .text + vErrorChecks CCCF 35 53 1 .text + prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text + vApplicationIdleHook CD2A 73 115 1 .text + vButtonTask CD9D 4F 79 1 .text + vButtonPush C123 2F 47 1 NON_BANKED +- VARIABLES: + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss +MODULE: -- heap_1.c.o -- +- PROCEDURES: + pvPortMalloc CDEC 2D 45 4 .text + vPortFree CE19 1 1 2 .text +- VARIABLES: + xNextFreeByte 88D 2 2 4 .bss + xHeap 88F 704 1796 1 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestToggleLED CE1A 13 19 4 .text +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + Cpu_Interrupt C152 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk D3AD D 13 1 Byte1_CODE + Byte1_NegBit D3BA A 10 1 Byte1_CODE +- VARIABLES: + Byte1_Table FB3 8 8 1 Byte1_DATA +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV D30E B 11 2 TickTimer_CODE + SetPV D319 9 9 1 TickTimer_CODE + HWEnDi D322 11 17 2 TickTimer_CODE + TickTimer_Enable D333 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE + TickTimer_Init D38F 14 20 1 TickTimer_CODE +- VARIABLES: + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATDDIEN 8D 1 1 0 .abs_section_8d + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRAD 272 1 1 0 .abs_section_272 + _DDRE 9 1 1 0 .abs_section_9 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 1 .abs_section_25a + _DDRS 24A 1 1 0 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _EBICTL E 1 1 0 .abs_section_e + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _INITEE 12 1 1 0 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 247 1 1 0 .abs_section_247 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PEAR A 1 1 0 .abs_section_a + _PERAD 274 1 1 0 .abs_section_274 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 1 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 2 .abs_section_25e + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 2 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSAD 275 1 1 0 .abs_section_275 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 1 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 0 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMSDN FE 1 1 1 .abs_section_fe + _RDRAD 273 1 1 0 .abs_section_273 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SPIBR DA 1 1 0 .abs_section_da + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIDR DD 1 1 0 .abs_section_dd + _SPISR DB 1 1 0 .abs_section_db + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _DDRAB 2 2 2 1 .abs_section_2 + _PACNT 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 3 .abs_section_0 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _SCIBD C8 2 2 0 .abs_section_c8 + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 CE2D 4A 74 1 .text +- VARIABLES: +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main CE77 8 8 0 .text +- VARIABLES: +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks CE7F 42 66 1 .text + vPolledQueueProducer CEC1 4D 77 1 .text + vPolledQueueConsumer CF0E 59 89 1 .text + xArePollingQueuesStillRunning CF67 15 21 1 .text +- VARIABLES: + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks CF7C 7C 124 1 .text + vLimitedIncrementTask CFF8 26 38 1 .text + vContinuousIncrementTask D01E 35 53 1 .text + vCounterControlTask D053 98 152 3 .text + vQueueSendWhenSuspendedTask D0EB 34 52 1 .text + vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text + xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text +- VARIABLES: + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + usCheckVariable F97 2 2 3 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common +MODULE: -- ButtonInterrupt.C.o -- +- PROCEDURES: + ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE +- VARIABLES: + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 57 0 + STRING.C.o (ansisi.lib) 0 103 0 + rtshc12.c.o (ansisi.lib) 0 373 0 + tasks.c.o 135 1527 5 + queue.c.o 0 809 0 + list.c.o 0 194 0 + port.c.o 1 122 0 + flash.c.o 1 128 5 + main.c.o 4 398 13 + heap_1.c.o 1798 46 0 + ParTest.c.o 0 19 0 + Cpu.C.o 0 119 0 + Byte1.C.o 8 23 0 + TickTimer.C.o 3 149 0 + IO_Map.C.o 256 0 0 + PE_Timer.C.o 0 74 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 8 0 + PollQ.c.o 4 253 16 + dynamic.c.o 28 541 39 + ButtonInterrupt.C.o 0 10 0 + other 48 29 19 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init _Startup _memcpy_8bitCount memset strncpy xTaskCreate vTaskDelayUntil + vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume + vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack + xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive + uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull + vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask + pvPortMalloc vPortFree vParTestToggleLED PE_Timer_LngHi1 main + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vStartDynamicPriorityTasks + vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask + vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask + xAreDynamicPriorityTasksStillRunning +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority + uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks + uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 + pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList + xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue + xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount + xPolledQueue.1 usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 + STRING.SUSP_TX.4 STRING.SUSP_RX.5 +SECTION: "NON_BANKED" + xBankedStartScheduler vPortYield vPortTickInterrupt vButtonPush + Cpu_Interrupt +SECTION: "RUNTIME" + _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS +SECTION: ".common" + xSuspendedTestQueue +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "ButtonInterrupt_CODE" + ButtonInterrupt_Enable +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_NegBit +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "TickTimer_DATA" + EnUser CmpHighVal +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATDDIEN +SECTION: ".abs_section_86" + _ATDSTAT0 +SECTION: ".abs_section_8b" + _ATDSTAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CANBTR0 +SECTION: ".abs_section_143" + _CANBTR1 +SECTION: ".abs_section_140" + _CANCTL0 +SECTION: ".abs_section_141" + _CANCTL1 +SECTION: ".abs_section_14b" + _CANIDAC +SECTION: ".abs_section_150" + _CANIDAR0 +SECTION: ".abs_section_151" + _CANIDAR1 +SECTION: ".abs_section_152" + _CANIDAR2 +SECTION: ".abs_section_153" + _CANIDAR3 +SECTION: ".abs_section_158" + _CANIDAR4 +SECTION: ".abs_section_159" + _CANIDAR5 +SECTION: ".abs_section_15a" + _CANIDAR6 +SECTION: ".abs_section_15b" + _CANIDAR7 +SECTION: ".abs_section_154" + _CANIDMR0 +SECTION: ".abs_section_155" + _CANIDMR1 +SECTION: ".abs_section_156" + _CANIDMR2 +SECTION: ".abs_section_157" + _CANIDMR3 +SECTION: ".abs_section_15c" + _CANIDMR4 +SECTION: ".abs_section_15d" + _CANIDMR5 +SECTION: ".abs_section_15e" + _CANIDMR6 +SECTION: ".abs_section_15f" + _CANIDMR7 +SECTION: ".abs_section_144" + _CANRFLG +SECTION: ".abs_section_145" + _CANRIER +SECTION: ".abs_section_16c" + _CANRXDLR +SECTION: ".abs_section_164" + _CANRXDSR0 +SECTION: ".abs_section_165" + _CANRXDSR1 +SECTION: ".abs_section_166" + _CANRXDSR2 +SECTION: ".abs_section_167" + _CANRXDSR3 +SECTION: ".abs_section_168" + _CANRXDSR4 +SECTION: ".abs_section_169" + _CANRXDSR5 +SECTION: ".abs_section_16a" + _CANRXDSR6 +SECTION: ".abs_section_16b" + _CANRXDSR7 +SECTION: ".abs_section_14e" + _CANRXERR +SECTION: ".abs_section_160" + _CANRXIDR0 +SECTION: ".abs_section_161" + _CANRXIDR1 +SECTION: ".abs_section_162" + _CANRXIDR2 +SECTION: ".abs_section_163" + _CANRXIDR3 +SECTION: ".abs_section_149" + _CANTAAK +SECTION: ".abs_section_148" + _CANTARQ +SECTION: ".abs_section_14a" + _CANTBSEL +SECTION: ".abs_section_146" + _CANTFLG +SECTION: ".abs_section_147" + _CANTIER +SECTION: ".abs_section_17c" + _CANTXDLR +SECTION: ".abs_section_174" + _CANTXDSR0 +SECTION: ".abs_section_175" + _CANTXDSR1 +SECTION: ".abs_section_176" + _CANTXDSR2 +SECTION: ".abs_section_177" + _CANTXDSR3 +SECTION: ".abs_section_178" + _CANTXDSR4 +SECTION: ".abs_section_179" + _CANTXDSR5 +SECTION: ".abs_section_17a" + _CANTXDSR6 +SECTION: ".abs_section_17b" + _CANTXDSR7 +SECTION: ".abs_section_14f" + _CANTXERR +SECTION: ".abs_section_170" + _CANTXIDR0 +SECTION: ".abs_section_171" + _CANTXIDR1 +SECTION: ".abs_section_172" + _CANTXIDR2 +SECTION: ".abs_section_173" + _CANTXIDR3 +SECTION: ".abs_section_17f" + _CANTXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_272" + _DDRAD +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_247" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_274" + _PERAD +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_275" + _PPSAD +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_270" + _PTAD +SECTION: ".abs_section_271" + _PTIAD +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_e4" + _PWMCAE +SECTION: ".abs_section_e2" + _PWMCLK +SECTION: ".abs_section_e5" + _PWMCTL +SECTION: ".abs_section_e0" + _PWME +SECTION: ".abs_section_e1" + _PWMPOL +SECTION: ".abs_section_e3" + _PWMPRCLK +SECTION: ".abs_section_e8" + _PWMSCLA +SECTION: ".abs_section_e9" + _PWMSCLB +SECTION: ".abs_section_fe" + _PWMSDN +SECTION: ".abs_section_273" + _RDRAD +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCICR1 +SECTION: ".abs_section_cb" + _SCICR2 +SECTION: ".abs_section_ce" + _SCIDRH +SECTION: ".abs_section_cf" + _SCIDRL +SECTION: ".abs_section_cc" + _SCISR1 +SECTION: ".abs_section_cd" + _SCISR2 +SECTION: ".abs_section_da" + _SPIBR +SECTION: ".abs_section_d8" + _SPICR1 +SECTION: ".abs_section_d9" + _SPICR2 +SECTION: ".abs_section_dd" + _SPIDR +SECTION: ".abs_section_db" + _SPISR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATDCTL23 +SECTION: ".abs_section_84" + _ATDCTL45 +SECTION: ".abs_section_90" + _ATDDR0 +SECTION: ".abs_section_92" + _ATDDR1 +SECTION: ".abs_section_94" + _ATDDR2 +SECTION: ".abs_section_96" + _ATDDR3 +SECTION: ".abs_section_98" + _ATDDR4 +SECTION: ".abs_section_9a" + _ATDDR5 +SECTION: ".abs_section_9c" + _ATDDR6 +SECTION: ".abs_section_9e" + _ATDDR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_62" + _PACNT +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ec" + _PWMCNT01 +SECTION: ".abs_section_ee" + _PWMCNT23 +SECTION: ".abs_section_f0" + _PWMCNT45 +SECTION: ".abs_section_f8" + _PWMDTY01 +SECTION: ".abs_section_fa" + _PWMDTY23 +SECTION: ".abs_section_fc" + _PWMDTY45 +SECTION: ".abs_section_f2" + _PWMPER01 +SECTION: ".abs_section_f4" + _PWMPER23 +SECTION: ".abs_section_f6" + _PWMPER45 +SECTION: ".abs_section_c8" + _SCIBD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACNT 62 2 2 0 .abs_section_62 + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _ATDDIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _SCIBD C8 2 2 0 .abs_section_c8 + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIBR DA 1 1 0 .abs_section_da + _SPISR DB 1 1 0 .abs_section_db + _SPIDR DD 1 1 0 .abs_section_dd + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMSDN FE 1 1 1 .abs_section_fe + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _MODRR 247 1 1 0 .abs_section_247 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 1 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 1 .abs_section_25c + _PPSP 25D 1 1 1 .abs_section_25d + _PIEP 25E 1 1 2 .abs_section_25e + _PIFP 25F 1 1 2 .abs_section_25f + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _DDRAD 272 1 1 0 .abs_section_272 + _RDRAD 273 1 1 0 .abs_section_273 + _PERAD 274 1 1 0 .abs_section_274 + _PPSAD 275 1 1 0 .abs_section_275 + uxCriticalNesting 800 1 1 91 .data + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss + uxFlashTaskNumber 888 1 1 2 .bss + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss + xNextFreeByte 88D 2 2 4 .bss + xHeap 88F 704 1796 1 .bss + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss + usCheckVariable F97 2 2 3 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common + Byte1_Table FB3 8 8 1 Byte1_DATA + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + STRING.IDLE.2 C093 5 5 1 .rodata1 + STRING.LEDx.1 C098 5 5 1 .rodata1 + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + xBankedStartScheduler C0E1 F 15 1 NON_BANKED + vPortYield C0F0 16 22 1 NON_BANKED + vPortTickInterrupt C106 1D 29 1 NON_BANKED + vButtonPush C123 2F 47 1 NON_BANKED + Cpu_Interrupt C152 1 1 60 NON_BANKED + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text + _memcpy_8bitCount C18C 1C 28 3 .text + memset C1A8 1E 30 1 .text + strncpy C1C6 2D 45 1 .text + xTaskCreate C1F3 CE 206 11 .text + vTaskDelayUntil C2C1 74 116 3 .text + vTaskDelay C335 46 70 4 .text + uxTaskPriorityGet C37B 26 38 1 .text + vTaskPrioritySet C3A1 69 105 2 .text + vTaskSuspend C40A 44 68 3 .text + vTaskResume C44E 59 89 3 .text + vTaskStartScheduler C4A7 30 48 1 .text + vTaskSuspendAll C4D7 13 19 11 .text + xTaskResumeAll C4EA 9F 159 13 .text + xTaskGetTickCount C589 17 23 2 .text + vTaskIncrementTick C5A0 81 129 2 .text + vTaskSwitchContext C621 5B 91 3 .text + vTaskPlaceOnEventList C67C 3E 62 2 .text + xTaskRemoveFromEventList C6BA 65 101 3 .text + prvIdleTask C71F 10 16 1 .text + prvInitialiseTCBVariables C72F 4A 74 1 .text + prvInitialiseTaskLists C779 37 55 1 .text + prvCheckTasksWaitingTermination C7B0 1 1 1 .text + prvAllocateTCBAndStack C7B1 39 57 1 .text + xQueueCreate C7EA 76 118 3 .text + xQueueSend C860 C9 201 3 .text + xQueueSendFromISR C929 58 88 1 .text + xQueueReceive C981 C3 195 4 .text + uxQueueMessagesWaiting CA44 1B 27 1 .text + prvUnlockQueue CA5F 6F 111 4 .text + prvIsQueueEmpty CACE 21 33 1 .text + prvIsQueueFull CAEF 24 36 1 .text + vListInitialise CB13 1F 31 7 .text + vListInitialiseItem CB32 7 7 3 .text + vListInsertEnd CB39 25 37 7 .text + vListInsert CB5E 54 84 4 .text + vListRemove CBB2 23 35 13 .text + pxPortInitialiseStack CBD5 2B 43 1 .text + prvSetupTimerInterrupt CC00 9 9 1 .text + xPortStartScheduler CC09 4 4 1 .text + vStartLEDFlashTasks CC0D 2E 46 1 .text + vLEDFlashTask CC3B 52 82 1 .text + vMain CC8D 42 66 1 .text + vErrorChecks CCCF 35 53 1 .text + prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text + vApplicationIdleHook CD2A 73 115 1 .text + vButtonTask CD9D 4F 79 1 .text + pvPortMalloc CDEC 2D 45 4 .text + vPortFree CE19 1 1 2 .text + vParTestToggleLED CE1A 13 19 4 .text + PE_Timer_LngHi1 CE2D 4A 74 1 .text + main CE77 8 8 0 .text + vStartPolledQueueTasks CE7F 42 66 1 .text + vPolledQueueProducer CEC1 4D 77 1 .text + vPolledQueueConsumer CF0E 59 89 1 .text + xArePollingQueuesStillRunning CF67 15 21 1 .text + vStartDynamicPriorityTasks CF7C 7C 124 1 .text + vLimitedIncrementTask CFF8 26 38 1 .text + vContinuousIncrementTask D01E 35 53 1 .text + vCounterControlTask D053 98 152 3 .text + vQueueSendWhenSuspendedTask D0EB 34 52 1 .text + vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text + xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text + _LCMP D199 19 25 2 RUNTIME + _LCMP_P D1B2 15 21 2 RUNTIME + _LNEG D1C7 D 13 1 RUNTIME + _LINC D1D4 5 5 4 RUNTIME + _lDivMod D1D9 E3 227 3 RUNTIME + _LDIVU D2BC E 14 1 RUNTIME + _NEG_P D2CA F 15 4 RUNTIME + _LDIVS D2D9 35 53 1 RUNTIME + SetCV D30E B 11 2 TickTimer_CODE + SetPV D319 9 9 1 TickTimer_CODE + HWEnDi D322 11 17 2 TickTimer_CODE + TickTimer_Enable D333 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE + TickTimer_Init D38F 14 20 1 TickTimer_CODE + ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE + Byte1_GetMsk D3AD D 13 1 Byte1_CODE + Byte1_NegBit D3BA A 10 1 Byte1_CODE + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansisi.lib): + strerror memchr memcmp memcpy2 memcpy memmove _memset_clear_8bitCount strlen + strset strcat strncat strcpy strcmp strncmp strchr strrchr strspn strcspn + strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU + _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +tasks.c.o: + vTaskEndScheduler uxTaskGetNumberOfTasks +queue.c.o: + xQueueReceiveFromISR vQueueDelete +port.c.o: + vPortEndScheduler +heap_1.c.o: + vPortInitialiseBlocks +ParTest.c.o: + vParTestSetLED +Byte1.C.o: + Byte1_PutBit +TickTimer.C.o: + TickTimer_Interrupt +ButtonInterrupt.C.o: + ButtonInterrupt_Interrupt +NOT USED VARIABLES +STRING.C.o (ansisi.lib): + STRING..1 next.2 +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xD3C4 ---- SIZE 4 --- +Filling bytes inserted + 00010800 +------- ROM-ADDRESS: 0xD3C8 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xD3C9 ---- SIZE 4 --- +Filling bytes inserted + 00080FB3 +------- ROM-ADDRESS: 0xD3CD ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xD3D5 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV + _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB + TickTimer_Init _PIEP _INTCR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +vButtonPush USES uxValToSend.3 _PIFP xButtonQueue + xQueueSendFromISR uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +Init USES _startupData +_Startup USES _startupData Init +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise + xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll _memcpy_8bitCount +xQueueSendFromISR USES _memcpy_8bitCount xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll _memcpy_8bitCount +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate + vButtonTask STRING.Button.2 vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vButtonTask USES xQueueCreate xButtonQueue + ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError + vParTestToggleLED +pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap + xTaskResumeAll +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +PE_Timer_LngHi1 USES _LCMP +main USES PE_low_level_init vMain +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES EnUser _TFLG1 _TIE +TickTimer_Enable USES EnUser HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi +ButtonInterrupt_Enable USES _PIFP _PIEP +Byte1_GetMsk USES Byte1_Table +Byte1_NegBit USES Byte1_GetMsk _PORTAB +_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt + vPortYield _EntryPoint + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- SetCV + | | | + | | +- SetPV + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- _memcpy_8bitCount + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- _memcpy_8bitCount (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vButtonTask + | | | + | | +- xQueueCreate (see above) + | | | + | | +- ButtonInterrupt_Enable + | | | + | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG + | | | + | | +- _LDIVS + | | | | + | | | +- _NEG_P + | | | | + | | | +- _lDivMod + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vButtonPush + | | + | +- xQueueSendFromISR + | | | + | | +- _memcpy_8bitCount (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- vTaskSwitchContext + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext (see above) + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 11 +Total size of all blocks to be downloaded: 5207 + diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/main.c b/Demo/HCS12_CodeWarrior_small/main.c new file mode 100644 index 000000000..ba110d682 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/main.c @@ -0,0 +1,364 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * + * vMain() is effectively the demo application entry point. It is called by + * the main() function generated by the Processor Expert application. + * + * vMain() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * This file also includes the functionality normally implemented within the + * standard demo application file integer.c. Due to the limited memory + * available on the microcontroller the functionality has been included within + * the idle task hook [vApplicationIdleHook()] - instead of within the usual + * separate task. See the documentation within integer.c for the rationale + * of the integer task functionality. + * + * + * + * The demo applications included with other FreeRTOS ports make use of the + * standard ComTest tasks. These use a loopback connector to transmit and + * receive RS232 characters between two tasks. The test is important for two + * reasons: + * + * 1) It tests the mechanism of context switching from within an application + * ISR. + * + * 2) It generates some randomised timing. + * + * The demo board used to develop this port does not include an RS232 interface + * so the ComTest tasks could not easily be included. Instead these two tests + * are created using a 'Button Push' task. + * + * The 'Button Push' task blocks on a queue, waiting for data to arrive. A + * simple interrupt routine connected to the PP0 input on the demo board places + * data in the queue each time the PP0 button is pushed (this button is built + * onto the demo board). As the 'Button Push' task is created with a + * relatively high priority it will unblock and want to execute as soon as data + * arrives in the queue - resulting in a context switch within the PP0 input + * ISR. If the data retrieved from the queue is that expected the 'Button Push' + * task toggles LED 5. Therefore correct operation is indicated by the LED + * toggling each time the PP0 button is pressed. + * + * This test is not as satisfactory as the ComTest method - but the simple + * nature of the port makes is just about adequate. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "flash.h" +#include "PollQ.h" +#include "dynamic.h" +#include "partest.h" + +/* Processor expert includes. */ +#include "ButtonInterrupt.h" + +/*----------------------------------------------------------- + Definitions. +-----------------------------------------------------------*/ + +/* Priorities assigned to demo application tasks. */ +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainBUTTON_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +then the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 7 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* LED that is toggled by the button push interrupt. */ +#define mainBUTTON_PUSH_LED ( 5 ) + +/* The constants used in the idle task calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +/* The length of the queue between is button push ISR and the Button Push task +is greater than 1 to account for switch bounces generating multiple inputs. */ +#define mainBUTTON_QUEUE_SIZE 6 + +/*----------------------------------------------------------- + Local functions prototypes. +-----------------------------------------------------------*/ + +/* + * The 'Check' task function. See the explanation at the top of the file. + */ +static void vErrorChecks( void* pvParameters ); + +/* + * The 'Button Push' task. See the explanation at the top of the file. + */ +static void vButtonTask( void *pvParameters ); + +/* + * The idle task hook - in which the integer task is implemented. See the + * explanation at the top of the file. + */ +void vApplicationIdleHook( void ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + + +/*----------------------------------------------------------- + Local variables. +-----------------------------------------------------------*/ + +/* A few tasks are defined within this file. This flag is used to indicate +their status. If an error is detected in one of the locally defined tasks then +this flag is set to pdTRUE. */ +portBASE_TYPE xLocalError = pdFALSE; + +/* The queue used to send data from the button push ISR to the Button Push +task. */ +static xQueueHandle xButtonQueue; + + +/*-----------------------------------------------------------*/ + +/* + * This is called from the main() function generated by the Processor Expert. + */ +void vMain( void ) +{ + /* Start some of the standard demo tasks. */ + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + + /* Start the locally defined tasks. There is also a task implemented as + the idle hook. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainBUTTON_TASK_PRIORITY, NULL ); + + /* All the tasks have been created - start the scheduler. */ + vTaskStartScheduler(); + + /* Should not reach here! */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the demo application tasks are executing without + error. If an error is found the delay period is shortened - this + has the effect of increasing the flash rate of the 'check' task + LED. */ + if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + /* Toggle the LED each cycle round. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xAllTasksPassed = pdPASS; + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + /* Also check the status flag for the tasks defined within this function. */ + if( xLocalError != pdFALSE ) + { + xAllTasksPassed = pdFAIL; + } + + return xAllTasksPassed; +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +/* This variable is effectively set to a constant so it is made volatile to +ensure the compiler does not just get rid of it. */ +volatile portLONG lValue; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* Did we perform the calculation correctly with no corruption? */ + if( lValue != intgEXPECTED_ANSWER ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +static void vButtonTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxExpected = 1, uxReceived; + + /* Create the queue used by the producer and consumer. */ + xButtonQueue = xQueueCreate( mainBUTTON_QUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + if( xButtonQueue ) + { + /* Now the queue is created it is safe to enable the button interrupt. */ + ButtonInterrupt_Enable(); + + for( ;; ) + { + /* Simply wait for data to arrive from the button push interrupt. */ + if( xQueueReceive( xButtonQueue, &uxReceived, portMAX_DELAY ) == pdPASS ) + { + /* Was the data we received that expected? */ + if( uxReceived != uxExpected ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + else + { + /* Toggle the LED for every successful push. */ + vParTestToggleLED( mainBUTTON_PUSH_LED ); + } + + uxExpected++; + } + } + } + + /* Will only get here if the queue could not be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Button push ISR. */ + void interrupt vButtonPush( void ) + { + static unsigned portBASE_TYPE uxValToSend = 0; + + /* Send an incrementing value to the button push task each run. */ + uxValToSend++; + + /* Clear the interrupt flag. */ + PIFP = 1; + + /* Send the incremented value down the queue. The button push task is + blocked waiting for the data. As the button push task is high priority + it will wake and a context switch should be performed before leaving + the ISR. */ + if( xQueueSendFromISR( xButtonQueue, &uxValToSend, pdFALSE ) ) + { + /* NOTE: This macro can only be used if there are no local + variables defined. This function uses a static variable so it's + use is permitted. If the variable were not static portYIELD() + would have to be used in it's place. */ + portTASK_SWITCH_FROM_ISR(); + } + } + +#pragma CODE_SEG DEFAULT + + diff --git a/Demo/HCS12_CodeWarrior_small/prm/burner.bbl b/Demo/HCS12_CodeWarrior_small/prm/burner.bbl new file mode 100644 index 000000000..639ffdef3 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/prm/burner.bbl @@ -0,0 +1,223 @@ +/* logical s-record file */ +OPENFILE "%ABS_FILE%.s19" +format=motorola +busWidth=1 +origin=0 +len=0x1000000 +destination=0 +SRECORD=Sx +SENDBYTE 1 "%ABS_FILE%" +CLOSE + +/* physical s-record file */ +OPENFILE "%ABS_FILE%.phy" +format = motorola +busWidth = 1 +len = 0x4000 + +origin = 0x008000 +destination = 0x000000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x004000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x028000 +destination = 0x008000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x038000 +destination = 0x00C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x048000 +destination = 0x010000 +SENDBYTE 1 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0x0F8000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x3F8000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x00C000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +CLOSE + diff --git a/Demo/HCS12_CodeWarrior_small/readme.txt b/Demo/HCS12_CodeWarrior_small/readme.txt new file mode 100644 index 000000000..417a9af56 --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/readme.txt @@ -0,0 +1,117 @@ +//------------------------------------------------------------------------ +// Readme.txt +//------------------------------------------------------------------------ +This project stationery is designed to get you up and running +quickly with CodeWarrior for MC9S12C32. +It is set up for the selected CPU and target connection, +but can be easily modified. + +Sample code for the following language(s) is at your disposal: +- C + +The wizard has prepared CodeWarrior target(s) with the connection methods of +your choice: +- Simulator: + This interface/target is prepared to use the FCS (Full Chip Simulation). + +- SofTec: + This target interface connects to any of the USB-based SofTec Microsystems tools for HC(S)12. + + +Additional connections can be chosen in the simulator/debugger, +use the menu Component > Set Target. + +//------------------------------------------------------------------------ +// Processor Expert +//------------------------------------------------------------------------ +This project is prepared to be designed with Processor Expert. +The project has an additional 'tab' named 'Processor Expert' where you +can configure the CPU and its beans. +The CPU selected is inserted into the Processor Expert project panel, in +the Debug and Release configurations. +Change of the configuration is possible by the mouse double-click on it. +All the installed Embedded Beans are accessible in the Bean Selector +window, grouped into folders according to their function. The mouse +double-click on selected Embedded Bean in the Bean Selector window adds +the Bean to the project. The mouse double-click on the Bean icon in the +Project panel opens the Bean Inspector window, which is used to set the +Bean properties. Source code is generated after selecting the +(Code Design 'Project_name.mcp') menu command from the CodeWarrior main +window (Processor Expert > Code design 'Project_name.mcp'). +Use the bean methods and events to write your code in the main module +'Project_name'.c and the event module Events.c. + +For more help please read Processor Expert help: + (Processor Expert > Help > 'Topic'). + +The following folders are used in CodeWarrior project window for +ProcessorExpert: +- User modules: contains your sources. The main module 'Project_name'.c + and event module Events.c are located here after the Processor Expert + code generation. +- Prm: Linker parameter file used for linking. Note that the file used + for the linker is specified in the Linker Preference Panel. To open + the Preference Panel, please press or open the + (Edit > 'Current Build Target Name' Settings...) menu item in the + CodeWarrior main window menu, while the project window is opened). + After Processor Expert code generation 'Project_name'.prm file + will be placed here. You can switch off the .prm file generation in + Processor Expert if you want (in the CPU bean, Build Options) +- Generated code: this folder appears after the Processor Expert code + generation and contains generated code from Processor Expert. +- Doc: other files generated from the Processor Expert (documentation) + +//------------------------------------------------------------------------ +// Getting Started +//------------------------------------------------------------------------ +To build/debug your project, use the menu Project > Debug or press F5. +This will open the simulator/debugger. +Press again F5 in the debugger (or menu Run > Start/Continue) to start +the application. The menu Run > Halt or F6 stops the application. +In the debugger menu Component > Open you can load additional components. + +//------------------------------------------------------------------------ +// Project structure +//------------------------------------------------------------------------ +The project generated contains various files/folders: +- readme.txt: this file +- Sources: folder with the application source code +- Startup Code: C/C++ startup code +- Prm: + - burner.bbl file to generate S-Records +- Linker Map: the .map file generated by the linker +- Libraries: needed library files (ANSI, derivative header/implementation files) +- Debugger Project File: contains a .ini file for the debugger for each + connection +- Debugger Cmd Files: contains sub-folders for each connection with command + files + +//------------------------------------------------------------------------ +// Adding your own code +//------------------------------------------------------------------------ +Once everything is working as expected, you can begin adding your own code +to the project. Keep in mind that we provide this as an example of how to +get up and running quickly with CodeWarrior. There are certainly other +ways to handle interrupts and set up your linker command file. Feel free +to modify any of the source files provided. + +//------------------------------------------------------------------------ +// Simulator/Debugger: Additional components +//------------------------------------------------------------------------ +In the simulator/debugger, you can load additional components. Try the menu +Component > Open. + +//------------------------------------------------------------------------ +// Additional documentation +//------------------------------------------------------------------------ +Check out the online documentation provided. Use in CodeWarrior IDE the +menu Help > Online Manuals. + +//------------------------------------------------------------------------ +// Contacting Metrowerks +//------------------------------------------------------------------------ +For bug reports, technical questions, and suggestions, please use the +forms installed in the Release_Notes folder and send them to: +USA: support@metrowerks.com +EUROPE: support_europe@metrowerks.com +ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/serial/serial.c b/Demo/HCS12_CodeWarrior_small/serial/serial.c new file mode 100644 index 000000000..9c04a0cac --- /dev/null +++ b/Demo/HCS12_CodeWarrior_small/serial/serial.c @@ -0,0 +1,80 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. */ + +/* Standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + + +/* + * Initialise port 1 for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn = pdPASS; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/MicroBlaze/FreeRTOSConfig.h b/Demo/MicroBlaze/FreeRTOSConfig.h new file mode 100644 index 000000000..ad675f0f0 --- /dev/null +++ b/Demo/MicroBlaze/FreeRTOSConfig.h @@ -0,0 +1,77 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "xparameters.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 5 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/MicroBlaze/ParTest/ParTest.c b/Demo/MicroBlaze/ParTest/ParTest.c new file mode 100644 index 000000000..e79c43016 --- /dev/null +++ b/Demo/MicroBlaze/ParTest/ParTest.c @@ -0,0 +1,152 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Library includes. */ +#include "xgpio_l.h" + +/* Misc hardware specific definitions. */ +#define partstALL_AS_OUTPUT 0x00 +#define partstCHANNEL_1 0x01 +#define partstMAX_4BIT_LED 0x03 + +/* The outputs are split into two IO sections, these variables maintain the +current value of either section. */ +static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; + +/*-----------------------------------------------------------*/ +/* + * Setup the IO for the LED outputs. + */ +void vParTestInitialise( void ) +{ + /* Set both sets of LED's on the demo board to outputs. */ + XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + + /* Start with all outputs off. */ + uxCurrentOutput4Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); + uxCurrentOutput5Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being set/cleared belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( xValue ) + { + *puxCurrentValue |= uxLED; + } + else + { + *puxCurrentValue &= ~uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being toggled belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( *puxCurrentValue & uxLED ) + { + *puxCurrentValue &= ~uxLED; + } + else + { + *puxCurrentValue |= uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} + + diff --git a/Demo/MicroBlaze/__xps/bitinit.opt b/Demo/MicroBlaze/__xps/bitinit.opt new file mode 100644 index 000000000..2496fab76 --- /dev/null +++ b/Demo/MicroBlaze/__xps/bitinit.opt @@ -0,0 +1 @@ + -pe microblaze_0 RTOSDemo/executable.elf diff --git a/Demo/MicroBlaze/__xps/libgen.opt b/Demo/MicroBlaze/__xps/libgen.opt new file mode 100644 index 000000000..77b154845 --- /dev/null +++ b/Demo/MicroBlaze/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex4 diff --git a/Demo/MicroBlaze/__xps/platgen.opt b/Demo/MicroBlaze/__xps/platgen.opt new file mode 100644 index 000000000..f56ee64ea --- /dev/null +++ b/Demo/MicroBlaze/__xps/platgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -st xst diff --git a/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt b/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..c108c4082 --- /dev/null +++ b/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt @@ -0,0 +1,23 @@ +microblaze_0 +RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c +RTOSDEMO_HEADERS = FreeRTOSConfig.h +RTOSDEMO_CC = mb-gcc +RTOSDEMO_CC_SIZE = mb-size +RTOSDEMO_CC_OPT = -Os +RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_CC_PREPROC_FLAG = # -Wp, +RTOSDEMO_CC_ASM_FLAG = # -Wa, +RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map +RTOSDEMO_LINKER_SCRIPT = +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt +RTOSDEMO_MODE = executable +RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 +RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= + $(RTOSDEMO_CC_SOFTMUL_FLAG) \ diff --git a/Demo/MicroBlaze/__xps/simgen.opt b/Demo/MicroBlaze/__xps/simgen.opt new file mode 100644 index 000000000..236453ae0 --- /dev/null +++ b/Demo/MicroBlaze/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti diff --git a/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt b/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt new file mode 100644 index 000000000..67e70306a --- /dev/null +++ b/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt @@ -0,0 +1,23 @@ +microblaze_0 +TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c +TESTAPP_PERIPHERAL_HEADERS = +TESTAPP_PERIPHERAL_CC = mb-gcc +TESTAPP_PERIPHERAL_CC_SIZE = mb-size +TESTAPP_PERIPHERAL_CC_OPT = -O2 +TESTAPP_PERIPHERAL_CFLAGS = +TESTAPP_PERIPHERAL_CC_SEARCH = # -B +TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L +TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I +TESTAPP_PERIPHERAL_LFLAGS = # -l +TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp, +TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa, +TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl, +TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr +TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g +TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt +TESTAPP_PERIPHERAL_MODE = executable +TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0 +TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= + $(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \ diff --git a/Demo/MicroBlaze/__xps/vpgen.opt b/Demo/MicroBlaze/__xps/vpgen.opt new file mode 100644 index 000000000..8ea8f6640 --- /dev/null +++ b/Demo/MicroBlaze/__xps/vpgen.opt @@ -0,0 +1 @@ + -p xc4vfx12ff668-10 diff --git a/Demo/MicroBlaze/__xps/xpsxflow.opt b/Demo/MicroBlaze/__xps/xpsxflow.opt new file mode 100644 index 000000000..bf6b9048d --- /dev/null +++ b/Demo/MicroBlaze/__xps/xpsxflow.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10 diff --git a/Demo/MicroBlaze/_impact.cmd b/Demo/MicroBlaze/_impact.cmd new file mode 100644 index 000000000..a712a7180 --- /dev/null +++ b/Demo/MicroBlaze/_impact.cmd @@ -0,0 +1,7 @@ +setMode -bs +setCable -port auto +identify +identifyMPM +setAttribute -position 3 -attr configFileName -value "implementation/download.bit" +program -p 3 +quit diff --git a/Demo/MicroBlaze/crt0.s b/Demo/MicroBlaze/crt0.s new file mode 100644 index 000000000..8198096e8 --- /dev/null +++ b/Demo/MicroBlaze/crt0.s @@ -0,0 +1,126 @@ +###################################-*-asm*- +# +# Copyright (c) 2001 Xilinx, Inc. All rights reserved. +# +# Xilinx, Inc. CONFIDENTIAL +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE. +# +# crt0.s +# +# C RunTime: +# Used for initialization of small data +# anchors and stack for programs compiled using +# Xilinx Gnu Tools. This routine also intializes the +# exception and interrupt handlers +# +# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $ +# +####################################### + +/* Vector map (Interrupts, Exceptions, Breakpoints) */ +# # 0x00 # Jump to Start +# # 0x04 # nop +# # 0x08 # Imm instr for soft exception address [Hi halfword] +# # 0x0c # Jump to sof Exception handler [Lo halfword] +# # 0x10 # Imm instr for interrupt address [Hi halfword] +# # 0x14 # Jump to interrupt handler [Lo halfword] +# # 0x18 # nop - Reserved for breakpoint vector +# # 0x1C # nop - Reserved for breakpoint vector +# # 0x20 # Imm instr for hw exception address [Hi halfword] +# # 0x24 # Jump instr to hw exception handler [Lo halfword] + + .globl _start + +/* Set the exception and interrupt address vectors */ +/* to jump to the appropriate handlers */ + + .align 2 + .ent _start + _start: + bri _start1 # 0x00 + nop # 0x04 + nop # 0x08 # Reserve space for software exception vector + nop # 0x0c + nop # 0x10 # Reserve space for interrupt vector + nop # 0x14 + nop # 0x18 # Reserve space for breakpoint vector + nop # 0x1c + nop # 0x18 # Reserve space for hw exception vector + nop # 0x1c + + _start1: +/* Set the Small Data Anchors and the Stack pointer */ + la r13, r0, _SDA_BASE_ + la r2, r0, _SDA2_BASE_ + la r1, r0, _stack-16 # 16 bytes (4 words are needed by + # crt for args and link reg ) + +/* Set the opcodes brai and imm for handlers */ + la r6,r0,0xb8080000 # [opcode for brai ] + swi r6,r0,0x4 # [brai opcode for reset] + swi r6,r0,0xc # [brai opcode for exception] + swi r6,r0,0x14 # [brai opcode for interrupt] + swi r6,r0,0x24 # [brai opcode for hw exceptions] + + la r6,r0,0xb0000000 # [opcode for imm ] + swi r6,r0,0x0 # [imm opcode for reset] + swi r6,r0,0x8 # [imm opcode for exception] + swi r6,r0,0x10 # [imm opocde for interrupt] + swi r6,r0,0x20 # [imm opocde for hw exceptions] + +/* Set Reset vector */ + la r6,r0,_start1 + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x2 # [imm for reset] + shi r6,r0, 0x6 # [lower half for reset] + +/* Set Software Exception Handler */ + la r6,r0,_exception_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0xa # [imm for exception] + shi r6,r0, 0xe # [lower half for exception ] + +/* Set Interrupt Handler */ + la r6,r0,_interrupt_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x12 # [imm for exception] + shi r6,r0, 0x16 # [lower half for intterupt ] + +/* Set HW Exception Handler */ + la r6,r0,_hw_exception_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x22 # [imm for exception] + shi r6,r0, 0x26 # [lower half for hw exception] + +/* initialize bss sections */ + brlid r15,_crtinit + nop + +/* Adjust the stack pointer */ + addi r1,r1,16 + +/* Fall through to exit */ + .end _start + +/* Use this exit function */ + .globl exit # exit library call + .ent exit +exit: + bri exit + .end exit + diff --git a/Demo/MicroBlaze/data/system.ucf b/Demo/MicroBlaze/data/system.ucf new file mode 100644 index 000000000..81a63a2f8 --- /dev/null +++ b/Demo/MicroBlaze/data/system.ucf @@ -0,0 +1,74 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AE14; +Net sys_clk_pin IOSTANDARD = LVCMOS33; +Net sys_rst_pin LOC=D6; +Net sys_rst_pin PULLUP; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; + +## FPGA pin constraints +Net fpga_0_RS232_Uart_RX_pin LOC=W2; +Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_TX_pin LOC=W1; +Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; diff --git a/Demo/MicroBlaze/etc/bitgen.ut b/Demo/MicroBlaze/etc/bitgen.ut new file mode 100644 index 000000000..442444880 --- /dev/null +++ b/Demo/MicroBlaze/etc/bitgen.ut @@ -0,0 +1,21 @@ +-g ConfigRate:4 +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No diff --git a/Demo/MicroBlaze/etc/bitgen_spartan3.ut b/Demo/MicroBlaze/etc/bitgen_spartan3.ut new file mode 100644 index 000000000..65522563b --- /dev/null +++ b/Demo/MicroBlaze/etc/bitgen_spartan3.ut @@ -0,0 +1,15 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g StartUpClk:JTAGCLK +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No diff --git a/Demo/MicroBlaze/etc/download.cmd b/Demo/MicroBlaze/etc/download.cmd new file mode 100644 index 000000000..15728dcff --- /dev/null +++ b/Demo/MicroBlaze/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit diff --git a/Demo/MicroBlaze/etc/fast_runtime.opt b/Demo/MicroBlaze/etc/fast_runtime.opt new file mode 100644 index 000000000..7335e7a21 --- /dev/null +++ b/Demo/MicroBlaze/etc/fast_runtime.opt @@ -0,0 +1,80 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/MicroBlaze/etc/xmd_microblaze_0.opt b/Demo/MicroBlaze/etc/xmd_microblaze_0.opt new file mode 100644 index 000000000..43994b0af --- /dev/null +++ b/Demo/MicroBlaze/etc/xmd_microblaze_0.opt @@ -0,0 +1 @@ +connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1 diff --git a/Demo/MicroBlaze/main.c b/Demo/MicroBlaze/main.c new file mode 100644 index 000000000..9ab9331cf --- /dev/null +++ b/Demo/MicroBlaze/main.c @@ -0,0 +1,436 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * + * In addition to the standard tasks, main() creates two "Register Check" + * tasks. These tasks write known values into every general purpose register, + * then check each register to ensure it still contains the expected (written) + * value. The register check tasks operate at the idle priority so will get + * repeatedly preempted. A register being found to contain an incorrect value + * following such a preemption would be indicative of an error in the context + * switch mechanism. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "ParTest.h" +#include "flash.h" +#include "comtest2.h" +#include "integer.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "PollQ.h" + +/* Hardware library includes. */ +#include + +/* The rate at which the 'check' LED will flash when no errors have been +detected. */ +#define mainNO_ERROR_CHECK_PERIOD 3000 + +/* The rate at which the 'check' LED will flash when an error has been +detected in one of the demo tasks. */ +#define mainERROR_CHECK_PERIOD 500 + +/* Demo application task priorities. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Software cannot influence the BAUD rate used by the simple UART +implementation. */ +#define mainBAUD_RATE 0 + +/* The LED flashed by the 'check' task to indicate the system status. */ +#define mainCHECK_TASK_LED 3 + +/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1 +will also be used. */ +#define mainCOM_TEST_LED 4 + +/* The register test task does not make any function calls so does not require +much stack at all. */ +#define mainTINY_STACK 70 + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/* + * The register test task as described at the top of this file. + */ +static void vRegisterTest( void *pvParameters ); + +/* + * Perform any necessary hardware configuration. + */ +static void prvSetupHardware( void ); + +/* Set to pdFAIL should an error be discovered in the register test tasks. */ +static unsigned portLONG ulRegisterTestStatus = pdPASS; +const unsigned portLONG *pulStatusAddr = &ulRegisterTestStatus; + +/*-----------------------------------------------------------*/ + +/* + * Create all the demo tasks - then start the scheduler. + */ +int main (void) +{ + /* When re-starting a debug session (rather than cold booting) we want + to ensure the installed interrupt handlers do not execute until after the + scheduler has been started. */ + portDISABLE_INTERRUPTS(); + + prvSetupHardware(); + + /* Start the standard demo application tasks. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + /* Create two register check tasks - using a different parameter for each. + The parameter is used to generate the known values written to the registers. */ + #if configUSE_PREEMPTION == 1 + xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL ); + #endif + + /* Create the 'check' task that is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Should not get here as the processor is now under control of the + scheduler! */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_PERIOD; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The delay period used will depend on whether + or not an error has been discovered in one of the demo tasks. */ + for( ;; ) + { + vTaskDelay( xDelayPeriod ); + if( !prvCheckOtherTasksAreStillRunning() ) + { + /* An error has been found. Shorten the delay period to make + the LED flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xAllTestsPass = pdTRUE; + + /* Return pdFALSE if any demo application task set has encountered + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTestsPass = ( portLONG ) pdFAIL; + } + + /* Mutual exclusion on this variable is not necessary as we only read it. */ + if( ulRegisterTestStatus != pdPASS ) + { + xAllTestsPass = pdFALSE; + } + + return xAllTestsPass; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Ensure the interrupt controller is enabled in order that subsequent + code can successfully configure the peripherals. */ + XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR ); + + /* Initialise the GPIO used for the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vRegisterTest( void *pvParameters ) +{ + for( ;; ) + { + /* Fill the registers with their register number plus the offset + (added) value. The added value is passed in as a parameter so + is contained in r5. */ + asm volatile ( "addi r3, r5, 3 \n\t" \ + "addi r4, r5, 4 \n\t" \ + "addi r6, r5, 6 \n\t" \ + "addi r7, r5, 7 \n\t" \ + "addi r8, r5, 8 \n\t" \ + "addi r9, r5, 9 \n\t" \ + "addi r10, r5, 10 \n\t" \ + "addi r11, r5, 11 \n\t" \ + "addi r12, r5, 12 \n\t" \ + "addi r16, r5, 16 \n\t" \ + "addi r17, r5, 17 \n\t" \ + "addi r18, r5, 18 \n\t" \ + "addi r19, r5, 19 \n\t" \ + "addi r20, r5, 20 \n\t" \ + "addi r21, r5, 21 \n\t" \ + "addi r22, r5, 22 \n\t" \ + "addi r23, r5, 23 \n\t" \ + "addi r24, r5, 24 \n\t" \ + "addi r25, r5, 25 \n\t" \ + "addi r26, r5, 26 \n\t" \ + "addi r27, r5, 27 \n\t" \ + "addi r28, r5, 28 \n\t" \ + "addi r29, r5, 29 \n\t" \ + "addi r30, r5, 30 \n\t" \ + "addi r31, r5, 31 \n\t" + ); + + /* Now read back the register values to ensure they are as we expect. + This task will get preempted frequently so other tasks are likely to + have executed since the register values were written. */ + + /* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */ + asm volatile ( "addi r3, r3, -3 " ); + + /* Compare r3 and r5. If they are not equal then either r3 or r5 + contains the wrong value and *pulStatusAddr is to pdFAIL. */ + asm volatile ( "cmp r3, r3, r5 \n\t" \ + "beqi r3, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" + ); + + /* Repeat for all the other registers. */ + asm volatile ( "addi r4, r4, -4 \n\t" \ + "cmp r4, r4, r5 \n\t" \ + "beqi r4, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r6, r6, -6 \n\t" \ + "cmp r6, r6, r5 \n\t" \ + "beqi r6, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r7, r7, -7 \n\t" \ + "cmp r7, r7, r5 \n\t" \ + "beqi r7, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r8, r8, -8 \n\t" \ + "cmp r8, r8, r5 \n\t" \ + "beqi r8, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r9, r9, -9 \n\t" \ + "cmp r9, r9, r5 \n\t" \ + "beqi r9, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r10, r10, -10 \n\t" \ + "cmp r10, r10, r5 \n\t" \ + "beqi r10, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r11, r11, -11 \n\t" \ + "cmp r11, r11, r5 \n\t" \ + "beqi r11, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r12, r12, -12 \n\t" \ + "cmp r12, r12, r5 \n\t" \ + "beqi r12, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r16, r16, -16 \n\t" \ + "cmp r16, r16, r5 \n\t" \ + "beqi r16, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r17, r17, -17 \n\t" \ + "cmp r17, r17, r5 \n\t" \ + "beqi r17, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r18, r18, -18 \n\t" \ + "cmp r18, r18, r5 \n\t" \ + "beqi r18, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r19, r19, -19 \n\t" \ + "cmp r19, r19, r5 \n\t" \ + "beqi r19, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r20, r20, -20 \n\t" \ + "cmp r20, r20, r5 \n\t" \ + "beqi r20, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r21, r21, -21 \n\t" \ + "cmp r21, r21, r5 \n\t" \ + "beqi r21, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r22, r22, -22 \n\t" \ + "cmp r22, r22, r5 \n\t" \ + "beqi r22, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r23, r23, -23 \n\t" \ + "cmp r23, r23, r5 \n\t" \ + "beqi r23, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r24, r24, -24 \n\t" \ + "cmp r24, r24, r5 \n\t" \ + "beqi r24, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r25, r25, -25 \n\t" \ + "cmp r25, r25, r5 \n\t" \ + "beqi r25, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r26, r26, -26 \n\t" \ + "cmp r26, r26, r5 \n\t" \ + "beqi r26, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r27, r27, -27 \n\t" \ + "cmp r27, r27, r5 \n\t" \ + "beqi r27, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r28, r28, -28 \n\t" \ + "cmp r28, r28, r5 \n\t" \ + "beqi r28, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r29, r29, -29 \n\t" \ + "cmp r29, r29, r5 \n\t" \ + "beqi r29, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r30, r30, -30 \n\t" \ + "cmp r30, r30, r5 \n\t" \ + "beqi r30, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r31, r31, -31 \n\t" \ + "cmp r31, r31, r5 \n\t" \ + "beqi r31, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" + ); + } +} + + + diff --git a/Demo/MicroBlaze/platgen.opt b/Demo/MicroBlaze/platgen.opt new file mode 100644 index 000000000..1a984fdb6 --- /dev/null +++ b/Demo/MicroBlaze/platgen.opt @@ -0,0 +1,7 @@ +-p +xc4vfx12ff668-10 +-lang +vhdl +-st +xst +system.mhs diff --git a/Demo/MicroBlaze/serial/serial.c b/Demo/MicroBlaze/serial/serial.c new file mode 100644 index 000000000..ef17165ec --- /dev/null +++ b/Demo/MicroBlaze/serial/serial.c @@ -0,0 +1,195 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Microblaze driver includes. */ +#include "xuartlite_l.h" +#include "xintc_l.h" + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulControlReg, ulMask; + + /* NOTE: The baud rate used by this driver is determined by the hardware + parameterization of the UART Lite peripheral, and the baud value passed to + this function has no effect. */ + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + if( ( xRxedChars ) && ( xCharsForTx ) ) + { + /* Disable the interrupt. */ + XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR ); + + /* Flush the fifos. */ + ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET ); + + /* Enable the interrupt again. The interrupt controller has not yet been + initialised so there is no chance of receiving an interrupt until the + scheduler has been started. */ + XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR ); + + /* Enable the interrupt in the interrupt controller while maintaining + all the other bit settings. */ + ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + ulMask |= XPAR_RS232_UART_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 ); + } + + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one UART. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn = pdTRUE; + + portENTER_CRITICAL(); + { + /* If the UART FIFO is full we can block posting the new data on the + Tx queue. */ + if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* Otherwise, if there is data already in the queue we should add the + new data to the back of the queue to ensure the sequencing is + maintained. */ + else if( uxQueueMessagesWaiting( xCharsForTx ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* If the UART FIFO is not full and there is no data already in the + queue we can write directly to the FIFO without disrupting the + sequence. */ + else + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +void vSerialISR( void *pvBaseAddress ) +{ +unsigned portLONG ulISRStatus; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; +portCHAR cChar; + + /* Determine the cause of the interrupt. */ + ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + + if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 ) + { + /* A character is available - place it in the queue of received + characters. This might wake a task that was blocked waiting for + data. */ + cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); + xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx ); + } + + if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) + { + /* There is space in the FIFO - if there are any characters queue for + transmission they can be send to the UART now. This might unblock a + task that was waiting for space to become available on the Tx queue. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); + } + } + + /* If we woke any tasks we may require a context switch. */ + if( xTaskWokenByTx || xTaskWokenByRx ) + { + portYIELD_FROM_ISR(); + } +} diff --git a/Demo/MicroBlaze/system.bsb b/Demo/MicroBlaze/system.bsb new file mode 100644 index 000000000..cc6c27827 --- /dev/null +++ b/Demo/MicroBlaze/system.bsb @@ -0,0 +1 @@ +„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dn\b\dDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@š˜h`f@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðhDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@DˆŠ¬’†Š¾¦’´ŠD@DðÆhìÌðbdDv%„æÄ®ÒôttªàÈÂèʌ Ž‚@D ‚†–‚ŽŠD@DÌÌllpDv&„æÄ®ÒôttªàÈÂèʌ Ž‚@D¦ ŠŠˆŽ¤‚ˆŠD@DZb`Dv"„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôÊDv=„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D„ª¦¾Œ¤Š¢D@Db``\``````Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D†‚†ŠD@Dœž@†‚†ŠDvN„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D†‚†Š˜’œ–@†žš žœŠœ¨D@Dˆˆ¤¾¦ˆ¤‚š¾lhšðfdDv=„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D†˜–¾Œ¤Š¢D@Db``\``````DvJ„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@DˆŠ„ªŽ¾’ŒD@DžÜZ†ÐÒà@®@ˆÊÄêÎ@šÞÈêØÊDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D˜š„„¤‚š@¦’´ŠD@DljjflDv>„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D ¤ž†¾Œ¤Š¢D@Db``\``````Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@DÞàľêÂäèØÒèÊDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv7„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾žˆˆ¾ ‚¤’¨²D@D`Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ª¦Š¾ ‚¤’¨²D@D`Dv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D’ž¨² ŠD@D°’˜¾ª‚¤¨¾¬bDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv-„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèD@DÞàľÎàÒÞDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@DÞàľÎàÒÞDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv0„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@DÞàľèÒÚÊä¾bD@DÞàľèÒÚÊäDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D†¾†žªœ¨¾®’ˆ¨D@DfdDv=„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@D†¾žœŠ¾¨’šŠ¤¾žœ˜²D@DbDv=„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DÞàľèÒÚÊä¾bD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv/„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@DŒ‚˜¦ŠDv1„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠDv#„æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨ˆ’œD@DœÞÜÊDv$„æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨ˆžª¨D@DœÞÜÊDvA„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ˆ‚¨‚¾’œ¦D@DÈØÚľÆÜèØäD@D¨Êæè‚àྠÊäÒàÐÊäÂØDvA„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤D@D¨Êæè‚àྠÊäÒàÐÊäÂØDvD„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤žŽ¤‚š¾’œ¦D@DÒØÚľÆÜèØäD@D¨Êæè‚àྠÊäÒàÐÊäÂØDvD„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤D@D¨Êæè‚àྠÊäÒàÐÊäÂØDvB„æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨‚†–¾’œ¦D@DÈØÚľÆÜèØäD@D¨Êæè‚àྠÊäÒàÐÊäÂØDvB„æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨‚†–¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤D@D¨Êæè‚àྠÊäÒàÐÊäÂØDv \ No newline at end of file diff --git a/Demo/MicroBlaze/system.make b/Demo/MicroBlaze/system.make new file mode 100644 index 000000000..143cd8096 --- /dev/null +++ b/Demo/MicroBlaze/system.make @@ -0,0 +1,258 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs +# The software specification of the system is in file : +# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss + +include system_incl.make + + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttopn:Export to ProjNav" + @echo " " + @echo " libs : Configures the sw libraries for this system" + @echo " program : Compiles the program sources for all the processor instances" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " behavioral_model:Generates behavioral HDL models with BRAM initialization" + @echo " structural_model:Generates structural simulation HDL models with BRAM initialization" + @echo " timing_model : Generates timing simulation HDL models with BRAM initialization" + @echo " vp : Generates virtual platform model" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " libsclean: Deletes sw libraries" + @echo " programclean: Deletes compiled ELF files" + @echo " swclean : Deletes sw libraries and ELF files" + @echo " simclean : Deletes simulation dir" + @echo " vpclean : Deletes virtualplatform dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + @echo " make : (Default)" + @echo " Creates a Microprocessor system using default initializations" + @echo " specified for each processor in MSS file" + + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +netlist: $(POSTSYN_NETLIST) + +libs: $(LIBRARIES) + +program: $(ALL_USER_ELF_FILES) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral; \ + $(SIM_CMD) & + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +timing_model: $(TIMING_SIM_SCRIPT) + +vp: $(VPEXEC) + +clean: hwclean libsclean programclean simclean vpclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + +bitsclean: + +simclean: + rm -rf simulation/behavioral + +swclean: libsclean programclean + @echo "" + +libsclean: $(LIBSCLEAN_TARGETS) + +programclean: $(PROGRAMCLEAN_TARGETS) + +vpclean: + rm -rf virtualplatform + +################################################################# +# SOFTWARE PLATFORM FLOW +################################################################# + + +$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt + @echo "*********************************************" + @echo "Creating software libraries..." + @echo "*********************************************" + libgen $(LIBGEN_OPTIONS) $(MSSFILE) + + +microblaze_0_libsclean: + rm -rf microblaze_0/lib/ + +$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES) + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDemo_program: $(RTOSDEMO_OUTPUT) + +$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ + $(LIBRARIES) __xps/rtosdemo_compiler.opt + @mkdir -p $(RTOSDEMO_OUTPUT_DIR) + $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ + $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ + -xl-mode-$(RTOSDEMO_MODE) \ + $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) + $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) + +RTOSDemo_programclean: + rm -f $(RTOSDEMO_OUTPUT) + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + + +$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP) + @mkdir -p $(BOOTLOOP_DIR) + cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + bash -c "cd synthesis; ./synthesis.sh; cd .." + +$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \ + $(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE) + @echo "Copying Xilinx Implementation tool scripts.." + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + @cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc + cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) + +exporttopn: + @echo "You have chosen XPS for implementation tool flow." + @echo "Please select ProjNav as your implementation flow in Project Options." + @echo "In batch mode, use commad xset pnproj ." + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) + @echo "*********************************************" + @echo "Creating system ace file" + @echo "*********************************************" + xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +################################################################# +# VIRTUAL PLATFORM FLOW +################################################################# + + +$(VPEXEC): $(MHSFILE) __xps/vpgen.opt + @echo "****************************************************" + @echo "Creating virtual platform for hardware specification.." + @echo "****************************************************" + vpgen $(VPGEN_OPTIONS) $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/MicroBlaze/system.mhs b/Demo/MicroBlaze/system.mhs new file mode 100644 index 000000000..2999abcea --- /dev/null +++ b/Demo/MicroBlaze/system.mhs @@ -0,0 +1,196 @@ +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 +# Sun Nov 13 16:46:19 2005 +# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 +# Family: virtex4 +# Device: xc4vfx12 +# Package: ff668 +# Speed Grade: -10 +# Processor: Microblaze +# System clock frequency: 100.000000 MHz +# Debug interface: On-Chip HW Debug Module +# On Chip Memory : 64 KB +# ############################################################################## + + + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT + PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT + PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4] + PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK + PORT sys_rst_pin = sys_rst_s, DIR = INPUT + + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 4.00.a + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 + BUS_INTERFACE DLMB = dlmb + BUS_INTERFACE ILMB = ilmb + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + PORT CLK = sys_clk_s + PORT DBG_CAPTURE = DBG_CAPTURE_s + PORT DBG_CLK = DBG_CLK_s + PORT DBG_REG_EN = DBG_REG_EN_s + PORT DBG_TDI = DBG_TDI_s + PORT DBG_TDO = DBG_TDO_s + PORT DBG_UPDATE = DBG_UPDATE_s + PORT Interrupt = Interrupt +END + +BEGIN opb_v20 + PARAMETER INSTANCE = mb_opb + PARAMETER HW_VER = 1.10.c + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT OPB_Clk = sys_clk_s +END + +BEGIN opb_mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.a + PARAMETER C_MB_DBG_PORTS = 1 + PARAMETER C_USE_UART = 1 + PARAMETER C_UART_WIDTH = 8 + PARAMETER C_BASEADDR = 0x41400000 + PARAMETER C_HIGHADDR = 0x4140ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT DBG_CAPTURE_0 = DBG_CAPTURE_s + PORT DBG_CLK_0 = DBG_CLK_s + PORT DBG_REG_EN_0 = DBG_REG_EN_s + PORT DBG_TDI_0 = DBG_TDI_s + PORT DBG_TDO_0 = DBG_TDO_s + PORT DBG_UPDATE_0 = DBG_UPDATE_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = dlmb + BUS_INTERFACE BRAM_PORT = dlmb_port +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = ilmb + BUS_INTERFACE BRAM_PORT = ilmb_port +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port + BUS_INTERFACE PORTB = dlmb_port +END + +BEGIN opb_uartlite + PARAMETER INSTANCE = RS232_Uart + PARAMETER HW_VER = 1.00.b + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_CLK_FREQ = 100000000 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT Interrupt = RS232_Uart_Interrupt + PORT RX = fpga_0_RS232_Uart_RX + PORT TX = fpga_0_RS232_Uart_TX +END + +BEGIN opb_gpio + PARAMETER INSTANCE = LEDs_4Bit + PARAMETER HW_VER = 3.01.b + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO +END + +BEGIN opb_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER HW_VER = 3.01.b + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO +END + +BEGIN opb_timer + PARAMETER INSTANCE = opb_timer_1 + PARAMETER HW_VER = 1.00.b + PARAMETER C_COUNT_WIDTH = 32 + PARAMETER C_ONE_TIMER_ONLY = 1 + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT Interrupt = opb_timer_1_Interrupt +END + +BEGIN opb_intc + PARAMETER INSTANCE = opb_intc_0 + PARAMETER HW_VER = 1.00.c + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + PARAMETER C_HAS_IPR = 0 + BUS_INTERFACE SOPB = mb_opb + PORT Irq = Interrupt + PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt +END + +BEGIN dcm_module + PARAMETER INSTANCE = dcm_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_CLK0_BUF = TRUE + PARAMETER C_CLKIN_PERIOD = 10.000000 + PARAMETER C_CLK_FEEDBACK = 1X + PARAMETER C_EXT_RESET_HIGH = 1 + PORT CLKIN = dcm_clk_s + PORT CLK0 = sys_clk_s + PORT CLKFB = sys_clk_s + PORT RST = net_gnd + PORT LOCKED = dcm_0_lock +END + diff --git a/Demo/MicroBlaze/system.mss b/Demo/MicroBlaze/system.mss new file mode 100644 index 000000000..6c13869ca --- /dev/null +++ b/Demo/MicroBlaze/system.mss @@ -0,0 +1,84 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_0 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_0 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar + PARAMETER XMDSTUB_PERIPHERAL = debug_module +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = opbarb + PARAMETER DRIVER_VER = 1.02.a + PARAMETER HW_INSTANCE = mb_opb +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = debug_module +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = RS232_Uart + PARAMETER int_handler = vSerialISR, int_port = Interrupt +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = LEDs_4Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = tmrctr + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = opb_timer_1 + PARAMETER int_handler = vTickISR, int_port = Interrupt +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.00.c + PARAMETER HW_INSTANCE = opb_intc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dcm_0 +END + + diff --git a/Demo/MicroBlaze/system.xmp b/Demo/MicroBlaze/system.xmp new file mode 100644 index 000000000..c899fd9b5 --- /dev/null +++ b/Demo/MicroBlaze/system.xmp @@ -0,0 +1,66 @@ +#Please do not modify this file by hand +XmpVersion: 7.1 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +NPL File: projnav/system.ise +Architecture: virtex4 +Device: xc4vfx12 +Package: ff668 +SpeedGrade: -10 +UseProjNav: 0 +AddToNPL: 0 +PNImportBitFile: +PNImportBmmFile: +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +SynProj: xst +ReloadPbde: 0 +MainMhsEditor: 0 +InsertNoPads: 0 +HdlLang: VHDL +Simulator: mti +SimModel: BEHAVIORAL +SimXLib: +SimEdkLib: +MixLangSim: 1 +UcfFile: data/system.ucf +Processor: microblaze_0 +BootLoop: 0 +XmdStub: 0 +SwProj: RTOSDemo +Processor: microblaze_0 +Executable: RTOSDemo/executable.elf +Source: main.c +Source: ParTest/ParTest.c +Source: ../../Source/tasks.c +Source: ../../Source/queue.c +Source: ../../Source/list.c +Source: ../../Source/portable/MemMang/heap_1.c +Source: ../../Source/portable/GCC/MicroBlaze/port.c +Source: ../../Source/portable/GCC/MicroBlaze/portasm.s +Source: ../Common/Minimal/flash.c +Source: serial/serial.c +Source: ../Common/Minimal/comtest.c +Source: ../Common/Minimal/integer.c +Source: ../Common/Minimal/semtest.c +Source: ../Common/Minimal/dynamic.c +Source: ../Common/Minimal/PollQ.c +Source: ../Common/Minimal/BlockQ.c +Header: FreeRTOSConfig.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 4 +GlobPtrOpt: 0 +DebugSym: 1 +SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze +AsmOpt: +LinkOpt: -Map=rtosdemo.map +ProgStart: +StackSize: +HeapSize: +LinkerScript: +ProgCCFlags: -D MICROBLAZE_GCC -Wall diff --git a/Demo/MicroBlaze/system_incl.make b/Demo/MicroBlaze/system_incl.make new file mode 100644 index 000000000..9973ee322 --- /dev/null +++ b/Demo/MicroBlaze/system_incl.make @@ -0,0 +1,134 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp +################################################################# + +XILINX_EDK_DIR = C:/devtools/xilinx/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +MSSFILE = system.mss + +FPGA_ARCH = virtex4 + +DEVICE = xc4vfx12ff668-10 + +LANGUAGE = vhdl + +SEARCHPATHOPT = + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) + +LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \ + $(MICROBLAZE_0_LIBG_OPT) + +VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) + +RTOSDEMO_OUTPUT_DIR = RTOSDemo +RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +BOOTLOOP_DIR = bootloops + +MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf +MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf + +BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT) +BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT) + +ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) + +SIM_CMD = vsim + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti + +MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf + +LIBRARIES = \ + microblaze_0/lib/libxil.a +VPEXEC = virtualplatform/vpexec.exe + +LIBSCLEAN_TARGETS = microblaze_0_libsclean + +PROGRAMCLEAN_TARGETS = RTOSDemo_programclean + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \ +implementation/mb_opb_wrapper.ngc \ +implementation/debug_module_wrapper.ngc \ +implementation/ilmb_wrapper.ngc \ +implementation/dlmb_wrapper.ngc \ +implementation/dlmb_cntlr_wrapper.ngc \ +implementation/ilmb_cntlr_wrapper.ngc \ +implementation/lmb_bram_wrapper.ngc \ +implementation/rs232_uart_wrapper.ngc \ +implementation/leds_4bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/opb_timer_1_wrapper.ngc \ +implementation/opb_intc_0_wrapper.ngc \ +implementation/dcm_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt +BITGEN_UT_FILE = etc/bitgen.ut + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c + +RTOSDEMO_HEADERS = FreeRTOSConfig.h + +RTOSDEMO_CC = mb-gcc +RTOSDEMO_CC_SIZE = mb-size +RTOSDEMO_CC_OPT = -Os +RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_CC_PREPROC_FLAG = # -Wp, +RTOSDEMO_CC_ASM_FLAG = # -Wa, +RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map +RTOSDEMO_LINKER_SCRIPT = +RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt +RTOSDEMO_MODE = executable +RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 +RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ + $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \ + $(RTOSDEMO_CC_SOFTMUL_FLAG) \ + $(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \ + $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) diff --git a/Demo/PC/FRConfig.h b/Demo/PC/FRConfig.h new file mode 100644 index 000000000..55b1d8f5d --- /dev/null +++ b/Demo/PC/FRConfig.h @@ -0,0 +1,84 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions for the x86 port. + *----------------------------------------------------------*/ + +/* These are the only definitions that can be modified!. */ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* The maximum number of characters a task name can take, +including the null terminator. */ +#define configMAX_TASK_NAME_LEN ( 16 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +/* + * The tick count (and times defined in tick count units) can be either a 16bit + * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide + * which to use. + */ +#define configUSE_16_BIT_TICKS 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PC/FileIO/fileIO.c b/Demo/PC/FileIO/fileIO.c new file mode 100644 index 000000000..2b494b7b4 --- /dev/null +++ b/Demo/PC/FileIO/fileIO.c @@ -0,0 +1,88 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "fileio.h" + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ) +{ + taskENTER_CRITICAL(); + printf( "%s", pcMessageToPrint ); + fflush( stdout ); + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vWriteMessageToDisk( const portCHAR * const pcMessage ) +{ +const portCHAR * const pcFileName = "a:\\RTOSlog.txt"; +const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "a" ); + if( pf != NULL ) + { + fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); + fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) +{ +const portCHAR * const pcFileName = "a:\\trace.bin"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "wb" ); + if( pf ) + { + fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +} + diff --git a/Demo/PC/FreeRTOSConfig.h b/Demo/PC/FreeRTOSConfig.h new file mode 100644 index 000000000..245b9a0d9 --- /dev/null +++ b/Demo/PC/FreeRTOSConfig.h @@ -0,0 +1,77 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PC/ParTest/ParTest.c b/Demo/PC/ParTest/ParTest.c new file mode 100644 index 000000000..853a39441 --- /dev/null +++ b/Demo/PC/ParTest/ParTest.c @@ -0,0 +1,121 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.01: + + + Types used updated. + + Add vParTestToggleLED(); + + +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + +#include "FreeRTOS.h" +#include "partest.h" +#include "task.h" + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +/*lint -e956 File scope parameters okay here. */ +static unsigned portSHORT usPortAddress = partstDEFAULT_PORT_ADDRESS; +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; +/*lint +e956 */ + + +/*----------------------------------------------------------- + * Simple parallel port IO routines + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) partstALL_OUTPUTS_OFF ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); + } +} + diff --git a/Demo/PC/RTOSDEMO.IDE b/Demo/PC/RTOSDEMO.IDE new file mode 100644 index 000000000..18c17b616 Binary files /dev/null and b/Demo/PC/RTOSDEMO.IDE differ diff --git a/Demo/PC/main.c b/Demo/PC/main.c new file mode 100644 index 000000000..59c44e8a6 --- /dev/null +++ b/Demo/PC/main.c @@ -0,0 +1,419 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/** + * Creates all the demo application tasks and co-routines, then starts the + * scheduler. + * + * Main. c also creates a task called "Print". This only executes every + * five seconds but has the highest priority so is guaranteed to get + * processor time. Its main function is to check that all the other tasks + * are still operational. Nearly all the tasks in the demo application + * maintain a unique count that is incremented each time the task successfully + * completes its function. Should any error occur within the task the count is + * permanently halted. The print task checks the count of each task to ensure + * it has changed since the last time the print task executed. If any count is + * found not to have changed the print task displays an appropriate message. + * If all the tasks are still incrementing their unique counts the print task + * displays an "OK" message. + * + * The LED flash tasks do not maintain a count as they already provide visual + * feedback of their status. + * + * The print task blocks on the queue into which messages that require + * displaying are posted. It will therefore only block for the full 5 seconds + * if no messages are posted onto the queue. + * + * Main. c also provides a demonstration of how the trace visualisation utility + * can be used, and how the scheduler can be stopped. + * + * \page MainC main.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + Prevent the call to kbhit() for debug builds as the debugger seems to + have problems stepping over the call. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.6 + + + Create new tasks as defined by the new demo application file dynamic.c. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V3.1.1 + + + The tasks defined in the new file "events.c" are now created and + monitored for errors. + +Changes from V3.2.4 + + + Now includes the flash co-routine demo rather than the flash task demo. + This is to demonstrate the co-routine functionality. +*/ + +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" +#include "partest.h" +#include "serial.h" + +/* Demo file headers. */ +#include "BlockQ.h" +#include "PollQ.h" +#include "death.h" +#include "crflash.h" +#include "flop.h" +#include "print.h" +#include "comtest.h" +#include "fileio.h" +#include "semtest.h" +#include "integer.h" +#include "dynamic.h" +#include "mevents.h" +#include "crhook.h" + +/* Priority definitions for the tasks in the demo application. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 512 ) +#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 8 ) + +/* Task function for the "Print" task as described at the top of the file. */ +static void vErrorChecks( void *pvParameters ); + +/* Function that checks the unique count of all the other tasks as described at +the top of the file. */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* Key presses can be used to start/stop the trace visualisation utility or stop +the scheduler. */ +static void prvCheckForKeyPresses( void ); + +/* Buffer used by the trace visualisation utility so only needed if the trace +being used. */ +#if configUSE_TRACE_FACILITY == 1 + static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; +#endif + +/* Constant definition used to turn on/off the pre-emptive scheduler. */ +static const portSHORT sUsingPreemption = pdTRUE; + +/* Start the math tasks appropriate to the build. The Borland port does +not yet support floating point so uses the integer equivalent. */ +static void prvStartMathTasks( void ); + +/* Check which ever tasks are relevant to this build. */ +static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +portSHORT main( void ) +{ + /* Initialise hardware and utilities. */ + vParTestInitialise(); + vPrintInitialise(); + + /* CREATE ALL THE DEMO APPLICATION TASKS. */ + prvStartMathTasks(); + vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM1, ser115200 ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + + vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartMultiEventTasks(); + + /* Create the "Print" task as described at the top of the file. */ + xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routines that communicate with the tick hook. */ + vStartHookCoRoutines(); + + /* Set the scheduler running. This function will not return unless a task + calls vTaskEndScheduler(). */ + vTaskStartScheduler(); + + return 1; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xExpectedWakeTime; +const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; +const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; +portTickType xWakeTime; +portLONG lTimeDifference; +const portCHAR *pcReceivedMessage; +const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; + + ( void ) pvParameters; + + /* Loop continuously, blocking, then checking all the other tasks are still + running, before blocking once again. This task blocks on the queue of + messages that require displaying so will wake either by its time out expiring, + or a message becoming available. */ + for( ;; ) + { + /* Calculate the time we will unblock if no messages are received + on the queue. This is used to check that we have not blocked for too long. */ + xExpectedWakeTime = xTaskGetTickCount(); + xExpectedWakeTime += xPrintRate; + + /* Block waiting for either a time out or a message to be posted that + required displaying. */ + pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); + + /* Was a message received? */ + if( pcReceivedMessage == NULL ) + { + /* A message was not received so we timed out, did we unblock at the + expected time? */ + xWakeTime = xTaskGetTickCount(); + + /* Calculate the difference between the time we unblocked and the + time we should have unblocked. */ + if( xWakeTime > xExpectedWakeTime ) + { + lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); + } + else + { + lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); + } + + if( lTimeDifference > lMaxAllowableTimeDifference ) + { + /* We blocked too long - create a message that will get + printed out the next time around. If we are not using + preemption then we won't expect the timing to be so + accurate. */ + if( sUsingPreemption == pdTRUE ) + { + vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); + } + } + + /* Check the other tasks are still running, just in case. */ + prvCheckOtherTasksAreStillRunning(); + } + else + { + /* We unblocked due to a message becoming available. Send the message + for printing. */ + vDisplayMessage( pcReceivedMessage ); + } + + /* Key presses are used to invoke the trace visualisation utility, or end + the program. */ + prvCheckForKeyPresses(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckForKeyPresses( void ) +{ +portSHORT sIn; + + taskENTER_CRITICAL(); + #ifdef DEBUG_BUILD + /* kbhit can be used in .exe's that are executed from the command + line, but not if executed through the debugger. */ + sIn = 0; + #else + sIn = kbhit(); + #endif + taskEXIT_CRITICAL(); + + if( sIn ) + { + /* Key presses can be used to start/stop the trace utility, or end the + program. */ + sIn = getch(); + switch( sIn ) + { + /* Only define keys for turning on and off the trace if the trace + is being used. */ + #if configUSE_TRACE_FACILITY == 1 + case 't' : vTaskList( pcWriteBuffer ); + vWriteMessageToDisk( pcWriteBuffer ); + break; + case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); + break; + + case 'e' : { + unsigned portLONG ulBufferLength; + ulBufferLength = ulTaskEndTrace(); + vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); + } + break; + #endif + + default : vTaskEndScheduler(); + break; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portSHORT sErrorHasOccurred = pdFALSE; + + if( prvCheckMathTasksAreStillRunning() != pdTRUE ) + { + vDisplayMessage( "Maths task count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Com test count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Blocking queues count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Polling queue count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Incorrect number of tasks running!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Semaphore take count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Dynamic priority count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreMultiEventTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in multi events tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in co-routine flash tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreHookCoRoutinesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in tick hook to co-routine communications!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( sErrorHasOccurred == pdFALSE ) + { + vDisplayMessage( "OK " ); + } +} +/*-----------------------------------------------------------*/ + +static void prvStartMathTasks( void ) +{ + #ifdef BCC_INDUSTRIAL_PC_PORT + /* The Borland project does not yet support floating point. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + #else + vStartMathTasks( tskIDLE_PRIORITY ); + #endif +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ) +{ + #ifdef BCC_INDUSTRIAL_PC_PORT + /* The Borland project does not yet support floating point. */ + return xAreIntegerMathsTaskStillRunning(); + #else + return xAreMathsTaskStillRunning(); + #endif +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + vCoRoutineSchedule(); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/PC/rtosdemo.DSW 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b/Demo/PC/serial/serial.c @@ -0,0 +1,674 @@ +/* + This serial port driver is borrowed heavily from DZComm. I have + simplified it by removing a lot of the functionality (hardware + flow control, etc.). For more details and the full version see + http://dzcomm.sourceforge.net + + + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to the more efficient portSWITCH_CONTEXT() replaces the call to + taskYIELD() in the ISR. + +Changes from V1.2.0: + + + Added vSerialPutString(). + +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes From V2.0.0 + + + Use portTickType in place of unsigned pdLONG for delay periods. + + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. +*/ + + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "semphr.h" +#include "portasm.h" + +#define serMAX_IRQs ( 16 ) +#define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 ) +#define serCOM1_STANDARD_IRQ ( ( unsigned portCHAR ) 4 ) +#define serCOM2_STANDARD_IRQ ( ( unsigned portCHAR ) 3 ) + + +#define serIMR_8259_0 ( ( unsigned portCHAR ) 0x21 ) +#define serIMR_8259_1 ( ( unsigned portCHAR ) 0xa1 ) +#define serISR_8259_0 ( ( unsigned portCHAR ) 0x20 ) +#define serISR_8259_1 ( ( unsigned portCHAR ) 0xa0 ) +#define serALL_COMS_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) +#define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) + +#define serTRANSMIT_HOLD_OFFSET ( 0 ) +#define serRECEIVE_DATA_OFFSET ( 0 ) +#define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 ) +#define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 ) +#define serINTERRUPT_ENABLE_OFFSET ( 1 ) +#define serINTERRUPT_ID_OFFSET ( 2 ) +#define serFIFO_CTRL_OFFSET ( 2 ) +#define serLINE_CTRL_OFFSET ( 3 ) +#define serMODEM_CTRL_OFFSET ( 4 ) +#define serLINE_STATUS_OFFSET ( 5 ) +#define serMODEM_STATUS_OFFSET ( 6 ) +#define serSCR_OFFSET ( 7 ) + +#define serMAX_BAUD ( ( unsigned portLONG ) 115200UL ) + +#define serNO_INTERRUPTS ( 0x00 ) + +#define vInterruptOn( pxPort, ucInterrupt ) \ +{ \ + unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ + if( !( ucIn & ucInterrupt ) ) \ + { \ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \ + } \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff( pxPort, ucInterrupt ) \ +{ \ + unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ + if( ucIn & ucInterrupt ) \ + { \ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \ + } \ +} +/*-----------------------------------------------------------*/ + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +/* This *MUST* match the order in the eBaud definition. */ +unsigned portLONG ulBaudFromEnum[] = +{ + ( unsigned portLONG ) 50, + ( unsigned portLONG ) 75, + ( unsigned portLONG ) 110, + ( unsigned portLONG ) 134, + ( unsigned portLONG ) 150, + ( unsigned portLONG ) 200, + ( unsigned portLONG ) 300, + ( unsigned portLONG ) 600, + ( unsigned portLONG ) 1200, + ( unsigned portLONG ) 1800, + ( unsigned portLONG ) 2400, + ( unsigned portLONG ) 4800, + ( unsigned portLONG ) 9600, + ( unsigned portLONG ) 19200, + ( unsigned portLONG ) 38400UL, + ( unsigned portLONG ) 57600UL, + ( unsigned portLONG ) 115200UL +}; + +typedef struct xCOM_PORT +{ + unsigned portSHORT sPort; /* comm port address eg. 0x3f8 */ + unsigned portCHAR ucIRQ; /* comm IRQ eg. 3 */ + + /* Next two fields used for setting up the IRQ routine and + * (un)masking the interrupt in certain circumstances. + */ + unsigned portSHORT usIRQVector; + unsigned portCHAR ucInterruptEnableMast; + + /* Read/Write buffers. */ + xQueueHandle xRxedChars; + xQueueHandle xCharsForTx; + + /* This lot are set up to minimise CPU time where accessing the comm + * port's registers. + */ + unsigned portSHORT usTransmitHoldReg; + unsigned portSHORT usReceiveDataRegister; + unsigned portSHORT usBaudRateDivisorLow; + unsigned portSHORT usBaudRateDivisorHigh; + unsigned portSHORT usInterruptEnableReg; + unsigned portSHORT usInterruptIDReg; + unsigned portSHORT usFIFOCtrlReg; + unsigned portSHORT usLineCtrlReg; + unsigned portSHORT usModemCtrlReg; + unsigned portSHORT usLineStatusReg; + unsigned portSHORT usModemStatusReg; + unsigned portSHORT usSCRReg; + unsigned portSHORT us8259InterruptServiceReg; + unsigned portSHORT us8259InterruptMaskReg; + + /* This semaphore does nothing useful except test a feature of the + scheduler. */ + xSemaphoreHandle xTestSem; + +} xComPort; + +typedef xComPort *xComPortHandle; + +/* A xComPort structure can be associated with each IRQ. Initially none +are create/installed. */ +xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*-----------------------------------------------------------*/ + +/* These prototypes are repeated here so we don't have to include the serial header. This allows +the xComPortHandle structure details to be private to this file. */ +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); + +static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ); +static portSHORT sComPortISR( const xComPort * const pxPort ); + +/*-----------------------------------------------------------*/ + +/* Define an interrupt handler for each slot in the xPortStatus array. */ + +#define COM_IRQ_WRAPPER(N) \ + static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ + { \ + portDISABLE_INTERRUPTS(); \ + if( sComPortISR( xPortStatus[##N##] ) ) \ + { \ + portSWITCH_CONTEXT(); \ + } \ + } + +COM_IRQ_WRAPPER( 0 ) +COM_IRQ_WRAPPER( 1 ) +COM_IRQ_WRAPPER( 2 ) +COM_IRQ_WRAPPER( 3 ) +COM_IRQ_WRAPPER( 4 ) +COM_IRQ_WRAPPER( 5 ) +COM_IRQ_WRAPPER( 6 ) +COM_IRQ_WRAPPER( 7 ) +COM_IRQ_WRAPPER( 8 ) +COM_IRQ_WRAPPER( 9 ) +COM_IRQ_WRAPPER( 10 ) +COM_IRQ_WRAPPER( 11 ) +COM_IRQ_WRAPPER( 12 ) +COM_IRQ_WRAPPER( 13 ) +COM_IRQ_WRAPPER( 14 ) +COM_IRQ_WRAPPER( 15 ) + +static pxISR xISRs[ serMAX_IRQs ] = +{ + COM_IRQ0_WRAPPER, + COM_IRQ1_WRAPPER, + COM_IRQ2_WRAPPER, + COM_IRQ3_WRAPPER, + COM_IRQ4_WRAPPER, + COM_IRQ5_WRAPPER, + COM_IRQ6_WRAPPER, + COM_IRQ7_WRAPPER, + COM_IRQ8_WRAPPER, + COM_IRQ9_WRAPPER, + COM_IRQ10_WRAPPER, + COM_IRQ11_WRAPPER, + COM_IRQ12_WRAPPER, + COM_IRQ13_WRAPPER, + COM_IRQ14_WRAPPER, + COM_IRQ15_WRAPPER +}; + +static pxISR xOldISRs[ serMAX_IRQs ] = { NULL }; + +/*-----------------------------------------------------------*/ + + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ +xComPort *pxPort; + + /* Create a structure to handle this port. */ + pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) ); + + if( pxPort != NULL ) + { + /* Create the queues used by the comtest task. */ + pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ + vSemaphoreCreateBinary( pxPort->xTestSem ); + + prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits ); + + return pxPort; + } + + return NULL; +} +/*-----------------------------------------------------------*/ + +static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ) +{ +portSHORT sIn; +unsigned portLONG ulDivisor; +unsigned portCHAR ucDivisorLow; +unsigned portCHAR ucDivisorHigh; +unsigned portCHAR ucCommParam; + + /* IRQ numbers - standard */ + if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) ) + { + pxPort->ucIRQ = serCOM1_STANDARD_IRQ; + pxPort->sPort = 0x3f8; + } + else + { + pxPort->ucIRQ = serCOM2_STANDARD_IRQ; + pxPort->sPort = 0x2f8; + } + + /* Set up variables in port making it easy to see which sIn/o address is which */ + pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET; + pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET; + pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET; + pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET; + pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET; + pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET; + pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET; + pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET; + pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET; + pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET; + pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET; + pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET; + + /* Set communication parameters. */ + ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ]; + ucDivisorLow = ( unsigned portCHAR ) ulDivisor & ( unsigned portCHAR ) 0xff; + ucDivisorHigh = ( unsigned portCHAR ) ( ( ( unsigned portSHORT ) ulDivisor >> 8 ) & 0xff ); + + switch( eWantedParity ) + { + case serNO_PARITY: ucCommParam = 0x00; + break; + case serODD_PARITY: ucCommParam = 0x08; + break; + case serEVEN_PARITY: ucCommParam = 0x18; + break; + case serMARK_PARITY: ucCommParam = 0x28; + break; + case serSPACE_PARITY: ucCommParam = 0x38; + break; + default: ucCommParam = 0x00; + break; + } + + switch ( eWantedDataBits ) + { + case serBITS_5: ucCommParam |= 0x00; + break; + case serBITS_6: ucCommParam |= 0x01; + break; + case serBITS_7: ucCommParam |= 0x02; + break; + case serBITS_8: ucCommParam |= 0x03; + break; + default: ucCommParam |= 0x03; + break; + } + + if( eWantedStopBits == serSTOP_2 ) + { + ucCommParam |= 0x04; + } + + /* Reset UART into known state - Thanks to Bradley Town */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */ + portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */ + + /* Code based on stuff from SVAsync lib. Clear UART Status and data registers + setting up FIFO if possible */ + sIn = portINPUT_BYTE( pxPort->usSCRReg ); + portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 ); + + if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 ) + { + /* The chip is better than an 8250 */ + portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */ + portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */ + + /* Try and start the FIFO. It appears that some chips need a two call + protocol, but those that don't seem to work even if you do start it twice. + The first call is simply to start it, the second starts it and sets an 8 + byte FIFO trigger level. */ + portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 ); + portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */ + portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 ); + + /* Check that the FIFO initialised */ + if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 ) + { + /* It didn't so we assume it isn't there but disable it to be on the + safe side. */ + portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe ); + } + } + + /* End of (modified) SVAsync code. + Set interrupt parameters calculating mask for 8259 controller's + IMR and number of interrupt handler for given irq level */ + if (pxPort->ucIRQ <= 7) + { + /* if 0<=irq<=7 first IMR address used */ + pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ); + pxPort->usIRQVector = pxPort->ucIRQ + 8; + pxPort->us8259InterruptMaskReg = serIMR_8259_0; + pxPort->us8259InterruptServiceReg = serISR_8259_0; + } + else + { + pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) ); + pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ; + pxPort->us8259InterruptMaskReg = serIMR_8259_1; + pxPort->us8259InterruptServiceReg = serISR_8259_1; + } + + /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers + to set baud rate */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 ); + portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow ); + portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh ); + + /* reset usLineCtrlReg and Port Toggleout */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F ); + + portENTER_CRITICAL(); + + if( xPortStatus[ pxPort->ucIRQ ] == NULL ) + { + xPortStatus[ pxPort->ucIRQ ] = pxPort; + } + + xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector ); + _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] ); + + /* enable interrupt pxPort->ucIRQ level */ + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); + + /* And allow interrupts again now the hairy bit's done */ + portEXIT_CRITICAL(); + + /* This version does not allow flow control. */ + portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS ); + + /* enable all communication's interrupts */ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS ); +} +/*-----------------------------------------------------------*/ + +static portSHORT sComPortISR( const xComPort * const pxPort ) +{ +portSHORT sInterruptID; +portCHAR cIn, cOut; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; + + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) ); + + /* Decide which UART has issued the interrupt */ + sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ); + + /* service whatever requests the calling UART may have. The top 4 bits are + either unused or indicate the presence of a functioning FIFO, which we don't + need to know. So trim them off to simplify the switch statement below. */ + sInterruptID &= 0x0f; + do + { + switch( sInterruptID ) + { + case 0x0c: /* Timeout + Called when FIFO not up to trigger level but no activity for + a while. Handled exactly as RDAINT, see below for + description. */ + do + { + cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. */ + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); + break; + + case 0x06: /* LSINT */ + portINPUT_BYTE( pxPort->usLineStatusReg ); + break; + + case 0x04: /* RDAINT */ + /* The usInterruptIDReg flag tested above stops when the + FIFO is below the trigger level rather than empty, whereas + this flag allows one to empty it: (do loop because there + must be at least one to read by virtue of having got here.) */ + do + { + cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. */ + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); + break; + + case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */ + if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xTaskWokenByTx ) != pdTRUE ) + { + /* Queue empty, nothing to send */ + vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT); + } + else + { + portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( portSHORT ) cOut ); + } + break; + + case 0x00: /* MSINT */ + portINPUT_BYTE( pxPort->usModemStatusReg ); + break; + } + + /* Get the next instruction, trimming as above */ + sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f; + + } while( !( sInterruptID & 0x01 ) ); + + if( pxPort->ucIRQ > 7 ) + { + portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) ); + portOUTPUT_BYTE( 0x20, 0x62); + } + else + { + portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ ); + } + + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); + + /* If posting any of the characters to a queue woke a task that was blocked on + the queue we may want to return to the task just woken (depending on its + priority relative to the task this ISR interrupted. */ + if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer, note that this routine is only + called having checked that the is (at least) one to get */ + if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +portCHAR * pcNextChar; +const portTickType xNoBlock = ( portTickType ) 0; + + /* Stop warnings. */ + ( void ) usStringLength; + + pcNextChar = ( portCHAR * ) pcString; + while( *pcNextChar ) + { + xSerialPutChar( pxPort, *pcNextChar, xNoBlock ); + pcNextChar++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) +{ +const portTickType xBlockTime = ( portTickType ) 0xffff; + + /* This function does nothing interesting, but test the + semaphore from ISR mechanism. */ + return xSemaphoreTake( xPort->xTestSem, xBlockTime ); +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + portENTER_CRITICAL(); + + /* Turn off the interrupts. */ + portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS ); + portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS ); + + /* Put back the original ISR. */ + _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] ); + + /* Remove the reference in the array of xComPort structures. */ + xPortStatus[ xPort->ucIRQ ] = NULL; + + /* Delete the queues. */ + vQueueDelete( xPort->xRxedChars ); + vQueueDelete( xPort->xCharsForTx ); + + vPortFree( ( void * ) xPort ); + + portEXIT_CRITICAL(); +} + diff --git a/Demo/PIC18_MPLAB/18f452.lkr b/Demo/PIC18_MPLAB/18f452.lkr new file mode 100644 index 000000000..3e844289c --- /dev/null +++ b/Demo/PIC18_MPLAB/18f452.lkr @@ -0,0 +1,24 @@ +// $Id: 18f452.lkr,v 1.4 2003/03/13 05:02:23 sealep Exp $ +// File: 18f452.lkr +// Sample linker script for the PIC18F452 processor + +LIBPATH . + +FILES c018i.o +FILES clib.lib +FILES p18f452.lib + +CODEPAGE NAME=vectors START=0x0 END=0x39 PROTECTED +CODEPAGE NAME=page START=0x3A END=0x7FFF +CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED +CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED +CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED +CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED + +ACCESSBANK NAME=accessram START=0x0 END=0x7F +DATABANK NAME=BIG_BLOCK START=0x80 END=0x5FF +ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED + +SECTION NAME=CONFIG ROM=config + +STACK SIZE=0x60 RAM=BIG_BLOCK diff --git a/Demo/PIC18_MPLAB/FreeRTOSConfig.h b/Demo/PIC18_MPLAB/FreeRTOSConfig.h new file mode 100644 index 000000000..0192466ed --- /dev/null +++ b/Demo/PIC18_MPLAB/FreeRTOSConfig.h @@ -0,0 +1,77 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( 105 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 1024 ) +#define configMAX_TASK_NAME_LEN ( 4 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_MPLAB/ParTest/ParTest.c b/Demo/PIC18_MPLAB/ParTest/ParTest.c new file mode 100644 index 000000000..e8a77585a --- /dev/null +++ b/Demo/PIC18_MPLAB/ParTest/ParTest.c @@ -0,0 +1,123 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the FED 40pin demo board. + * The four LED's are connected to D4 to D7. + *-----------------------------------------------------------*/ + +#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) +#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) +#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) + +#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Set the top four bits of port D to output. */ + TRISDbits.TRISD7 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD6 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD5 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD4 = partstBIT_AS_OUTPUT; + + /* Start with all bits off. */ + PORTDbits.RD7 = partstCLEAR_OUTPUT; + PORTDbits.RD6 = partstCLEAR_OUTPUT; + PORTDbits.RD5 = partstCLEAR_OUTPUT; + PORTDbits.RD4 = partstCLEAR_OUTPUT; + + /* Enable the driver. */ + ADCON1 = partstENABLE_GENERAL_IO; + TRISEbits.TRISE2 = partstBIT_AS_OUTPUT; + PORTEbits.RE2 = partstSET_OUTPUT; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 3 : PORTDbits.RD7 = ( portSHORT ) xValue; + break; + case 2 : PORTDbits.RD6 = ( portSHORT ) xValue; + break; + case 1 : PORTDbits.RD5 = ( portSHORT ) xValue; + break; + case 0 : PORTDbits.RD4 = ( portSHORT ) xValue; + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 3 : PORTDbits.RD7 = !( PORTDbits.RD7 ); + break; + case 2 : PORTDbits.RD6 = !( PORTDbits.RD6 ); + break; + case 1 : PORTDbits.RD5 = !( PORTDbits.RD5 ); + break; + case 0 : PORTDbits.RD4 = !( PORTDbits.RD4 ); + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} + + + diff --git a/Demo/PIC18_MPLAB/main1.c b/Demo/PIC18_MPLAB/main1.c new file mode 100644 index 000000000..c88855aae --- /dev/null +++ b/Demo/PIC18_MPLAB/main1.c @@ -0,0 +1,186 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the first. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo1 project is configured for a PIC18F452 device. Main1.c starts 5 + * tasks (including the idle task). + * + * The first task runs at the idle priority. It repeatedly performs a 32bit + * calculation and checks it's result against the expected value. This checks + * that the temporary storage utilised by the compiler to hold intermediate + * results does not get corrupted when the task gets switched in and out. See + * demo/common/minimal/integer.c for more information. + * + * The second and third tasks pass an incrementing value between each other on + * a message queue. See demo/common/minimal/PollQ.c for more information. + * + * Main1.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report and error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "pollq.h" +#include "integer.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* The LED that is flashed by the check task. */ +#define mainCHECK_TASK_LED ( 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + vPortInitialiseBlocks(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portBASE_TYPE xErrorOccurred; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks. */ + vTaskDelay( xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + xErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( xErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + return xErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_MPLAB/main2.c b/Demo/PIC18_MPLAB/main2.c new file mode 100644 index 000000000..89d5c18c2 --- /dev/null +++ b/Demo/PIC18_MPLAB/main2.c @@ -0,0 +1,161 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the second. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo2 project is configured for a PIC18F452 device. Main2.c starts + * 5 tasks (including the idle task). + * + * The first, second and third tasks do nothing but flash an LED. This gives + * visual feedback that everything is executing as expected. One task flashes + * an LED every 333ms (i.e. on and off every 333/2 ms), then next every 666ms + * and the last every 999ms. + * + * The last task runs at the idle priority. It repeatedly performs a 32bit + * calculation and checks it's result against the expected value. This checks + * that the temporary storage utilised by the compiler to hold intermediate + * results does not get corrupted when the task gets switched in and out. + * should the calculation ever provide an incorrect result the final LED is + * turned on. + * + * On entry to main() an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* Priority definitions for the LED tasks. Other tasks just use the idle +priority. */ +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 1 ) + +/* The LED that is lit when should the calculation fail. */ +#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 3 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) + +/* + * The task that performs the 32 bit calculation at the idle priority. + */ +static void vCalculationTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + vPortInitialiseBlocks(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard LED flash tasks as defined in demo/common/minimal. */ + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vCalculationTask, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vCalculationTask( void *pvParameters ) +{ +volatile unsigned long ulCalculatedValue; /* Volatile to ensure optimisation is minimal. */ + + /* Continuously perform a calculation. If the calculation result is ever + incorrect turn the LED on. */ + for( ;; ) + { + /* A good optimising compiler would just remove all this! */ + ulCalculatedValue = 1234UL; + ulCalculatedValue *= 99UL; + + if( ulCalculatedValue != 122166UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue *= 9876UL; + + if( ulCalculatedValue != 1206511416UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue /= 15UL; + + if( ulCalculatedValue != 80434094UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue += 918273UL; + + if( ulCalculatedValue != 81352367UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/PIC18_MPLAB/main3.c b/Demo/PIC18_MPLAB/main3.c new file mode 100644 index 000000000..50cf5ed20 --- /dev/null +++ b/Demo/PIC18_MPLAB/main3.c @@ -0,0 +1,190 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * THIS DEMO APPLICATION REQUIRES A LOOPBACK CONNECTOR TO BE FITTED TO THE PIC + * USART PORT - connect pin 2 to pin 3 on J2. + * + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the third. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo3 project is configured for a PIC18F452 device. Main3.c starts + * 5 tasks (including the idle task). + * + * The first task repeatedly transmits a string of characters on the PIC USART + * port. The second task receives the characters, checking that the correct + * sequence is maintained (i.e. what is transmitted is identical to that + * received). Each transmitted and each received character causes an LED to + * flash. See demo/common/minimal/comtest. c for more information. + * + * The third task continuously performs a 32 bit calculation. This is a good + * test of the context switch mechanism as the 8 bit architecture requires + * the use of several file registers to perform the 32 bit operations. See + * demo/common/minimal/integer. c for more information. + * + * The third task is the check task. This periodically checks that the other + * tasks are still running and have not experienced any errors. If no errors + * have been reported by either the comms or integer tasks an LED is flashed + * with a frequency mainNO_ERROR_CHECK_PERIOD. If an error is discovered the + * frequency is increased to mainERROR_FLASH_RATE. + * + * The check task also provides a visual indication of a system reset by + * flashing the one remaining LED (mainRESET_LED) when it starts. After + * this initial flash mainRESET_LED should remain off. + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "partest.h" +#include "serial.h" +#include "comtest.h" +#include "integer.h" + +/* Priority definitions for the LED tasks. Other tasks just use the idle +priority. */ +#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 3 ) + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* The period for which mainRESET_LED remain on every reset. */ +#define mainRESET_LED_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The LED that is toggled whenever a character is transmitted. +mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ +#define mainCOMM_TX_RX_LED ( ( unsigned portBASE_TYPE ) 2 ) + +/* The LED that is flashed by the check task at a rate that indicates the +error status. */ +#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 1 ) + +/* The LED that is flashed once upon every reset. */ +#define mainRESET_LED ( ( unsigned portBASE_TYPE ) 0 ) + +/* Constants required for the communications. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) +/*-----------------------------------------------------------*/ + +/* + * Task function which periodically checks the other tasks for errors. Flashes + * an LED at a rate that indicates whether an error has ever been detected. + */ +static void vErrorChecks( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Initialise the block memory allocator. */ + vPortInitialiseBlocks(); + + /* Start the standard comtest tasks as defined in demo/common/minimal. */ + vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); + + /* Start the standard 32bit calculation task as defined in + demo/common/minimal. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. This will never return. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +volatile unsigned portLONG ulDummy = 3UL; + + /* Toggle the LED so we can see when a reset occurs. */ + vParTestSetLED( mainRESET_LED, pdTRUE ); + vTaskDelay( mainRESET_LED_PERIOD ); + vParTestSetLED( mainRESET_LED, pdFALSE ); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks. */ + vTaskDelay( xDelayTime ); + + /* Perform an integer calculation - just to ensure the registers + get used. The result is not important. */ + ulDummy *= 3UL; + + /* Check all the other tasks are running, and running without ever + having an error. The delay period is lowered if an error is reported, + causing the LED to flash at a higher rate. */ + if( xAreIntegerMathsTaskStillRunning() == pdFALSE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + if( xAreComTestTasksStillRunning() == pdFALSE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. The rate of the flash will + indicate the health of the system. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/PIC18_MPLAB/makebin1.bat b/Demo/PIC18_MPLAB/makebin1.bat new file mode 100644 index 000000000..2e9132f61 --- /dev/null +++ b/Demo/PIC18_MPLAB/makebin1.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo1.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/makebin2.bat b/Demo/PIC18_MPLAB/makebin2.bat new file mode 100644 index 000000000..9c4a7e56e --- /dev/null +++ b/Demo/PIC18_MPLAB/makebin2.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo2.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/makebin3.bat b/Demo/PIC18_MPLAB/makebin3.bat new file mode 100644 index 000000000..57db0de0e --- /dev/null +++ b/Demo/PIC18_MPLAB/makebin3.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo3.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/readme.txt b/Demo/PIC18_MPLAB/readme.txt new file mode 100644 index 000000000..a46af4d5d --- /dev/null +++ b/Demo/PIC18_MPLAB/readme.txt @@ -0,0 +1,12 @@ +Unfortunately the project files: + +RTOSDemo1.mcp +RTOSDemo2.mcp +and RTOSDemo3.mcp + +contain absolute paths. I don't know how to get around this, so if somebody knows, let me know! + +Edit the paths in a text editor before use. + +See the PIC port section of www.FreeRTOS.org for more information. + diff --git a/Demo/PIC18_MPLAB/rtosdemo.mcw b/Demo/PIC18_MPLAB/rtosdemo.mcw new file mode 100644 index 000000000..1b81b6c19 Binary files /dev/null and b/Demo/PIC18_MPLAB/rtosdemo.mcw differ diff --git a/Demo/PIC18_MPLAB/rtosdemo1.mcp b/Demo/PIC18_MPLAB/rtosdemo1.mcp new file mode 100644 index 000000000..3d84a0562 --- /dev/null +++ b/Demo/PIC18_MPLAB/rtosdemo1.mcp @@ -0,0 +1,72 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +[PATH_INFO] +dir_src= +dir_bin= +dir_tmp= +dir_sin= +dir_inc=D:\DevTools\mcc18\h;e:\dev\freertos\demo\common\include;e:\dev\freertos\source\include;e:\dev\freertos\source\portable\mplab\PIC18F;e:\dev\freertos\demo\PIC18_MPLAB +dir_lib=D:\DevTools\mcc18\lib +dir_lkr= +[CAT_FILTERS] +filter_src=*.asm;*.c +filter_inc=*.h;*.inc +filter_obj=*.o +filter_lib=*.lib +filter_lkr=*.lkr +[OTHER_FILES] +file_000=no +file_001=no +file_002=no +file_003=no +file_004=no +file_005=no +file_006=no +file_007=no +file_008=no +file_009=no +file_010=no +file_011=no +file_012=no +file_013=no +file_014=no +file_015=no +file_016=no +file_017=no +file_018=no +file_019=no +file_020=no +[FILE_INFO] +file_000=E:\Dev\FreeRTOS\Source\tasks.c +file_001=E:\Dev\FreeRTOS\Source\queue.c +file_002=E:\Dev\FreeRTOS\Source\list.c +file_003=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\port.c +file_004=E:\Dev\FreeRTOS\Demo\Common\Minimal\PollQ.c +file_005=main1.c +file_006=ParTest\ParTest.c +file_007=serial\serial.c +file_008=E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c +file_009=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c +file_010=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\portmacro.h +file_011=E:\Dev\FreeRTOS\Source\include\task.h +file_012=E:\Dev\FreeRTOS\Source\include\list.h +file_013=E:\Dev\FreeRTOS\Source\include\portable.h +file_014=E:\Dev\FreeRTOS\Source\include\projdefs.h +file_015=E:\Dev\FreeRTOS\Source\include\queue.h +file_016=E:\Dev\FreeRTOS\Demo\Common\include\integer.h +file_017=E:\Dev\FreeRTOS\Demo\Common\include\PollQ.h +file_018=E:\Dev\FreeRTOS\Demo\Common\include\serial.h +file_019=FreeRTOSConfig.h +file_020=18f452.lkr +[SUITE_INFO] +suite_guid={5B7D72DD-9861-47BD-9F60-2BE967BF8416} +suite_state= +[TOOL_SETTINGS] +TS{DD2213A8-6310-47B1-8376-9430CDFC013F}=/aINHX8M +TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/m"$(BINDIR_)$(TARGETBASE).map" /aINHX8M /o"$(TARGETBASE).cof" +TS{C2AF05E7-1416-4625-923D-E114DB6E2B96}=-w3 -DMPLAB_PIC18F_PORT -Ls -Opa- -nw 2074 -nw 2066 +TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}= +[TOOL_LOC_STAMPS] +tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=D:\DevTools\mcc18\bin\mplink.exe +tool_loc{E56A1C86-9D32-4DF6-8C34-FE0388B1B644}=D:\DevTools\mcc18\bin\mcc18.exe diff --git a/Demo/PIC18_MPLAB/rtosdemo2.mcp b/Demo/PIC18_MPLAB/rtosdemo2.mcp new file mode 100644 index 000000000..bbc543a0d --- /dev/null +++ b/Demo/PIC18_MPLAB/rtosdemo2.mcp @@ -0,0 +1,68 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +[PATH_INFO] +dir_src= +dir_bin= +dir_tmp= +dir_sin= +dir_inc=D:\DevTools\mcc18\h;e:\dev\freertos\demo\common\include;e:\dev\freertos\source\include;e:\dev\freertos\source\portable\mplab\PIC18F;e:\dev\freertos\demo\PIC18_MPLAB +dir_lib=D:\DevTools\mcc18\lib +dir_lkr= +[CAT_FILTERS] +filter_src=*.asm;*.c +filter_inc=*.h;*.inc +filter_obj=*.o +filter_lib=*.lib +filter_lkr=*.lkr +[OTHER_FILES] +file_000=no +file_001=no +file_002=no +file_003=no +file_004=no +file_005=no +file_006=no +file_007=no +file_008=no +file_009=no +file_010=no +file_011=no +file_012=no +file_013=no +file_014=no +file_015=no +file_016=no +file_017=no +file_018=no +[FILE_INFO] +file_000=main2.c +file_001=serial\serial.c +file_002=ParTest\ParTest.c +file_003=E:\Dev\FreeRTOS\Source\tasks.c +file_004=E:\Dev\FreeRTOS\Source\queue.c +file_005=E:\Dev\FreeRTOS\Source\list.c +file_006=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c +file_007=E:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c +file_008=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\port.c +file_009=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\portmacro.h +file_010=E:\Dev\FreeRTOS\Source\include\task.h +file_011=E:\Dev\FreeRTOS\Source\include\list.h +file_012=E:\Dev\FreeRTOS\Source\include\portable.h +file_013=E:\Dev\FreeRTOS\Source\include\projdefs.h +file_014=E:\Dev\FreeRTOS\Source\include\queue.h +file_015=E:\Dev\FreeRTOS\Demo\Common\include\serial.h +file_016=E:\Dev\FreeRTOS\Demo\Common\include\flash.h +file_017=FreeRTOSConfig.h +file_018=18f452.lkr +[SUITE_INFO] +suite_guid={5B7D72DD-9861-47BD-9F60-2BE967BF8416} +suite_state= +[TOOL_SETTINGS] +TS{DD2213A8-6310-47B1-8376-9430CDFC013F}=/aINHX8M +TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/m"$(BINDIR_)$(TARGETBASE).map" /aINHX8M /o"$(TARGETBASE).cof" +TS{C2AF05E7-1416-4625-923D-E114DB6E2B96}=-DMPLAB_PIC18F_PORT -Ls -Opa- -nw 2074 -nw 2066 +TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}= +[TOOL_LOC_STAMPS] +tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=D:\DevTools\mcc18\bin\mplink.exe +tool_loc{E56A1C86-9D32-4DF6-8C34-FE0388B1B644}=D:\DevTools\mcc18\bin\mcc18.exe diff --git a/Demo/PIC18_MPLAB/rtosdemo3.mcp b/Demo/PIC18_MPLAB/rtosdemo3.mcp new file mode 100644 index 000000000..0b6b8de04 --- /dev/null +++ b/Demo/PIC18_MPLAB/rtosdemo3.mcp @@ -0,0 +1,70 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +[PATH_INFO] +dir_src= +dir_bin= +dir_tmp= +dir_sin= +dir_inc=D:\DevTools\mcc18\h;e:\dev\freertos\demo\common\include;e:\dev\freertos\source\include;e:\dev\freertos\source\portable\mplab\PIC18F;e:\dev\freertos\demo\PIC18_MPLAB +dir_lib=D:\DevTools\mcc18\lib +dir_lkr= +[CAT_FILTERS] +filter_src=*.asm;*.c +filter_inc=*.h;*.inc +filter_obj=*.o +filter_lib=*.lib +filter_lkr=*.lkr +[OTHER_FILES] +file_000=no +file_001=no +file_002=no +file_003=no +file_004=no +file_005=no +file_006=no +file_007=no +file_008=no +file_009=no +file_010=no +file_011=no +file_012=no +file_013=no +file_014=no +file_015=no +file_016=no +file_017=no +file_018=no +file_019=no +[FILE_INFO] +file_000=E:\Dev\FreeRTOS\Source\tasks.c +file_001=E:\Dev\FreeRTOS\Source\queue.c +file_002=E:\Dev\FreeRTOS\Source\list.c +file_003=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\port.c +file_004=serial\serial.c +file_005=main3.c +file_006=E:\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c +file_007=E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c +file_008=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c +file_009=ParTest\ParTest.c +file_010=E:\Dev\FreeRTOS\Source\portable\MPLAB\PIC18F\portmacro.h +file_011=E:\Dev\FreeRTOS\Source\include\task.h +file_012=E:\Dev\FreeRTOS\Source\include\list.h +file_013=E:\Dev\FreeRTOS\Source\include\portable.h +file_014=E:\Dev\FreeRTOS\Source\include\projdefs.h +file_015=E:\Dev\FreeRTOS\Source\include\queue.h +file_016=E:\Dev\FreeRTOS\Demo\Common\include\serial.h +file_017=E:\Dev\FreeRTOS\Demo\Common\include\comtest.h +file_018=FreeRTOSConfig.h +file_019=18f452.lkr +[SUITE_INFO] +suite_guid={5B7D72DD-9861-47BD-9F60-2BE967BF8416} +suite_state= +[TOOL_SETTINGS] +TS{DD2213A8-6310-47B1-8376-9430CDFC013F}=/aINHX8M +TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/m"$(BINDIR_)$(TARGETBASE).map" /aINHX8M /o"$(TARGETBASE).cof" +TS{C2AF05E7-1416-4625-923D-E114DB6E2B96}=-DMPLAB_PIC18F_PORT -Ls -Ou- -Ot- -Ob- -Op- -Or- -Od- -Opa- -nw 2074 -nw 2066 +TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}= +[TOOL_LOC_STAMPS] +tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=D:\DevTools\mcc18\bin\mplink.exe +tool_loc{E56A1C86-9D32-4DF6-8C34-FE0388B1B644}=D:\DevTools\mcc18\bin\mcc18.exe diff --git a/Demo/PIC18_MPLAB/serial/serial.c b/Demo/PIC18_MPLAB/serial/serial.c new file mode 100644 index 000000000..ad7f556ea --- /dev/null +++ b/Demo/PIC18_MPLAB/serial/serial.c @@ -0,0 +1,228 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.5 + + + Clear overrun errors in the Rx ISR. Overrun errors prevent any further + characters being received. + +Changes from V2.0.0 + + + Use portTickType in place of unsigned pdLONG for delay periods. + + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ + +/* Scheduler header files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "serial.h" +#include "queue.h" + +/* + * Prototypes for ISR's. The PIC architecture means that these functions + * have to be called from port.c. The prototypes are not however included + * in the header as the header is common to all ports. + */ +void vSerialTxISR( void ); +void vSerialRxISR( void ); + +/* Hardware pin definitions. */ +#define serTX_PIN TRISCbits.TRISC6 +#define serRX_PIN TRISCbits.TRISC7 + +/* Bit/register definitions. */ +#define serINPUT ( 1 ) +#define serOUTPUT ( 0 ) +#define serTX_ENABLE ( ( unsigned portSHORT ) 1 ) +#define serRX_ENABLE ( ( unsigned portSHORT ) 1 ) +#define serHIGH_SPEED ( ( unsigned portSHORT ) 1 ) +#define serCONTINUOUS_RX ( ( unsigned portSHORT ) 1 ) +#define serCLEAR_OVERRUN ( ( unsigned portSHORT ) 0 ) +#define serINTERRUPT_ENABLED ( ( unsigned portSHORT ) 1 ) +#define serINTERRUPT_DISABLED ( ( unsigned portSHORT ) 0 ) + +/* All ISR's use the PIC18 low priority interrupt. */ +#define serLOW_PRIORITY ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues to interface between comms API and interrupt routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulBaud; + + /* Calculate the baud rate generator constant. + SPBRG = ( (FOSC / Desired Baud Rate) / 16 ) - 1 */ + ulBaud = configCPU_CLOCK_HZ / ulWantedBaud; + ulBaud /= ( unsigned portLONG ) 16; + ulBaud -= ( unsigned portLONG ) 1; + + /* Create the queues used by the ISR's to interface to tasks. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + portENTER_CRITICAL(); + { + /* Start with config registers cleared, so we can just set the wanted + bits. */ + TXSTA = ( unsigned portSHORT ) 0; + RCSTA = ( unsigned portSHORT ) 0; + + /* Set the baud rate generator using the above calculated constant. */ + SPBRG = ( unsigned portCHAR ) ulBaud; + + /* Setup the IO pins to enable the USART IO. */ + serTX_PIN = serOUTPUT; + serRX_PIN = serINPUT; + + /* Set the serial interrupts to use the same priority as the tick. */ + IPR1bits.TXIP = serLOW_PRIORITY; + IPR1bits.RCIP = serLOW_PRIORITY; + + /* Setup Tx configuration. */ + TXSTAbits.BRGH = serHIGH_SPEED; + TXSTAbits.TXEN = serTX_ENABLE; + + /* Setup Rx configuration. */ + RCSTAbits.SPEN = serRX_ENABLE; + RCSTAbits.CREN = serCONTINUOUS_RX; + + /* Enable the Rx interrupt now, the Tx interrupt will get enabled when + we have data to send. */ + PIE1bits.RCIE = serINTERRUPT_ENABLED; + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and + can instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ + /* This is not implemented in this port. + Use xSerialPortInitMinimal() instead. */ +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn interrupt on - ensure the compiler only generates a single + instruction for this. */ + PIE1bits.TXIE = serINTERRUPT_ENABLED; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not implemented for this port. + To implement, turn off the interrupts and delete the memory + allocated to the queues. */ +} +/*-----------------------------------------------------------*/ + +#pragma interruptlow vSerialRxISR save=PRODH, PRODL, TABLAT, section(".tmpdata") +void vSerialRxISR( void ) +{ +portCHAR cChar; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = RCREG; + + /* Clear any overrun errors. */ + if( RCSTAbits.OERR ) + { + RCSTAbits.CREN = serCLEAR_OVERRUN; + RCSTAbits.CREN = serCONTINUOUS_RX; + } + + if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +#pragma interruptlow vSerialTxISR save=PRODH, PRODL, TABLAT, section(".tmpdata") +void vSerialTxISR( void ) +{ +portCHAR cChar, cTaskWoken; + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + TXREG = cChar; + } + else + { + /* Queue empty, nothing to send. */ + PIE1bits.TXIE = serINTERRUPT_DISABLED; + } +} + + + diff --git a/Demo/PIC18_WizC/Demo1/Demo1.PC b/Demo/PIC18_WizC/Demo1/Demo1.PC new file mode 100644 index 000000000..7dc2e20ac --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/Demo1.PC @@ -0,0 +1,557 @@ +[F29746990] +x=0 +y=122 +[F10478061] +x=0 +y=48 +[F15207742] +x=0 +y=48 +[F20376480] +x=0 +y=1332 +[F29843090] +x=5 +y=23 +[F20121086] +x=0 +y=84 +[F29765107] +x=31 +y=45 +[F29843242] +x=13 +y=8 +[F20539803] +x=0 +y=266 +[F15568046] +x=1 +y=293 +[F20441499] +x=0 +y=105 +[F20558577] +x=0 +y=4714 +[F20528681] +x=0 +y=44 +[ProjectGroup] +nFiles=1 +FileName0=Demo1.PC +[Project] +nFiles=3 +UseAD=0 +CompatOpts=0 +AutoHead= +IdentifierPrint=0 +TreePrint=0 +StatementResultPrint=0 +SourcePrint=0 +spoPrint=0 +AsmPrint=0 +CaseSens=1 +Optimise=45 +AProcFreq=40000000 +LOptBytes=16 +LOptBytesReg=6 +TopROM=32767 +StackPointer=3839 +HeapPointer=3584 +HasDoneOptionDialog=1 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FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 1 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 0 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo1/MallocConfig.h b/Demo/PIC18_WizC/Demo1/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo1/WIZCmake.h b/Demo/PIC18_WizC/Demo1/WIZCmake.h new file mode 100644 index 000000000..5c5f91360 --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/WIZCmake.h @@ -0,0 +1,50 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif diff --git a/Demo/PIC18_WizC/Demo1/fuses.c b/Demo/PIC18_WizC/Demo1/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo1/interrupt.c b/Demo/PIC18_WizC/Demo1/interrupt.c new file mode 100644 index 000000000..babecb028 --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/interrupt.c @@ -0,0 +1,109 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo1/main.c b/Demo/PIC18_WizC/Demo1/main.c new file mode 100644 index 000000000..33bc92785 --- /dev/null +++ b/Demo/PIC18_WizC/Demo1/main.c @@ -0,0 +1,202 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the first. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo1 project is configured for a PIC18F4620 device. Main.c starts 9 + * tasks (including the idle task). + + * This first demo is included to do a quick check on the FreeRTOS + * installation. It is also included to demonstrate a minimal project-setup + * to use FreeRTOS in a wizC environment. + * + * Eight independant tasks are created. All tasks share the same taskcode. + * Each task blinks a different led on portB. The blinkrate for each task + * is different, but chosen in such a way that portB will show a binary + * counter pattern. All blinkrates are derived from a single master-rate. + * By default, this masterrate is set to 100 milliseconds. Although such + * a low value will make it almost impossible to see some of the leds + * actually blink, it is a good value when using the wizC-simulator. + * When testing on a real chip, changing the value to eg. 500 milliseconds + * would be appropiate. + */ + +/* Scheduler include files. */ +#include +#include + +#define mainBLINK_LED_INTERVAL ( ( portTickType ) 100 / ( portTICK_RATE_MS ) ) + +/* The LED that is flashed by the B0 task. */ +#define mainBLINK_LED0_PORT LATD +#define mainBLINK_LED0_TRIS TRISD +#define mainBLINK_LED0_PIN 0 +#define mainBLINK_LED0_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED0_PIN)) + +/* The LED that is flashed by the B1 task. */ +#define mainBLINK_LED1_PORT LATD +#define mainBLINK_LED1_TRIS TRISD +#define mainBLINK_LED1_PIN 1 +#define mainBLINK_LED1_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED1_PIN)) + +/* The LED that is flashed by the B2 task. */ +#define mainBLINK_LED2_PORT LATD +#define mainBLINK_LED2_TRIS TRISD +#define mainBLINK_LED2_PIN 2 +#define mainBLINK_LED2_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED2_PIN)) + +/* The LED that is flashed by the B3 task. */ +#define mainBLINK_LED3_PORT LATD +#define mainBLINK_LED3_TRIS TRISD +#define mainBLINK_LED3_PIN 3 +#define mainBLINK_LED3_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED3_PIN)) + +/* The LED that is flashed by the B4 task. */ +#define mainBLINK_LED4_PORT LATD +#define mainBLINK_LED4_TRIS TRISD +#define mainBLINK_LED4_PIN 4 +#define mainBLINK_LED4_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED4_PIN)) + +/* The LED that is flashed by the B5 task. */ +#define mainBLINK_LED5_PORT LATD +#define mainBLINK_LED5_TRIS TRISD +#define mainBLINK_LED5_PIN 5 +#define mainBLINK_LED5_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED5_PIN)) + +/* The LED that is flashed by the B6 task. */ +#define mainBLINK_LED6_PORT LATD +#define mainBLINK_LED6_TRIS TRISD +#define mainBLINK_LED6_PIN 6 +#define mainBLINK_LED6_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED6_PIN)) + +/* The LED that is flashed by the B7 task. */ +#define mainBLINK_LED7_PORT LATD +#define mainBLINK_LED7_TRIS TRISD +#define mainBLINK_LED7_PIN 7 +#define mainBLINK_LED7_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED7_PIN)) + +typedef struct { + unsigned char *port; + unsigned char *tris; + unsigned char pin; + portTickType interval; +} SBLINK; + +const SBLINK sled0 = {&mainBLINK_LED0_PORT, &mainBLINK_LED0_TRIS, mainBLINK_LED0_PIN, mainBLINK_LED0_INTERVAL}; +const SBLINK sled1 = {&mainBLINK_LED1_PORT, &mainBLINK_LED1_TRIS, mainBLINK_LED1_PIN, mainBLINK_LED1_INTERVAL}; +const SBLINK sled2 = {&mainBLINK_LED2_PORT, &mainBLINK_LED2_TRIS, mainBLINK_LED2_PIN, mainBLINK_LED2_INTERVAL}; +const SBLINK sled3 = {&mainBLINK_LED3_PORT, &mainBLINK_LED3_TRIS, mainBLINK_LED3_PIN, mainBLINK_LED3_INTERVAL}; +const SBLINK sled4 = {&mainBLINK_LED4_PORT, &mainBLINK_LED4_TRIS, mainBLINK_LED4_PIN, mainBLINK_LED4_INTERVAL}; +const SBLINK sled5 = {&mainBLINK_LED5_PORT, &mainBLINK_LED5_TRIS, mainBLINK_LED5_PIN, mainBLINK_LED5_INTERVAL}; +const SBLINK sled6 = {&mainBLINK_LED6_PORT, &mainBLINK_LED6_TRIS, mainBLINK_LED6_PIN, mainBLINK_LED6_INTERVAL}; +const SBLINK sled7 = {&mainBLINK_LED7_PORT, &mainBLINK_LED7_TRIS, mainBLINK_LED7_PIN, mainBLINK_LED7_INTERVAL}; + +/* + * The task code for the "vBlink" task. + */ +static portTASK_FUNCTION_PROTO(vBlink, pvParameters); + +/*-----------------------------------------------------------*/ + +/* + * Creates the tasks, then starts the scheduler. + */ +void main( void ) +{ + /* + * Start the blink tasks defined in this file. + */ + xTaskCreate( vBlink, "B0", configMINIMAL_STACK_SIZE, &sled0, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B1", configMINIMAL_STACK_SIZE, &sled1, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B2", configMINIMAL_STACK_SIZE, &sled2, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B3", configMINIMAL_STACK_SIZE, &sled3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B4", configMINIMAL_STACK_SIZE, &sled4, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B5", configMINIMAL_STACK_SIZE, &sled5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B6", configMINIMAL_STACK_SIZE, &sled6, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B7", configMINIMAL_STACK_SIZE, &sled7, tskIDLE_PRIORITY, NULL ); + + /* + * Start the scheduler. + */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION(vBlink, pvParameters) +{ + unsigned char *Port = ((SBLINK *)pvParameters)->port; + unsigned char *Tris = ((SBLINK *)pvParameters)->tris; + unsigned char Pin = ((SBLINK *)pvParameters)->pin; + portTickType Interval = ((SBLINK *)pvParameters)->interval; + + portTickType xLastWakeTime; + + /* + * Initialize the hardware + */ + *Tris &= ~(1< diff --git a/Demo/PIC18_WizC/Demo2/fuses.c b/Demo/PIC18_WizC/Demo2/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo2/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo2/interrupt.c b/Demo/PIC18_WizC/Demo2/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo2/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo2/main.c b/Demo/PIC18_WizC/Demo2/main.c new file mode 100644 index 000000000..1321306dd --- /dev/null +++ b/Demo/PIC18_WizC/Demo2/main.c @@ -0,0 +1,198 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the second. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo2 project is configured for a PIC18F4620 device. Main.c starts 12 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/PollQ.c: Creates 2 tasks + * demo/common/minimal/semtest.c: Creates 4 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "pollq.h" +#include "semtest.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/Demo3/Demo3.PC b/Demo/PIC18_WizC/Demo3/Demo3.PC new file mode 100644 index 000000000..1fed171da --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/Demo3.PC @@ -0,0 +1,503 @@ +[F29011781] +x=0 +y=118 +[F29216334] +x=0 +y=189 +[F15207742] +x=0 +y=48 +[F28413281] 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later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 0 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo3/MallocConfig.h b/Demo/PIC18_WizC/Demo3/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo3/WIZCmake.h b/Demo/PIC18_WizC/Demo3/WIZCmake.h new file mode 100644 index 000000000..0d1e297f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/WIZCmake.h @@ -0,0 +1,53 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo3/fuses.c b/Demo/PIC18_WizC/Demo3/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo3/interrupt.c b/Demo/PIC18_WizC/Demo3/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo3/main.c b/Demo/PIC18_WizC/Demo3/main.c new file mode 100644 index 000000000..8dd2e1253 --- /dev/null +++ b/Demo/PIC18_WizC/Demo3/main.c @@ -0,0 +1,190 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the third. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo3 project is configured for a PIC18F4620 device. Main.c starts 12 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/BlockQ.c: Creates 6 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "BlockQ.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ + portTickType xLastCheckTime; + portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; + portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} + +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/Demo4/Demo4.PC b/Demo/PIC18_WizC/Demo4/Demo4.PC new file mode 100644 index 000000000..f4ee06de5 --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/Demo4.PC @@ -0,0 +1,475 @@ +[F29012037] +x=0 +y=115 +[F15207742] +x=0 +y=48 +[F10478061] +x=0 +y=48 +[F28429921] +x=0 +y=0 +[ProjectGroup] +nFiles=1 +FileName0=Demo4.PC +[Project] +nFiles=8 +UseAD=0 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b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h new file mode 100644 index 000000000..e17465cdb --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h @@ -0,0 +1,82 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 1 ) +#define INCLUDE_uxTaskPriorityGet ( 1 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 1 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo4/MallocConfig.h b/Demo/PIC18_WizC/Demo4/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo4/WIZCmake.h b/Demo/PIC18_WizC/Demo4/WIZCmake.h new file mode 100644 index 000000000..0d1e297f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/WIZCmake.h @@ -0,0 +1,53 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo4/fuses.c b/Demo/PIC18_WizC/Demo4/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo4/interrupt.c b/Demo/PIC18_WizC/Demo4/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo4/main.c b/Demo/PIC18_WizC/Demo4/main.c new file mode 100644 index 000000000..87f4788f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo4/main.c @@ -0,0 +1,189 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the fourth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo4 project is configured for a PIC18F4620 device. Main.c starts 11 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/dynamic.c: Creates 5 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "dynamic.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ + portTickType xLastCheckTime; + portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; + portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} + +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/Demo5/Demo5.PC b/Demo/PIC18_WizC/Demo5/Demo5.PC new file mode 100644 index 000000000..479208633 --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/Demo5.PC @@ -0,0 +1,536 @@ +[F29012293] +x=0 +y=114 +[F10478061] +x=0 +y=48 +[F15207742] +x=0 +y=48 +[F28446561] +x=0 +y=0 +[F30163742] +x=38 +y=56 +[F29565566] +x=0 +y=0 +[ProjectGroup] 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be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 3 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 0 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo5/MallocConfig.h b/Demo/PIC18_WizC/Demo5/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo5/WIZCmake.h b/Demo/PIC18_WizC/Demo5/WIZCmake.h new file mode 100644 index 000000000..0d1e297f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/WIZCmake.h @@ -0,0 +1,53 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo5/fuses.c b/Demo/PIC18_WizC/Demo5/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo5/interrupt.c b/Demo/PIC18_WizC/Demo5/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo5/main.c b/Demo/PIC18_WizC/Demo5/main.c new file mode 100644 index 000000000..e37eeaa7f --- /dev/null +++ b/Demo/PIC18_WizC/Demo5/main.c @@ -0,0 +1,178 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the fifth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo5 project is configured for a PIC18F4620 device. Main.c starts 13 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/flop.c: Creates 8 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "flop.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/Demo6/Demo6.PC b/Demo/PIC18_WizC/Demo6/Demo6.PC new file mode 100644 index 000000000..5f5f39862 --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/Demo6.PC @@ -0,0 +1,632 @@ +[F29012549] +x=0 +y=111 +[F15207742] +x=0 +y=48 +[F28463201] +x=0 +y=0 +[F30163998] +x=60 +y=44 +[F29565822] +x=2 +y=23 +[F26101515] +x=0 +y=269 +[ProjectGroup] +nFiles=1 +FileName0=Demo6.PC +[Project] +nFiles=6 +UseAD=0 +CompatOpts=0 +AutoHead= +IdentifierPrint=0 +TreePrint=0 +StatementResultPrint=0 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but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 3 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo6/MallocConfig.h b/Demo/PIC18_WizC/Demo6/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo6/WIZCmake.h b/Demo/PIC18_WizC/Demo6/WIZCmake.h new file mode 100644 index 000000000..0d1e297f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/WIZCmake.h @@ -0,0 +1,53 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo6/fuses.c b/Demo/PIC18_WizC/Demo6/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo6/interrupt.c b/Demo/PIC18_WizC/Demo6/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo6/main.c b/Demo/PIC18_WizC/Demo6/main.c new file mode 100644 index 000000000..ae03d71d2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo6/main.c @@ -0,0 +1,170 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the sixth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo6 project is configured for a PIC18F4620 device. Main.c starts 4 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/comtest.c: Creates 2 tasks + * ATTENTION: Comtest needs a loopback-connector on the serial port. + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "partest.h" +#include "serial.h" +#include "comtest.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* The LED that is toggled whenever a character is transmitted. +mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ +#define mainCOMM_TX_RX_LED ( ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. */ +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/Demo7/Demo7.PC b/Demo/PIC18_WizC/Demo7/Demo7.PC new file mode 100644 index 000000000..a89bd1912 --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/Demo7.PC @@ -0,0 +1,546 @@ +[F29012549] +x=0 +y=111 +[F15207742] +x=0 +y=48 +[F26101515] +x=0 +y=269 +[F28463201] +x=0 +y=0 +[F20539803] +x=0 +y=233 +[ProjectGroup] +nFiles=1 +FileName0=Demo7.PC +[Project] +nFiles=7 +UseAD=0 +CompatOpts=0 +AutoHead= +IdentifierPrint=0 +TreePrint=0 +StatementResultPrint=0 +SourcePrint=0 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000000000..7c5844ccd --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h @@ -0,0 +1,82 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 1 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo7/MallocConfig.h b/Demo/PIC18_WizC/Demo7/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo7/WIZCmake.h b/Demo/PIC18_WizC/Demo7/WIZCmake.h new file mode 100644 index 000000000..0d1e297f2 --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/WIZCmake.h @@ -0,0 +1,53 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo7/fuses.c b/Demo/PIC18_WizC/Demo7/fuses.c new file mode 100644 index 000000000..fa53d36dc --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/fuses.c @@ -0,0 +1,58 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo7/interrupt.c b/Demo/PIC18_WizC/Demo7/interrupt.c new file mode 100644 index 000000000..9e0c4e9d9 --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/interrupt.c @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/Demo/PIC18_WizC/Demo7/main.c b/Demo/PIC18_WizC/Demo7/main.c new file mode 100644 index 000000000..67395a039 --- /dev/null +++ b/Demo/PIC18_WizC/Demo7/main.c @@ -0,0 +1,184 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the seventh. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo7 project is configured for a PIC18F4620 device. Main.c starts 10 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/flash.c: Creates 3 tasks + * demo/common/minimal/death.c: Creates 1 controltask and + * creates/deletes 4 suicidaltasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "death.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/Demo/PIC18_WizC/ParTest/ParTest.c b/Demo/PIC18_WizC/ParTest/ParTest.c new file mode 100644 index 000000000..32257bf22 --- /dev/null +++ b/Demo/PIC18_WizC/ParTest/ParTest.c @@ -0,0 +1,125 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include + +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the FED 40pin demo board. + * The four LED's are connected to D4 to D7. + *-----------------------------------------------------------*/ + +#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) +#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) +#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) + +#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Set the top four bits of port D to output. */ + bTRD7 = partstBIT_AS_OUTPUT; + bTRD6 = partstBIT_AS_OUTPUT; + bTRD5 = partstBIT_AS_OUTPUT; + bTRD4 = partstBIT_AS_OUTPUT; + + /* Start with all bits off. */ + bRD7 = partstCLEAR_OUTPUT; + bRD6 = partstCLEAR_OUTPUT; + bRD5 = partstCLEAR_OUTPUT; + bRD4 = partstCLEAR_OUTPUT; + + /* Enable the driver. */ + ADCON1 = partstENABLE_GENERAL_IO; + bTRE2 = partstBIT_AS_OUTPUT; + bRE2 = partstSET_OUTPUT; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portCHAR ucLED, portCHAR cValue ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( ucLED ) + { + case 3 : bRD7 = ( portSHORT ) cValue; + break; + case 2 : bRD6 = ( portSHORT ) cValue; + break; + case 1 : bRD5 = ( portSHORT ) cValue; + break; + case 0 : bRD4 = ( portSHORT ) cValue; + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portCHAR ucLED ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( ucLED ) + { + case 3 : bRD7 = !bRD7; + break; + case 2 : bRD6 = !bRD6; + break; + case 1 : bRD5 = !bRD5; + break; + case 0 : bRD4 = !bRD4 ); + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} + + + diff --git a/Demo/PIC18_WizC/serial/isrSerialRx.c b/Demo/PIC18_WizC/serial/isrSerialRx.c new file mode 100644 index 000000000..3b7b69bd6 --- /dev/null +++ b/Demo/PIC18_WizC/serial/isrSerialRx.c @@ -0,0 +1,106 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +#ifndef _FREERTOS_SERIAL_ISRSERIALRX_C +#define _FREERTOS_SERIAL_ISRSERIALRX_C + +#define serCONTINUOUS_RX ( 1 ) +#define serCLEAR_OVERRUN ( 0 ) + +{ + /* + * Was the interrupt a byte being received? + */ + if( bRCIF && bRCIE) + { + /* + * Queue to interface between comms API and interrupt routine. + */ + extern xQueueHandle xRxedChars; + + /* + * Because we are not allowed to use local variables here, + * PRODL is (ab)used as temporary storage. This is allowed + * because this SFR will be restored before exiting the ISR. + */ + extern portCHAR cChar; + #pragma locate cChar &PRODL + + /* + * If there was a framing error, just get and ignore + * the character + */ + if( bFERR ) + { + cChar = RCREG; + } + else + { + /* + * Get the character and post it on the queue of Rxed + * characters. If the post causes a task to wake ask + * for a context switch as the woken task may have a + * higher priority than the task we have interrupted. + */ + cChar = RCREG; + + /* + * Clear any overrun errors. + */ + if( bOERR ) + { + bCREN = serCLEAR_OVERRUN; + bCREN = serCONTINUOUS_RX; + } + + if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) ) + { + uxSwitchRequested = pdTRUE; + } + } + } +} + +#endif /* _FREERTOS_SERIAL_ISRSERIALRX_C */ diff --git a/Demo/PIC18_WizC/serial/isrSerialTx.c b/Demo/PIC18_WizC/serial/isrSerialTx.c new file mode 100644 index 000000000..8a289f078 --- /dev/null +++ b/Demo/PIC18_WizC/serial/isrSerialTx.c @@ -0,0 +1,99 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +#ifndef _FREERTOS_SERIAL_ISRSERIALTX_C +#define _FREERTOS_SERIAL_ISRSERIALTX_C + +#define serINTERRUPT_DISABLED ( 0 ) + + +{ + /* + * Was the interrupt the Tx register becoming empty? + */ + if( bTXIF && bTXIE) + { + /* + * Queue to interface between comms API and interrupt routine. + */ + extern xQueueHandle xCharsForTx; + + /* + * Because we are not allowed to use local variables here, + * PRODL and PRODH are (ab)used as temporary storage. This + * is allowed because these SFR's will be restored before + * exiting the ISR. + */ + extern portCHAR cChar; + #pragma locate cChar &PRODL + extern portBASE_TYPE pxTaskWoken; + #pragma locate pxTaskWoken &PRODH + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &pxTaskWoken ) == pdTRUE ) + { + /* + * Send the next character queued for Tx. + */ + TXREG = cChar; + } + else + { + /* + * Queue empty, nothing to send. + */ + bTXIE = serINTERRUPT_DISABLED; + } + + /* + * If we woke another task, ask for a contextswitch + */ + if( pxTaskWoken == pdTRUE ) + { + uxSwitchRequested = pdTRUE; + } + } +} + +#endif /* _FREERTOS_SERIAL_ISRSERIALTX_C */ diff --git a/Demo/PIC18_WizC/serial/serial.c b/Demo/PIC18_WizC/serial/serial.c new file mode 100644 index 000000000..92fd9440c --- /dev/null +++ b/Demo/PIC18_WizC/serial/serial.c @@ -0,0 +1,177 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode removed. Is now pulled inline to reduce stack-usage. + +Changes from V3.0.1 +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ + +/* Scheduler header files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#include "serial.h" + +/* Hardware pin definitions. */ +#define serTX_PIN bTRC6 +#define serRX_PIN bTRC7 + +/* Bit/register definitions. */ +#define serINPUT ( 1 ) +#define serOUTPUT ( 0 ) +#define serINTERRUPT_ENABLED ( 1 ) + +/* All ISR's use the PIC18 low priority interrupt. */ +#define serLOW_PRIORITY ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues to interface between comms API and interrupt routines. */ +xQueueHandle xRxedChars; +xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portCHAR ucQueueLength ) +{ + unsigned portSHORT usSPBRG; + + /* Create the queues used by the ISR's to interface to tasks. */ + xRxedChars = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + xCharsForTx = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + portENTER_CRITICAL(); + + /* Setup the IO pins to enable the USART IO. */ + serTX_PIN = serINPUT; // YES really! See datasheet + serRX_PIN = serINPUT; + + /* Set the TX config register. */ + TXSTA = 0b00100000; + // ||||||||--bit0: TX9D = n/a + // |||||||---bit1: TRMT = ReadOnly + // ||||||----bit2: BRGH = High speed + // |||||-----bit3: SENDB = n/a + // ||||------bit4: SYNC = Asynchronous mode + // |||-------bit5: TXEN = Transmit enable + // ||--------bit6: TX9 = 8-bit transmission + // |---------bit7: CSRC = n/a + + /* Set the Receive config register. */ + RCSTA = 0b10010000; + // ||||||||--bit0: RX9D = ReadOnly + // |||||||---bit1: OERR = ReadOnly + // ||||||----bit2: FERR = ReadOnly + // |||||-----bit3: ADDEN = n/a + // ||||------bit4: CREN = Enable receiver + // |||-------bit5: SREN = n/a + // ||--------bit6: RX9 = 8-bit reception + // |---------bit7: SPEN = Serial port enabled + + /* Calculate the baud rate generator value. + We use low-speed (BRGH=0), the formula is + SPBRG = ( ( FOSC / Desired Baud Rate ) / 64 ) - 1 */ + usSPBRG = ( ( APROCFREQ / ulWantedBaud ) / 64 ) - 1; + if( usSPBRG > 255 ) + { + SPBRG = 255; + } + else + { + SPBRG = usSPBRG; + } + + /* Set the serial interrupts to use the same priority as the tick. */ + bTXIP = serLOW_PRIORITY; + bRCIP = serLOW_PRIORITY; + + /* Enable the Rx interrupt now, the Tx interrupt will get enabled when + we have data to send. */ + bRCIE = serINTERRUPT_ENABLED; + + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and + can instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portCHAR ucBufferLength ) +{ + /* This is not implemented in this port. + Use xSerialPortInitMinimal() instead. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return ( portCHAR ) pdTRUE; + } + + return ( portCHAR ) pdFALSE; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != ( portCHAR ) pdPASS ) + { + return pdFAIL; + } + + /* Turn interrupt on - ensure the compiler only generates a single + instruction for this. */ + bTXIE = serINTERRUPT_ENABLED; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not implemented for this port. + To implement, turn off the interrupts and delete the memory + allocated to the queues. */ +} diff --git a/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h b/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h new file mode 100644 index 000000000..e063dae47 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h @@ -0,0 +1,81 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c new file mode 100644 index 000000000..d3e0332d7 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c @@ -0,0 +1,86 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Application includes. */ +#include "tcp.h" + +/* Misc constants. */ +#define tcpPOLL_DELAY ( ( portTickType ) 12 / portTICK_RATE_MS ) +#define tcpCONNECTION_DELAY ( ( portTickType ) 8 / portTICK_RATE_MS ) +/*-----------------------------------------------------------*/ + +/* + * This task initialises the hardware then processes one TCP connection at a + * time. When an HTTP client connects we just simply send a single page then + * disconnect - reset the socket data and wait for the next connection. + */ +void vHTTPServerTask( void *pvParameters ) +{ + /* Reset the network hardware. */ + vTCPHardReset(); + + /* Loop, processing connections are they arrive. */ + for( ;; ) + { + /* Initialise the TCP interface. + + The current minimal implementation does not check for buffer overflows + in the WIZnet hardware, so simply resets all the buffers for each + connection - and only processes one connection at a time. */ + if( lTCPSoftReset() ) + { + /* Create the socket that is going to accept incoming connections. */ + if( lTCPCreateSocket() ) + { + /* Wait for a connection. */ + vTCPListen(); + + /* Process connections as they arrive. This function will only + return once the connection has been closed. */ + lProcessConnection(); + } + } + + /* If we get here then the connection completed or failed. Wait a + while then try or start again. */ + vTaskDelay( tcpCONNECTION_DELAY ); + } +} + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h new file mode 100644 index 000000000..39c8a8871 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h @@ -0,0 +1,38 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef HTTP_H +#define HTTP_H + +void vHTTPServerTask( void *pvParameters ); + +#endif diff --git a/Demo/WizNET_DEMO_GCC_ARM7/Makefile b/Demo/WizNET_DEMO_GCC_ARM7/Makefile new file mode 100644 index 000000000..8dbf8b7ed --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/Makefile @@ -0,0 +1,116 @@ +# FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s +USE_THUMB_MODE=YES +DEBUG=-g +OPTIM=-Os +RUN_MODE=RUN_FROM_ROM +LDSCRIPT=lpc2106-rom.ld + + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=-Wall -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + -Wcast-align $(OPTIM) + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -oWebServeDemo.elf -Xlinker -M -Xlinker -Map=WebServeDemo.map + +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +../../Source/tasks.c \ +../../Source/queue.c \ +../../Source/list.c \ +../../Source/portable/MemMang/heap_2.c \ +../../Source/portable/GCC/ARM7_LPC2000/port.c \ +../Common/Minimal/flash.c \ +../Common/Minimal/dynamic.c \ +../Common/Minimal/semtest.c \ +../Common/Minimal/PollQ.c \ +../Common/Minimal/BlockQ.c \ +../Common/Minimal/integer.c \ +../ARM7_LPC2106_GCC/ParTest/ParTest.c \ +main.c \ +TCP.c \ +HTTP_Serv.c \ +i2c.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +../../Source/portable/GCC/ARM7_LPC2000/portISR.c \ +i2cISR.c \ +TCPISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +WebServeDemo.hex : WebServeDemo.elf + $(OBJCOPY) WebServeDemo.elf -O ihex WebServeDemo.hex + +WebServeDemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch makefile + + + + + + + + + + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.c b/Demo/WizNET_DEMO_GCC_ARM7/TCP.c new file mode 100644 index 000000000..d154b13cb --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/TCP.c @@ -0,0 +1,740 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified char* types to compile without warning when using GCC V4.0.1. + + Corrected the address to which the MAC address is written. Thanks to + Bill Knight for this correction. + + Changes from V3.2.4 + + + Changed the default MAC address to something more realistic. + +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "tcp.h" +#include "serial.h" + +/* Application includes. */ +#include "i2c.h" +#include "html_pages.h" + +/*-----------------------------------------------------------*/ + +/* Hardwired i2c address of the WIZNet device. */ +#define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 ) + +/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet +device. */ +#define tcp8K_RX ( ( unsigned portCHAR ) 0x03 ) +#define tcp8K_TX ( ( unsigned portCHAR ) 0x03 ) + +/* Constants used to generate the WIZnet internal buffer addresses. */ +#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff ) +#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 ) + +/* Bit definitions of the commands that can be sent to the command register. */ +#define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 ) +#define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 ) +#define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 ) +#define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 ) +#define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 ) +#define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 ) +#define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 ) +#define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 ) + +/* Constants required to handle the interrupts. */ +#define tcpCLEAR_EINT0 ( 1 ) +#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff ) +#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 ) +#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 ) +#define tcpWAKE_ON_EINT0 ( 1 ) +#define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 ) +#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) +#define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 ) +#define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Various delays used in the driver. */ +#define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS ) +#define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS ) +#define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS ) +#define tcpNO_DELAY ( ( portTickType ) 0 ) + +/* Length of the data to read for various register reads. */ +#define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 ) +#define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 ) + +/* Register addresses within the WIZnet device. */ +#define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 ) +#define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 ) +#define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 ) +#define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 ) +#define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E ) +#define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 ) +#define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE ) +#define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 ) +#define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 ) +#define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 ) +#define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 ) +#define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 ) +#define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 ) +#define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 ) +#define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 ) +#define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 ) +#define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 ) +#define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 ) + +/* Constants required for hardware setup. */ +#define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 ) +#define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 ) + +/* Constants defining the source of the WIZnet ISR. */ +#define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 ) +#define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 ) +#define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 ) +#define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 ) +#define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 ) +#define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 ) +#define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 ) + +/* Constants defining the socket status bits. */ +#define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 ) +#define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 ) + +/* Misc constants. */ +#define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 ) +#define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 ) +#define i2cNO_DATA_REQUIRED ( 0x0000 ) +#define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 ) +#define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 ) +#define tcpBUFFER_LEN ( 4 * 1024 ) +#define tcpMAX_REGISTER_LEN ( 4 ) +#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 ) +#define tcpMAX_NON_LISTEN_STAUS_READS ( 5 ) + +/* Message definitions. The IP address, MAC address, gateway address, etc. +is set here! */ +const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */ +const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */ +const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */ +const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */ + +/* Other fixed messages. */ +const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD }; +const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD }; +const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM }; +const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC }; +const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT }; +const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD }; +const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD }; +const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX }; +const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX }; +const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD }; +const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD }; +const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE }; +const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE }; +const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS }; + +static xSemaphoreHandle xMessageComplete = NULL; +xQueueHandle xTCPISRQueue = NULL; + +/* Dynamically generate and send an html page. */ +static void prvSendSamplePage( void ); + +/* Read a register from the WIZnet device via the i2c interface. */ +static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ); + +/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */ +static void prvFlushBuffer( unsigned portLONG ulTxAddress ); + +/* Write a string to the WIZnet Tx buffer. */ +static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ); + +/* Convert a number to a string. */ +void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ); + +/*-----------------------------------------------------------*/ + +void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ) +{ +unsigned portLONG lNibble; +portLONG lIndex; + + /* Simple routine to convert an unsigned long value into a string in hex + format. */ + + /* For each nibble in the number we are converting. */ + for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ ) + { + /* Take the top four bits of the number. */ + lNibble = ( ulVal >> 28 ); + + /* We are converting it to a hex string, so is the number in the range + 0-10 or A-F? */ + if( lNibble < 10 ) + { + pcBuffer[ lIndex ] = '0' + lNibble; + } + else + { + lNibble -= 10; + pcBuffer[ lIndex ] = 'A' + lNibble; + } + + /* Shift off the top nibble so we use the next nibble next time around. */ + ulVal <<= 4; + } + + /* Mark the end of the string with a null terminator. */ + pcBuffer[ lIndex ] = 0x00; +} +/*-----------------------------------------------------------*/ + +static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ) +{ +unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ]; + + /* Read a register value from the WIZnet device. */ + + /* First write out the address of the register we want to read. */ + i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY ); + + /* Then read back from that address. */ + i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY ); + + /* I2C messages are queued so use the semaphore to wait for the read to + complete - otherwise we will leave this function before the I2C + transactions have completed. */ + xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); +} +/*-----------------------------------------------------------*/ + +void vTCPHardReset( void ) +{ + /* Physical reset of the WIZnet device by using the GPIO lines to hold the + WIZnet reset lines active for a few milliseconds. */ + + /* Make sure the interrupt from the WIZnet is disabled. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + + /* If xMessageComplete is NULL then this is the first time that this + function has been called and the queue and semaphore used in this file + have not yet been created. */ + if( xMessageComplete == NULL ) + { + /* Create and obtain the semaphore used when we want to wait for an i2c + message to be completed. */ + vSemaphoreCreateBinary( xMessageComplete ); + xSemaphoreTake( xMessageComplete, tcpNO_DELAY ); + + /* Create the queue used to communicate between the WIZnet and TCP tasks. */ + xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE ); + } + + /* Use the GPIO to reset the network hardware. */ + GPIO_IOCLR = tcpRESET_ACTIVE_LOW; + GPIO_IOSET = tcpRESET_ACTIVE_HIGH; + + /* Delay with the network hardware in reset for a short while. */ + vTaskDelay( tcpRESET_DELAY ); + + GPIO_IOCLR = tcpRESET_ACTIVE_HIGH; + GPIO_IOSET = tcpRESET_ACTIVE_LOW; + + vTaskDelay( tcpINIT_DELAY ); + + /* Setup the EINT0 to interrupt on required events from the WIZnet device. + First enable the EINT0 function of the pin. */ + PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION; + + /* We want the TCP comms to wake us from power save. */ + SCB_EXTWAKE = tcpWAKE_ON_EINT0; + + /* Install the ISR into the VIC - but don't enable it yet! */ + portENTER_CRITICAL(); + { + extern void ( vEINT0_ISR )( void ); + + VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT ); + VICVectAddr3 = ( portLONG ) vEINT0_ISR; + + VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE; + } + portEXIT_CRITICAL(); + + /* Enable interrupts in the WIZnet itself. */ + i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); + + vTaskDelay( tcpLONG_DELAY ); +} +/*-----------------------------------------------------------*/ + +portLONG lTCPSoftReset( void ) +{ +unsigned portCHAR ucStatus; +extern volatile portLONG lTransactionCompleted; + + /* Send a message to the WIZnet device to tell it set all it's registers + back to their default states. Then setup the WIZnet device as required. */ + + /* Reset the internal WIZnet registers. */ + i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Now we can configure the protocol. Here the MAC address, gateway + address, subnet mask and IP address are configured. */ + i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Next the memory buffers are configured to give all the WIZnet internal + memory over to a single socket. This gives the socket the maximum internal + Tx and Rx buffer space. */ + i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Send the sys init command so the above parameters take effect. */ + i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Seems to like a little wait here. */ + vTaskDelay( tcpINIT_DELAY ); + + /* Read back the status to ensure the system initialised ok. */ + prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* We should find that the sys init was successful. */ + if( ucStatus != tcpISR_SYS_INIT ) + { + return ( portLONG ) pdFAIL; + } + + /* No i2c errors yet. */ + portENTER_CRITICAL(); + lTransactionCompleted = pdTRUE; + portEXIT_CRITICAL(); + + return ( portLONG ) pdPASS; +} +/*-----------------------------------------------------------*/ + +portLONG lTCPCreateSocket( void ) +{ +unsigned portCHAR ucStatus; + + /* Create and configure a socket. */ + + /* Setup and init the socket. Here the port number is set and the socket + is initialised. */ + i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + /* Wait for the Init command to be sent. */ + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + /* For some reason the message was not transmitted within our block + period. */ + return ( portLONG ) pdFAIL; + } + + /* Allow the socket to initialise. */ + vTaskDelay( tcpINIT_DELAY ); + + /* Read back the status to ensure the socket initialised ok. */ + prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* We should find that the socket init was successful. */ + if( ucStatus != tcpISR_SOCKET_INIT ) + { + return ( portLONG ) pdFAIL; + } + + + /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */ + i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + + return ( portLONG ) pdPASS; +} +/*-----------------------------------------------------------*/ + +void vTCPListen( void ) +{ +unsigned portCHAR ucISR; + + /* Start a passive listen on the socket. */ + + /* Enable interrupts in the WizNet device after ensuring none are + currently pending. */ + while( SCB_EXTINT & tcpCLEAR_EINT0 ) + { + /* The WIZnet device is still asserting and interrupt so tell it to + clear. */ + i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); + + vTaskDelay( 1 ); + SCB_EXTINT = tcpCLEAR_EINT0; + } + + while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) ) + { + /* Just clearing the queue used by the ISR routine to tell this task + that the WIZnet device needs attention. */ + } + + /* Now all the pending interrupts have been cleared we can enable the + processor interrupts. */ + VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Then start listening for incoming connections. */ + i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); +} +/*-----------------------------------------------------------*/ + +portLONG lProcessConnection( void ) +{ +unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow; +extern volatile portLONG lTransactionCompleted; +portLONG lSameStateCount = 0, lDataSent = pdFALSE; +unsigned portLONG ulWritePointer, ulAckPointer; + + /* No I2C errors can yet have occurred. */ + portENTER_CRITICAL(); + lTransactionCompleted = pdTRUE; + portEXIT_CRITICAL(); + + /* Keep looping - processing interrupts, until we have completed a + transaction. This uses the WIZnet in it's simplest form. The socket + accepts a connection - we process the connection - then close the socket. + We then go back to reinitialise everything and start again. */ + while( lTransactionCompleted == pdTRUE ) + { + /* Wait for a message on the queue from the WIZnet ISR. When the + WIZnet device asserts an interrupt the ISR simply posts a message + onto this queue to wake this task. */ + if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) ) + { + /* The ISR posted a message on this queue to tell us that the + WIZnet device asserted an interrupt. The ISR cannot process + an I2C message so cannot tell us what caused the interrupt so + we have to query the device here. This task is the highest + priority in the system so will run immediately following the ISR. */ + prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* Once we have read what caused the ISR we can clear the interrupt + in the WIZnet. */ + i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Now we can clear the processor interrupt and re-enable ready for + the next. */ + SCB_EXTINT = tcpCLEAR_EINT0; + VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Process the interrupt ... */ + + if( ucISR & tcpISR_ESTABLISHED ) + { + /* A connection has been established - respond by sending + a receive command. */ + i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + } + + if( ucISR & tcpISR_RX_COMPLETE ) + { + /* We message has been received. This will be an HTTP get + command. We only have one page to send so just send it without + regard to what the actual requested page was. */ + prvSendSamplePage(); + } + + if( ucISR & tcpISR_TX_COMPLETE ) + { + /* We have a TX complete interrupt - which oddly does not + indicate that the message being sent is complete so we cannot + yet close the socket. Instead we read the position of the Tx + pointer within the WIZnet device so we know how much data it + has to send. Later we will read the ack pointer and compare + this to the Tx pointer to ascertain whether the transmission + has completed. */ + + /* First read the shadow register. */ + prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); + + /* Now a short delay is required. */ + vTaskDelay( tcpSHORT_DELAY ); + + /* Then we can read the real register. */ + prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) ); + + /* We cannot do anything more here but need to remember that + this interrupt has occurred. */ + lDataSent = pdTRUE; + } + + if( ucISR & tcpISR_CLOSED ) + { + /* The socket has been closed so we can leave this function. */ + lTransactionCompleted = pdFALSE; + } + } + else + { + /* We have not received an interrupt from the WIZnet device for a + while. Read the socket status and check that everything is as + expected. */ + prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN ); + + if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) ) + { + /* The socket is established and we have already received a Tx + end interrupt. We must therefore be waiting for the Tx buffer + inside the WIZnet device to be empty before we can close the + socket. + + Read the Ack pointer register to see if it has caught up with + the Tx pointer register. First we have to read the shadow + register. */ + prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN ); + vTaskDelay( tcpSHORT_DELAY ); + prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) ); + + if( ulAckPointer == ulWritePointer ) + { + /* The Ack and write pointer are now equal and we can + safely close the socket. */ + i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + } + else + { + /* Keep a count of how many times we encounter the Tx + buffer still containing data. */ + lDataSent++; + if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ) + { + /* Assume we cannot complete sending the data and + therefore cannot safely close the socket. Start over. */ + vTCPHardReset(); + lTransactionCompleted = pdFALSE; + } + } + } + else if( ucState != tcpSTATUS_LISTEN ) + { + /* If we have not yet received a Tx end interrupt we would only + ever expect to find the socket still listening for any + sustained period. */ + if( ucState == ucLastState ) + { + lSameStateCount++; + if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS ) + { + /* We are persistently in an unexpected state. Assume + we cannot safely close the socket and start over. */ + vTCPHardReset(); + lTransactionCompleted = pdFALSE; + } + } + } + else + { + /* We are in the listen state so are happy that everything + is as expected. */ + lSameStateCount = 0; + } + + /* Remember what state we are in this time around so we can check + for a persistence on an unexpected state. */ + ucLastState = ucState; + } + } + + /* We are going to reinitialise the WIZnet device so do not want our + interrupts from the WIZnet to be processed. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + return lTransactionCompleted; +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ) +{ +unsigned portLONG ulSendAddress; + + /* Send a string to the Tx buffer internal to the WIZnet device. */ + + /* Calculate the address to which we are going to write in the buffer. */ + ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET; + + /* Send the buffer to the calculated address. Use the semaphore so we + can wait until the entire message has been transferred. */ + i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + /* Wait until the semaphore indicates that the message has been transferred. */ + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } + + /* Return the new address of the end of the buffer (within the WIZnet + device). */ + *pulTxAddress += ( unsigned portLONG ) lTxLen; +} +/*-----------------------------------------------------------*/ + +static void prvFlushBuffer( unsigned portLONG ulTxAddress ) +{ +unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ]; + + /* We have written some data to the Tx buffer internal to the WIZnet + device. Now we update the Tx pointer inside the WIZnet then send a + Send command - which causes the data up to the new Tx pointer to be + transmitted. */ + + /* Make sure endieness is correct for transmission. */ + ulTxAddress = htonl( ulTxAddress ); + + /* Place the new Tx pointer in the string to be transmitted. */ + ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + + /* And send it to the WIZnet device. */ + i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } + + vTaskDelay( tcpSHORT_DELAY ); + + /* Transmit! */ + i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } +} +/*-----------------------------------------------------------*/ + +static void prvSendSamplePage( void ) +{ +extern portLONG lErrorInTask; +unsigned portLONG ulTxAddress; +unsigned portCHAR ucShadow; +portLONG lIndex; +static unsigned portLONG ulRefreshCount = 0x00; +static portCHAR cPageBuffer[ tcpBUFFER_LEN ]; + + + /* This function just generates a sample page of HTML which gets + sent each time a client attaches to the socket. The page is created + from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart) + with a bit of dynamically generated data in the middle. */ + + /* We need to know the address to which the html string should be sent + in the WIZnet Tx buffer. First read the shadow register. */ + prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); + + /* Now a short delay is required. */ + vTaskDelay( tcpSHORT_DELAY ); + + /* Now we can read the real pointer value. */ + prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) ); + + /* Make sure endieness is correct. */ + ulTxAddress = htonl( ulTxAddress ); + + /* Send the start of the page. */ + prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress ); + + /* Generate a bit of dynamic data and place it in the buffer ready to be + transmitted. */ + strcpy( cPageBuffer, "
Number of ticks since boot = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
Number of tasks executing = "); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
IO port 0 state (used by flash tasks) = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
Refresh = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 ); + + if( lErrorInTask ) + { + strcat( cPageBuffer, "

An error has occurred in at least one task." ); + } + else + { + strcat( cPageBuffer, "

All tasks executing without error." ); + } + + ulRefreshCount++; + + /* Send the dynamically generated string. */ + prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress ); + + /* Finish the page. */ + prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress ); + + /* Tell the WIZnet to send the data we have just written to its Tx buffer. */ + prvFlushBuffer( ulTxAddress ); +} + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.h b/Demo/WizNET_DEMO_GCC_ARM7/TCP.h new file mode 100644 index 000000000..9e734749c --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/TCP.h @@ -0,0 +1,45 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef TCP_H +#define TCP_H + +#define htonl(A) ((((A) & 0xff000000) >> 24) | (((A) & 0x00ff0000) >> 8) | (((A) & 0x0000ff00) << 8) | (((A) & 0x000000ff) << 24)) + +void vTCPHardReset( void ); +portLONG lTCPSoftReset( void ); +portLONG lTCPCreateSocket( void ); +portLONG lTCPListen( void ); +portLONG lProcessConnection( void ); +void vTCPListen( void ); + +#endif diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c b/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c new file mode 100644 index 000000000..c92f0622a --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c @@ -0,0 +1,78 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Constants required for interrupt management. */ +#define tcpCLEAR_VIC_INTERRUPT ( 0 ) +#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) + +/* EINT0 interrupt handler. This processes interrupts from the WIZnet device. */ +void vEINT0_ISR( void ) __attribute__((naked)); + +/* Variable is required for its address, but does not otherwise get used. */ +static portLONG lDummyVariable; + +/* + * When the WIZnet device asserts an interrupt we send an (empty) message to + * the TCP task. This wakes the task so the interrupt can be processed. The + * source of the interrupt has to be ascertained by the TCP task as this + * requires an I2C transaction which cannot be performed from this ISR. + */ +void vEINT0_ISR( void ) +{ + portENTER_SWITCHING_ISR(); + + extern xQueueHandle xTCPISRQueue; + portBASE_TYPE xTaskWoken = pdFALSE; + + /* Just wake the TCP task so it knows an ISR has occurred. */ + xQueueSendFromISR( xTCPISRQueue, ( void * ) &lDummyVariable, xTaskWoken ); + + /* We cannot carry on processing interrupts until the TCP task has + processed this one - so for now interrupts are disabled. The TCP task will + re-enable it. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Clear the interrupt bit. */ + VICVectAddr = tcpCLEAR_VIC_INTERRUPT; + + /* Switch to the TCP task immediately so the cause of the interrupt can + be ascertained. It is the responsibility of the TCP task to clear the + interrupts. */ + portEXIT_SWITCHING_ISR( ( xTaskWoken ) ); +} + + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/boot.s b/Demo/WizNET_DEMO_GCC_ARM7/boot.s new file mode 100644 index 000000000..33e5226eb --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h b/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h new file mode 100644 index 000000000..46e01bc2b --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h @@ -0,0 +1,66 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef HTML_PAGES_H +#define HTML_PAGES_H + +/* Simply defines some strings that get sent as HTML pages. */ + +const portCHAR * const cSamplePageFirstPart = +"HTTP/1.0 200 OK\r\n" +"Content-type: text/html\r\n" +"\r\n" +"\r\n" +"\r\n" +"\r\n" +"FreeRTOS - Live embedded WEB server demo\r\n" +"\r\n" +"\r\n" +"\r\n" +"FreeRTOS Homepage

" +"

Embedded WEB Server
On the FreeRTOS real time kernel

\r\n" +"

\r\n" +"This demo is now using FreeRTOS V4.x.x!

" +"This page is being served by the FreeRTOS embedded WEB server running on an ARM7 microcontroller.\r\n

";
+
+const portCHAR * const cSamplePageSecondPart =
+"
" +"If all is well you should see that 18 tasks are executing - 15 standard demo tasks, the embedded WEB server" +" task, the error check task and the idle task.

" +"\r\n" +"\r\n" +"\r\n"; + + + +#endif + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.c b/Demo/WizNET_DEMO_GCC_ARM7/i2c.c new file mode 100644 index 000000000..462a616be --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/i2c.c @@ -0,0 +1,209 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "semphr.h" + +/* Application includes. */ +#include "i2c.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup the microcontroller IO. */ +#define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 ) +#define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 ) + +/* Bit definitions within the I2CONCLR register. */ +#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) +#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) +#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) + +/* Constants required to setup the VIC. */ +#define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 ) +#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 ) +#define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Misc constants. */ +#define i2cNO_BLOCK ( ( portTickType ) 0 ) +#define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 ) +#define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 ) +#define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 ) +#define i2cTIMERL ( 200 ) +#define i2cTIMERH ( 200 ) + +/* Array of message definitions. See the header file for more information +on the structure members. There are two more places in the queue than as +defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free +message available - one can be in the process of being transmitted and one +can be left free. */ +static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ]; + +/* Function in the ARM part of the code used to create the queues. */ +extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ); + +/* Index to the next free message in the xTxMessages array. */ +unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0; + +/* Queue of messages that are waiting transmission. */ +static xQueueHandle xMessagesForTx; + +/* Flag to indicate the state of the I2C ISR state machine. */ +static unsigned portLONG *pulBusFree; + +/*-----------------------------------------------------------*/ +void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ) +{ +extern volatile xI2CMessage *pxCurrentMessage; +xI2CMessage *pxNextFreeMessage; +signed portBASE_TYPE xReturn; + + portENTER_CRITICAL(); + { + /* This message is guaranteed to be free as there are two more messages + than spaces in the queue allowing for one message to be in process of + being transmitted and one to be left free. */ + pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] ); + + /* Fill the message with the data to be sent. */ + + /* Pointer to the actual data. Only a pointer is stored (i.e. the + actual data is not copied, so the data being pointed to must still + be valid when the message eventually gets sent (it may be queued for + a while. */ + pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage; + + /* This is the address of the I2C device we are going to transmit this + message to. */ + pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection; + + /* A semaphore can be used to allow the I2C ISR to indicate that the + message has been sent. This can be NULL if you don't want to wait for + the message transmission to complete. */ + pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore; + + /* How many bytes are to be sent? */ + pxNextFreeMessage->lMessageLength = lMessageLength; + + /* The address within the WIZnet device to which the data will be + written. This could be the address of a register, or alternatively + a location within the WIZnet Tx buffer. */ + pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); + + /* Second byte of the address. */ + usBufferAddress >>= 8; + pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); + + /* Increment to the next message in the array - with a wrap around check. */ + ulNextFreeMessage++; + if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) ) + { + ulNextFreeMessage = ( unsigned portLONG ) 0; + } + + /* Is the I2C interrupt in the middle of transmitting a message? */ + if( *pulBusFree == ( unsigned portLONG ) pdTRUE ) + { + /* No message is currently being sent or queued to be sent. We + can start the ISR sending this message immediately. */ + pxCurrentMessage = pxNextFreeMessage; + + I2C_I2CONCLR = i2cSI_BIT; + I2C_I2CONSET = i2cSTA_BIT; + + *pulBusFree = ( unsigned portLONG ) pdFALSE; + } + else + { + /* The I2C interrupt routine is mid sending a message. Queue + this message ready to be sent. */ + xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime ); + + /* We may have blocked while trying to queue the message. If this + was the case then the interrupt would have been enabled and we may + now find that the I2C interrupt routine is no longer sending a + message. */ + if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) + { + /* Get the next message in the queue (this should be the + message we just posted) and start off the transmission + again. */ + xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK ); + pxCurrentMessage = pxNextFreeMessage; + + I2C_I2CONCLR = i2cSI_BIT; + I2C_I2CONSET = i2cSTA_BIT; + + *pulBusFree = ( unsigned portLONG ) pdFALSE; + } + } + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void i2cInit( void ) +{ +extern void ( vI2C_ISR )( void ); + + /* Create the queue used to send messages to the ISR. */ + vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree ); + + /* Configure the I2C hardware. */ + + I2C_I2CONCLR = 0xff; + + PCB_PINSEL0 |= mainSDA_ENABLE; + PCB_PINSEL0 |= mainSCL_ENABLE; + + I2C_I2SCLL = i2cTIMERL; + I2C_I2SCLH = i2cTIMERH; + I2C_I2CONSET = i2cACTIVE_MASTER_MODE; + + portENTER_CRITICAL(); + { + /* Setup the VIC for the i2c interrupt. */ + VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT ); + VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT; + VICVectAddr2 = ( portLONG ) vI2C_ISR; + + VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE; + } + portEXIT_CRITICAL(); +} + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.h b/Demo/WizNET_DEMO_GCC_ARM7/i2c.h new file mode 100644 index 000000000..2e2468375 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/i2c.h @@ -0,0 +1,86 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef I2C_H +#define I2C_H + +/* Structure used to capture the I2C message details. The structure is then + * queued for processing by the I2C ISR. + */ +typedef struct AN_I2C_MESSAGE +{ + portLONG lMessageLength; /*< How many bytes of data to send or received - excluding the buffer address. */ + unsigned portCHAR ucSlaveAddress; /*< The slave address of the WIZnet on the I2C bus. */ + unsigned portCHAR ucBufferAddressLowByte; /*< The address within the WIZnet device to which data should be read from / written to. */ + unsigned portCHAR ucBufferAddressHighByte; /*< As above, high byte. */ + xSemaphoreHandle xMessageCompleteSemaphore; /*< Contains a reference to a semaphore if the application tasks wants notifying when the message has been transacted. */ + unsigned portCHAR *pucBuffer; /*< Pointer to the buffer from where data will be read for transmission, or into which received data will be placed. */ +} xI2CMessage; + +/* Constants to use as the ulDirection parameter of i2cMessage(). */ +#define i2cWRITE ( ( unsigned portLONG ) 0 ) +#define i2cREAD ( ( unsigned portLONG ) 1 ) + +/** + * Must be called once before any calls to i2cMessage. + */ +void i2cInit( void ); + +/** + * Send or receive a message over the I2C bus. + * + * @param pucMessage The data to be transmitted or the buffer into which + * received data will be placed. + * + * @param lMessageLength The number of bytes to either transmit or receive. + * + * @param ucSlaveAddress The slave address of the WIZNet device on the I2C bus. + * + * @param usBufferAddress The address within the WIZNet device to which data is + * either written to or read from. The WIZnet has it's + * own Rx and Tx buffers. + * + * @param ulDirection Must be either i2cWRITE or i2cREAD as #defined above. + * + * @param xMessageCompleteSemaphore + * Can be used to pass a semaphore reference if the + * calling task want notification of when the message has + * completed. Otherwise NULL can be passed. + * + * @param xBlockTime The time to wait for a space in the message queue to + * become available should one not be available + * immediately. + */ +void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ); + +#endif + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c b/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c new file mode 100644 index 000000000..f1499813d --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c @@ -0,0 +1,340 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Application includes. */ +#include "i2c.h" + +/*-----------------------------------------------------------*/ + +/* Bit definitions within the I2CONCLR register. */ +#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) +#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) +#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) +#define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 ) + +/* Status codes for the I2STAT register. */ +#define i2cSTATUS_START_TXED ( 0x08 ) +#define i2cSTATUS_REP_START_TXED ( 0x10 ) +#define i2cSTATUS_TX_ADDR_ACKED ( 0x18 ) +#define i2cSTATUS_DATA_TXED ( 0x28 ) +#define i2cSTATUS_RX_ADDR_ACKED ( 0x40 ) +#define i2cSTATUS_DATA_RXED ( 0x50 ) +#define i2cSTATUS_LAST_BYTE_RXED ( 0x58 ) + +/* Constants for operation of the VIC. */ +#define i2cCLEAR_VIC_INTERRUPT ( 0 ) + +/* Misc constants. */ +#define i2cJUST_ONE_BYTE_TO_RX ( 1 ) +#define i2cBUFFER_ADDRESS_BYTES ( 2 ) + +/* End the current transmission and free the bus. */ +#define i2cEND_TRANSMISSION( lStatus ) \ +{ \ + I2C_I2CONCLR = i2cAA_BIT; \ + I2C_I2CONSET = i2cSTO_BIT; \ + eCurrentState = eSentStart; \ + lTransactionCompleted = lStatus; \ +} +/*-----------------------------------------------------------*/ + +/* Valid i2c communication states. */ +typedef enum +{ + eSentStart, /*<< Last action was the transmission of a start bit. */ + eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */ + eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */ + eSentData, /*<< Last action was the transmission of a data byte. */ + eReceiveData /*<< We expected data to be received. */ +} I2C_STATE; +/*-----------------------------------------------------------*/ + +/* Points to the message currently being sent. */ +volatile xI2CMessage *pxCurrentMessage = NULL; + +/* The queue of messages waiting to be transmitted. */ +static xQueueHandle xMessagesForTx; + +/* Flag used to indicate whether or not the ISR is amid sending a message. */ +unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE; + +/* Setting this to true will cause the TCP task to think a message is +complete and thus restart. It can therefore be used under error states +to force a restart. */ +volatile portLONG lTransactionCompleted = pdTRUE; + +/*-----------------------------------------------------------*/ + +void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) ); + + /* Pass back a reference to the queue and bus free flag so the I2C API file + can post messages. */ + *pxTxMessages = xMessagesForTx; + *ppulBusFree = &ulBusFree; +} +/*-----------------------------------------------------------*/ + +void vI2C_ISR( void ) __attribute__ (( naked )); +void vI2C_ISR( void ) +{ + portENTER_SWITCHING_ISR(); + + /* Holds the current transmission state. */ + static I2C_STATE eCurrentState = eSentStart; + static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */ + portBASE_TYPE xTaskWokenByTx = pdFALSE; + portLONG lBytesLeft; + + /* The action taken for this interrupt depends on our current state. */ + switch( eCurrentState ) + { + case eSentStart : + + /* We sent a start bit, if it was successful we can + go on to send the slave address. */ + if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) ) + { + /* Send the slave address. */ + I2C_I2DAT = pxCurrentMessage->ucSlaveAddress; + + if( pxCurrentMessage->ucSlaveAddress & i2cREAD ) + { + /* We are then going to read bytes back from the + slave. */ + eCurrentState = eSentAddressForRead; + + /* Initialise the buffer index so the first byte goes + into the first buffer position. */ + lMessageIndex = 0; + } + else + { + /* We are then going to write some data to the slave. */ + eCurrentState = eSentAddressForWrite; + + /* When writing bytes we first have to send the two + byte buffer address so lMessageIndex is set negative, + when it reaches 0 it is time to send the actual data. */ + lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; + } + } + else + { + /* Could not send the start bit so give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + + I2C_I2CONCLR = i2cSTA_BIT; + + break; + + case eSentAddressForWrite : + + /* We sent the address of the slave we are going to write to. + If this was acknowledged we can go on to send the data. */ + if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED ) + { + /* Start the first byte transmitting which is the + first byte of the buffer address to which the data will + be sent. */ + I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte; + eCurrentState = eSentData; + } + else + { + /* Address was not acknowledged so give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + case eSentAddressForRead : + + /* We sent the address of the slave we are going to read from. + If this was acknowledged we can go on to read the data. */ + if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED ) + { + eCurrentState = eReceiveData; + if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX ) + { + /* Don't ack the last byte of the message. */ + I2C_I2CONSET = i2cAA_BIT; + } + } + else + { + /* Something unexpected happened - give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + case eReceiveData : + + /* We have just received a byte from the slave. */ + if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) ) + { + /* Buffer the byte just received then increment the index + so it points to the next free space. */ + pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT; + lMessageIndex++; + + /* How many more bytes are we expecting to receive? */ + lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex; + if( lBytesLeft == ( unsigned portLONG ) 0 ) + { + /* This was the last byte in the message. */ + i2cEND_TRANSMISSION( pdPASS ); + + /* If xMessageCompleteSemaphore is not null then there + is a task waiting for this message to complete and we + must 'give' the semaphore so the task is woken.*/ + if( pxCurrentMessage->xMessageCompleteSemaphore ) + { + xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); + } + + /* Are there any other messages to transact? */ + if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) + { + /* Start the next message - which was + retrieved from the queue. */ + I2C_I2CONSET = i2cSTA_BIT; + } + else + { + /* No more messages were found to be waiting for + transaction so the bus is free. */ + ulBusFree = ( unsigned portLONG ) pdTRUE; + } + } + else + { + /* There are more bytes to receive but don't ack the + last byte. */ + if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX ) + { + I2C_I2CONCLR = i2cAA_BIT; + } + } + } + else + { + /* Something unexpected happened - give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + + break; + + case eSentData : + + /* We sent a data byte, if successful send the next byte in + the message. */ + if( I2C_I2STAT == i2cSTATUS_DATA_TXED ) + { + /* Index to the next byte to send. */ + lMessageIndex++; + if( lMessageIndex < 0 ) + { + /* lMessage index is still negative so we have so far + only sent the first byte of the buffer address. Send + the second byte now, then initialise the buffer index + to zero so the next byte sent comes from the actual + data buffer. */ + I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte; + } + else if( lMessageIndex < pxCurrentMessage->lMessageLength ) + { + /* Simply send the next byte in the tx buffer. */ + I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ]; + } + else + { + /* No more bytes in this message to be send. Finished + sending message - send a stop bit. */ + i2cEND_TRANSMISSION( pdPASS ); + + /* If xMessageCompleteSemaphore is not null then there + is a task waiting for this message to be sent and the + semaphore must be 'given' to wake the task. */ + if( pxCurrentMessage->xMessageCompleteSemaphore ) + { + xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); + } + + /* Are there any other messages to transact? */ + if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) + { + /* Start the next message from the Tx queue. */ + I2C_I2CONSET = i2cSTA_BIT; + } + else + { + /* No more message were queues for transaction so + the bus is free. */ + ulBusFree = ( unsigned portLONG ) pdTRUE; + } + } + } + else + { + /* Something unexpected happened, give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + default : + + /* Should never get here. */ + eCurrentState = eSentStart; + break; + } + + /* Clear the interrupt. */ + I2C_I2CONCLR = i2cSI_BIT; + VICVectAddr = i2cCLEAR_VIC_INTERRUPT; + + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx ) ); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld b/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld new file mode 100644 index 000000000..e7cf25a22 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h b/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h new file mode 100644 index 000000000..3f1e3042d --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h @@ -0,0 +1,321 @@ +#ifndef lpc210x_h +#define lpc210x_h +/******************************************************************************* +lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 + + +THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, +EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY +WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY +PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS +OF OTHERS. + +This file may be freely used for commercial and non-commercial applications, +including being redistributed with any tools. + +If you find a problem with the file, please report it so that it can be fixed. + +Created by Sten Larsson (sten_larsson at yahoo com) + +Edited by Richard Barry. +*******************************************************************************/ + +#define REG8 (volatile unsigned char*) +#define REG16 (volatile unsigned short*) +#define REG32 (volatile unsigned int*) + + +/*############################################################################## +## MISC +##############################################################################*/ + + /* Constants for data to put in IRQ/FIQ Exception Vectors */ +#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ +#define VECTDATA_FIQ /* __TODO */ + + +/*############################################################################## +## VECTORED INTERRUPT CONTROLLER +##############################################################################*/ + +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) + +#define VICVectAddr0 (*(REG32 (0xFFFFF100))) +#define VICVectAddr1 (*(REG32 (0xFFFFF104))) +#define VICVectAddr2 (*(REG32 (0xFFFFF108))) +#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF110))) +#define VICVectAddr5 (*(REG32 (0xFFFFF114))) +#define VICVectAddr6 (*(REG32 (0xFFFFF118))) +#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF120))) +#define VICVectAddr9 (*(REG32 (0xFFFFF124))) +#define VICVectAddr10 (*(REG32 (0xFFFFF128))) +#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF130))) +#define VICVectAddr13 (*(REG32 (0xFFFFF134))) +#define VICVectAddr14 (*(REG32 (0xFFFFF138))) +#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) + +#define VICVectCntl0 (*(REG32 (0xFFFFF200))) +#define VICVectCntl1 (*(REG32 (0xFFFFF204))) +#define VICVectCntl2 (*(REG32 (0xFFFFF208))) +#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF210))) +#define VICVectCntl5 (*(REG32 (0xFFFFF214))) +#define VICVectCntl6 (*(REG32 (0xFFFFF218))) +#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF220))) +#define VICVectCntl9 (*(REG32 (0xFFFFF224))) +#define VICVectCntl10 (*(REG32 (0xFFFFF228))) +#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) +#define VICVectCntl12 (*(REG32 (0xFFFFF230))) +#define VICVectCntl13 (*(REG32 (0xFFFFF234))) +#define VICVectCntl14 (*(REG32 (0xFFFFF238))) +#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) + +#define VICITCR (*(REG32 (0xFFFFF300))) +#define VICITIP1 (*(REG32 (0xFFFFF304))) +#define VICITIP2 (*(REG32 (0xFFFFF308))) +#define VICITOP1 (*(REG32 (0xFFFFF30C))) +#define VICITOP2 (*(REG32 (0xFFFFF310))) +#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) +#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) +#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) +#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) + +#define VICIntEnClr VICIntEnClear +#define VICSoftIntClr VICSoftIntClear + + +/*############################################################################## +## PCB - Pin Connect Block +##############################################################################*/ + +#define PCB_PINSEL0 (*(REG32 (0xE002C000))) +#define PCB_PINSEL1 (*(REG32 (0xE002C004))) + + +/*############################################################################## +## GPIO - General Purpose I/O +##############################################################################*/ + +#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO_IOSET (*(REG32 (0xE0028004))) +#define GPIO_IODIR (*(REG32 (0xE0028008))) +#define GPIO_IOCLR (*(REG32 (0xE002800C))) + +#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO0_IOSET (*(REG32 (0xE0028004))) +#define GPIO0_IODIR (*(REG32 (0xE0028008))) +#define GPIO0_IOCLR (*(REG32 (0xE002800C))) + + +/*############################################################################## +## UART0 / UART1 +##############################################################################*/ + +/* ---- UART 0 --------------------------------------------- */ +#define UART0_RBR (*(REG32 (0xE000C000))) +#define UART0_THR (*(REG32 (0xE000C000))) +#define UART0_IER (*(REG32 (0xE000C004))) +#define UART0_IIR (*(REG32 (0xE000C008))) +#define UART0_FCR (*(REG32 (0xE000C008))) +#define UART0_LCR (*(REG32 (0xE000C00C))) +#define UART0_LSR (*(REG32 (0xE000C014))) +#define UART0_SCR (*(REG32 (0xE000C01C))) +#define UART0_DLL (*(REG32 (0xE000C000))) +#define UART0_DLM (*(REG32 (0xE000C004))) + +/* ---- UART 1 --------------------------------------------- */ +#define UART1_RBR (*(REG32 (0xE0010000))) +#define UART1_THR (*(REG32 (0xE0010000))) +#define UART1_IER (*(REG32 (0xE0010004))) +#define UART1_IIR (*(REG32 (0xE0010008))) +#define UART1_FCR (*(REG32 (0xE0010008))) +#define UART1_LCR (*(REG32 (0xE001000C))) +#define UART1_LSR (*(REG32 (0xE0010014))) +#define UART1_SCR (*(REG32 (0xE001001C))) +#define UART1_DLL (*(REG32 (0xE0010000))) +#define UART1_DLM (*(REG32 (0xE0010004))) +#define UART1_MCR (*(REG32 (0xE0010010))) +#define UART1_MSR (*(REG32 (0xE0010018))) + + +/*############################################################################## +## I2C +##############################################################################*/ + +#define I2C_I2CONSET (*(REG32 (0xE001C000))) +#define I2C_I2STAT (*(REG32 (0xE001C004))) +#define I2C_I2DAT (*(REG32 (0xE001C008))) +#define I2C_I2ADR (*(REG32 (0xE001C00C))) +#define I2C_I2SCLH (*(REG32 (0xE001C010))) +#define I2C_I2SCLL (*(REG32 (0xE001C014))) +#define I2C_I2CONCLR (*(REG32 (0xE001C018))) + + +/*############################################################################## +## SPI - Serial Peripheral Interface +##############################################################################*/ + +#define SPI_SPCR (*(REG32 (0xE0020000))) +#define SPI_SPSR (*(REG32 (0xE0020004))) +#define SPI_SPDR (*(REG32 (0xE0020008))) +#define SPI_SPCCR (*(REG32 (0xE002000C))) +#define SPI_SPTCR (*(REG32 (0xE0020010))) +#define SPI_SPTSR (*(REG32 (0xE0020014))) +#define SPI_SPTOR (*(REG32 (0xE0020018))) +#define SPI_SPINT (*(REG32 (0xE002001C))) + + +/*############################################################################## +## Timer 0 and Timer 1 +##############################################################################*/ + +/* ---- Timer 0 -------------------------------------------- */ +#define T0_IR (*(REG32 (0xE0004000))) +#define T0_TCR (*(REG32 (0xE0004004))) +#define T0_TC (*(REG32 (0xE0004008))) +#define T0_PR (*(REG32 (0xE000400C))) +#define T0_PC (*(REG32 (0xE0004010))) +#define T0_MCR (*(REG32 (0xE0004014))) +#define T0_MR0 (*(REG32 (0xE0004018))) +#define T0_MR1 (*(REG32 (0xE000401C))) +#define T0_MR2 (*(REG32 (0xE0004020))) +#define T0_MR3 (*(REG32 (0xE0004024))) +#define T0_CCR (*(REG32 (0xE0004028))) +#define T0_CR0 (*(REG32 (0xE000402C))) +#define T0_CR1 (*(REG32 (0xE0004030))) +#define T0_CR2 (*(REG32 (0xE0004034))) +#define T0_CR3 (*(REG32 (0xE0004038))) +#define T0_EMR (*(REG32 (0xE000403C))) + +/* ---- Timer 1 -------------------------------------------- */ +#define T1_IR (*(REG32 (0xE0008000))) +#define T1_TCR (*(REG32 (0xE0008004))) +#define T1_TC (*(REG32 (0xE0008008))) +#define T1_PR (*(REG32 (0xE000800C))) +#define T1_PC (*(REG32 (0xE0008010))) +#define T1_MCR (*(REG32 (0xE0008014))) +#define T1_MR0 (*(REG32 (0xE0008018))) +#define T1_MR1 (*(REG32 (0xE000801C))) +#define T1_MR2 (*(REG32 (0xE0008020))) +#define T1_MR3 (*(REG32 (0xE0008024))) +#define T1_CCR (*(REG32 (0xE0008028))) +#define T1_CR0 (*(REG32 (0xE000802C))) +#define T1_CR1 (*(REG32 (0xE0008030))) +#define T1_CR2 (*(REG32 (0xE0008034))) +#define T1_CR3 (*(REG32 (0xE0008038))) +#define T1_EMR (*(REG32 (0xE000803C))) + + +/*############################################################################## +## PWM +##############################################################################*/ + +#define PWM_IR (*(REG32 (0xE0014000))) +#define PWM_TCR (*(REG32 (0xE0014004))) +#define PWM_TC (*(REG32 (0xE0014008))) +#define PWM_PR (*(REG32 (0xE001400C))) +#define PWM_PC (*(REG32 (0xE0014010))) +#define PWM_MCR (*(REG32 (0xE0014014))) +#define PWM_MR0 (*(REG32 (0xE0014018))) +#define PWM_MR1 (*(REG32 (0xE001401C))) +#define PWM_MR2 (*(REG32 (0xE0014020))) +#define PWM_MR3 (*(REG32 (0xE0014024))) +#define PWM_MR4 (*(REG32 (0xE0014040))) +#define PWM_MR5 (*(REG32 (0xE0014044))) +#define PWM_MR6 (*(REG32 (0xE0014048))) +#define PWM_EMR (*(REG32 (0xE001403C))) +#define PWM_PCR (*(REG32 (0xE001404C))) +#define PWM_LER (*(REG32 (0xE0014050))) +#define PWM_CCR (*(REG32 (0xE0014028))) +#define PWM_CR0 (*(REG32 (0xE001402C))) +#define PWM_CR1 (*(REG32 (0xE0014030))) +#define PWM_CR2 (*(REG32 (0xE0014034))) +#define PWM_CR3 (*(REG32 (0xE0014038))) + +/*############################################################################## +## RTC +##############################################################################*/ + +/* ---- RTC: Miscellaneous Register Group ------------------ */ +#define RTC_ILR (*(REG32 (0xE0024000))) +#define RTC_CTC (*(REG32 (0xE0024004))) +#define RTC_CCR (*(REG32 (0xE0024008))) +#define RTC_CIIR (*(REG32 (0xE002400C))) +#define RTC_AMR (*(REG32 (0xE0024010))) +#define RTC_CTIME0 (*(REG32 (0xE0024014))) +#define RTC_CTIME1 (*(REG32 (0xE0024018))) +#define RTC_CTIME2 (*(REG32 (0xE002401C))) + +/* ---- RTC: Timer Control Group --------------------------- */ +#define RTC_SEC (*(REG32 (0xE0024020))) +#define RTC_MIN (*(REG32 (0xE0024024))) +#define RTC_HOUR (*(REG32 (0xE0024028))) +#define RTC_DOM (*(REG32 (0xE002402C))) +#define RTC_DOW (*(REG32 (0xE0024030))) +#define RTC_DOY (*(REG32 (0xE0024034))) +#define RTC_MONTH (*(REG32 (0xE0024038))) +#define RTC_YEAR (*(REG32 (0xE002403C))) + +/* ---- RTC: Alarm Control Group --------------------------- */ +#define RTC_ALSEC (*(REG32 (0xE0024060))) +#define RTC_ALMIN (*(REG32 (0xE0024064))) +#define RTC_ALHOUR (*(REG32 (0xE0024068))) +#define RTC_ALDOM (*(REG32 (0xE002406C))) +#define RTC_ALDOW (*(REG32 (0xE0024070))) +#define RTC_ALDOY (*(REG32 (0xE0024074))) +#define RTC_ALMON (*(REG32 (0xE0024078))) +#define RTC_ALYEAR (*(REG32 (0xE002407C))) + +/* ---- RTC: Reference Clock Divider Group ----------------- */ +#define RTC_PREINT (*(REG32 (0xE0024080))) +#define RTC_PREFRAC (*(REG32 (0xE0024084))) + + +/*############################################################################## +## WD - Watchdog +##############################################################################*/ + +#define WD_WDMOD (*(REG32 (0xE0000000))) +#define WD_WDTC (*(REG32 (0xE0000004))) +#define WD_WDFEED (*(REG32 (0xE0000008))) +#define WD_WDTV (*(REG32 (0xE000000C))) + + +/*############################################################################## +## System Control Block +##############################################################################*/ + +#define SCB_EXTINT (*(REG32 (0xE01FC140))) +#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) +#define SCB_MEMMAP (*(REG32 (0xE01FC040))) +#define SCB_PLLCON (*(REG32 (0xE01FC080))) +#define SCB_PLLCFG (*(REG32 (0xE01FC084))) +#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) +#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) +#define SCB_PCON (*(REG32 (0xE01FC0C0))) +#define SCB_PCONP (*(REG32 (0xE01FC0C4))) +#define SCB_VPBDIV (*(REG32 (0xE01FC100))) + +/*############################################################################## +## Memory Accelerator Module (MAM) +##############################################################################*/ + +#define MAM_TIM (*(REG32 (0xE01FC004))) +#define MAM_CR (*(REG32 (0xE01FC000))) + +#endif /* lpc210x_h */ + diff --git a/Demo/WizNET_DEMO_GCC_ARM7/main.c b/Demo/WizNET_DEMO_GCC_ARM7/main.c new file mode 100644 index 000000000..792e6c942 --- /dev/null +++ b/Demo/WizNET_DEMO_GCC_ARM7/main.c @@ -0,0 +1,298 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Program entry point. + * + * main() is responsible for setting up the microcontroller peripherals, then + * starting the demo application tasks. Once the tasks have been created the + * scheduler is started and main() should never complete. + * + * The demo creates the three standard 'flash' tasks to provide some visual + * feedback that the system and scheduler are still operating correctly. + * + * The HTTP server task operates at the highest priority so will always preempt + * the flash or idle task on TCP/IP events. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* Application includes. */ +#include "i2c.h" +#include "HTTP_Serv.h" +#include "flash.h" +#include "partest.h" +#include "dynamic.h" +#include "semtest.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "integer.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* Constants to setup I/O and processor. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) +#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainERROR_CHECK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Flash rates of the on board LED to indicate the health of the system. */ +#define mainNO_ERROR_DELAY ( 3000 ) +#define mainERROR_DELAY ( 500 ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) + +/*-----------------------------------------------------------*/ + +/* + * The Olimex demo board has a single built in LED. This function simply + * toggles its state. + */ +void prvToggleOnBoardLED( void ); + +/* + * Configure the processor for use with the Olimex demo board. + */ +static void prvSetupHardware( void ); + +/* + * Simply check for errors and toggle the onboard LED. + */ +static void prvErrorChecks( void *pvParameters ); + +/* + * Return true if the demo tasks are executing without error - otherwise + * return false. + */ +static void prvMainCheckOtherTasksAreStillRunning( void ); +/*-----------------------------------------------------------*/ + +/* Flag set by prvMainCheckOtherTasksAreStillExecuting(). */ +portLONG lErrorInTask = pdFALSE; + +/* + * Application entry point: + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the standard flash tasks so the WEB server is not the only thing + running. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartSemaphoreTasks( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the WEB server task and the error check task. */ + xTaskCreate( vHTTPServerTask, ( signed portCHAR * ) "HTTP", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL ); + xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainERROR_CHECK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + The JTAG pins are left as input as I'm not sure what will happen if the + Wiggler is connected after powerup - not that it would be a good idea to + do that anyway. */ + GPIO_IODIR = ~( mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise the i2c peripheral. */ + i2cInit(); + + /* Initialise the LED's used by the flash tasks. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void prvMainCheckOtherTasksAreStillRunning( void ) +{ + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + /* This function is called from more than one task. */ + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned portLONG ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static void prvErrorChecks( void *pvParameters ) +{ +portTickType xDelay = mainNO_ERROR_DELAY; + + /* The parameters are not used. */ + ( void ) pvParameters; + + for( ;; ) + { + /* How long we delay depends on whether an error has been detected + or not. Therefore the flash rate of the on board LED indicates + whether or not an error has occurred. */ + vTaskDelay( xDelay ); + + /* Update the lErrorInTask flag. */ + prvMainCheckOtherTasksAreStillRunning(); + + if( lErrorInTask ) + { + /* An error has been found so reduce the delay period and in so + doing speed up the flash rate of the on board LED. */ + xDelay = mainERROR_DELAY; + } + + prvToggleOnBoardLED(); + } +} + diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml new file mode 100644 index 000000000..a8d8820fb --- /dev/null +++ b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml @@ -0,0 +1,3038 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s new file mode 100644 index 000000000..ba5c46218 --- /dev/null +++ b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s @@ -0,0 +1,173 @@ +/***************************************************************************** + Exception handlers and startup code for ATMEL AT91SAM7. + + Copyright (c) 2004 Rowley Associates Limited. + + This file may be distributed under the terms of the License Agreement + provided with this software. + + THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE + WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + *****************************************************************************/ + +#define REG_BASE 0xFFFFF000 +#define CKGR_MOR_OFFSET 0xC20 +#define CKGR_PLLR_OFFSET 0xC2C +#define PMC_MCKR_OFFSET 0xC30 +#define PMC_SR_OFFSET 0xC68 +#define WDT_MR_OFFSET 0xD44 +#define MC_RCR_OFFSET 0xF00 +#define MC_FMR_OFFSET 0xF60 + +#define CKGR_MOR_MOSCEN (1 << 0) +#define CKGR_MOR_OSCBYPASS (1 << 1) +#define CKGR_MOR_OSCOUNT_BIT_OFFSET (8) + +#define CKGR_PLLR_DIV_BIT_OFFSET (0) +#define CKGR_PLLR_PLLCOUNT_BIT_OFFSET (8) +#define CKGR_PLLR_OUT_BIT_OFFSET (14) +#define CKGR_PLLR_MUL_BIT_OFFSET (16) +#define CKGR_PLLR_USBDIV_BIT_OFFSET (28) + +#define PMC_MCKR_CSS_MAIN_CLOCK (0x1) +#define PMC_MCKR_CSS_PLL_CLOCK (0x3) +#define PMC_MCKR_PRES_CLK (0) +#define PMC_MCKR_PRES_CLK_2 (1 << 2) +#define PMC_MCKR_PRES_CLK_4 (2 << 2) +#define PMC_MCKR_PRES_CLK_8 (3 << 2) +#define PMC_MCKR_PRES_CLK_16 (4 << 2) +#define PMC_MCKR_PRES_CLK_32 (5 << 2) +#define PMC_MCKR_PRES_CLK_64 (6 << 2) + +#define PMC_SR_MOSCS (1 << 0) +#define PMC_SR_LOCK (1 << 2) +#define PMC_SR_MCKRDY (1 << 3) +#define PMC_SR_PCKRDY0 (1 << 8) +#define PMC_SR_PCKRDY1 (1 << 9) +#define PMC_SR_PCKRDY2 (1 << 10) + +#define MC_RCR_RCB (1 << 0) + +#define MC_FMR_FWS_0FWS (0) +#define MC_FMR_FWS_1FWS (1 << 8) +#define MC_FMR_FWS_2FWS (2 << 8) +#define MC_FMR_FWS_3FWS (3 << 8) +#define MC_FMR_FMCN_BIT_OFFSET 16 + +#define WDT_MR_WDDIS (1 << 15) + + .section .vectors, "ax" + .code 32 + .align 0 + +/***************************************************************************** + Exception Vectors + *****************************************************************************/ +_vectors: + ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ + ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ + ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ + ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ + ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ + nop + ldr pc, [PC, #-0xF20] /* irq */ + ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ + +reset_handler_address: + .word reset_handler +undef_handler_address: + .word undef_handler +swi_handler_address: + .word swi_handler +pabort_handler_address: + .word pabort_handler +dabort_handler_address: + .word dabort_handler +irq_handler_address: + .word irq_handler +fiq_handler_address: + .word fiq_handler + + .section .init, "ax" + .code 32 + .align 0 + +/****************************************************************************** + Reset handler + ******************************************************************************/ +reset_handler: + + + ldr r10, =REG_BASE + + /* Set up FLASH wait state */ + ldr r0, =(50 << MC_FMR_FMCN_BIT_OFFSET) | MC_FMR_FWS_1FWS + str r0, [r10, #MC_FMR_OFFSET] + + /* Disable Watchdog */ + ldr r0, =WDT_MR_WDDIS + str r0, [r10, #WDT_MR_OFFSET] + + /* Enable the main oscillator */ + ldr r0, =(6 << CKGR_MOR_OSCOUNT_BIT_OFFSET) | CKGR_MOR_MOSCEN + str r0, [r10, #CKGR_MOR_OFFSET] + +1:/* Wait for main oscillator to stabilize */ + ldr r0, [r10, #PMC_SR_OFFSET] + tst r0, #PMC_SR_MOSCS + beq 1b + + /* Set up the PLL */ + ldr r0, =(5 << CKGR_PLLR_DIV_BIT_OFFSET) | (28 << CKGR_PLLR_PLLCOUNT_BIT_OFFSET) | (25 << CKGR_PLLR_MUL_BIT_OFFSET) + str r0, [r10, #CKGR_PLLR_OFFSET] + +1:/* Wait for PLL to lock */ + ldr r0, [r10, #PMC_SR_OFFSET] + tst r0, #PMC_SR_LOCK + beq 1b + + /* Select PLL as clock source */ + ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK | PMC_MCKR_PRES_CLK_2) + str r0, [r10, #PMC_MCKR_OFFSET] + +#ifdef __FLASH_BUILD + /* Copy exception vectors into Internal SRAM */ + mov r8, #0x00200000 + ldr r9, =_vectors + ldmia r9!, {r0-r7} + stmia r8!, {r0-r7} + ldmia r9!, {r0-r6} + stmia r8!, {r0-r6} + + /* Remap Internal SRAM to 0x00000000 */ + ldr r0, =MC_RCR_RCB + strb r0, [r10, #MC_RCR_OFFSET] +#endif + + + /* Jump to the default C runtime startup code. */ + b _start + +/****************************************************************************** + Default exception handlers + (These are declared weak symbols so they can be redefined in user code) + ******************************************************************************/ +undef_handler: + b undef_handler + +swi_handler: + b swi_handler + +pabort_handler: + b pabort_handler + +dabort_handler: + b dabort_handler + +irq_handler: + b irq_handler + +fiq_handler: + b fiq_handler + + .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js new file mode 100644 index 000000000..d7cbc435d --- /dev/null +++ b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js @@ -0,0 +1,61 @@ +/****************************************************************************** + Target Script for ATMEL AT91SAM7. + + Copyright (c) 2004 Rowley Associates Limited. + + This file may be distributed under the terms of the License Agreement + provided with this software. + + THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE + WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + ******************************************************************************/ + +function Reset() +{ + /* Reset and stop target */ + TargetInterface.pokeWord(0xFFFFFD00, 0xA500000D); // RSTC_CR + TargetInterface.waitForDebugState(1000); + /* Configure Clock */ + TargetInterface.pokeWord(0xFFFFFC20, 0x00000601); // CKGR_MOR + TargetInterface.delay(10); + TargetInterface.pokeWord(0xFFFFFC2C, 0x00191C05); // CKGR_PLLR + TargetInterface.delay(10); + TargetInterface.pokeWord(0xFFFFFC30, 0x00000007); // CKGR_MCKR + TargetInterface.delay(10); +} + +function RAMReset() +{ + Reset(); + /* Remap SRAM to 0x00000000 */ + TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR +} + +function FLASHReset() +{ + Reset(); + +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + + TargetInterface.pokeWord(0xffffffff,0xFFFFF124); + TargetInterface.pokeWord(0xffffffff,0xFFFFF128); +// disable peripheral clock Peripheral Clock Disable Register + TargetInterface.pokeWord(0xffffffff,0xFFFFFC14); + +// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register + TargetInterface.peekWord(0xFFFA0020); + TargetInterface.peekWord(0xFFFA0060); + TargetInterface.peekWord(0xFFFA00A0); + +// for (__mac_i=0;__mac_i < 8; __mac_i++) +// { + // AT91C_BASE_AIC->AIC_EOICR +// __mac_pt = TargetInterface.peekWord(0xFFFFF130); + +// } +// __message "------------------------------- AIC 2 INIT ---------------------------------------------"; + +} + diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c new file mode 100644 index 000000000..2ddff273a --- /dev/null +++ b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c @@ -0,0 +1,220 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Implements a simplistic WEB server. Every time a connection is made and + data is received a dynamic page that shows the current TCP/IP statistics + is generated and returned. The connection is then closed. + + This file was adapted from a FreeRTOS lwIP slip demo supplied by a third + party. +*/ + +/* + Changes from V3.2.2 + + + Changed the page returned by the lwIP WEB server demo to display the + task status table rather than the TCP/IP statistics. +*/ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo includes. */ +#include "BasicWEB.h" +#include "SAM7_EMAC.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "netif/loopif.h" + +/* The size of the buffer in which the dynamic WEB page is created. */ +#define webMAX_PAGE_SIZE 2048 + +/* Standard GET response. */ +#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n" + +/* The port on which we listen. */ +#define webHTTP_PORT ( 80 ) + +/* Delay on close error. */ +#define webSHORT_DELAY ( 10 ) + +/* Format of the dynamic page that is returned on each connection. */ +#define webHTML_START \ +"\ +\ +\ +\ +\r\nPage Hits = " + +#define webHTML_END \ +"\r\n\ +\r\n\ +" + +/*------------------------------------------------------------*/ + +/* + * Process an incoming connection on port 80. + * + * This simply checks to see if the incoming data contains a GET request, and + * if so sends back a single dynamically created page. The connection is then + * closed. A more complete implementation could create a task for each + * connection. + */ +static void vProcessConnection( struct netconn *pxNetCon ); + +/*------------------------------------------------------------*/ + +static void vProcessConnection( struct netconn *pxNetCon ) +{ +static portCHAR cDynamicPage[ webMAX_PAGE_SIZE ], cPageHits[ 11 ]; +struct netbuf *pxRxBuffer; +portCHAR *pcRxString; +unsigned portSHORT usLength; +static unsigned portLONG ulPageHits = 0; + + /* We expect to immediately get data. */ + pxRxBuffer = netconn_recv( pxNetCon ); + + if( pxRxBuffer != NULL ) + { + /* Where is the data? */ + netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); + + /* Is this a GET? We don't handle anything else. */ + if( !strncmp( pcRxString, "GET", 3 ) ) + { + pcRxString = cDynamicPage; + + /* Update the hit count. */ + ulPageHits++; + sprintf( cPageHits, "%lu", ulPageHits ); + + /* Write out the HTTP OK header. */ + netconn_write(pxNetCon, webHTTP_OK, (u16_t)strlen( webHTTP_OK ), NETCONN_COPY ); + + /* Generate the dynamic page... + + ... First the page header. */ + strcpy( cDynamicPage, webHTML_START ); + /* ... Then the hit count... */ + strcat( cDynamicPage, cPageHits ); + strcat( cDynamicPage, "

Task          State  Priority  Stack	#
************************************************
" );
+			/* ... Then the list of tasks and their status... */
+			vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );	
+			/* ... Finally the page footer. */
+			strcat( cDynamicPage, webHTML_END );
+
+			/* Write out the dynamically generated page. */
+			netconn_write(pxNetCon, cDynamicPage, (u16_t)strlen( cDynamicPage ), NETCONN_COPY );
+		}
+ 
+		netbuf_delete( pxRxBuffer );
+	}
+
+	netconn_close( pxNetCon );
+}
+/*------------------------------------------------------------*/
+
+void vlwIPInit( void )
+{
+    /* Initialize lwIP and its interface layer. */
+	sys_init();
+	mem_init();								
+	memp_init();
+	pbuf_init(); 
+	netif_init();
+	ip_init();
+	tcpip_init( NULL, NULL );
+}
+/*------------------------------------------------------------*/
+
+void vBasicWEBServer( void *pvParameters )
+{
+struct netconn *pxHTTPListener, *pxNewConnection;
+struct ip_addr xIpAddr, xNetMast, xGateway;
+extern err_t ethernetif_init( struct netif *netif );
+static struct netif EMAC_if;
+
+	/* Parameters are not used - suppress compiler error. */
+	( void ) pvParameters;
+
+
+	/* Create and configure the EMAC interface. */
+	IP4_ADDR(&xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3);
+	IP4_ADDR(&xNetMast,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3);
+	IP4_ADDR(&xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3);
+	netif_add(&EMAC_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input);
+
+	/* make it the default interface */
+    netif_set_default(&EMAC_if);
+
+	/* bring it up */
+    netif_set_up(&EMAC_if);
+	
+	/* Create a new tcp connection handle */
+
+ 	pxHTTPListener = netconn_new( NETCONN_TCP );
+	netconn_bind(pxHTTPListener, NULL, webHTTP_PORT );
+	netconn_listen( pxHTTPListener );
+
+	/* Loop forever */
+	for( ;; )
+	{
+		/* Wait for connection. */
+		pxNewConnection = netconn_accept(pxHTTPListener);
+
+		if(pxNewConnection != NULL)
+		{
+			/* Service connection. */
+			vProcessConnection( pxNewConnection );
+			while( netconn_delete( pxNewConnection ) != ERR_OK )
+			{
+				vTaskDelay( webSHORT_DELAY );
+			}
+		}
+	}
+}
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
new file mode 100644
index 000000000..d13de7dff
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
@@ -0,0 +1,43 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+/* The function that implements the WEB server task. */
+void vBasicWEBServer( void *pvParameters );
+
+/* Initialisation required by lwIP. */
+void vlwIPInit( void );
+
+#endif
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/Board.h b/Demo/lwIP_Demo_Rowley_ARM7/Board.h
new file mode 100644
index 000000000..f3ae3c11d
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/Board.h
@@ -0,0 +1,68 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7X Evaluation Board Features Definition File.
+*
+* Creation            : JG   20/Jun/2005
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include "AT91SAM7X256.h"
+#include "ioat91sam7x256.h"
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
+
+#define  FLASH_PAGE_NB		256
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+#define LED1            (1<<19)	// PB19
+#define LED2            (1<<20)	// PB20
+#define LED3            (1<<21)	// PB21
+#define LED4            (1<<22)	// PB22
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+
+#define SW1_MASK        (1<<21)	// PA21
+#define SW2_MASK        (1<<22)	// PA22
+#define SW3_MASK        (1<<23)	// PA23
+#define SW4_MASK        (1<<24)	// PA24
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<21)	// PA21
+#define SW2 	(1<<22)	// PA22
+#define SW3 	(1<<23)	// PA23
+#define SW4 	(1<<24)	// PA24
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c b/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
new file mode 100644
index 000000000..d9716c0ef
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
@@ -0,0 +1,69 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Cstartup_SAM7.c
+//* Object              : Low level initializations written in C for IAR
+//*                       tools
+//* 1.0   08/Sep/04 JPP	: Creation
+//* 1.10  10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
+//*----------------------------------------------------------------------------
+
+
+// Include the board file description
+#include "Board.h"
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can be use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit( void);
+void AT91F_LowLevelInit( void )
+{
+ AT91PS_PMC     pPMC = AT91C_BASE_PMC;
+
+    //* Set Flash Waite sate
+	//  Single Cycle Access at Up to 30 MHz, or 40
+	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
+	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
+
+    //* Watchdog Disable
+        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+
+	//* Set MCK at 47 923 200
+    // 1 Enabling the Main Oscillator:
+        // SCK = 1/32768 = 30.51 uSeconde
+    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
+       pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
+	// 2 Checking the Main Oscillator Frequency (Optional)
+	// 3 Setting PLL and divider:
+		// - div by 5 Fin = 3,6864 =(18,432 / 5)
+		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+		// for 96 MHz the erroe is 0.16%
+		//eld out NOT USED = 0 Fi
+       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
+                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+                         (AT91C_CKGR_MUL & (25<<16)));
+
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
+	// 4. Selection of Master Clock and Processor Clock
+        // select the PLL clock divided by 2
+       pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+}
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
new file mode 100644
index 000000000..eac73b2d8
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
@@ -0,0 +1,117 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Emac.h
+//* Object              : Emac header file
+//* Creation            : Hi   11/18/2002
+//*
+//*----------------------------------------------------------------------------
+#ifndef AT91C_EMAC_H
+#define AT91C_EMAC_H
+
+#include "lwipopts.h"
+
+
+/* Number of receive buffers */
+#define NB_RX_BUFFERS			50		
+
+/* Size of each receive buffer - DO NOT CHANGE. */
+#define ETH_RX_BUFFER_SIZE		128         
+
+/* Number of Transmit buffers */
+#define NB_TX_BUFFERS			( MEMP_NUM_PBUF / 2 )	
+
+/* Size of each Transmit buffer. */
+#define ETH_TX_BUFFER_SIZE		( PBUF_POOL_BUFSIZE  )   
+
+/* Receive Transfer descriptor structure */
+typedef struct  _AT91S_RxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:1;
+			unsigned int Rxbuf_off:2;
+			unsigned int StartOfFrame:1;
+			unsigned int EndOfFrame:1;
+			unsigned int Cfi:1;
+			unsigned int VlanPriority:3;
+			unsigned int PriorityTag:1;
+			unsigned int VlanTag:1;
+			unsigned int TypeID:1;
+			unsigned int Sa4Match:1;
+			unsigned int Sa3Match:1;
+			unsigned int Sa2Match:1;
+			unsigned int Sa1Match:1;
+			unsigned int Res1:1;
+			unsigned int ExternalAdd:1;
+			unsigned int UniCast:1;
+			unsigned int MultiCast:1;
+			unsigned int BroadCast:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
+
+
+/* Transmit Transfer descriptor structure */
+typedef struct _AT91S_TxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:4;
+			unsigned int LastBuff:1;
+			unsigned int NoCrc:1;
+			unsigned int Res1:10;
+			unsigned int BufExhausted:1;
+			unsigned int TransmitUnderrun:1;
+			unsigned int TransmitError:1;
+			unsigned int Wrap:1;
+			unsigned int BuffUsed:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
+
+#define AT91C_OWNERSHIP_BIT		0x00000001
+
+/* Receive status defintion */
+#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
+#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
+#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
+#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
+#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
+#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
+#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
+#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
+#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
+#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
+#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
+#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
+#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
+#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
+#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
+#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
+#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
+#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
+#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
+#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
+#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
+
+#define AT91C_EMAC_CLKEN 0x2
+
+#endif //* AT91C_EMAC_H
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
new file mode 100644
index 000000000..5aa34b13b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
@@ -0,0 +1,847 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * Interrupt driven driver for the EMAC peripheral.  This driver is not
+ * reentrant, re-entrancy is handled by a semaphore at the network interface
+ * level. 
+ */
+
+
+/*
+Changes from V3.2.2
+
+	+ Corrected the byte order when writing the MAC address to the MAC.
+	+ Support added for MII interfaces.  Previously only RMII was supported.
+
+Changes from V3.2.3
+
+	+ The MII interface is now the default.
+	+ Modified the initialisation sequence slightly to allow auto init more
+	  time to complete.
+*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "SAM7_EMAC.h"
+
+/* Hardware specific includes. */
+#include "Emac.h"
+#include "mii.h"
+#include "AT91SAM7X256.h"
+
+
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define USE_RMII_INTERFACE 0
+
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last few bits are zero.  These bits have special meaning for the EMAC
+peripheral and cannot be used as part of the address. */
+#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
+
+/* Bit used within the Tx descriptor status to indicate whether the
+descriptor is under the control of the EMAC or the software. */
+#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
+#define emacBUFFER_WAIT_DELAY		( 2 )
+#define emacMAX_WAIT_CYCLES			( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
+
+/* The time to block waiting for input. */
+#define emacBLOCK_TIME_WAITING_FOR_INPUT	( ( portTickType ) 100 )
+
+/* Peripheral setup for the EMAC. */
+#define emacPERIPHERAL_A_SETUP 		( ( unsigned portLONG ) AT91C_PB2_ETX0			) | \
+									( ( unsigned portLONG ) AT91C_PB12_ETXER		) | \
+									( ( unsigned portLONG ) AT91C_PB16_ECOL			) | \
+									( ( unsigned portLONG ) AT91C_PB11_ETX3			) | \
+									( ( unsigned portLONG ) AT91C_PB6_ERX1			) | \
+									( ( unsigned portLONG ) AT91C_PB15_ERXDV		) | \
+									( ( unsigned portLONG ) AT91C_PB13_ERX2			) | \
+									( ( unsigned portLONG ) AT91C_PB3_ETX1			) | \
+									( ( unsigned portLONG ) AT91C_PB8_EMDC			) | \
+									( ( unsigned portLONG ) AT91C_PB5_ERX0			) | \
+									( ( unsigned portLONG ) AT91C_PB14_ERX3			) | \
+									( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV	) | \
+									( ( unsigned portLONG ) AT91C_PB1_ETXEN			) | \
+									( ( unsigned portLONG ) AT91C_PB10_ETX2			) | \
+									( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK	) | \
+									( ( unsigned portLONG ) AT91C_PB9_EMDIO			) | \
+									( ( unsigned portLONG ) AT91C_PB7_ERXER			) | \
+									( ( unsigned portLONG ) AT91C_PB17_ERXCK		);
+
+/* Misc defines. */
+#define emacINTERRUPT_LEVEL			( 5 )
+#define emacNO_DELAY				( 0 )
+#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
+#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
+#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
+#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
+
+/*-----------------------------------------------------------*/
+
+/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
+comment above the emacADDRESS_MASK definition. */
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Buffer read by the EMAC DMA.  Must be aligned as described by the comment
+above the emacADDRESS_MASK definition. */
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Descriptors used to communicate between the program and the EMAC peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers. */
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
+
+/* The IP and Ethernet addresses are read from the header files. */
+const portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
+const unsigned char ucIPAddress[ 4 ]  = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+
+/*
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.
+ */
+void vEMACISR( void ) __attribute__ ((naked));
+
+/*
+ * Initialise both the Tx and Rx descriptors used by the EMAC.
+ */
+static void prvSetupDescriptors(void);
+
+/*
+ * Write our MAC address into the EMAC.  
+ */
+static void prvSetupMACAddress( void );
+
+/*
+ * Configure the EMAC and AIC for EMAC interrupts.
+ */
+static void prvSetupEMACInterrupt( void );
+
+/*
+ * Some initialisation functions taken from the Atmel EMAC sample code.
+ */
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
+static portBASE_TYPE xGetLinkSpeed( void );
+static portBASE_TYPE prvProbePHY( void );
+#if USE_RMII_INTERFACE != 1
+	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
+#endif
+
+
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/* Holds the index to the next buffer from which data will be read. */
+static volatile unsigned portLONG ulNextRxBuffer = 0;
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )
+{
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;
+portBASE_TYPE xWaitCycles = 0;
+portLONG lReturn = pdPASS;
+portCHAR *pcBuffer;
+unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
+
+	/* If the length of data to be transmitted is greater than each individual
+	transmit buffer then the data will be split into more than one buffer.
+	Loop until the entire length has been buffered. */
+	while( ulDataBuffered < ulLength )
+	{
+		/* Is a buffer available? */
+		while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
+		{
+			/* There is no room to write the Tx data to the Tx buffer.  Wait a
+			short while, then try again. */
+			xWaitCycles++;
+			if( xWaitCycles > emacMAX_WAIT_CYCLES )
+			{
+				/* Give up. */
+				lReturn = pdFAIL;
+				break;
+			}
+			else
+			{
+				vTaskDelay( emacBUFFER_WAIT_DELAY );
+			}
+		}
+	
+		/* lReturn will only be pdPASS if a buffer is available. */
+		if( lReturn == pdPASS )
+		{
+			portENTER_CRITICAL();
+			{
+				/* Get the address of the buffer from the descriptor, then copy 
+				the data into the buffer. */
+				pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+
+				/* How much can we write to the buffer? */
+				ulDataRemainingToSend = ulLength - ulDataBuffered;
+				if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
+				{
+					/* We can write all the remaining bytes. */
+					ulLengthToSend = ulDataRemainingToSend;
+				}
+				else
+				{
+					/* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
+					ulLengthToSend = ETH_TX_BUFFER_SIZE;
+				}
+
+				/* Copy the data into the buffer. */
+				memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
+				ulDataBuffered += ulLengthToSend;
+
+				/* Is this the last data for the frame? */
+				if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
+				{
+					/* No more data remains for this frame so we can start the 
+					transmission. */
+					ulLastBuffer = AT91C_LAST_BUFFER;
+				}
+				else
+				{
+					/* More data to come for this frame. */
+					ulLastBuffer = 0;
+				}
+	
+				/* Fill out the necessary in the descriptor to get the data sent, 
+				then move to the next descriptor, wrapping if necessary. */
+				if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
+				{				
+					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																			| ulLastBuffer
+																			| AT91C_TRANSMIT_WRAP;
+					uxTxBufferIndex = 0;
+				}
+				else
+				{
+					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																			| ulLastBuffer;
+					uxTxBufferIndex++;
+				}
+	
+				/* If this is the last buffer to be sent for this frame we can
+				start the transmission. */
+				if( ulLastBuffer )
+				{
+					AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
+				}
+			}
+			portEXIT_CRITICAL();
+		}
+		else
+		{
+			break;
+		}
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+unsigned portLONG ulEMACInputLength( void )
+{
+register unsigned portLONG ulIndex, ulLength = 0;
+
+	/* Skip any fragments.  We are looking for the first buffer that contains
+	data and has the SOF (start of frame) bit set. */
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
+	{
+		/* Ignoring this buffer.  Mark it as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* We are going to walk through the descriptors that make up this frame, 
+	but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
+	from finding the data.  Therefore use a copy of ulNextRxBuffer instead. */
+	ulIndex = ulNextRxBuffer;
+
+	/* Walk through the descriptors until we find the last buffer for this 
+	frame.  The last buffer will give us the length of the entire frame. */
+	while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
+	{
+		ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AT91C_LENGTH_FRAME;
+
+		/* Increment to the next buffer, wrapping if necessary. */
+		ulIndex++;
+		if( ulIndex >= NB_RX_BUFFERS )
+		{
+			ulIndex = 0;
+		}
+	}
+
+	return ulLength;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )
+{
+static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
+static portCHAR *pcSource;
+register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;
+
+	/* Read ulSectionLength bytes from the Rx buffers.  This is not necessarily any
+	correspondence between the length of our Rx buffers, and the length of the
+	data we are returning or the length of the data being requested.  Therefore, 
+	between calls  we have to remember not only which buffer we are currently 
+	processing, but our position within that buffer.  This would be greatly
+	simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
+	the size of each Rx buffer, and that memory fragmentation did not occur.
+	
+	This function should only be called after a call to ulEMACInputLength().
+	This will ensure ulNextRxBuffer is set to the correct buffer. */
+
+
+
+	/* vEMACRead is called with pcTo set to NULL to indicate that we are about
+	to read a new frame.  Any fragments remaining in the frame we were 
+	processing during the last call should be dropped. */
+	if( pcTo == NULL )
+	{
+		/* How many bytes are indicated as being in this buffer?  If none then
+		the buffer is completely full and the frame is contained within more
+		than one buffer. */
+
+		/* Reset our state variables ready for the next read from this buffer. */
+        pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+        ulFameBytesReadSoFar = ( unsigned portLONG ) 0;
+		ulBufferPosition = ( unsigned portLONG ) 0;
+	}
+	else
+	{
+		/* Loop until we have obtained the required amount of data. */
+        ulSectionBytesReadSoFar = 0;
+		while( ulSectionBytesReadSoFar < ulSectionLength )
+		{
+			/* We may have already read some data from this buffer.  How much
+			data remains in the buffer? */
+			ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
+
+			/* How many more bytes do we need to read before we have the 
+			required amount of data? */
+            ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
+
+			/* Do we want more data than remains in the buffer? */
+			if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
+			{
+				/* We want more data than remains in the buffer so we can 
+				write the remains of the buffer to the destination, then move
+				onto the next buffer to get the rest. */
+				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
+				ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
+                ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
+
+				/* Mark the buffer as free again. */
+				xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+				/* Move onto the next buffer. */
+				ulNextRxBuffer++;
+				if( ulNextRxBuffer >= NB_RX_BUFFERS )
+				{
+					ulNextRxBuffer = ( unsigned portLONG ) 0;
+				}
+
+				/* Reset the variables for the new buffer. */
+				pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+				ulBufferPosition = ( unsigned portLONG ) 0;
+			}
+			else
+			{
+				/* We have enough data in this buffer to send back.  Read out
+				enough data and remember how far we read up to. */
+				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
+
+				/* There may be more data in this buffer yet.  Increment our 
+				position in this buffer past the data we have just read. */
+				ulBufferPosition += ulRemainingSectionBytes;
+				ulSectionBytesReadSoFar += ulRemainingSectionBytes;
+                ulFameBytesReadSoFar += ulRemainingSectionBytes;
+
+				/* Have we now finished with this buffer? */
+				if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
+				{
+					/* Mark the buffer as free again. */
+					xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+					/* Move onto the next buffer. */
+					ulNextRxBuffer++;
+					if( ulNextRxBuffer >= NB_RX_BUFFERS )
+					{
+						ulNextRxBuffer = 0;
+					}
+	
+					pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+					ulBufferPosition = 0;
+				}
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+xSemaphoreHandle xEMACInit( void )
+{
+	/* Code supplied by Atmel -------------------------------*/
+
+	/* Disable pull up on RXDV => PHY normal mode (not in test mode),
+	PHY has internal pull down. */
+	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
+
+	#if USE_RMII_INTERFACE != 1
+	  	/* PHY has internal pull down : set MII mode. */
+	  	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
+	#endif
+
+	/* Clear PB18 <=> PHY powerdown. */
+   	AT91C_BASE_PIOB->PIO_PER = 1 << 18;
+	AT91C_BASE_PIOB->PIO_OER = 1 << 18;
+	AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
+
+	/* After PHY power up, hardware reset. */
+	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
+	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
+
+	/* Wait for hardware reset end. */
+	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
+	{
+		__asm volatile ( "NOP" );
+	}
+    __asm volatile ( "NOP" );
+
+	/* Setup the pins. */
+	AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
+	AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
+
+	/* Enable com between EMAC PHY.
+
+	Enable management port. */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+
+	/* MDC = MCK/32. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
+
+	/* Wait for PHY auto init end (rather crude delay!). */
+	vTaskDelay( emacPHY_INIT_DELAY );
+
+	/* PHY configuration. */
+	#if USE_RMII_INTERFACE != 1
+	{
+		unsigned portLONG ulControl;
+
+		/* PHY has internal pull down : disable MII isolate. */
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		ulControl &= ~BMCR_ISOLATE;
+		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
+	}
+	#endif
+
+	/* Disable management port again. */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
+
+	#if USE_RMII_INTERFACE != 1
+		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
+	#else
+		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
+		on ERFCK). */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
+	#endif
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	/* Setup the buffers and descriptors. */
+	prvSetupDescriptors();
+	
+	/* Load our MAC address into the EMAC. */
+	prvSetupMACAddress();
+
+	/* Are we connected? */
+	if( prvProbePHY() )
+	{
+		/* Enable the interrupt! */
+		portENTER_CRITICAL();
+		{
+			prvSetupEMACInterrupt();
+			vPassEMACSemaphore( xSemaphore );
+		}
+		portEXIT_CRITICAL();
+	}
+
+	return xSemaphore;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+void vClearEMACTxBuffer( void )
+{
+static unsigned portBASE_TYPE uxNextBufferToClear = 0;
+
+	/* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each 
+	Tx buffer within the frame just transmitted.  This marks all the buffers
+	as available again.
+
+	The first buffer in the frame should have the bit set automatically. */
+	if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
+	{
+		/* Loop through the other buffers in the frame. */
+		while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
+		{
+			uxNextBufferToClear++;
+
+			if( uxNextBufferToClear >= NB_TX_BUFFERS )
+			{
+				uxNextBufferToClear = 0;
+			}
+
+			xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
+		}
+	}
+
+	/* Start with the next buffer the next time a Tx interrupt is called. */
+	uxNextBufferToClear++;
+
+	/* Do we need to wrap back to the first buffer? */
+	if( uxNextBufferToClear >= NB_TX_BUFFERS )
+	{
+		uxNextBufferToClear = 0;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupDescriptors(void)
+{
+unsigned portBASE_TYPE xIndex;
+unsigned portLONG ulAddress;
+
+	/* Initialise xRxDescriptors descriptor. */
+	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will place
+		the data at this address when this descriptor is being used.  Mask off
+		the bottom bits of the address as these have special meaning. */
+		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
+
+	/* Initialise xTxDescriptors. */
+	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will read
+		data from here when the descriptor is being used. */
+		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
+
+	/* Tell the EMAC where to find the descriptors. */
+	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
+	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
+	
+	/* Clear all the bits in the receive status register. */
+	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
+
+	/* Enable the copy of data into the buffers, ignore broadcasts, 
+	and don't copy FCS. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
+
+	/* Enable Rx and Tx, plus the stats register. */
+	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
+}	
+/*-----------------------------------------------------------*/
+
+static void prvSetupMACAddress( void )
+{
+	/* Must be written SA1L then SA1H. */
+	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
+									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
+									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
+									cMACAddress[ 0 ];
+
+	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
+									cMACAddress[ 4 ];
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupEMACInterrupt( void )
+{
+	/* Create the semaphore used to trigger the EMAC task. */
+	vSemaphoreCreateBinary( xSemaphore );
+	if( xSemaphore )
+	{
+		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
+		first interrupt occurs. */
+		xSemaphoreTake( xSemaphore, emacNO_DELAY );
+		portENTER_CRITICAL();
+		{
+			/* We want to interrupt on Rx and Tx events. */
+			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
+
+			/* Enable the interrupts in the AIC. */
+			AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR );
+            AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
+		}
+		portEXIT_CRITICAL();
+	}
+}
+
+
+
+
+
+/*
+ * The following functions are initialisation functions taken from the Atmel
+ * EMAC sample code.
+ */
+
+
+static portBASE_TYPE prvProbePHY( void )
+{
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
+portBASE_TYPE xReturn = pdPASS;
+	
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Enable management port */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+   	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
+
+	/* Read the PHY ID. */
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
+	vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
+
+	/* AMD AM79C875:
+			PHY_ID1 = 0x0022
+			PHY_ID2 = 0x5541
+			Bits 3:0 Revision Number Four bit manufacturer?s revision number.
+				0001 stands for Rev. A, etc.
+	*/
+	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
+	{
+		/* Did not expect this ID. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulStatus = xGetLinkSpeed();
+
+		if( ulStatus != pdPASS )
+		{
+			xReturn = pdFAIL;
+		}
+	}
+
+	/* Disable management port */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
+									| (2 << 16) | (2 << 28)
+									| ((ucPHYAddress & 0x1f) << 23)
+									| (ucAddress << 18);
+
+	/* Wait until IDLE bit in Network Status register is cleared. */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	}
+
+	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+/*-----------------------------------------------------------*/
+
+#if USE_RMII_INTERFACE != 1
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
+								| (2 << 16) | (1 << 28)
+								| ((ucPHYAddress & 0x1f) << 23)
+								| (ucAddress << 18))
+								| (ulValue & 0xffff);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	};
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+#endif
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xGetLinkSpeed( void )
+{
+	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
+
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Link status is latched, so read twice to get current value */
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+
+	if( !( ulBMSR & BMSR_LSTATUS ) )
+	{	
+		/* No Link. */
+		return pdFAIL;
+	}
+
+	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
+	if (ulBMCR & BMCR_ANENABLE)
+	{				
+		/* AutoNegotiation is enabled. */
+		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
+		{
+			/* Auto-negotitation in progress. */
+			return pdFAIL;				
+		}		
+
+		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
+		{
+			ulSpeed = SPEED_100;
+		}
+		else
+		{
+			ulSpeed = SPEED_10;
+		}
+
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
+		{
+			ulDuplex = DUPLEX_FULL;
+		}
+		else
+		{
+			ulDuplex = DUPLEX_HALF;
+		}
+	}
+	else
+	{
+		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
+		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* Update the MAC */
+	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
+	if( ulSpeed == SPEED_100 )
+	{
+		if( ulDuplex == DUPLEX_FULL )
+		{
+			/* 100 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		}
+		else
+		{					
+			/* 100 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
+		}
+	}
+	else
+	{
+		if (ulDuplex == DUPLEX_FULL)
+		{
+			/* 10 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
+		}
+		else
+		{			/* 10 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
+		}
+	}
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vEMACWaitForInput( void )
+{
+	/* Just wait until we are signled from an ISR that data is available, or
+	we simply time out. */
+	xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
new file mode 100644
index 000000000..9ce42af0b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
@@ -0,0 +1,120 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+Changes from V3.2.4
+
+	+ Modified the default MAC address as the one used previously was not liked
+	  by some routers.
+
+*/
+
+#ifndef SAM_7_EMAC_H
+#define SAM_7_EMAC_H
+
+/* MAC address definition.  The MAC address must be unique on the network. */
+#define emacETHADDR0 0
+#define emacETHADDR1 0xbd
+#define emacETHADDR2 0x33
+#define emacETHADDR3 0x06
+#define emacETHADDR4 0x68
+#define emacETHADDR5 0x22
+
+/* The IP address being used. */
+#define emacIPADDR0 172
+#define emacIPADDR1 25
+#define emacIPADDR2 218
+#define emacIPADDR3 205
+
+/* The gateway address being used. */
+#define emacGATEWAY_ADDR0 172
+#define emacGATEWAY_ADDR1 25
+#define emacGATEWAY_ADDR2 218
+#define emacGATEWAY_ADDR3 3
+
+/* The network mask being used. */
+#define emacNET_MASK0 255
+#define emacNET_MASK1 255
+#define emacNET_MASK2 0
+#define emacNET_MASK3 0
+
+/*
+ * Initialise the EMAC driver.  If successful a semaphore is returned that
+ * is used by the EMAC ISR to indicate that Rx packets have been received.
+ * If the initialisation fails then NULL is returned.
+ */
+xSemaphoreHandle xEMACInit( void );
+
+/*
+ * Send ulLength bytes from pcFrom.  This copies the buffer to one of the
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
+ * If lEndOfFrame is true then the data being copied is the end of the frame
+ * and the frame can be transmitted. 
+ */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );
+
+/*
+ * Frames can be read from the EMAC in multiple sections.
+ * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.  
+ * ulTotalFrameLength is the size of the entire frame.  Generally vEMACRead
+ * will be repetedly called until the sum of all the ulSectionLenths totals
+ * the value of ulTotalFrameLength.
+ */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );
+
+/*
+ * The EMAC driver and interrupt service routines are defined in different 
+ * files as the driver is compiled to THUMB, and the ISR to ARM.  This function
+ * simply passes the semaphore used to communicate between the two.
+ */
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );
+
+/* 
+ * Called by the Tx interrupt, this function traverses the buffers used to
+ * hold the frame that has just completed transmission and marks each as
+ * free again.
+ */
+void vClearEMACTxBuffer( void );
+
+/*
+ * Suspend on a semaphore waiting either for the semaphore to be obtained 
+ * or a timeout.  The semaphore is used by the EMAC ISR to indicate that
+ * data has been received and is ready for processing.
+ */
+void vEMACWaitForInput( void );
+
+/*
+ * Return the length of the next frame in the receive buffers.
+ */
+unsigned portLONG ulEMACInputLength( void );
+
+#endif
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
new file mode 100644
index 000000000..326a992cd
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
@@ -0,0 +1,106 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+Changes from V3.2.4
+
+	+ Also read the EMAC_RSR register in the EMAC ISR as a work around the 
+	  the EMAC bug that can reset the RX bit in EMAC_ISR register before the
+	  bit has been read.
+*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#include "SAM7_EMAC.h"
+#include "AT91SAM7X256.h"
+
+/*-----------------------------------------------------------*/
+
+/* The semaphore used to signal the arrival of new data to the interface
+task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+void vEMACISR( void ) __attribute__((naked));
+
+/*-----------------------------------------------------------*/
+/*
+ * The EMAC ISR.  Handles both Tx and Rx complete interrupts.
+ */
+void vEMACISR( void )
+{
+	/* This ISR can cause a context switch, so the first statement must be a
+	call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+	variable declarations. */
+	portENTER_SWITCHING_ISR();
+
+	/* Variable definitions can be made now. */
+	volatile unsigned portLONG ulIntStatus, ulEventStatus;
+	portBASE_TYPE xSwitchRequired = pdFALSE;
+    extern void vClearEMACTxBuffer( void );
+
+	/* Find the cause of the interrupt. */
+	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
+	ulEventStatus = AT91C_BASE_EMAC->EMAC_RSR;
+
+	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulEventStatus & AT91C_EMAC_REC ) )
+	{
+		/* A frame has been received, signal the lwIP task so it can process
+		the Rx descriptors. */
+		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
+		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
+	}
+
+	ulEventStatus = AT91C_BASE_EMAC->EMAC_TSR;
+	if( ( ulIntStatus & AT91C_EMAC_TCOMP ) || ( ulEventStatus & AT91C_EMAC_COMP ) )
+	{
+		/* A frame has been transmitted.  Mark all the buffers used by the
+		frame just transmitted as free again. */
+		vClearEMACTxBuffer();
+		AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
+	}
+
+	/* Clear the interrupt. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+
+	/* If a task was woken by either a frame being received then we may need to 
+	switch to another task. */
+	portEXIT_SWITCHING_ISR( xSwitchRequired );
+}
+/*-----------------------------------------------------------*/
+
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )
+{
+	/* Simply store the semaphore that should be used by the ISR. */
+	xSemaphore = xCreatedSemaphore;
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
new file mode 100644
index 000000000..29b2f53d5
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
@@ -0,0 +1,105 @@
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_RESV                0x1c00  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+#define SPEED_10				10
+#define SPEED_100				100
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF				0x00
+#define DUPLEX_FULL				0x01
+
+/* PHY ID */
+#define MII_DM9161_ID     0x0181b8a0
+#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
+
+#define AT91C_PHY_ADDR	31
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
new file mode 100644
index 000000000..9531cca35
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
@@ -0,0 +1,79 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+/* The SWI is used by the scheduler. */
+#define vPortYieldProcessor swi_handler
+
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			1
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 110 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 24000 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		0
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_xTaskGetCurrentTaskHandle	1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c b/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
new file mode 100644
index 000000000..a05d22d1a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
@@ -0,0 +1,86 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Hardware specific includes. */
+#include "Board.h"
+
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
+ * or toggled.
+ *-----------------------------------------------------------*/
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
+
+void vParTestInitialise( void )
+{	
+	/* Start with all LED's off. */
+    AT91C_BASE_PIOB->PIO_SODR = LED_MASK;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( xValue )
+		{
+			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
+		}
+		else
+		{
+			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( AT91C_BASE_PIOB->PIO_PDSR & ulLED_MASK[ uxLED ] )
+		{
+			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
+		}
+		else
+		{
+			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
+		}
+	}
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf b/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
new file mode 100644
index 000000000..eb3cb61c1
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
@@ -0,0 +1,48 @@
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%ATMEL%
+LayoutFile=layout.inf
+DriverVer=10/15/1999,5.0.2153.1
+
+[MANUFACTURER]
+%FreeRTOS%=FreeRTOS
+
+[FreeRTOS]
+%FreeRTOS_CDC%=Reader,USB\VID_EB03&PID_0920
+
+[Reader_Install.NTx86]
+;Windows2000
+
+[DestinationDirs]
+DefaultDestDir=12
+Reader.NT.Copy=12
+
+[Reader.NT]
+CopyFiles=Reader.NT.Copy
+AddReg=Reader.NT.AddReg
+
+[Reader.NT.Copy]
+usbser.sys
+
+[Reader.NT.AddReg]
+HKR,,NTMPDriver,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+[Reader.NT.Services]
+AddService = usbser, 0x00000002,Service_Inst
+
+[Service_Inst]
+DisplayName = %Serial.SvcDesc%
+ServiceType = 1 ; SERVICE_KERNEL_DRIVER
+StartType = 3 ; SERVICE_DEMAND_START
+ErrorControl = 1 ;SERVICE_ERROR_NORMAL
+ServiceBinary = %12%\usbser.sys
+LoadOrderGroup = Base
+
+[Strings]
+FreeRTOS = "FreeRTOS"
+FreeRTOS_CDC = "FreeRTOS CDC Demo"
+Serial.SvcDesc = "USB Serial emulation driver"
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
new file mode 100644
index 000000000..4ff961fb6
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
@@ -0,0 +1,863 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+	USB Communications Device Class driver.
+	Implements task vUSBCDCTask and provides an Abstract Control Model serial 
+	interface.  Control is through endpoint 0, device-to-host notification is 
+	provided by interrupt-in endpoint 3, and raw data is transferred through 
+	bulk endpoints 1 and 2.
+
+	- developed from original FreeRTOS HID example by Scott Miller
+	- modified to support 3.2 GCC by najay
+*/
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Demo board includes. */
+#include "Board.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo app includes. */
+#include "USB-CDC.h"
+#include "descriptors.h"
+
+#define usbNO_BLOCK ( ( portTickType ) 0 )
+
+/* Reset all endpoints */
+static void prvResetEndPoints( void );
+
+/* Clear pull up resistor to detach device from host */
+static void vDetachUSBInterface( void );
+
+/* Set up interface and initialize variables */
+static void vInitUSBInterface( void );
+
+/* Handle control endpoint events. */
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage );
+
+/* Handle standard device requests. */
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle standard interface requests. */
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle endpoint requests. */
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle class interface requests. */
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest );
+
+/* Prepare control data transfer.  prvSendNextSegment starts transfer. */
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor );
+
+/* Send next segment of data for the control transfer */
+static void prvSendNextSegment( void );
+
+/* Send stall - used to respond to unsupported requests */
+static void prvSendStall( void );
+
+/* Send a zero-length (null) packet */
+static void prvSendZLP( void );
+
+/* Handle requests for standard interface descriptors */
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest );
+
+/*------------------------------------------------------------*/
+
+/* File scope static variables */
+static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0;
+static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0;
+static eDRIVER_STATE eDriverState = eNOTHING;
+
+/* Incoming and outgoing control data structures */
+static xCONTROL_MESSAGE pxControlTx;
+static xCONTROL_MESSAGE pxControlRx;
+
+/* Queue holding pointers to pending messages */
+xQueueHandle xUSBInterruptQueue; 
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted.  Rx queue must be larger than FIFO size. */
+static xQueueHandle xRxCDC; 
+static xQueueHandle xTxCDC; 
+
+/* Line coding - 115,200 baud, N-8-1 */
+static const unsigned portCHAR pxLineCoding[] = { 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08 };
+
+/* Status variables. */
+static unsigned portCHAR ucControlState;
+static unsigned int uiCurrentBank;
+
+
+/*------------------------------------------------------------*/
+
+
+void vUSBCDCTask( void *pvParameters )
+{
+xISRStatus *pxMessage;
+unsigned portLONG ulStatus;
+unsigned portLONG ulRxBytes;
+unsigned portCHAR ucByte;
+portBASE_TYPE xByte;
+
+	( void ) pvParameters;
+
+	/* Disconnect USB device from hub.  For debugging - causes host to register reset */
+	portENTER_CRITICAL();
+		 vDetachUSBInterface();
+	portEXIT_CRITICAL();
+	
+	vTaskDelay( portTICK_RATE_MS * 60 );
+
+	/* Init USB interface */
+	portENTER_CRITICAL();
+		vInitUSBInterface();
+	portEXIT_CRITICAL();
+	
+	/* Main task loop.  Process incoming endpoint 0 interrupts, handle data transfers. */
+	 
+	for( ;; )
+	{
+		/* Look for data coming from the ISR. */
+		if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORTEST_DELAY ) )
+		{
+			if( pxMessage->ulISR & AT91C_UDP_EPINT0 )
+			{
+				/* All endpoint 0 interrupts are handled here. */
+				prvProcessEndPoint0Interrupt( pxMessage );
+			}
+
+			if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES )
+			{
+				/* End of bus reset - reset the endpoints and de-configure. */
+				prvResetEndPoints();		
+			}
+		}
+		
+		/* See if we're ready to send and receive data. */
+		if( eDriverState == eREADY_TO_SEND && ucControlState ) 
+		{
+			if( ( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] & AT91C_UDP_TXPKTRDY) ) && uxQueueMessagesWaiting( xTxCDC ) )
+			{
+				for( xByte = 0; xByte < 64; xByte++ )
+				{				   
+					if( !xQueueReceive( xTxCDC, &ucByte, 0 ) ) 
+					{
+						/* No data buffered to transmit. */
+						break;
+					}
+
+					/* Got a byte to transmit. */
+					AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_2 ] = ucByte;
+				} 
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] |= AT91C_UDP_TXPKTRDY;
+			}
+
+			/* Check for incoming data (host-to-device) on endpoint 1. */
+			while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & (AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1) )
+			{
+				ulRxBytes = (AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] >> 16) & usbRX_COUNT_MASK;
+
+				/* Only process FIFO if there's room to store it in the queue */
+				if( ulRxBytes < ( USB_CDC_QUEUE_SIZE - uxQueueMessagesWaiting( xRxCDC ) ) )
+				{
+					while( ulRxBytes-- )
+					{
+						ucByte = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ];
+						xQueueSend( xRxCDC, &ucByte, 0 );
+					}
+
+					/* Release the FIFO */
+					portENTER_CRITICAL();
+					{
+						ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
+						usbCSR_CLEAR_BIT( &ulStatus, uiCurrentBank );
+						AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus;
+					}
+					portEXIT_CRITICAL();
+
+					/* Re-enable endpoint 1's interrupts */
+					AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
+				
+					/* Update the current bank in use */
+					if( uiCurrentBank == AT91C_UDP_RX_DATA_BK0 ) 
+					{
+						uiCurrentBank = AT91C_UDP_RX_DATA_BK1;
+					}
+					else 
+					{
+						uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+					}
+
+				}
+				else 
+				{
+					break;
+				}
+			}
+		}
+	}
+}
+/*------------------------------------------------------------*/
+
+void vUSBSendByte( portCHAR cByte )
+{
+	/* Queue the byte to be sent.  The USB task will send it. */
+	xQueueSend( xTxCDC, &cByte, usbNO_BLOCK );
+}
+/*------------------------------------------------------------*/
+
+static void prvSendZLP( void )
+{
+unsigned portLONG ulStatus;
+
+	/* Wait until the FIFO is free - even though we are not going to use it.
+	THERE IS NO TIMEOUT HERE! */
+	while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
+	{
+		vTaskDelay( usbSHORTEST_DELAY );
+	}
+
+	portENTER_CRITICAL();
+	{
+		/* Cancel any further pending data */
+		pxControlTx.ulTotalDataLength = pxControlTx.ulNextCharIndex;
+
+		/* Set the TXPKTRDY bit to cause a transmission with no data. */
+		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_TXPKTRDY );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+	}
+	portEXIT_CRITICAL();
+}
+/*------------------------------------------------------------*/
+
+static void prvSendStall( void )
+{
+	unsigned portLONG ulStatus;
+
+	portENTER_CRITICAL();
+	{
+		/* Force a stall by simply setting the FORCESTALL bit in the CSR. */
+		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+	}
+	portEXIT_CRITICAL();
+}
+/*------------------------------------------------------------*/
+
+static void prvResetEndPoints( void )
+{
+unsigned portLONG ulTemp;
+
+	eDriverState = eJUST_RESET;
+	ucControlState = 0;
+
+	/* Reset all the end points. */
+	AT91C_BASE_UDP->UDP_RSTEP  = usbEND_POINT_RESET_MASK;
+	AT91C_BASE_UDP->UDP_RSTEP  = ( unsigned portLONG ) 0x00;
+
+	/* Enable data to be sent and received. */
+	AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;
+
+	/* Repair the configuration end point. */
+	portENTER_CRITICAL();
+	{
+		ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
+		AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT0;
+	}
+	portEXIT_CRITICAL();
+	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+}
+/*------------------------------------------------------------*/
+
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage )
+{
+static xUSB_REQUEST xRequest;
+unsigned portLONG ulRxBytes;
+
+	/* Get number of bytes received, if any */
+	ulRxBytes = pxMessage->ulCSR0 >> 16;
+	ulRxBytes &= usbRX_COUNT_MASK;
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP )
+	{
+		/* We received a TX complete interrupt.  What we do depends on
+		what we sent to get this interrupt. */
+
+		if( eDriverState == eJUST_GOT_CONFIG )
+		{
+			/* We sent an acknowledgement of a SET_CONFIG request.  We
+			are now at the end of the enumeration.
+			
+			TODO: Config 0 sets unconfigured state, should enter Address state.
+			Request for unsupported config should stall. */
+			AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;
+			
+			/* Set up endpoints */
+			portENTER_CRITICAL();
+			{
+				unsigned portLONG ulTemp;
+
+				/* Set endpoint 1 to bulk-out */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;		
+				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
+				/* Set endpoint 2 to bulk-in */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] = ulTemp;		
+				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT2;
+					/* Set endpoint 3 to interrupt-in, enable it, and enable interrupts */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] = ulTemp;		
+				/*AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT3 );				 */
+			}
+			portEXIT_CRITICAL();
+
+			eDriverState = eREADY_TO_SEND;
+		}		
+		else if( eDriverState == eJUST_GOT_ADDRESS )
+		{
+			/* We sent an acknowledgement of a SET_ADDRESS request.  Move
+			to the addressed state. */
+			if( ulReceivedAddress != ( unsigned portLONG ) 0 )
+			{			
+				AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;
+			}
+			else
+			{
+				AT91C_BASE_UDP->UDP_GLBSTATE = 0;
+			}			
+
+			AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress );		
+			eDriverState = eNOTHING;
+		}
+		else
+		{		
+			/* The TXCOMP was not for any special type of transmission.  See
+			if there is any more data to send. */
+			prvSendNextSegment();
+		}
+	}
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 )
+	{
+		/* Received a control data packet.  May be a 0-length ACK or a data stage. */
+		unsigned portCHAR ucBytesToGet;
+	 
+		/* Got data.  Cancel any outgoing data. */
+		pxControlTx.ulNextCharIndex = pxControlTx.ulTotalDataLength;
+		
+		 /* Determine how many bytes we need to receive. */
+		ucBytesToGet = pxControlRx.ulTotalDataLength - pxControlRx.ulNextCharIndex;
+		if( ucBytesToGet > ulRxBytes ) 
+		{	
+			ucBytesToGet = ulRxBytes;
+		}
+
+		/* If we're not expecting any data, it's an ack - just quit now. */
+		if( !ucBytesToGet )
+		{
+			 return;
+		}
+
+		/* Get the required data and update the index. */
+		memcpy( pxControlRx.ucBuffer, pxMessage->ucFifoData, ucBytesToGet );
+		pxControlRx.ulNextCharIndex += ucBytesToGet;	
+	}
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP )
+	{
+		/* Received a SETUP packet.  May be followed by data packets. */
+
+		if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES )
+		{		 		
+			/* Create an xUSB_REQUEST variable from the raw bytes array. */
+
+			xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ];
+			xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ];
+
+			xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ];
+			xRequest.usValue <<= 8;
+			xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ];
+						
+			xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ];
+			xRequest.usIndex <<= 8;
+			xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ];
+			
+			xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ];
+			xRequest.usLength <<= 8;
+			xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ];
+
+			pxControlRx.ulNextCharIndex = 0;
+			if( ! (xRequest.ucReqType & 0x80) ) /* Host-to-Device transfer, may need to get data first */
+			{
+				if( xRequest.usLength > usbMAX_CONTROL_MESSAGE_SIZE )
+				{	
+					/* Too big!  No space for control data, stall and abort. */
+					prvSendStall();
+					return;
+				}
+
+				pxControlRx.ulTotalDataLength = xRequest.usLength;
+			}
+			else
+			{
+				/* We're sending the data, don't wait for any. */
+				pxControlRx.ulTotalDataLength = 0; 
+			}
+		}
+	}
+
+	/* See if we've got a pending request and all its associated data ready */
+	if( ( pxMessage->ulCSR0 & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RXSETUP ) ) 
+		&& ( pxControlRx.ulNextCharIndex >= pxControlRx.ulTotalDataLength ) )
+	{
+		unsigned portCHAR ucRequest;
+
+		/* Manipulate the ucRequestType and the ucRequest parameters to 
+		generate a zero based request selection.  This is just done to 
+		break up the requests into subsections for clarity.  The 
+		alternative would be to have more huge switch statement that would
+		be difficult to optimise. */
+		ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 );
+		ucRequest |= ( xRequest.ucReqType & 0x03 );
+			
+		switch( ucRequest )
+		{
+			case usbSTANDARD_DEVICE_REQUEST:	
+				/* Standard Device request */
+				prvHandleStandardDeviceRequest( &xRequest );
+				break;
+
+			case usbSTANDARD_INTERFACE_REQUEST:	
+				/* Standard Interface request */
+				prvHandleStandardInterfaceRequest( &xRequest );
+				break;
+
+			case usbSTANDARD_END_POINT_REQUEST:	
+				/* Standard Endpoint request */
+				prvHandleStandardEndPointRequest( &xRequest );
+				break;
+
+			case usbCLASS_INTERFACE_REQUEST:	
+				/* Class Interface request */
+				prvHandleClassInterfaceRequest( &xRequest );
+				break;
+
+			default:	/* This is not something we want to respond to. */
+				prvSendStall();	
+		}
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest )
+{
+	/* The type is in the high byte.  Return whatever has been requested. */
+	switch( ( pxRequest->usValue & 0xff00 ) >> 8 )
+	{
+		case usbDESCRIPTOR_TYPE_DEVICE:
+			prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE );
+			break;
+
+		case usbDESCRIPTOR_TYPE_CONFIGURATION:
+			prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE );
+			break;
+
+		case usbDESCRIPTOR_TYPE_STRING:
+
+			/* The index to the string descriptor is the lower byte. */
+			switch( pxRequest->usValue & 0xff )
+			{			
+				case usbLANGUAGE_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE );
+					break;
+
+				case usbMANUFACTURER_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE );
+					break;
+
+				case usbPRODUCT_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE );
+					break;
+
+				case usbCONFIGURATION_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE );
+					break;
+
+				case usbINTERFACE_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE );
+					break;
+
+				default:
+					prvSendStall();
+					break;
+			}
+			break;
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest )
+{
+unsigned portSHORT usStatus = 0;
+
+	switch( pxRequest->ucRequest )
+	{
+		case usbGET_STATUS_REQUEST:
+			/* Just send two byte dummy status. */
+			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
+			break;
+
+		case usbGET_DESCRIPTOR_REQUEST:
+			/* Send device descriptor */
+			prvGetStandardDeviceDescriptor( pxRequest );
+			break;
+
+		case usbGET_CONFIGURATION_REQUEST:
+			/* Send selected device configuration */
+			prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE );
+			break;
+
+		case usbSET_FEATURE_REQUEST:
+			prvSendZLP();
+			break;
+
+		case usbSET_ADDRESS_REQUEST:			
+			/* Get assigned address and send ack, but don't implement new address until we get a TXCOMP */
+			prvSendZLP();			
+			eDriverState = eJUST_GOT_ADDRESS;			
+			ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue;
+			break;
+
+		case usbSET_CONFIGURATION_REQUEST:
+			/* Ack SET_CONFIGURATION request, but don't implement until TXCOMP */
+			ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff );
+			eDriverState = eJUST_GOT_CONFIG;
+			prvSendZLP();
+			break;
+
+		default:
+			/* Any unsupported request results in a STALL response. */
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest )
+{
+	switch( pxRequest->ucRequest )
+	{
+		case usbSEND_ENCAPSULATED_COMMAND:
+			prvSendStall();
+			break;
+
+		case usbGET_ENCAPSULATED_RESPONSE:
+			prvSendStall();
+			break;
+
+		case usbSET_LINE_CODING:
+			/* Set line coding - baud rate, data bits, parity, stop bits */
+			prvSendZLP();
+			memcpy( ( void * ) pxLineCoding, pxControlRx.ucBuffer, sizeof( pxLineCoding ) );
+			break;
+
+		case usbGET_LINE_CODING:
+			/* Get line coding */
+			prvSendControlData( (unsigned portCHAR *) &pxLineCoding, pxRequest->usLength, sizeof( pxLineCoding ), pdFALSE );
+			break;
+
+		case usbSET_CONTROL_LINE_STATE:
+			/* D0: 1=DTR, 0=No DTR,  D1: 1=Activate Carrier, 0=Deactivate carrier (RTS, half-duplex) */
+			prvSendZLP();
+			ucControlState = pxRequest->usValue;
+			break;
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest )
+{
+	switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 )
+	{
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest )
+{
+unsigned portSHORT usStatus = 0;
+
+	switch( pxRequest->ucRequest )
+	{
+		case usbGET_STATUS_REQUEST:
+			/* Send dummy 2 bytes. */
+			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
+			break;
+
+		case usbGET_DESCRIPTOR_REQUEST:
+			prvGetStandardInterfaceDescriptor( pxRequest ); 
+			break;
+
+		/* This minimal implementation does not respond to these. */
+		case usbGET_INTERFACE_REQUEST:
+		case usbSET_FEATURE_REQUEST:
+		case usbSET_INTERFACE_REQUEST:	
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest )
+{
+	switch( pxRequest->ucRequest )
+	{
+		/* This minimal implementation does not expect to respond to these. */
+		case usbGET_STATUS_REQUEST:
+		case usbCLEAR_FEATURE_REQUEST: 
+		case usbSET_FEATURE_REQUEST:
+
+		default:			
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vDetachUSBInterface( void)
+{
+	/* Setup the PIO for the USB pull up resistor. */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
+
+
+	/* Disable pull up */
+	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
+} 
+/*-----------------------------------------------------------*/
+
+static void vInitUSBInterface( void )
+{
+extern void ( vUSB_ISR )( void );
+
+	/* Create the queue used to communicate between the USB ISR and task. */
+	xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) );
+	
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
+	xTxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE + 1, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
+
+	if( (!xUSBInterruptQueue) || (!xRxCDC) || (!xTxCDC) )
+	{	
+		/* Not enough RAM to create queues!. */
+		return;
+	}
+	
+	/* Initialise a few state variables. */
+	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
+	pxControlRx.ulNextCharIndex = ( unsigned portLONG ) 0;
+	ucUSBConfig = ( unsigned portCHAR ) 0;
+	eDriverState = eNOTHING;
+	ucControlState = 0;
+	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+
+
+	/* HARDWARE SETUP */
+
+	/* Set the PLL USB Divider */
+	AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
+
+	/* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */
+	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;
+	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);
+
+	/* Setup the PIO for the USB pull up resistor. */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
+
+
+	/* Start without the pullup - this will get set at the end of this 
+	function. */
+   	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
+
+
+	/* When using the USB debugger the peripheral registers do not always get
+	set to the correct default values.  To make sure set the relevant registers
+	manually here. */
+	AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff;
+	AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff;
+	AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 2 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 3 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_GLBSTATE = 0;
+	AT91C_BASE_UDP->UDP_FADDR = 0;
+
+	/* Enable the transceiver. */
+	AT91C_UDP_TRANSCEIVER_ENABLE = 0;
+
+	/* Enable the USB interrupts - other interrupts get enabled as the 
+	enumeration process progresses. */
+	AT91F_AIC_ConfigureIt( AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vUSB_ISR );
+	AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_UDP;
+
+
+	/* Wait a short while before making our presence known. */
+	vTaskDelay( usbINIT_DELAY );
+	AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA16;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor )
+{
+	if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) )
+	{
+		/* Cap the data length to that requested. */
+		ulLengthToSend = ( unsigned portSHORT ) usRequestedLength;
+	}
+	else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor )
+	{
+		/* We are sending a descriptor.  If the descriptor is an exact 
+		multiple of the FIFO length then it will have to be terminated
+		with a NULL packet.  Set the state to indicate this if
+		necessary. */
+		if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 )
+		{
+			eDriverState = eSENDING_EVEN_DESCRIPTOR;
+		}
+	}
+
+	/* Here we assume that the previous message has been sent.  THERE IS NO
+	BUFFER OVERFLOW PROTECTION HERE.
+
+	Copy the data to send into the buffer as we cannot send it all at once
+	(if it is greater than 8 bytes in length). */
+	memcpy( pxControlTx.ucBuffer, pucData, ulLengthToSend );
+
+	/* Reinitialise the buffer index so we start sending from the start of 
+	the data. */
+	pxControlTx.ulTotalDataLength = ulLengthToSend;
+	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
+
+	/* Send the first 8 bytes now.  The rest will get sent in response to 
+	TXCOMP interrupts. */
+	prvSendNextSegment();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendNextSegment( void )
+{
+volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend;
+
+	/* Is there any data to send? */
+	if( pxControlTx.ulTotalDataLength > pxControlTx.ulNextCharIndex )
+	{
+		ulLengthLeftToSend = pxControlTx.ulTotalDataLength - pxControlTx.ulNextCharIndex;
+	
+		/* We can only send 8 bytes to the fifo at a time. */
+		if( ulLengthLeftToSend > usbFIFO_LENGTH )
+		{
+			ulNextLength = usbFIFO_LENGTH;
+		}
+		else
+		{
+			ulNextLength = ulLengthLeftToSend;
+		}
+
+		/* Wait until we can place data in the fifo.  THERE IS NO TIMEOUT
+		HERE! */
+		while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
+		{
+			vTaskDelay( usbSHORTEST_DELAY );
+		}
+
+		/* Write the data to the FIFO. */
+		while( ulNextLength > ( unsigned portLONG ) 0 )
+		{
+			AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxControlTx.ucBuffer[ pxControlTx.ulNextCharIndex ];
+	
+			ulNextLength--;
+			pxControlTx.ulNextCharIndex++;
+		}
+	
+		/* Start the transmission. */
+		portENTER_CRITICAL();
+		{
+			ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+			usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) );
+			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+		}
+		portEXIT_CRITICAL();
+	}
+	else
+	{
+		/* There is no data to send.  If we were sending a descriptor and the 
+		descriptor was an exact multiple of the max packet size then we need
+		to send a null to terminate the transmission. */
+		if( eDriverState == eSENDING_EVEN_DESCRIPTOR )
+		{
+			prvSendZLP();
+			eDriverState = eNOTHING;
+		}
+	}
+}
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
new file mode 100644
index 000000000..753492735
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
@@ -0,0 +1,86 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef USB_CDC_H
+#define USB_CDC_H
+
+#include "usb.h"
+
+#define USB_CDC_QUEUE_SIZE    200
+
+/* Structure used to take a snapshot of the USB status from within the ISR. */
+typedef struct X_ISR_STATUS
+{
+	unsigned portLONG ulISR;
+	unsigned portLONG ulCSR0;
+	unsigned portCHAR ucFifoData[ 8 ];
+} xISRStatus;
+
+/* Structure used to hold the received requests. */
+typedef struct 
+{
+	unsigned portCHAR ucReqType;
+	unsigned portCHAR ucRequest;
+	unsigned portSHORT usValue;
+	unsigned portSHORT usIndex;
+	unsigned portSHORT usLength;
+} xUSB_REQUEST;
+
+typedef enum
+{
+	eNOTHING,
+	eJUST_RESET,
+	eJUST_GOT_CONFIG,
+	eJUST_GOT_ADDRESS,
+	eSENDING_EVEN_DESCRIPTOR,
+	eREADY_TO_SEND
+} eDRIVER_STATE;
+
+/* Structure used to control the data being sent to the host. */
+typedef struct
+{
+	unsigned portCHAR ucBuffer[ usbMAX_CONTROL_MESSAGE_SIZE ];
+	unsigned portLONG ulNextCharIndex;
+	unsigned portLONG ulTotalDataLength;
+} xCONTROL_MESSAGE;
+
+/*-----------------------------------------------------------*/
+void vUSBCDCTask( void *pvParameters );
+
+/* Send cByte down the USB port.  Characters are simply buffered and not
+sent unless the port is connected. */
+void vUSBSendByte( portCHAR cByte );
+
+
+#endif
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
new file mode 100644
index 000000000..5f0196b42
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
@@ -0,0 +1,160 @@
+/*
+  FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+  This file is part of the FreeRTOS distribution.
+
+  FreeRTOS is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  FreeRTOS is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with FreeRTOS; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+  A special exception to the GPL can be applied should you wish to distribute
+  a combined work that includes FreeRTOS, without being obliged to provide
+  the source code for any proprietary components.  See the licensing section 
+  of http://www.FreeRTOS.org for full details of how and when the exception
+  can be applied.
+
+  ***************************************************************************
+  See http://www.FreeRTOS.org for documentation, latest information, license 
+  and contact details.  Please ensure to read the configuration and relevant 
+  port sections of the online documentation.
+  ***************************************************************************
+*/
+
+
+/* 
+  BASIC INTERRUPT DRIVEN DRIVER FOR USB. 
+
+  This file contains all the usb components that must be compiled
+  to ARM mode.  The components that can be compiled to either ARM or THUMB
+  mode are contained in USB-CDC.c.
+
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "Board.h"
+#include "usb.h"
+#include "USB-CDC.h"
+
+#define usbINT_CLEAR_MASK	(AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
+/*-----------------------------------------------------------*/
+
+/* Messages and queue used to communicate between the ISR and the USB task. */
+static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
+extern xQueueHandle xUSBInterruptQueue;
+/*-----------------------------------------------------------*/
+
+/* The ISR can cause a context switch so is declared naked. */
+void vUSB_ISR( void ) __attribute__ ((naked));
+
+/*-----------------------------------------------------------*/
+
+
+void vUSB_ISR( void )
+{
+	/* This ISR can cause a context switch.  Therefore a call to the 
+	portENTER_SWITCHING_ISR() macro is made.  This must come BEFORE any 
+	stack variable declarations. */
+	portENTER_SWITCHING_ISR();
+
+	/* Now variables can be declared. */
+	portCHAR cTaskWokenByPost = pdFALSE; 
+	static volatile unsigned portLONG ulNextMessage = 0;
+	xISRStatus *pxMessage;
+	unsigned portLONG ulRxBytes;
+	unsigned portCHAR ucFifoIndex;
+
+    /* Use the next message from the array. */
+	pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
+	ulNextMessage++;
+
+    /* Save UDP ISR state for task-level processing. */
+	pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
+	pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+
+    /* Clear interrupts from ICR. */
+	AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
+	
+    
+	/* Process incoming FIFO data.  Must set DIR (if needed) and clear RXSETUP 
+	before exit. */
+
+    /* Read CSR and get incoming byte count. */
+	ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;
+	
+	/* Receive control transfers on endpoint 0. */
+	if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )
+	{
+		/* Save FIFO data buffer for either a SETUP or DATA stage */
+		for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )
+		{
+			pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
+		}
+
+		/* Set direction for data stage.  Must be done before RXSETUP is 
+		cleared. */
+		if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )
+		{
+			if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )
+			{
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;
+
+				/* Might not be wise in an ISR! */
+				while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );
+			}
+
+			/* Clear RXSETUP */
+			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;
+
+			/* Might not be wise in an ISR! */
+			while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );
+		}
+		else
+		{
+		   /* Clear RX_DATA_BK0 */
+		   AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;
+
+		   /* Might not be wise in an ISR! */
+		   while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );
+		}
+	}
+	
+	/* If we received data on endpoint 1, disable its interrupts until it is 
+	processed in the main loop */
+	if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )
+	{
+		AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;
+	}
+	
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );
+     
+	/* Clear interrupts for the other endpoints, retain data flags for endpoint 
+	1. */
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;
+
+	/* Post ISR data to queue for task-level processing */
+	cTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, cTaskWokenByPost );
+
+	/* Clear AIC to complete ISR processing */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+
+	/* Do a task switch if needed */
+	portEXIT_SWITCHING_ISR( cTaskWokenByPost )
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
new file mode 100644
index 000000000..fcf822969
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
@@ -0,0 +1,203 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+	- DESCRIPTOR DEFINITIONS -
+*/
+
+/* String descriptors used during the enumeration process.
+These take the form:
+
+{
+	Length of descriptor,
+	Descriptor type,
+	Data
+}
+*/
+
+const portCHAR pxLanguageStringDescriptor[] =
+{
+	4,
+	usbDESCRIPTOR_TYPE_STRING,
+	0x09, 0x04
+};
+
+const portCHAR pxManufacturerStringDescriptor[] = 
+{
+	18,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00
+};
+
+const portCHAR pxProductStringDescriptor[] = 
+{
+	36,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00, ' ', 0x00, 'C', 0x00, 'D', 0x00,
+	'C', 0x00, ' ', 0x00, 'D', 0x00, 'E', 0x00, 'M', 0x00, 'O', 0x00
+};
+
+const portCHAR pxConfigurationStringDescriptor[] = 
+{
+	38,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'C', 0x00, 'o', 0x00, 'n', 0x00, 'f', 0x00, 'i', 0x00, 'g', 0x00, 'u', 0x00, 'r', 0x00, 'a', 0x00, 't', 0x00, 'i', 0x00,
+	'o', 0x00, 'n', 0x00, ' ', 0x00, 'N', 0x00, 'a', 0x00, 'm', 0x00, 'e', 0x00
+};
+
+const portCHAR pxInterfaceStringDescriptor[] = 
+{
+	30,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, ' ', 0x00, 'N', 0x00,
+	'a', 0x00, 'm', 0x00, 'e', 0x00
+};
+
+/* Device should properly be 0x134A:0x9001, using 0x05F9:0xFFFF for Linux testing */
+const char pxDeviceDescriptor[] = 
+{
+	/* Device descriptor */
+	0x12,								/* bLength				*/
+	0x01,								/* bDescriptorType		*/
+	0x10, 0x01,							/* bcdUSBL				*/
+	0x02,								/* bDeviceClass:		*/
+	0x00,								/* bDeviceSubclass:		*/
+	0x00,								/* bDeviceProtocol:		*/
+	0x08,								/* bMaxPacketSize0		*/
+	0x03, 0xEB,							/* idVendorL			*/
+	0x20, 0x09,							/* idProductL			*/
+	0x10, 0x01,							/* bcdDeviceL			*/
+	usbMANUFACTURER_STRING,  			/* iManufacturer		*/
+	usbPRODUCT_STRING,					/* iProduct				*/
+	0x00,								/* SerialNumber			*/
+	0x01								/* bNumConfigs			*/
+};
+
+const char pxConfigDescriptor[] = {
+
+	/* Configuration 1 descriptor
+	Here we define two interfaces (0 and 1) and a total of 3 endpoints.
+	Interface 0 is a CDC Abstract Control Model interface with one interrupt-in endpoint.
+	Interface 1 is a CDC Data Interface class, with a bulk-in and bulk-out endpoint.
+	Endpoint 0 gets used as the CDC management element.
+	*/
+	0x09,				/* CbLength								*/
+	0x02,				/* CbDescriptorType					  	*/
+	0x43, 0x00,			/* CwTotalLength 2 EP + Control		?	*/
+	0x02,				/* CbNumInterfaces			  			*/
+	0x01,				/* CbConfigurationValue					*/
+	usbCONFIGURATION_STRING,/* CiConfiguration					*/
+	usbBUS_POWERED,		/* CbmAttributes Bus powered + Remote Wakeup*/
+	0x32,				/* CMaxPower: 100mA						*/
+
+	/* Communication Class Interface Descriptor Requirement		*/
+	0x09,				/* bLength								*/
+	0x04,				/* bDescriptorType						*/
+	0x00,				/* bInterfaceNumber						*/
+	0x00,				/* bAlternateSetting					*/
+	0x01,				/* bNumEndpoints						*/
+	0x02,				/* bInterfaceClass: Comm Interface Class */
+	0x02,				/* bInterfaceSubclass: Abstract Control Model*/
+	0x00,				/* bInterfaceProtocol					*/
+	usbINTERFACE_STRING,/* iInterface							*/
+
+	/* Header Functional Descriptor								*/
+	0x05,				/* bLength								*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x00,				/* bDescriptor subtype: Header Func Desc*/
+	0x10, 0x01,			/* bcdCDC:1.1  							*/
+
+	/* ACM Functional Descriptor								*/
+	0x04,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x02,				/* bDescriptor subtype: ACM Func Desc	*/
+	0x00,				/* bmCapabilities: We don't support squat*/
+
+	/* Union Functional Descriptor								*/
+	0x05,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x06,				/* bDescriptor subtype: Union Func Desc	*/
+	0x00,				/* bMasterInterface: CDC Interface		*/
+	0x01,				/* bSlaveInterface0: Data Class Interface*/
+
+	/* Call Management Functional Descriptor
+	0 in D1 and D0 indicates that device does not handle call management*/
+	0x05,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x01,				/* bDescriptor subtype: Call Management Func*/
+	0x00,				/* bmCapabilities: D1 + D0				*/
+	0x01,				/* bDataInterface: Data Class Interface 1*/
+
+	/* CDC Control - Endpoint 3 descriptor
+	This endpoint serves as a notification element.				*/
+
+	0x07,				/* bLength								*/
+	0x05,				/* bDescriptorType						*/
+	0x83,				/* bEndpointAddress, Endpoint 03 - IN	*/
+	0x03,				/* bmAttributes	  INT					*/
+	0x08, 0x00,			/* wMaxPacketSize: 8 bytes		   		*/
+	0xFF,				/* bInterval							*/
+
+	/* Data Class Interface Descriptor Requirement				*/
+	0x09,				/* bLength								*/
+	0x04,				/* bDescriptorType						*/
+	0x01,				/* bInterfaceNumber						*/
+	0x00,				/* bAlternateSetting					*/
+	0x02,				/* bNumEndPoints						*/
+	0x0A,				/* bInterfaceClass						*/
+	0x00,				/* bInterfaceSubclass					*/
+	0x00,				/* bInterfaceProtocol					*/
+	0x00,				/* iInterface							*/
+
+	/* CDC Data - Endpoint 1 descriptor */
+	0x07,				/* bLenght								*/
+	0x05,				/* bDescriptorType						*/
+	0x01,				/* bEndPointAddress, Endpoint 01 - OUT	*/
+	0x02,				/* bmAttributes BULK					*/
+	64,					/* wMaxPacketSize						*/
+	0x00,
+	0x00,				/* bInterval							*/
+
+	/* CDC Data - Endpoint 2 descriptor */
+	0x07,				/* bLength								*/
+	0x05,				/* bDescriptorType						*/
+	0x82,				/* bEndPointAddress, Endpoint 02 - IN	*/
+	0x02,				/* bmAttributes BULK					*/
+	64,					/* wMaxPacketSize						*/
+	0x00,
+	0x00				/* bInterval							*/
+};
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
new file mode 100644
index 000000000..c3ca325a1
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
@@ -0,0 +1,144 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* Descriptor type definitions. */
+#define usbDESCRIPTOR_TYPE_DEVICE			( 0x01 )
+#define usbDESCRIPTOR_TYPE_CONFIGURATION	( 0x02 )
+#define usbDESCRIPTOR_TYPE_STRING			( 0x03 )
+
+/* USB request type definitions. */
+#define usbGET_REPORT_REQUEST				( 0x01 )
+#define usbGET_IDLE_REQUEST					( 0x02 )
+#define usbGET_PROTOCOL_REQUEST				( 0x03 )
+#define usbSET_REPORT_REQUEST				( 0x09 )
+#define usbSET_IDLE_REQUEST					( 0x0A )
+#define usbSET_PROTOCOL_REQUEST				( 0x0B )
+#define usbGET_CONFIGURATION_REQUEST		( 0x08 )
+#define usbGET_STATUS_REQUEST				( 0x00 )
+#define usbCLEAR_FEATURE_REQUEST			( 0x01 )
+#define usbSET_FEATURE_REQUEST				( 0x03 )
+#define usbSET_ADDRESS_REQUEST				( 0x05 )
+#define usbGET_DESCRIPTOR_REQUEST			( 0x06 )
+#define usbSET_CONFIGURATION_REQUEST		( 0x09 )
+#define usbGET_INTERFACE_REQUEST			( 0x0A )
+#define usbSET_INTERFACE_REQUEST			( 0x0B )
+
+/* ACM Requests */
+#define usbSEND_ENCAPSULATED_COMMAND		( 0x00 )
+#define usbGET_ENCAPSULATED_RESPONSE		( 0x01 )
+#define usbSET_LINE_CODING					( 0x20 )
+#define usbGET_LINE_CODING					( 0x21 )
+#define usbSET_CONTROL_LINE_STATE			( 0x22 )
+
+/* Misc USB definitions. */
+#define usbDEVICE_CLASS_VENDOR_SPECIFIC		( 0xFF )
+#define usbBUS_POWERED						( 0x80 )
+#define usbHID_REPORT_DESCRIPTOR			( 0x22 )
+#define AT91C_UDP_TRANSCEIVER_ENABLE		( *( ( unsigned long * ) 0xfffb0074 ) )
+
+/* Index to the various string. */
+#define usbLANGUAGE_STRING					( 0 )
+#define usbMANUFACTURER_STRING				( 1 )
+#define usbPRODUCT_STRING					( 2 )
+#define usbCONFIGURATION_STRING				( 3 )
+#define usbINTERFACE_STRING					( 4 )
+
+/* Defines fields of standard SETUP request.  Now in normal order. */
+#define usbREQUEST_TYPE_INDEX				( 0 )
+#define usbREQUEST_INDEX					( 1 )
+#define usbVALUE_HIGH_BYTE					( 3 )
+#define usbVALUE_LOW_BYTE					( 2 )
+#define usbINDEX_HIGH_BYTE					( 5 )
+#define usbINDEX_LOW_BYTE					( 4 )
+#define usbLENGTH_HIGH_BYTE					( 7 )
+#define usbLENGTH_LOW_BYTE					( 6 )
+
+/* Misc application definitions. */
+#define usbINTERRUPT_PRIORITY				( 3 )
+#define usbQUEUE_LENGTH						( 0x3 )	/* Must have all bits set! */
+#define usbFIFO_LENGTH						( ( unsigned portLONG ) 8 )
+#define usbEND_POINT_0						( 0 )
+#define usbEND_POINT_1						( 1 )
+#define usbEND_POINT_2						( 2 )
+#define usbEND_POINT_3						( 3 )
+#define usbMAX_CONTROL_MESSAGE_SIZE			( 128 )
+#define usbRX_COUNT_MASK					( ( unsigned portLONG ) 0x7ff )
+#define AT91C_UDP_STALLSENT					AT91C_UDP_ISOERROR
+#define usbSHORTEST_DELAY					( ( portTickType ) 1 )
+#define usbINIT_DELAY						( ( portTickType ) 1000 / portTICK_RATE_MS )
+#define usbSHORT_DELAY						( ( portTickType ) 50 / portTICK_RATE_MS )
+#define usbEND_POINT_RESET_MASK				( ( unsigned portLONG ) 0x0f )
+#define usbDATA_INC							( ( portCHAR ) 5 )
+#define usbEXPECTED_NUMBER_OF_BYTES			( ( unsigned portLONG ) 8 )
+
+/* Control request types. */
+#define usbSTANDARD_DEVICE_REQUEST			( 0 )
+#define usbSTANDARD_INTERFACE_REQUEST		( 1 )
+#define usbSTANDARD_END_POINT_REQUEST		( 2 )
+#define usbCLASS_INTERFACE_REQUEST			( 5 )
+
+
+/* Macros to manipulate the control and status registers.  These registers 
+cannot be accessed using a direct read modify write operation outside of the 
+ISR as some bits are left unchanged by writing with a 0, and some are left 
+unchanged by writing with a 1. */
+
+
+#define usbCSR_SET_BIT( pulValueNow, ulBit )											\
+{																						\
+	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
+	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
+	/* write has no effect. */															\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
+																						\
+	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
+	/* so the write has no effect. */													\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
+																						\
+	/* Set whichever bit we want set. */												\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit );							\
+}
+
+#define usbCSR_CLEAR_BIT( pulValueNow, ulBit )											\
+{																						\
+	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
+	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
+	/* write has no effect. */															\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
+																						\
+	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
+	/* so the write has no effect. */													\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
+																						\
+	/* Clear whichever bit we want clear. */											\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit );						\
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld b/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
new file mode 100644
index 000000000..db22b4acd
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
@@ -0,0 +1,49 @@
+MEMORY 
+{
+	flash	: ORIGIN = 0x00100000, LENGTH = 256K
+	ram		: ORIGIN = 0x00200000, LENGTH = 64K
+}
+
+__stack_end__ = 0x00200000 + 64K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >flash
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >flash
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram AT>flash
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/boot.s b/Demo/lwIP_Demo_Rowley_ARM7/boot.s
new file mode 100644
index 000000000..88fac35db
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/boot.s
@@ -0,0 +1,161 @@
+	/* Sample initialization file */
+
+	.extern main
+	.extern exit
+	.extern AT91F_LowLevelInit
+
+	.text
+	.code 32
+
+
+	.align  0
+
+	.extern __stack_end__
+	.extern __bss_beg__
+	.extern __bss_end__
+	.extern __data_beg__
+	.extern __data_end__
+	.extern __data+beg_src__
+
+	.global start
+	.global endless_loop
+
+	/* Stack Sizes */
+    .set  UND_STACK_SIZE, 0x00000004
+    .set  ABT_STACK_SIZE, 0x00000004
+    .set  FIQ_STACK_SIZE, 0x00000004
+    .set  IRQ_STACK_SIZE, 0X00000400
+    .set  SVC_STACK_SIZE, 0x00000400
+
+	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+    .set  MODE_USR, 0x10            /* User Mode */
+    .set  MODE_FIQ, 0x11            /* FIQ Mode */
+    .set  MODE_IRQ, 0x12            /* IRQ Mode */
+    .set  MODE_SVC, 0x13            /* Supervisor Mode */
+    .set  MODE_ABT, 0x17            /* Abort Mode */
+    .set  MODE_UND, 0x1B            /* Undefined Mode */
+    .set  MODE_SYS, 0x1F            /* System Mode */
+
+    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
+    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
+
+
+start:
+_start:
+_mainCRTStartup:
+
+	/* Setup a stack for each mode - note that this only sets up a usable stack
+	for system/user, SWI and IRQ modes.   Also each mode is setup with
+	interrupts initially disabled. */
+    ldr   r0, .LC6
+    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
+    mov   sp, r0
+    sub   r0, r0, #UND_STACK_SIZE
+    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
+    mov   sp, r0
+    sub   r0, r0, #ABT_STACK_SIZE
+    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #FIQ_STACK_SIZE
+    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #IRQ_STACK_SIZE
+    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
+    mov   sp, r0
+    sub   r0, r0, #SVC_STACK_SIZE
+    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
+    mov   sp, r0
+
+	/* We want to start in supervisor mode.  Operation will switch to system
+	mode when the first task starts. */
+	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
+
+    bl		AT91F_LowLevelInit
+
+	/* Clear BSS. */
+
+	mov     a2, #0			/* Fill value */
+	mov		fp, a2			/* Null frame pointer */
+	mov		r7, a2			/* Null frame pointer for Thumb */
+
+	ldr		r1, .LC1		/* Start of memory block */
+	ldr		r3, .LC2		/* End of memory block */
+	subs	r3, r3, r1      /* Length of block */
+	beq		.end_clear_loop
+	mov		r2, #0
+
+.clear_loop:
+	strb	r2, [r1], #1
+	subs	r3, r3, #1
+	bgt		.clear_loop
+
+.end_clear_loop:
+
+	/* Initialise data. */
+
+	ldr		r1, .LC3		/* Start of memory block */
+	ldr		r2, .LC4		/* End of memory block */
+	ldr		r3, .LC5
+	subs	r3, r3, r1		/* Length of block */
+	beq		.end_set_loop
+
+.set_loop:
+	ldrb	r4, [r2], #1
+	strb	r4, [r1], #1
+	subs	r3, r3, #1
+	bgt		.set_loop
+
+.end_set_loop:
+
+	mov		r0, #0          /* no arguments  */
+	mov		r1, #0          /* no argv either */
+
+    ldr lr, =main	
+	bx	lr
+
+endless_loop:
+	b               endless_loop
+
+
+	.align 0
+
+	.LC1:
+	.word   __bss_beg__
+	.LC2:
+	.word   __bss_end__
+	.LC3:
+	.word   __data_beg__
+	.LC4:
+	.word   __data_beg_src__
+	.LC5:
+	.word   __data_end__
+	.LC6:
+	.word	__stack_end__
+
+
+	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
+	a null loop. */
+
+.section .startup,"ax"
+         .code 32
+         .align 0
+
+	b     _start						/* reset - _start			*/
+	ldr   pc, _undf						/* undefined - _undf		*/
+	ldr   pc, _swi						/* SWI - _swi				*/
+	ldr   pc, _pabt						/* program abort - _pabt	*/
+	ldr   pc, _dabt						/* data abort - _dabt		*/
+	nop									/* reserved					*/
+	ldr   pc, [pc,#-0xF20]				/* IRQ - read the AIC		*/
+	ldr   pc, _fiq						/* FIQ - _fiq				*/
+
+_undf:  .word __undf                    /* undefined				*/
+_swi:   .word swi_handler				/* SWI						*/
+_pabt:  .word __pabt                    /* program abort			*/
+_dabt:  .word __dabt                    /* data abort				*/
+_fiq:   .word __fiq                     /* FIQ						*/
+
+__undf: b     .                         /* undefined				*/
+__pabt: b     .                         /* program abort			*/
+__dabt: b     .                         /* data abort				*/
+__fiq:  b     .                         /* FIQ						*/
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/crt0.s b/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
new file mode 100644
index 000000000..a16c22012
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
@@ -0,0 +1,265 @@
+/*****************************************************************************
+ * Copyright (c) 2001, 2002 Rowley Associates Limited.                       *
+ *                                                                           *
+ * This file may be distributed under the terms of the License Agreement     *
+ * provided with this software.                                              *
+ *                                                                           *
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
+ *****************************************************************************/
+  .section .init, "ax"
+  .code 32
+  .align 0
+                
+  .weak _start
+  .global __start
+  .global __gccmain
+  .extern main
+  .extern exit
+
+/*****************************************************************************
+ * Function    : _start                                                      *
+ * Description : Main entry point and startup code for C system.             *
+ *****************************************************************************/
+_start:
+__start:                        
+  mrs r0, cpsr
+  bic r0, r0, #0x1F
+
+  /* Setup stacks */ 
+  orr r1, r0, #0x1B /* Undefined mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_und_end__
+  
+  orr r1, r0, #0x17 /* Abort mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_abt_end__
+
+  orr r1, r0, #0x12 /* IRQ mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_irq_end__
+
+  orr r1, r0, #0x11 /* FIQ mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_fiq_end__
+
+  orr r1, r0, #0x13 /* Supervisor mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_svc_end__
+#ifdef SUPERVISOR_START
+  /* Start application in supervisor mode */
+  ldr r1, =__stack_end__ /* Setup user/system mode stack */ 
+  mov r2, sp
+  stmfd r2!, {r1}
+  ldmfd r2, {sp}^
+#else
+  /* Start application in system mode */
+  orr r1, r0, #0x1F /* System mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_end__
+#endif
+  
+  /* Copy from initialised data section to data section (if necessary). */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  cmp r0, r1
+  beq copy_data_end
+  
+  ldr r2, =__data_end__
+  subs r2, r2, r1
+  beq copy_data_end
+  
+copy_data_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_data_loop
+copy_data_end:  
+
+  /* Copy from initialised text section to text section (if necessary). */
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  cmp r0, r1
+  beq copy_text_end
+  
+  ldr r2, =__text_end__
+  subs r2, r2, r1
+  beq copy_text_end
+  
+copy_text_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_text_loop
+copy_text_end:  
+
+  /* Copy from initialised fast_text section to fast_text section (if necessary). */
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  cmp r0, r1
+  beq copy_fast_end
+  
+  ldr r2, =__fast_end__
+  subs r2, r2, r1
+  beq copy_fast_end
+  
+copy_fast_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_fast_loop
+copy_fast_end:  
+
+  /* Zero the bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+zero_bss_loop:
+  cmp r0, r1
+  beq zero_bss_end
+  strb r2, [r0], #+1
+  b zero_bss_loop
+zero_bss_end:    
+
+#ifdef CHECK  
+  /* Check data */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  cmp r0, r1
+  beq check_data_end
+  ldr r2, =__data_end__
+  subs r2, r2, r1
+  beq check_data_end
+  
+check_data_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne data_error_loop
+  subs r2, r2, #1
+  bne check_data_loop
+check_data_end:  
+
+  /* Check text */
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  cmp r0, r1
+  beq check_text_end
+  ldr r2, =__text_end__
+  subs r2, r2, r1
+  beq check_text_end
+  
+check_text_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne text_error_loop
+  subs r2, r2, #1
+  bne check_text_loop
+check_text_end:  
+
+  /* Check fast */
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  cmp r0, r1
+  beq check_fast_end
+  ldr r2, =__fast_end__
+  subs r2, r2, r1
+  beq check_fast_end
+  
+check_fast_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne fast_error_loop
+  subs r2, r2, #1
+  bne check_fast_loop
+check_fast_end:  
+
+  /* Check bss */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+check_bss_loop:
+  cmp r0, r1
+  beq check_bss_end
+  ldrb r2, [r0], #+1
+  cmp r2, #0
+  bne bss_error_loop  
+  b check_bss_loop
+check_bss_end:    
+#endif
+
+  /* Initialise the heap */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  sub r1, r1, r0     /* r1 = r1-r0 */ 
+  mov r2, #0
+  str r2, [r0], #+4 /* *r0++ = 0 */
+  str r1, [r0]      /* *r0 = __heap_end__ - __heap_start__ */
+
+  /* Call constructors */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+ctor_loop:
+  cmp r0, r1
+  beq ctor_end
+  ldr r2, [r0], #+4
+  stmfd sp!, {r0-r1}
+  mov lr, pc
+  mov pc, r2
+  ldmfd sp!, {r0-r1}
+  b ctor_loop
+ctor_end:
+
+  /* Setup initial call frame */
+  mov lr, #4
+  mov r12, sp
+  stmfd sp!, {r11-r12, lr-pc}
+  sub r11, r12, #0x00000004
+
+start:
+  /* Jump to main entry point */
+  mov r0, #0
+  mov r1, #0
+  ldr r2, =main
+  mov lr, pc
+#ifdef __ARM_ARCH_3__
+  mov pc, r2
+#else    
+  bx r2
+#endif
+
+  /* Call destructors */
+  ldr r0, =__dtors_start__
+  ldr r1, =__dtors_end__
+dtor_loop:
+  cmp r0, r1
+  beq dtor_end
+  ldr r2, [r0], #+4
+  stmfd sp!, {r0-r1}
+  mov lr, pc
+  mov pc, r2
+  ldmfd sp!, {r0-r1}
+  b dtor_loop
+dtor_end:
+
+  /* Return from main, loop forever. */
+exit_loop:
+  b exit_loop
+
+#ifdef CHECK
+data_error_loop:
+  b data_error_loop
+
+text_error_loop:
+  b text_error_loop
+  
+fast_error_loop:
+  b fast_error_loop
+  
+bss_error_loop:
+  b bss_error_loop  
+#endif
+  
+                  
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml b/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
new file mode 100644
index 000000000..0df08fd26
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
@@ -0,0 +1,29 @@
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+    
+  
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
new file mode 100644
index 000000000..67a56cd62
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
@@ -0,0 +1,536 @@
+FUTURE
+
+  * TODO: The lwIP source code makes some invalid assumptions on processor
+    word-length, storage sizes and alignment. See the mailing lists for
+    problems with exoteric (/DSP) architectures showing these problems.
+    We still have to fix some of these issues neatly.
+
+  * TODO: the ARP layer is not protected against concurrent access. If
+    you run from a multitasking OS, serialize access to ARP (called from
+    your network device driver and from a timeout thread.)
+
+HISTORY
+
+(HEAD)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+    
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+	even if one is already pending, if the rcv_wnd is above a threshold
+	(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+	delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+  
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+  
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
new file mode 100644
index 000000000..e23898b5e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
new file mode 100644
index 000000000..66253196f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
new file mode 100644
index 000000000..4795d3afe
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
@@ -0,0 +1,92 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tenths of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+ * IP (Internet Protocol) including packet forwarding over multiple
+   network interfaces
+ * ICMP (Internet Control Message Protocol) for network maintenance
+   and debugging
+ * UDP (User Datagram Protocol) including experimental UDP-lite
+   extensions
+ * TCP (Transmission Control Protocol) with congestion control, RTT
+   estimation and fast recovery/fast retransmit
+ * Specialized API for enhanced performance
+ * Optional Berkeley socket API
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+The CVS main trunk is the stable branch, which contains bug fixes and
+tested features. The latest stable branch can be checked out by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co lwip
+
+The 'STABLE' tag in the stable branch will represent the most stable
+revision (which may be somewhat older to protect us from errors
+introduced by merges). This 'STABLE' tagged version can be checked out
+by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r STABLE lwip
+
+The 'DEVEL' branch is the active development branch, which contains
+bleeding edge changes, and may be instable. It can be checkout by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r DEVEL lwip
+
+The current contrib CVS tree can be checked out by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co contrib
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 		    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
new file mode 100644
index 000000000..cbb300a12
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+#include "cpu.h"
+
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+typedef u32_t mem_ptr_t;
+typedef int sys_prot_t;
+
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif /* __CC_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
new file mode 100644
index 000000000..2af31a864
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define BYTE_ORDER LITTLE_ENDIAN
+
+#endif /* __CPU_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
new file mode 100644
index 000000000..14b95158b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_INIT_H__
+#define __ARCH_INIT_H__
+
+#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
+
+void tcpip_init_done(void *);
+int wait_for_tcpip_init(void);
+
+#endif /* __ARCH_INIT_H__ */
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
new file mode 100644
index 000000000..9726dee12
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LIB_H__
+#define __LIB_H__
+
+#include 
+
+
+#endif /* __LIB_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
new file mode 100644
index 000000000..68afdb56f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
new file mode 100644
index 000000000..406f1f641
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (xQueueHandle)0
+#define SYS_SEM_NULL  (xSemaphoreHandle)0
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+#endif /* __SYS_RTXC_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
new file mode 100644
index 000000000..a48fa78f9
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH	( 6 )
+#define archPOST_BLOCK_TIME_MS	( ( unsigned portLONG ) 10000 )
+
+struct timeoutlist 
+{
+	struct sys_timeouts timeouts;
+	xTaskHandle pid;
+};
+
+/* This is the number of threads that can be started with sys_thread_new() */
+#define SYS_THREAD_MAX 4
+
+#define lwipTCP_STACK_SIZE			600
+#define lwipBASIC_SERVER_STACK_SIZE	250
+
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];
+static u16_t nextthread = 0;
+int intlevel = 0;
+
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+sys_mbox_t
+sys_mbox_new(void)
+{
+	xQueueHandle mbox;
+
+	mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
+
+	return mbox;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free(sys_mbox_t mbox)
+{
+	if( uxQueueMessagesWaiting( mbox ) )
+	{
+		/* Line for breakpoint.  Should never break here! */
+		__asm volatile ( "NOP" );
+	}
+
+	vQueueDelete( mbox ); 
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void
+sys_mbox_post(sys_mbox_t mbox, void *data)
+{   
+	xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+{
+void *dummyptr;
+portTickType StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if( msg == NULL )
+	{
+		msg = &dummyptr;
+	}
+		
+	if(	timeout != 0 )
+	{
+		if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = EndTime - StartTime;
+			if( Elapsed == 0 )
+			{
+				Elapsed = 1;
+			}
+			return ( Elapsed );
+		}
+		else // timed out blocking for message
+		{
+			*msg = NULL;
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // block forever for a message.
+	{
+		while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary
+		{
+			;
+		}
+		EndTime = xTaskGetTickCount();
+		Elapsed = EndTime - StartTime;
+		if( Elapsed == 0 )
+		{
+			Elapsed = 1;
+		}
+		return ( Elapsed ); // return time blocked TBD test	
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates and returns a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore. TBD finish and test
+sys_sem_t
+sys_sem_new(u8_t count)
+{
+	xSemaphoreHandle  xSemaphore;
+
+	portENTER_CRITICAL();
+	vSemaphoreCreateBinary( xSemaphore );
+	if(count == 0)	// Means it can't be taken
+	{
+		xSemaphoreTake(xSemaphore,1);
+	}
+	portEXIT_CRITICAL();
+
+	if( xSemaphore == NULL )
+	{
+		return NULL;	// TBD need assert
+	}
+	else
+	{
+		return xSemaphore;
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+{
+portTickType StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if(	timeout != 0)
+	{
+		if( xSemaphoreTake( sem, timeout ) == pdTRUE )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = EndTime - StartTime;
+			if( Elapsed == 0 )
+			{
+				Elapsed = 1;
+			}
+			return (Elapsed); // return time blocked TBD test	
+		}
+		else
+		{
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // must block without a timeout
+	{
+		while( xSemaphoreTake( sem, 10000 ) != pdTRUE )
+		{
+			;
+		}
+		EndTime = xTaskGetTickCount();
+		Elapsed = EndTime - StartTime;
+		if( Elapsed == 0 )
+		{
+			Elapsed = 1;
+		}
+
+		return ( Elapsed ); // return time blocked	
+		 
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void
+sys_sem_signal(sys_sem_t sem)
+{
+	xSemaphoreGive( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void
+sys_sem_free(sys_sem_t sem)
+{
+	vQueueDelete( sem ); 
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Initialize sys arch
+void
+sys_init(void)
+{
+
+	int i;
+
+	// Initialize the the per-thread sys_timeouts structures
+	// make sure there are no valid pids in the list
+	for(i = 0; i < SYS_THREAD_MAX; i++)
+	{
+		timeoutlist[i].pid = 0;
+	}
+
+	// keep track of how many threads have been created
+	nextthread = 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is represented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threaded sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+*/
+struct sys_timeouts *
+sys_arch_timeouts(void)
+{
+int i;
+xTaskHandle pid;
+struct timeoutlist *tl;  
+
+	pid = xTaskGetCurrentTaskHandle( ); 
+
+	for(i = 0; i < nextthread; i++) 
+	{
+		tl = &timeoutlist[i];
+		if(tl->pid == pid) 
+		{
+			return &(tl->timeouts);
+		}
+	}
+
+	// Error
+	return NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+// TBD 
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+{
+xTaskHandle CreatedTask;
+int result;
+static int iCall = 0;
+
+	if( iCall == 0 )
+	{
+		/* The first time this is called we are creating the lwIP handler. */
+		result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipTCP_STACK_SIZE, arg, prio, &CreatedTask );
+		iCall++;
+	}
+	else
+	{
+		result = xTaskCreate( thread, ( signed portCHAR * ) "WEBSvr", lwipBASIC_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+	}
+
+	// For each task created, store the task handle (pid) in the timers array.
+	// This scheme doesn't allow for threads to be deleted
+	timeoutlist[nextthread++].pid = CreatedTask;
+
+	if(result == pdPASS)
+	{
+		return CreatedTask;
+	}
+	else
+	{
+		return NULL;
+	}
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+*/
+sys_prot_t sys_arch_protect(void)
+{
+	vPortEnterCritical();
+	return 1;
+}
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{ 
+	( void ) pval;
+	vPortExitCritical();
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
new file mode 100644
index 000000000..7c99b9be2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
@@ -0,0 +1,62 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
new file mode 100644
index 000000000..6d1c93cab
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
@@ -0,0 +1,292 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg
+
+lwIP provides two Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "connected"
+  function will be called with an the "err" argument set accordingly.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+		               u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+	       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
new file mode 100644
index 000000000..56cc1f190
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+Or, obtain a development branch (considered unstable!) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r DEVEL -d lwip-DEVEL lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@subversions.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:your_login@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip export -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
new file mode 100644
index 000000000..95d0add73
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
@@ -0,0 +1,194 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(void)
+
+  Creates an empty mailbox.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+  
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is repressented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threadd sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
new file mode 100644
index 000000000..2b6573185
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+	    
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
new file mode 100644
index 000000000..48d0a384b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
@@ -0,0 +1,729 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+
+
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+void
+netbuf_free(struct netbuf *buf)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+void
+netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  buf->p->payload = dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  pbuf_chain(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+u16_t
+netbuf_len(struct netbuf *buf)
+{
+  return buf->p->tot_len;
+}
+
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+void
+netbuf_first(struct netbuf *buf)
+{
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t i, left;
+
+  left = 0;
+
+  if(buf == NULL || dataptr == NULL) {
+    return;
+  }
+  
+  /* This implementation is bad. It should use bcopy
+     instead. */
+  for(p = buf->p; left < len && p != NULL; p = p->next) {
+    if (offset != 0 && offset >= p->len) {
+      offset -= p->len;
+    } else {    
+      for(i = offset; i < p->len; ++i) {
+  ((char *)dataptr)[left] = ((char *)p->payload)[i];
+  if (++left >= len) {
+    return;
+  }
+      }
+      offset = 0;
+    }
+  }
+}
+
+void
+netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
+{
+  netbuf_copy_partial(buf, dataptr, len, 0);
+}
+
+struct ip_addr *
+netbuf_fromaddr(struct netbuf *buf)
+{
+  return buf->fromaddr;
+}
+
+u16_t
+netbuf_fromport(struct netbuf *buf)
+{
+  return buf->fromport;
+}
+
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  struct netconn *conn;
+  struct api_msg *msg;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  conn->recvmbox = SYS_MBOX_NULL;
+  conn->acceptmbox = SYS_MBOX_NULL;
+  conn->sem = SYS_SEM_NULL;
+  conn->state = NETCONN_NONE;
+  conn->socket = 0;
+  conn->callback = callback;
+  conn->recv_avail = 0;
+
+  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  
+  msg->type = API_MSG_NEWCONN;
+  msg->msg.msg.bc.port = proto; /* misusing the port field */
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  if ( conn->err != ERR_OK ) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  return conn;
+}
+
+
+struct
+netconn *netconn_new(enum netconn_type t)
+{
+  return netconn_new_with_proto_and_callback(t,0,NULL);
+}
+
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  return netconn_new_with_proto_and_callback(t,0,callback);
+}
+
+
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg *msg;
+  void *mem;
+  
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  
+  msg->type = API_MSG_DELCONN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL)
+          pbuf_free((struct pbuf *)mem);
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+ 
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      netconn_delete((struct netconn *)mem);
+    }
+    
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_mbox_free(conn->mbox);
+  conn->mbox = SYS_MBOX_NULL;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+  }
+  /*  conn->sem = SYS_SEM_NULL;*/
+  memp_free(MEMP_NETCONN, conn);
+  return ERR_OK;
+}
+
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+  return conn->type;
+}
+
+err_t
+netconn_peer(struct netconn *conn, struct ip_addr *addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    /* return an error as connecting is only a helper for upper layers */
+    return ERR_CONN;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    if (conn->pcb.udp == NULL ||
+  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
+     return ERR_CONN;
+    *addr = (conn->pcb.udp->remote_ip);
+    *port = conn->pcb.udp->remote_port;
+    break;
+  case NETCONN_TCP:
+    if (conn->pcb.tcp == NULL)
+      return ERR_CONN;
+    *addr = (conn->pcb.tcp->remote_ip);
+    *port = conn->pcb.tcp->remote_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_addr(struct netconn *conn, struct ip_addr **addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    *addr = &(conn->pcb.raw->local_ip);
+    *port = conn->pcb.raw->protocol;
+    break;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    *addr = &(conn->pcb.udp->local_ip);
+    *port = conn->pcb.udp->local_port;
+    break;
+  case NETCONN_TCP:
+    *addr = &(conn->pcb.tcp->local_ip);
+    *port = conn->pcb.tcp->local_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr,
+      u16_t port)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->type != NETCONN_TCP &&
+     conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_BIND;
+  msg->msg.conn = conn;
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr,
+       u16_t port)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_CONNECT;
+  msg->msg.conn = conn;  
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_DISCONNECT;
+  msg->msg.conn = conn;  
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+
+}
+
+err_t
+netconn_listen(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->acceptmbox == SYS_MBOX_NULL) {
+    conn->acceptmbox = sys_mbox_new();
+    if (conn->acceptmbox == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_LISTEN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+  
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
+  /* Register event with callback */
+  if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
+  
+  return newconn;
+}
+
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg *msg;
+  struct netbuf *buf;
+  struct pbuf *p;
+  u16_t len;
+    
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+    if (conn->pcb.tcp->state == LISTEN) {
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+    
+    sys_mbox_fetch(conn->recvmbox, (void **)&p);
+
+    if (p != NULL)
+    {
+        len = p->tot_len;
+        conn->recv_avail -= len;
+    }
+    else
+        len = 0;
+    
+    /* Register event with callback */
+      if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to receive
+       data by setting conn->recvmbox to SYS_MBOX_NULL. */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      sys_mbox_free(conn->recvmbox);
+      conn->recvmbox = SYS_MBOX_NULL;
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromport = 0;
+    buf->fromaddr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+      conn->err = ERR_MEM;
+      return buf;
+    }
+    msg->type = API_MSG_RECV;
+    msg->msg.conn = conn;
+    if (buf != NULL) {
+      msg->msg.msg.len = buf->p->tot_len;
+    } else {
+      msg->msg.msg.len = 1;
+    }
+    api_msg_post(msg);
+
+    sys_mbox_fetch(conn->mbox, NULL);
+    memp_free(MEMP_API_MSG, msg);
+  } else {
+    sys_mbox_fetch(conn->recvmbox, (void **)&buf);
+  conn->recv_avail -= buf->p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+  }
+
+  
+
+    
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+
+  return buf;
+}
+
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+  msg->type = API_MSG_SEND;
+  msg->msg.conn = conn;
+  msg->msg.msg.p = buf->p;
+  api_msg_post(msg);
+
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
+{
+  struct api_msg *msg;
+  u16_t len;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+  
+  if (conn->sem == SYS_SEM_NULL) {
+    conn->sem = sys_sem_new(0);
+    if (conn->sem == SYS_SEM_NULL) {
+      return ERR_MEM;
+    }
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_WRITE;
+  msg->msg.conn = conn;
+        
+
+  conn->state = NETCONN_WRITE;
+  while (conn->err == ERR_OK && size > 0) {
+    msg->msg.msg.w.dataptr = dataptr;
+    msg->msg.msg.w.copy = copy;
+    
+    if (conn->type == NETCONN_TCP) {
+      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
+  sys_sem_wait(conn->sem);
+  if (conn->err != ERR_OK) {
+    goto ret;
+  }
+      }
+      if (size > tcp_sndbuf(conn->pcb.tcp)) {
+  /* We cannot send more than one send buffer's worth of data at a
+     time. */
+  len = tcp_sndbuf(conn->pcb.tcp);
+      } else {
+  len = size;
+      }
+    } else {
+      len = size;
+    }
+    
+    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
+    msg->msg.msg.w.len = len;
+    api_msg_post(msg);
+    sys_mbox_fetch(conn->mbox, NULL);    
+    if (conn->err == ERR_OK) {
+      dataptr = (void *)((char *)dataptr + len);
+      size -= len;
+    } else if (conn->err == ERR_MEM) {
+      conn->err = ERR_OK;
+      sys_sem_wait(conn->sem);
+    } else {
+      goto ret;
+    }
+  }
+ ret:
+  memp_free(MEMP_API_MSG, msg);
+  conn->state = NETCONN_NONE;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+    conn->sem = SYS_SEM_NULL;
+  }
+  
+  return conn->err;
+}
+
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  conn->state = NETCONN_CLOSE;
+ again:
+  msg->type = API_MSG_CLOSE;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  if (conn->err == ERR_MEM &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_wait(conn->sem);
+    goto again;
+  }
+  conn->state = NETCONN_NONE;
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_err(struct netconn *conn)
+{
+  return conn->err;
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
new file mode 100644
index 000000000..8247aaaab
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
@@ -0,0 +1,810 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/tcpip.h"
+
+#if LWIP_RAW
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  if (!conn) return 0;
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    if (!(buf = memp_malloc(MEMP_NETBUF))) {
+      return 0;
+    }
+    pbuf_ref(p);
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromaddr = addr;
+    buf->fromport = pcb->protocol;
+
+    conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif
+#if LWIP_UDP
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  
+  if (conn == NULL) {
+    pbuf_free(p);
+    return;
+  }
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    buf = memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      pbuf_free(p);
+      return;
+    } else {
+      buf->p = p;
+      buf->ptr = p;
+      buf->fromaddr = addr;
+      buf->fromport = port;
+    }
+
+  conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+}
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+
+  (void)pcb;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    pbuf_free(p);
+    return ERR_VAL;
+  }
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+        
+    conn->err = err;
+    if (p != NULL) {
+        len = p->tot_len;
+        conn->recv_avail += len;
+    }
+    else
+        len = 0;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
+    sys_mbox_post(conn->recvmbox, p);
+  }  
+  return ERR_OK;
+}
+
+
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  if (conn != NULL &&
+     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+  return ERR_OK;
+}
+
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+
+  if (conn && conn->callback)
+      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
+          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
+  
+  return ERR_OK;
+}
+
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  conn->pcb.tcp = NULL;
+
+  
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(conn->mbox, NULL);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+     /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+}
+
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+  
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  sys_mbox_t mbox;
+  struct netconn *newconn;
+  struct netconn *conn;
+  
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+  mbox = conn->acceptmbox;
+  newconn = memp_malloc(MEMP_NETCONN);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->type = NETCONN_TCP;
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->recvmbox = sys_mbox_new();
+  if (newconn->recvmbox == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->mbox = sys_mbox_new();
+  if (newconn->mbox == SYS_MBOX_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->sem = sys_sem_new(0);
+  if (newconn->sem == SYS_SEM_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    sys_mbox_free(newconn->mbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->acceptmbox = SYS_MBOX_NULL;
+  newconn->err = err;
+  /* Register event with callback */
+  if (conn->callback)
+  {
+    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    /* We have to set the callback here even though
+     * the new socket is unknown. Mark the socket as -1. */
+    newconn->callback = conn->callback;
+    newconn->socket = -1;
+  }
+  
+  sys_mbox_post(mbox, newconn);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+static void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp != NULL) {
+   /* This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? 
+      We currently just are happy and return. */
+     sys_mbox_post(msg->conn->mbox, NULL);
+     return;
+   }
+
+   msg->conn->err = ERR_OK;
+
+   /* Allocate a PCB for this connection */
+   switch(msg->conn->type) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif
+#if LWIP_UDP
+   case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      if(msg->conn->pcb.tcp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      setup_tcp(msg->conn);
+      break;
+#endif
+   }
+   
+  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_accept(msg->conn->pcb.tcp, NULL);  
+  tcp_close(msg->conn->pcb.tcp);
+      } else {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_sent(msg->conn->pcb.tcp, NULL);
+  tcp_recv(msg->conn->pcb.tcp, NULL);  
+  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
+  tcp_err(msg->conn->pcb.tcp, NULL);
+  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
+    tcp_abort(msg->conn->pcb.tcp);
+  }
+      }
+#endif
+    default:  
+    break;
+    }
+  }
+  /* Trigger select() in socket layer */
+  if (msg->conn->callback)
+  {
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  
+  if (msg->conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(msg->conn->mbox, NULL);
+  }
+}
+
+static void
+do_bind(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      setup_tcp(msg->conn);
+#endif /* LWIP_TCP */
+    default:  
+    break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
+            msg->msg.bc.ipaddr, msg->msg.bc.port);
+#endif /* LWIP_TCP */
+  default:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+#if LWIP_TCP
+
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  
+  conn->err = err;
+  if (conn->type == NETCONN_TCP && err == ERR_OK) {
+    setup_tcp(conn);
+  }    
+  sys_mbox_post(conn->mbox, NULL);
+  return ERR_OK;
+}
+#endif  
+
+static void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();      
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif 
+#if LWIP_TCP      
+  case NETCONN_TCP:
+    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
+    setup_tcp(msg->conn);
+    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+    do_connected);
+    /*tcp_output(msg->conn->pcb.tcp);*/
+#endif
+
+  default:
+    break;
+  }
+}
+
+static void
+do_disconnect(struct api_msg_msg *msg)
+{
+
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    /* Do nothing as connecting is only a helper for upper lwip layers */
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_disconnect(msg->conn->pcb.udp);
+    break;
+#endif 
+  case NETCONN_TCP:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_listen(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+      } else {
+  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+    msg->conn->acceptmbox = sys_mbox_new();
+    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+      msg->conn->err = ERR_MEM;
+      break;
+    }
+  }
+  tcp_arg(msg->conn->pcb.tcp, msg->conn);
+  tcp_accept(msg->conn->pcb.tcp, accept_function);
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_accept(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:    
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+}
+
+static void
+do_send(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_send(msg->conn->pcb.raw, msg->msg.p);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      udp_send(msg->conn->pcb.udp, msg->msg.p);
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (msg->conn->pcb.tcp != NULL) {
+    if (msg->conn->type == NETCONN_TCP) {
+      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
+    }
+  }
+#endif  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_write(struct api_msg_msg *msg)
+{
+#if LWIP_TCP  
+  err_t err;
+#endif  
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif
+#if LWIP_UDP 
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP 
+    case NETCONN_TCP:      
+      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
+                      msg->msg.w.len, msg->msg.w.copy);
+      /* This is the Nagle algorithm: inhibit the sending of new TCP
+   segments when new outgoing data arrives from the user if any
+   previously transmitted data on the connection remains
+   unacknowledged. */
+      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {
+  tcp_output(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;
+      if (msg->conn->callback)
+          if (err == ERR_OK)
+          {
+              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
+                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
+          }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_close(struct api_msg_msg *msg)
+{
+  err_t err;
+
+  err = ERR_OK;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  err = tcp_close(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;      
+#endif
+    default:      
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+typedef void (* api_msg_decode)(struct api_msg_msg *msg);
+static api_msg_decode decode[API_MSG_MAX] = {
+  do_newconn,
+  do_delconn,
+  do_bind,
+  do_connect,
+  do_disconnect,
+  do_listen,
+  do_accept,
+  do_send,
+  do_recv,
+  do_write,
+  do_close
+  };
+void
+api_msg_input(struct api_msg *msg)
+{  
+  decode[msg->type](&(msg->msg));
+}
+
+void
+api_msg_post(struct api_msg *msg)
+{
+  tcpip_apimsg(msg);
+}
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
new file mode 100644
index 000000000..b582d88a2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static char *err_strerr[] = {"Ok.",
+           "Out of memory error.",
+           "Buffer error.",
+           "Connection aborted.",
+           "Connection reset.",
+           "Connection closed.",
+           "Not connected.",
+           "Illegal value.",
+           "Illegal argument.",
+           "Routing problem.",
+           "Address in use."
+};
+
+
+char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+
+#endif /* LWIP_DEBUG */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
new file mode 100644
index 000000000..0528ac44f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
@@ -0,0 +1,1359 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include 
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/arch.h"
+#include "lwip/sys.h"
+
+#include "lwip/sockets.h"
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+struct lwip_socket {
+  struct netconn *conn;
+  struct netbuf *lastdata;
+  u16_t lastoffset;
+  u16_t rcvevent;
+  u16_t sendevent;
+  u16_t  flags;
+  int err;
+};
+
+struct lwip_select_cb
+{
+    struct lwip_select_cb *next;
+    fd_set *readset;
+    fd_set *writeset;
+    fd_set *exceptset;
+    int sem_signalled;
+    sys_sem_t sem;
+};
+
+static struct lwip_socket sockets[NUM_SOCKETS];
+static struct lwip_select_cb *select_cb_list = 0;
+
+static sys_sem_t socksem = 0;
+static sys_sem_t selectsem = 0;
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+
+static int err_to_errno_table[11] = {
+    0,      /* ERR_OK    0      No error, everything OK. */
+    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
+    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
+    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
+    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
+    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
+    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
+    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
+    EIO,    /* ERR_ARG  -8      Illegal argument.        */
+    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
+    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
+};
+
+#define err_to_errno(err) \
+  ((err) < (sizeof(err_to_errno_table)/sizeof(int))) ? \
+    err_to_errno_table[-(err)] : EIO
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+      sk->err = (e); \
+      set_errno(sk->err); \
+} while (0)
+
+
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s > NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for(i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn = newconn;
+      sockets[i].lastdata = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent = 0;
+      sockets[i].sendevent = 1; /* TCP send buf is empty */
+      sockets[i].flags = 0;
+      sockets[i].err = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  newconn = netconn_accept(sock->conn);
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(newconn, &naddr, &port);
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+  sin.sin_port = htons(port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+  memcpy(addr, &sin, *addrlen);
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+  sock_set_errno(sock, ENOBUFS);
+  return -1;
+  }
+  newconn->callback = event_callback;
+  sock = get_socket(newsock);
+
+  sys_sem_wait(socksem);
+  sock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* We cannot allow multiple closes of the same socket. */
+  sys_sem_wait(socksem);
+
+  sock = get_socket(s);
+  if (!sock) {
+      sys_sem_signal(socksem);
+      set_errno(EBADF);
+      return -1;
+  }
+
+  netconn_delete(sock->conn);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata = NULL;
+  sock->lastoffset = 0;
+  sock->conn = NULL;
+  sys_sem_signal(socksem);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+   }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  err = netconn_listen(sock->conn);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  u16_t buflen, copylen;
+  struct ip_addr *addr;
+  u16_t port;
+
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* Check if there is data left from the last recv operation. */
+  if (sock->lastdata) {
+    buf = sock->lastdata;
+  } else {
+    /* If this is non-blocking call, then check first */
+    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
+  && !sock->rcvevent)
+    {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+      sock_set_errno(sock, EWOULDBLOCK);
+      return -1;
+    }
+
+    /* No data was left from the previous operation, so we try to get
+       some from the network. */
+    buf = netconn_recv(sock->conn);
+
+    if (!buf) {
+      /* We should really do some error checking here. */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+      sock_set_errno(sock, 0);
+      return 0;
+    }
+  }
+
+  buflen = netbuf_len(buf);
+
+  buflen -= sock->lastoffset;
+
+  if (len > buflen) {
+    copylen = buflen;
+  } else {
+    copylen = len;
+  }
+
+  /* copy the contents of the received buffer into
+     the supplied memory pointer mem */
+  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
+
+  /* Check to see from where the data was. */
+  if (from && fromlen) {
+    struct sockaddr_in sin;
+
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = addr->addr;
+
+    if (*fromlen > sizeof(sin))
+      *fromlen = sizeof(sin);
+
+    memcpy(from, &sin, *fromlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+  } else {
+#if SOCKETS_DEBUG
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+#endif
+
+  }
+
+  /* If this is a TCP socket, check if there is data left in the
+     buffer. If so, it should be saved in the sock structure for next
+     time around. */
+  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
+    sock->lastdata = buf;
+    sock->lastoffset += copylen;
+  } else {
+    sock->lastdata = NULL;
+    sock->lastoffset = 0;
+    netbuf_delete(buf);
+  }
+
+
+  sock_set_errno(sock, 0);
+  return copylen;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, void *data, int size, unsigned int flags)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  switch (netconn_type(sock->conn)) {
+  case NETCONN_RAW:
+  case NETCONN_UDP:
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+    /* create a buffer */
+    buf = netbuf_new();
+
+    if (!buf) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
+      sock_set_errno(sock, ENOBUFS);
+      return -1;
+    }
+
+    /* make the buffer point to the data that should
+       be sent */
+    netbuf_ref(buf, data, size);
+
+    /* send the data */
+    err = netconn_send(sock->conn, buf);
+
+    /* deallocated the buffer */
+    netbuf_delete(buf);
+    break;
+  case NETCONN_TCP:
+    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
+    break;
+  default:
+    err = ERR_ARG;
+    break;
+  }
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
+  sock_set_errno(sock, 0);
+  return size;
+}
+
+int
+lwip_sendto(int s, void *data, int size, unsigned int flags,
+       struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr, addr;
+  u16_t remote_port, port;
+  int ret,connected;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* get the peer if currently connected */
+  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
+
+  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+  remote_port = ((struct sockaddr_in *)to)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
+
+  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+
+  ret = lwip_send(s, data, size, flags);
+
+  /* reset the remote address and port number
+     of the connection */
+  if (connected)
+    netconn_connect(sock->conn, &addr, port);
+  else
+  netconn_disconnect(sock->conn);
+  return ret;
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+  set_errno(ENOBUFS);
+  return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, void *data, int size)
+{
+   return lwip_send(s, data, size, 0);
+}
+
+
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+    int i, nready = 0;
+    fd_set lreadset, lwriteset, lexceptset;
+    struct lwip_socket *p_sock;
+
+    FD_ZERO(&lreadset);
+    FD_ZERO(&lwriteset);
+    FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    for(i = 0; i < maxfdp1; i++)
+    {
+        if (FD_ISSET(i, readset))
+        {
+            /* See if netconn of this socket is ready for read */
+            p_sock = get_socket(i);
+            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
+            {
+                FD_SET(i, &lreadset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+                nready++;
+            }
+        }
+        if (FD_ISSET(i, writeset))
+        {
+            /* See if netconn of this socket is ready for write */
+            p_sock = get_socket(i);
+            if (p_sock && p_sock->sendevent)
+            {
+                FD_SET(i, &lwriteset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+                nready++;
+            }
+        }
+    }
+    *readset = lreadset;
+    *writeset = lwriteset;
+    FD_ZERO(exceptset);
+
+    return nready;
+}
+
+
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+    int i;
+    int nready;
+    fd_set lreadset, lwriteset, lexceptset;
+    u32_t msectimeout;
+    struct lwip_select_cb select_cb;
+    struct lwip_select_cb *p_selcb;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+    select_cb.next = 0;
+    select_cb.readset = readset;
+    select_cb.writeset = writeset;
+    select_cb.exceptset = exceptset;
+    select_cb.sem_signalled = 0;
+
+    /* Protect ourselves searching through the list */
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+    sys_sem_wait(selectsem);
+
+    if (readset)
+        lreadset = *readset;
+    else
+        FD_ZERO(&lreadset);
+    if (writeset)
+        lwriteset = *writeset;
+    else
+        FD_ZERO(&lwriteset);
+    if (exceptset)
+        lexceptset = *exceptset;
+    else
+        FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+    /* If we don't have any current events, then suspend if we are supposed to */
+    if (!nready)
+    {
+        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
+        {
+            sys_sem_signal(selectsem);
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        /* add our semaphore to list */
+        /* We don't actually need any dynamic memory. Our entry on the
+         * list is only valid while we are in this function, so it's ok
+         * to use local variables */
+
+        select_cb.sem = sys_sem_new(0);
+        /* Note that we are still protected */
+        /* Put this select_cb on top of list */
+        select_cb.next = select_cb_list;
+        select_cb_list = &select_cb;
+
+        /* Now we can safely unprotect */
+        sys_sem_signal(selectsem);
+
+        /* Now just wait to be woken */
+        if (timeout == 0)
+            /* Wait forever */
+            msectimeout = 0;
+        else
+            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+
+        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+        /* Take us off the list */
+        sys_sem_wait(selectsem);
+        if (select_cb_list == &select_cb)
+            select_cb_list = select_cb.next;
+        else
+            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
+                if (p_selcb->next == &select_cb)
+                {
+                    p_selcb->next = select_cb.next;
+                    break;
+                }
+
+        sys_sem_signal(selectsem);
+
+        sys_sem_free(select_cb.sem);
+        if (i == 0)             /* Timeout */
+        {
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        if (readset)
+            lreadset = *readset;
+        else
+            FD_ZERO(&lreadset);
+        if (writeset)
+            lwriteset = *writeset;
+        else
+            FD_ZERO(&lwriteset);
+        if (exceptset)
+            lexceptset = *exceptset;
+        else
+            FD_ZERO(&lexceptset);
+
+        /* See what's set */
+        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+    }
+    else
+        sys_sem_signal(selectsem);
+
+    if (readset)
+        *readset = lreadset;
+    if (writeset)
+        *writeset = lwriteset;
+    if (exceptset)
+        *exceptset = lexceptset;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+    set_errno(0);
+
+    return nready;
+}
+
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+    int s;
+    struct lwip_socket *sock;
+    struct lwip_select_cb *scb;
+
+    /* Get socket */
+    if (conn)
+    {
+        s = conn->socket;
+        if (s < 0)
+        {
+            /* Data comes in right away after an accept, even though
+             * the server task might not have created a new socket yet.
+             * Just count down (or up) if that's the case and we
+             * will use the data later. Note that only receive events
+             * can happen before the new socket is set up. */
+            if (evt == NETCONN_EVT_RCVPLUS)
+                conn->socket--;
+            return;
+        }
+
+        sock = get_socket(s);
+        if (!sock)
+            return;
+    }
+    else
+        return;
+
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+
+    sys_sem_wait(selectsem);
+    /* Set event as required */
+    switch (evt)
+    {
+      case NETCONN_EVT_RCVPLUS:
+        sock->rcvevent++;
+        break;
+      case NETCONN_EVT_RCVMINUS:
+        sock->rcvevent--;
+        break;
+      case NETCONN_EVT_SENDPLUS:
+        sock->sendevent = 1;
+        break;
+      case NETCONN_EVT_SENDMINUS:
+        sock->sendevent = 0;
+        break;
+    }
+    sys_sem_signal(selectsem);
+
+    /* Now decide if anyone is waiting for this socket */
+    /* NOTE: This code is written this way to protect the select link list
+       but to avoid a deadlock situation by releasing socksem before
+       signalling for the select. This means we need to go through the list
+       multiple times ONLY IF a select was actually waiting. We go through
+       the list the number of waiting select calls + 1. This list is
+       expected to be small. */
+    while (1)
+    {
+        sys_sem_wait(selectsem);
+        for (scb = select_cb_list; scb; scb = scb->next)
+        {
+            if (scb->sem_signalled == 0)
+            {
+                /* Test this select call for our socket */
+                if (scb->readset && FD_ISSET(s, scb->readset))
+                    if (sock->rcvevent)
+                        break;
+                if (scb->writeset && FD_ISSET(s, scb->writeset))
+                    if (sock->sendevent)
+                        break;
+            }
+        }
+        if (scb)
+        {
+            scb->sem_signalled = 1;
+            sys_sem_signal(selectsem);
+            sys_sem_signal(scb->sem);
+        } else {
+            sys_sem_signal(selectsem);
+            break;
+        }
+    }
+
+}
+
+
+
+
+int lwip_shutdown(int s, int how)
+{
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr *naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_addr(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr->addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err = 0;
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval || NULL == optlen ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+      switch(optname) {
+         
+      case SO_ACCEPTCONN:
+      case SO_BROADCAST:
+      /* UNIMPL case SO_DEBUG: */
+      /* UNIMPL case SO_DONTROUTE: */
+      case SO_ERROR:
+      case SO_KEEPALIVE:
+      /* UNIMPL case SO_OOBINLINE: */
+      /* UNIMPL case SO_RCVBUF: */
+      /* UNIMPL case SO_SNDBUF: */
+      /* UNIMPL case SO_RCVLOWAT: */
+      /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+      case SO_REUSEADDR:
+      case SO_REUSEPORT:
+#endif /* SO_REUSE */
+      case SO_TYPE:
+      /* UNIMPL case SO_USELOOPBACK: */
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+          break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+      switch(optname) {
+      /* UNIMPL case IP_HDRINCL: */
+      /* UNIMPL case IP_RCVDSTADDR: */
+      /* UNIMPL case IP_RCVIF: */
+      case IP_TTL:
+      case IP_TOS:
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+        break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+         
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+      if( *optlen < sizeof(int) ) {
+        err = EINVAL;
+        break;
+    }
+      
+      /* If this is no TCP socket, ignore any options. */
+      if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+      switch( optname ) {
+      case TCP_NODELAY:
+      case TCP_KEEPALIVE:
+        break;
+         
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+   
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch( optname ) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (sock->conn->type) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+      case NETCONN_UDPLITE:
+      case NETCONN_UDPNOCHKSUM:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
+      }  /* switch */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.tcp->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.tcp->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+  }
+
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = 0;
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_RCVBUF: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch(optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+        break;
+      default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if( optlen < sizeof(int) ) {
+      err = EINVAL;
+        break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+    switch( optname ) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* UNDEFINED LEVEL */      
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch */
+
+
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->so_options |= optname;
+      } else {
+        sock->conn->pcb.tcp->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->flags |= TF_NODELAY;
+      } else {
+        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
+      break;
+    }  /* switch */
+    break;
+  }  /* switch */
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    *((u16_t*)argp) = sock->conn->recv_avail;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  }
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
new file mode 100644
index 000000000..b9e11f8e7
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/tcpip.h"
+
+static void (* tcpip_init_done)(void *arg) = NULL;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCP
+static int tcpip_tcp_timer_active = 0;
+
+static void
+tcpip_tcp_timer(void *arg)
+{
+  (void)arg;
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+
+  (void)arg;
+
+  ip_init();
+#if LWIP_UDP  
+  udp_init();
+#endif
+#if LWIP_TCP
+  tcp_init();
+#endif
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      api_msg_input(msg->msg.apimsg);
+      break;
+    case TCPIP_MSG_INPUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
+      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      break;
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      break;
+    default:
+      break;
+    }
+    memp_free(MEMP_TCPIP_MSG, msg);
+  }
+}
+
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    pbuf_free(p);    
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_INPUT;
+  msg->msg.inp.p = p;
+  msg->msg.inp.netif = inp;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+err_t
+tcpip_callback(void (*f)(void *ctx), void *ctx)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.f = f;
+  msg->msg.cb.ctx = ctx;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+void
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg *msg;
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    memp_free(MEMP_API_MSG, apimsg);
+    return;
+  }
+  msg->type = TCPIP_MSG_API;
+  msg->msg.apimsg = apimsg;
+  sys_mbox_post(mbox, msg);
+}
+
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new();
+  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
+}
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
new file mode 100644
index 000000000..2a9c1887d
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
@@ -0,0 +1,1454 @@
+/**
+ * @file
+ *
+ * Dynamic Host Configuration Protocol client
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+ 
+#include 
+ 
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/dhcp.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
+
+/** global transaction identifier, must be
+ *  unique for each DHCP request. We simply increment, starting
+ *  with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/** DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state);
+
+/** receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+static u16_t dhcp_get_option_short(u8_t *ptr);
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/** set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/** build outgoing messages */
+/** create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/** free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/** add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/** add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/** always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We back-off and will end up restarting a fresh DHCP negotiation later.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_nak(struct netif *netif) {
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t msecs = 10 * 1000;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%u\n", netif,
+    netif->name[0], netif->name[1], (unsigned int)netif->num));
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %u msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ */
+static void dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (unsigned int)netif->name[0],
+    (unsigned int)netif->name[1]));
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %u msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%u\n", netif,
+    netif->name[0], netif->name[1], netif->num));
+  if (option_ptr != NULL)
+  {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08lx\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08lx\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u32_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* TODO: we really should bind to a specific local interface here
+       but we cannot specify an unconfigured netif as it is addressless */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* send broadcast to any DHCP server */
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    /* reconnect to any (or to server here?!) */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
+    dhcp_set_state(dhcp, DHCP_REQUESTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ * 
+ */
+void dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (netif->dhcp->request_timeout-- == 1) {
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ *
+ */
+static void dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ */
+static void dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+  
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++)
+    {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
+    }
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ *
+ */
+err_t dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+  }
+  	
+	/* clear data structure */
+	memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+	dhcp->pcb = udp_new();
+	if (dhcp->pcb == NULL) {
+	  LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+	  mem_free((void *)dhcp);
+	  netif->dhcp = dhcp = NULL;
+	  return ERR_MEM;
+	}
+	LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ *
+ */
+void dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  netif->dhcp = dhcp;
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+    mem_free((void *)dhcp);
+    return;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu ?! */
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_send(dhcp->pcb, dhcp->p_out);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
+    dhcp->pcb = NULL;
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param addr The IP address we received a reply from
+ *
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+  /* is this DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08lx\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ */
+static err_t dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* @todo: should we really connect here? we are performing sendto() */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ */
+static err_t dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set receive callback function with netif as user data */
+    udp_recv(dhcp->pcb, dhcp_recv, netif);
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
+    dhcp_set_state(dhcp, DHCP_SELECTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void dhcp_bind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %lu secs\n", dhcp->offered_t1_renew));
+    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %lu secs\n", dhcp->offered_t2_rebind));
+    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
+    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
+    else sn_mask.addr = htonl(0xffff0000);
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08lx\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08lx\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08lx\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu in some way */
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set remote IP association to any DHCP server */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* broadcast to server */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %u msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  /* TODO: netif_down(netif); */
+  return result;
+}
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL)
+    {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    if (dhcp->p != NULL)
+    {
+      pbuf_free(dhcp->p);
+      dhcp->p = NULL;
+    }
+    /* free unfolded reply */
+    dhcp_free_reply(dhcp);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state)
+{
+  if (new_state != dhcp->state)
+  {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
+}
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t dhcp_unfold_reply(struct dhcp *dhcp)
+{
+  struct pbuf *p = dhcp->p;
+  u8_t *ptr;
+  u16_t i;
+  u16_t j = 0;
+  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
+  {
+    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL)
+    {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    return ERR_MEM;
+  }
+
+  ptr = (u8_t *)dhcp->msg_in;
+  /* proceed through struct dhcp_msg */
+  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
+  {
+    *ptr++ = ((u8_t *)p->payload)[j++];
+    /* reached end of pbuf? */
+    if (j == p->len)
+    {
+      /* proceed to next pbuf in chain */
+      p = p->next;
+      j = 0;
+    }
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes into dhcp->msg_in[]\n", i));
+  if (dhcp->options_in != NULL) {
+    ptr = (u8_t *)dhcp->options_in;
+    /* proceed through options */
+    for (i = 0; i < dhcp->options_in_len; i++) {
+      *ptr++ = ((u8_t *)p->payload)[j++];
+      /* reached end of pbuf? */
+      if (j == p->len) {
+        /* proceed to next pbuf in chain */
+        p = p->next;
+        j = 0;
+      }
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes to dhcp->options_in[]\n", i));
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %u.%u.%u.%u port %u\n", p,
+    (unsigned int)(ntohl(addr->addr) >> 24 & 0xff), (unsigned int)(ntohl(addr->addr) >> 16 & 0xff),
+    (unsigned int)(ntohl(addr->addr) >>  8 & 0xff), (unsigned int)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %u\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %u\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  (void)pcb; (void)addr; (void)port;
+  dhcp->p = p;
+  /* TODO: check packet length before reading them */
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %u\n", reply_msg->op));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%u]==%02x != reply_msg->chaddr[%u]==%02x\n",
+        i, netif->hwaddr[i], i, reply_msg->chaddr[i]));
+      pbuf_free(p);
+      dhcp->p = NULL;
+      return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+  pbuf_free(p);
+  dhcp->p = NULL;
+}
+
+
+static err_t dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t i;
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  /* give unique transaction identifier to this request */
+  dhcp->xid = xid++;
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
+  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
+  return ERR_OK;
+}
+
+static void dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  pbuf_free(dhcp->p_out);
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+
+static void dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_option_trailer: dhcp->options_out_len=%u, DHCP_OPTIONS_LEN=%u", dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param client DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%u, q->len=%u", msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %u in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %u in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%u\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %u\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return 0;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%u\n", *ptr));
+  return *ptr;
+}
+
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%u\n", value));
+  return value;
+}
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%lu\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
new file mode 100644
index 000000000..59c80ea48
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+#include "lwip/sys.h"
+
+/* This is a reference implementation of the checksum algorithm
+
+ - it may not work on all architectures, and all processors, particularly
+   if they have issues with alignment and 16 bit access.
+
+ - in this case you will need to port it to your architecture and 
+   #define LWIP_CHKSUM  
+   in your sys_arch.h
+*/
+#ifndef LWIP_CHKSUM
+#define LWIP_CHKSUM lwip_standard_chksum
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u32_t acc;
+
+  LWIP_DEBUGF(INET_DEBUG, ("lwip_chksum(%p, %d)\n", (void *)dataptr, len));
+  for(acc = 0; len > 1; len -= 2) {
+      /*    acc = acc + *((u16_t *)dataptr)++;*/
+    acc += *(u16_t *)dataptr;
+    dataptr = (void *)((u16_t *)dataptr + 1);
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)((*(u8_t *)dataptr) & 0xff) << 8);
+    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: odd byte %d\n", (unsigned int)(*(u8_t *)dataptr)));
+  } else {
+    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: no odd byte\n"));
+  }
+  acc = (acc >> 16) + (acc & 0xffffUL);
+
+  if ((acc & 0xffff0000) != 0) {
+    acc = (acc >> 16) + (acc & 0xffffUL);
+  }
+
+  return (u16_t)acc;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%lx \n", acc));*/
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%lx \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while (acc >> 16) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%lx\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+
+  acc = LWIP_CHKSUM(dataptr, len);
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return (u16_t)~(acc & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isascii
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isascii(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif		
+		
+
+ /*
+  * Ascii internet address interpretation routine.
+  * The value returned is in network order.
+  */
+
+ /*  */
+ /* inet_addr */
+ u32_t inet_addr(const char *cp)
+ {
+     struct in_addr val;
+
+     if (inet_aton(cp, &val)) {
+         return (val.s_addr);
+     }
+     return (INADDR_NONE);
+ }
+
+ /*
+  * Check whether "cp" is a valid ascii representation
+  * of an Internet address and convert to a binary address.
+  * Returns 1 if the address is valid, 0 if not.
+  * This replaces inet_addr, the return value from which
+  * cannot distinguish between failure and a local broadcast address.
+  */
+ /*  */
+ /* inet_aton */
+ int inet_aton(const char *cp, struct in_addr *addr)
+ {
+     u32_t val;
+     int base, n;
+     char c;
+     u32_t parts[4];
+     u32_t* pp = parts;
+
+     c = *cp;
+     for (;;) {
+         /*
+          * Collect number up to ``.''.
+          * Values are specified as for C:
+          * 0x=hex, 0=octal, isdigit=decimal.
+          */
+         if (!isdigit(c))
+             return (0);
+         val = 0; base = 10;
+         if (c == '0') {
+             c = *++cp;
+             if (c == 'x' || c == 'X')
+                 base = 16, c = *++cp;
+             else
+                 base = 8;
+         }
+         for (;;) {
+             if (isdigit(c)) {
+                 val = (val * base) + (int)(c - '0');
+                 c = *++cp;
+             } else if (base == 16 && isxdigit(c)) {
+                 val = (val << 4) |
+                     (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+                 c = *++cp;
+             } else
+             break;
+         }
+         if (c == '.') {
+             /*
+              * Internet format:
+              *  a.b.c.d
+              *  a.b.c   (with c treated as 16 bits)
+              *  a.b (with b treated as 24 bits)
+              */
+             if (pp >= parts + 3)
+                 return (0);
+             *pp++ = val;
+             c = *++cp;
+         } else
+             break;
+     }
+     /*
+      * Check for trailing characters.
+      */
+     if (c != '\0' && (!isascii(c) || !isspace(c)))
+         return (0);
+     /*
+      * Concoct the address according to
+      * the number of parts specified.
+      */
+     n = pp - parts + 1;
+     switch (n) {
+
+     case 0:
+         return (0);     /* initial nondigit */
+
+     case 1:             /* a -- 32 bits */
+         break;
+
+     case 2:             /* a.b -- 8.24 bits */
+         if (val > 0xffffff)
+             return (0);
+         val |= parts[0] << 24;
+         break;
+
+     case 3:             /* a.b.c -- 8.8.16 bits */
+         if (val > 0xffff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16);
+         break;
+
+     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+         if (val > 0xff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+         break;
+     }
+     if (addr)
+         addr->s_addr = htonl(val);
+     return (1);
+ }
+
+/* Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ */
+char *inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+
+#ifndef BYTE_ORDER
+#error BYTE_ORDER is not defined
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000) >> 8) |
+    ((n & 0xff000000) >> 24);
+}
+
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
new file mode 100644
index 000000000..c04915b73
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet6.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
new file mode 100644
index 000000000..45525e44c
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+#include "lwip/snmp.h"
+
+#include 
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  unsigned char type;
+  unsigned char code;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  u16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%u bytes) received\n", p->tot_len));
+    pbuf_free(p);
+    ICMP_STATS_INC(icmp.lenerr);
+    snmp_inc_icmpinerrors();
+    return;
+  }
+
+  type = *((u8_t *)p->payload);
+  code = *(((u8_t *)p->payload)+1);
+  switch (type) {
+  case ICMP_ECHO:
+    /* broadcast or multicast destination address? */
+    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+      ICMP_STATS_INC(icmp.err);
+      pbuf_free(p);
+      return;
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      snmp_inc_icmpinerrors();
+
+      return;
+    }
+    iecho = p->payload;
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    pbuf_header(p, hlen);
+    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+		 IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
+    break;
+  default:
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d code %d not supported.\n", (int)type, (int)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  ICMPH_TYPE_SET(idur, ICMP_DUR);
+  ICMPH_CODE_SET(idur, t);
+
+  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpoutdestunreachs();
+
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#if IP_FORWARD
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  tehdr = q->payload;
+  ICMPH_TYPE_SET(tehdr, ICMP_TE);
+  ICMPH_CODE_SET(tehdr, t);
+
+  /* copy fields from original packet */
+  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* IP_FORWARD */
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
new file mode 100644
index 000000000..368d97763
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
@@ -0,0 +1,508 @@
+/* @file
+ *
+ * This is the IP layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+#include "lwip/snmp.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+
+/**
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+  /* no initializations as of yet */
+}
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      /* return netif on which to forward IP packet */
+      return netif;
+    }
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+#if IP_FORWARD
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ */
+
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%lx found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+      snmp_inc_icmpouttimeexcds();
+    }
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%lx\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+    snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * 
+ * 
+ */
+
+err_t
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdrlen;
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %u\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+  /* obtain IP header length in number of 32-bit words */
+  iphdrlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdrlen *= 4;
+
+  /* header length exceeds first pbuf length? */
+  if (iphdrlen > p->len) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %u) does not fit in first pbuf (len %u), IP packet droppped.\n",
+      iphdrlen, p->len));
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdrlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%x) failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  for (netif = netif_list; netif != NULL; netif = netif->next) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%lx netif->ip_addr 0x%lx (0x%lx, 0x%lx, 0x%lx)\n",
+      iphdr->dest.addr, netif->ip_addr.addr,
+      iphdr->dest.addr & netif->netmask.addr,
+      netif->ip_addr.addr & netif->netmask.addr,
+      iphdr->dest.addr & ~(netif->netmask.addr)));
+
+    /* interface is up and configured? */
+    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
+    {
+      /* unicast to this interface address? */
+      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+         /* or broadcast on this interface network address? */
+         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+          netif->name[0], netif->name[1]));
+        /* break out of for loop */
+        break;
+      }
+    }
+  }
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %u\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    }
+    else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04x tot_len=%u len=%u MF=%u offset=%u), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%x) (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
+  if (iphdrlen > IP_HLEN) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0) {
+#endif /* LWIP_RAW */
+
+  switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+  case IP_PROTO_UDP:
+  case IP_PROTO_UDPLITE:
+    snmp_inc_ipindelivers();
+    udp_input(p, inp);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case IP_PROTO_TCP:
+    snmp_inc_ipindelivers();
+    tcp_input(p, inp);
+    break;
+#endif /* LWIP_TCP */
+  case IP_PROTO_ICMP:
+    snmp_inc_ipindelivers();
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable unless is was a broadcast */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+        !ip_addr_ismulticast(&(iphdr->dest))) {
+      p->payload = iphdr;
+      icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    }
+    pbuf_free(p);
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %d\n", IPH_PROTO(iphdr)));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+  }
+#if LWIP_RAW
+  } /* LWIP_RAW */
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ */
+
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+  u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  if (dest != IP_HDRINCL) {
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, htons(IP_DF));
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+  } else {
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu))
+    return ip_frag(p,netif,dest);
+#endif
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%u\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%lx\n", dest->addr));
+
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutdiscards();
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2d |%2d |  0x%02x |     %5u     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      |%u%u%u|    %4u   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |    0x%04x     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
new file mode 100644
index 000000000..2af526e9f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { 0x00000000UL };
+const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
+
+/* Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ *
+ */
+
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((addr->addr == ip_addr_broadcast.addr) ||
+      (addr->addr == ip_addr_any.addr))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr->addr == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr->addr & ~netif->netmask.addr) ==
+           (ip_addr_broadcast.addr & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
new file mode 100644
index 000000000..380929317
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
@@ -0,0 +1,345 @@
+/* @file
+ * 
+ * This is the IP packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include "lwip/opt.h"
+#include "lwip/sys.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/netif.h"
+
+#include "lwip/stats.h"
+
+#include 
+
+/*
+ * Copy len bytes from offset in pbuf to buffer 
+ *
+ * helper used by both ip_reass and ip_frag
+ */
+static struct pbuf *
+copy_from_pbuf(struct pbuf *p, u16_t * offset,
+           u8_t * buffer, u16_t len)
+{
+  u16_t l;
+
+  p->payload = (u8_t *)p->payload + *offset;
+  p->len -= *offset;
+  while (len) {
+    l = len < p->len ? len : p->len;
+    memcpy(buffer, p->payload, l);
+    buffer += l;
+    len -= l;
+    if (len)
+      p = p->next;
+    else
+      *offset = l;
+  }
+  return p;
+}
+
+#define IP_REASS_BUFSIZE 5760
+#define IP_REASS_MAXAGE 30
+#define IP_REASS_TMO 1000
+
+static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
+static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
+  0x0f, 0x07, 0x03, 0x01
+};
+static u16_t ip_reasslen;
+static u8_t ip_reassflags;
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+static u8_t ip_reasstmr;
+
+/* Reassembly timer */ 
+static void 
+ip_reass_timer(void *arg)
+{
+  (void)arg;
+  if (ip_reasstmr > 1) {
+    ip_reasstmr--;
+    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
+  } else if (ip_reasstmr == 1)
+  ip_reasstmr = 0;
+}
+
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *q;
+  struct ip_hdr *fraghdr, *iphdr;
+  u16_t offset, len;
+  u16_t i;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+
+  iphdr = (struct ip_hdr *) ip_reassbuf;
+  fraghdr = (struct ip_hdr *) p->payload;
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if (ip_reasstmr == 0) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
+    memcpy(iphdr, fraghdr, IP_HLEN);
+    ip_reasstmr = IP_REASS_MAXAGE;
+    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
+    ip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
+      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
+      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching old packet\n"));
+    IPFRAG_STATS_INC(ip_frag.cachehit);
+    /* Find out the offset in the reassembly buffer where we should
+       copy the fragment. */
+    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: fragment outside of buffer (%d:%d/%d).\n", offset,
+        offset + len, IP_REASS_BUFSIZE));
+      sys_untimeout(ip_reass_timer, NULL);
+      ip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: copying with offset %d into %d:%d\n", offset,
+      IP_HLEN + offset, IP_HLEN + offset + len));
+    i = IPH_HL(fraghdr) * 4;
+    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
+
+    /* Update the bitmap. */
+    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating single byte in bitmap.\n"));
+      /* If the two endpoints are in the same byte, we only update
+         that byte. */
+      ip_reassbitmap[offset / (8 * 8)] |=
+    bitmap_bits[(offset / 8) & 7] &
+    ~bitmap_bits[((offset + len) / 8) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+         bytes in the endpoints and fill the stuff inbetween with
+         0xff. */
+      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating many bytes in bitmap (%d:%d).\n",
+        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
+      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+  ip_reassbitmap[i] = 0xff;
+      }
+      ip_reassbitmap[(offset + len) / (8 * 8)] |=
+    ~bitmap_bits[((offset + len) / 8) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
+      ip_reasslen = offset + len;
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: last fragment seen, total len %d\n",
+        ip_reasslen));
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+         the bitmap. */
+      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
+  if (ip_reassbitmap[i] != 0xff) {
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: last fragment seen, bitmap %d/%d failed (%x)\n",
+      i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
+    goto nullreturn;
+  }
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+         right amount of bits. */
+      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
+    (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
+  LWIP_DEBUGF(IP_REASS_DEBUG,
+         ("ip_reass: last fragment seen, bitmap %d didn't contain %x (%x)\n",
+    ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
+    ip_reassbitmap[ip_reasslen / (8 * 8)]));
+  goto nullreturn;
+      }
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+         from now on. */
+      ip_reasslen += IP_HLEN;
+
+      IPH_LEN_SET(iphdr, htons(ip_reasslen));
+      IPH_OFFSET_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+      /* If we have come this far, we have a full packet in the
+         buffer, so we allocate a pbuf and copy the packet into it. We
+         also reset the timer. */
+      sys_untimeout(ip_reass_timer, NULL);
+      ip_reasstmr = 0;
+      pbuf_free(p);
+      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
+      if (p != NULL) {
+  i = 0;
+  for (q = p; q != NULL; q = q->next) {
+    /* Copy enough bytes to fill this pbuf in the chain. The
+       available data in the pbuf is given by the q->len
+       variable. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: memcpy from %p (%d) to %p, %d bytes\n",
+      (void *)&ip_reassbuf[i], i, q->payload,
+      q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
+    memcpy(q->payload, &ip_reassbuf[i],
+    q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
+    i += q->len;
+  }
+  IPFRAG_STATS_INC(ip_frag.fw);
+      } else {
+  IPFRAG_STATS_INC(ip_frag.memerr);
+      }
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
+      return p;
+    }
+  }
+
+nullreturn:
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+
+#define MAX_MTU 1500
+static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];
+
+/**
+ * Fragment an IP packet if too large
+ *
+ * Chop the packet in mtu sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_ROM)
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+  struct pbuf *header;
+  struct ip_hdr *iphdr;
+  u16_t nfb = 0;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+
+  /* Get a RAM based MTU sized pbuf */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  memcpy(iphdr, p->payload, IP_HLEN);
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    ofo += nfb;
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+
+    /* Fill this fragment */
+    nfb = (mtu - IP_HLEN) / 8;
+    cop = last ? left : nfb * 8;
+
+    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
+
+    /* Correct header */
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    pbuf_chain(header, rambuf);
+    netif->output(netif, header, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+    pbuf_free(header);
+
+    left -= cop;
+  }
+  pbuf_free(rambuf);
+  return ERR_OK;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
new file mode 100644
index 000000000..362000486
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
new file mode 100644
index 000000000..a162758aa
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  unsigned char type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.recv;
+#endif /* ICMP_STATS */
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((char *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.lenerr;
+#endif /* ICMP_STATS */
+
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((char *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.chkerr;
+#endif /* ICMP_STATS */
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+    /*    LWIP_DEBUGF("icmp: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d not supported.\n", (int)type));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.proterr;
+    ++lwip_stats.icmp.drop;
+#endif /* ICMP_STATS */
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (char)ICMP6_DUR;
+  idur->icode = (char)t;
+
+  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (char)ICMP6_TE;
+  tehdr->icode = (char)t;
+
+  /* copy fields from original packet */
+  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
new file mode 100644
index 000000000..abce830cf
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.fw;
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.recv;
+#endif /* IP_STATS */
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#ifdef IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+
+  pbuf_header(p, -IP_HLEN);
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p);
+    break;
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %u\n",
+          iphdr->nexthdr));
+
+#ifdef IP_STATS
+    ++lwip_stats.ip.proterr;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  printf("len %u tot_len %u\n", p->len, p->tot_len);
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+#endif /* IP_STATS */
+
+    return ERR_BUF;
+  }
+  printf("len %u tot_len %u\n", p->len, p->tot_len);
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    printf("!IP_HDRLINCL\n");
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %u)\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%lx\n", dest->addr));
+#ifdef IP_STATS
+    ++lwip_stats.ip.rterr;
+#endif /* IP_STATS */
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  char *payload;
+
+  payload = (char *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2d |  %x%x  |      %x%x           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      | %2u  |  %2u   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
new file mode 100644
index 000000000..d1bc358a6
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+
+int
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+int
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  memcpy(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+int
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
+
+
+/*#if IP_DEBUG*/
+void
+ip_addr_debug_print(struct ip_addr *addr)
+{
+  printf("%lx:%lx:%lx:%lx:%lx:%lx:%lx:%lx",
+         ntohl(addr->addr[0]) >> 16 & 0xffff,
+         ntohl(addr->addr[0]) & 0xffff,
+         ntohl(addr->addr[1]) >> 16 & 0xffff,
+         ntohl(addr->addr[1]) & 0xffff,
+         ntohl(addr->addr[2]) >> 16 & 0xffff,
+         ntohl(addr->addr[2]) & 0xffff,
+         ntohl(addr->addr[3]) >> 16 & 0xffff,
+         ntohl(addr->addr[3]) & 0xffff);
+}
+/*#endif*/ /* IP_DEBUG */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
new file mode 100644
index 000000000..aea62963b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
@@ -0,0 +1,310 @@
+/** @file
+ *
+ * Dynamic memory manager
+ *
+ */
+
+/* 
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/stats.h"
+
+struct mem {
+  mem_size_t next, prev;
+#if MEM_ALIGNMENT == 1
+  u8_t used;
+#elif MEM_ALIGNMENT == 2
+  u16_t used;
+#elif MEM_ALIGNMENT == 4
+  u32_t used;
+#elif MEM_ALIGNMENT == 8
+  u64_t used;
+#else
+#error "unhandled MEM_ALIGNMENT size"
+#endif /* MEM_ALIGNMENT */
+}; 
+
+static struct mem *ram_end;
+static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
+
+#define MIN_SIZE 12
+#if 0 /* this one does not align correctly for some, resulting in crashes */
+#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
+#else
+#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
+                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
+                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
+#endif
+
+static struct mem *lfree;   /* pointer to the lowest free block */
+
+static sys_sem_t mem_sem;
+
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+  
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
+  
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+
+}
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  memset(ram, 0, MEM_SIZE);
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE;
+  mem->prev = 0;
+  mem->used = 0;
+  ram_end = (struct mem *)&ram[MEM_SIZE];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE;
+  ram_end->prev = MEM_SIZE;
+
+  mem_sem = sys_sem_new(1);
+
+  lfree = (struct mem *)ram;
+
+#if MEM_STATS
+  lwip_stats.mem.avail = MEM_SIZE;
+#endif /* MEM_STATS */
+}
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+    ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+    sys_sem_signal(mem_sem);
+    return;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  
+  mem->used = 0;
+
+  if (mem < lfree) {
+    lfree = mem;
+  }
+  
+#if MEM_STATS
+  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+  
+#endif /* MEM_STATS */
+  plug_holes(mem);
+  sys_sem_signal(mem_sem);
+}
+void *
+mem_reallocm(void *rmem, mem_size_t newsize)
+{
+  void *nmem;
+  nmem = mem_malloc(newsize);
+  if (nmem == NULL) {
+    return mem_realloc(rmem, newsize);
+  }
+  memcpy(nmem, rmem, newsize);
+  mem_free(rmem);
+  return nmem;
+}
+
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((newsize % MEM_ALIGNMENT) != 0) {
+   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (newsize > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+  
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+    return rmem;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+#if MEM_STATS
+  lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+  
+  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+
+    plug_holes(mem2);
+  }
+  sys_sem_signal(mem_sem);  
+  return rmem;
+}
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((size % MEM_ALIGNMENT) != 0) {
+    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (size > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+    if (!mem->used &&
+       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
+      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+      mem2 = (struct mem *)&ram[ptr2];
+
+      mem2->prev = ptr;      
+      mem2->next = mem->next;
+      mem->next = ptr2;      
+      if (mem2->next != MEM_SIZE) {
+        ((struct mem *)&ram[mem2->next])->prev = ptr2;
+      }
+      
+      mem2->used = 0;      
+      mem->used = 1;
+#if MEM_STATS
+      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
+        lwip_stats.mem.max = lwip_stats.mem.used;
+  } */
+      if (lwip_stats.mem.max < ptr2) {
+        lwip_stats.mem.max = ptr2;
+      }      
+#endif /* MEM_STATS */
+
+      if (mem == lfree) {
+  /* Find next free block after mem */
+        while (lfree->used && lfree != ram_end) {
+    lfree = (struct mem *)&ram[lfree->next];
+        }
+        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+      }
+      sys_sem_signal(mem_sem);
+      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+    }    
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %d bytes\n", (int)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */  
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
new file mode 100644
index 000000000..c570b7e10
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+struct memp {
+  struct memp *next;
+};
+
+
+
+static struct memp *memp_tab[MEMP_MAX];
+
+static const u16_t memp_sizes[MEMP_MAX] = {
+  sizeof(struct pbuf),
+  sizeof(struct raw_pcb),
+  sizeof(struct udp_pcb),
+  sizeof(struct tcp_pcb),
+  sizeof(struct tcp_pcb_listen),
+  sizeof(struct tcp_seg),
+  sizeof(struct netbuf),
+  sizeof(struct netconn),
+  sizeof(struct api_msg),
+  sizeof(struct tcpip_msg),
+  sizeof(struct sys_timeout)
+};
+
+static const u16_t memp_num[MEMP_MAX] = {
+  MEMP_NUM_PBUF,
+  MEMP_NUM_RAW_PCB,
+  MEMP_NUM_UDP_PCB,
+  MEMP_NUM_TCP_PCB,
+  MEMP_NUM_TCP_PCB_LISTEN,
+  MEMP_NUM_TCP_SEG,
+  MEMP_NUM_NETBUF,
+  MEMP_NUM_NETCONN,
+  MEMP_NUM_API_MSG,
+  MEMP_NUM_TCPIP_MSG,
+  MEMP_NUM_SYS_TIMEOUT
+};
+
+static u8_t memp_memory[(MEMP_NUM_PBUF *
+       MEM_ALIGN_SIZE(sizeof(struct pbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_RAW_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_UDP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB_LISTEN *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_SEG *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETBUF *
+       MEM_ALIGN_SIZE(sizeof(struct netbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETCONN *
+       MEM_ALIGN_SIZE(sizeof(struct netconn) +
+          sizeof(struct memp)) +
+      MEMP_NUM_API_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct api_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCPIP_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_SYS_TIMEOUT *
+       MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
+          sizeof(struct memp)))];
+
+
+#if !SYS_LIGHTWEIGHT_PROT
+static sys_sem_t mutex;
+#endif
+
+#if MEMP_SANITY_CHECK
+static int
+memp_sanity(void)
+{
+  int i, c;
+  struct memp *m, *n;
+
+  for(i = 0; i < MEMP_MAX; i++) {
+    for(m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for(n = memp_tab[i]; n != NULL; n = n->next) {
+         if (n == m) {
+          --c;
+        }
+        if (c < 0) return 0; /* LW was: abort(); */
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+
+void
+memp_init(void)
+{
+  struct memp *m, *memp;
+  u16_t i, j;
+  u16_t size;
+      
+#if MEMP_STATS
+  for(i = 0; i < MEMP_MAX; ++i) {
+    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+      lwip_stats.memp[i].err = 0;
+    lwip_stats.memp[i].avail = memp_num[i];
+  }
+#endif /* MEMP_STATS */
+
+  memp = (struct memp *)&memp_memory[0];
+  for(i = 0; i < MEMP_MAX; ++i) {
+    size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
+    if (memp_num[i] > 0) {
+      memp_tab[i] = memp;
+      m = memp;
+      
+      for(j = 0; j < memp_num[i]; ++j) {
+  m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
+  memp = m;
+  m = m->next;
+      }
+      memp->next = NULL;
+      memp = m;
+    } else {
+      memp_tab[i] = NULL;
+    }
+  }
+
+#if !SYS_LIGHTWEIGHT_PROT
+  mutex = sys_sem_new(1);
+#endif
+
+  
+}
+
+void *
+memp_malloc(memp_t type)
+{
+  struct memp *memp;
+  void *mem;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif
+ 
+  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {    
+    memp_tab[type] = memp->next;    
+    memp->next = NULL;
+#if MEMP_STATS
+    ++lwip_stats.memp[type].used;
+    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+    }
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+    sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+     ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
+
+    mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
+    return mem;
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %d\n", type));
+#if MEMP_STATS
+    ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    return NULL;
+  }
+}
+
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  if (mem == NULL) {
+    return;
+  }
+  memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
+
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+#if MEMP_STATS
+  lwip_stats.memp[type].used--; 
+#endif /* MEMP_STATS */
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif  
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
new file mode 100644
index 000000000..32deb8d9d
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
@@ -0,0 +1,288 @@
+/**
+ * @file
+ *
+ * lwIP network interface abstraction
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+
+struct netif *netif_list = NULL;
+struct netif *netif_default = NULL;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static int netifnum = 0;
+  
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        break;
+        }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_default = NULL;
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
+  /** For Ethernet network interfaces, we would like to send a
+   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+   *  to spontaneously cause other nodes to update an entry in their
+   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+   */ 
+  etharp_query(netif, ipaddr, NULL);
+#endif
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  ip_addr_set(&(netif->netmask), netmask);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+void
+netif_set_default(struct netif *netif)
+{
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  netif->flags |= NETIF_FLAG_UP;
+}
+
+/**
+ * Ask if an interface is up
+ */ 
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  netif->flags &= ~NETIF_FLAG_UP;
+}
+
+void
+netif_init(void)
+{
+  netif_list = netif_default = NULL;
+}
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
new file mode 100644
index 000000000..ad929c6b5
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
@@ -0,0 +1,962 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. Currently, queues are only
+ * supported in a limited section of lwIP, this is the etharp queueing
+ * code. Outside of this section no packet queues are supported yet.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/stats.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/sys.h"
+
+#include "arch/perf.h"
+
+#include 
+
+static u8_t pbuf_pool_memory[(PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf)))];
+
+#if !SYS_LIGHTWEIGHT_PROT
+static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
+static sys_sem_t pbuf_pool_free_sem;
+#endif
+
+static struct pbuf *pbuf_pool = NULL;
+
+/**
+ * Initializes the pbuf module.
+ *
+ * A large part of memory is allocated for holding the pool of pbufs.
+ * The size of the individual pbufs in the pool is given by the size
+ * parameter, and the number of pbufs in the pool by the num parameter.
+ *
+ * After the memory has been allocated, the pbufs are set up. The
+ * ->next pointer in each pbuf is set up to point to the next pbuf in
+ * the pool.
+ *
+ */
+void
+pbuf_init(void)
+{
+  struct pbuf *p, *q = NULL;
+  u16_t i;
+
+  pbuf_pool = (struct pbuf *)&pbuf_pool_memory[0];
+  LWIP_ASSERT("pbuf_init: pool aligned", (mem_ptr_t)pbuf_pool % MEM_ALIGNMENT == 0);
+
+#if PBUF_STATS
+  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
+#endif /* PBUF_STATS */
+
+  /* Set up ->next pointers to link the pbufs of the pool together */
+  p = pbuf_pool;
+
+  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
+    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
+    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
+    p->flags = PBUF_FLAG_POOL;
+    q = p;
+    p = p->next;
+  }
+
+  /* The ->next pointer of last pbuf is NULL to indicate that there
+     are no more pbufs in the pool */
+  q->next = NULL;
+
+#if !SYS_LIGHTWEIGHT_PROT
+  pbuf_pool_alloc_lock = 0;
+  pbuf_pool_free_lock = 0;
+  pbuf_pool_free_sem = sys_sem_new(1);
+#endif
+}
+
+/**
+ * @internal only called from pbuf_alloc()
+ */
+static struct pbuf *
+pbuf_pool_alloc(void)
+{
+  struct pbuf *p = NULL;
+
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+
+#if !SYS_LIGHTWEIGHT_PROT
+  /* Next, check the actual pbuf pool, but if the pool is locked, we
+     pretend to be out of buffers and return NULL. */
+  if (pbuf_pool_free_lock) {
+#if PBUF_STATS
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+    return NULL;
+  }
+  pbuf_pool_alloc_lock = 1;
+  if (!pbuf_pool_free_lock) {
+#endif /* SYS_LIGHTWEIGHT_PROT */
+    p = pbuf_pool;
+    if (p) {
+      pbuf_pool = p->next;
+    }
+#if !SYS_LIGHTWEIGHT_PROT
+#if PBUF_STATS
+  } else {
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+  }
+  pbuf_pool_alloc_lock = 0;
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#if PBUF_STATS
+  if (p != NULL) {
+    ++lwip_stats.pbuf.used;
+    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
+      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
+    }
+  }
+#endif /* PBUF_STATS */
+
+  SYS_ARCH_UNPROTECT(old_level);
+  return p;
+}
+
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param flag this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u)\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (l) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (flag) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = pbuf_pool_alloc();
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+#if PBUF_STATS
+      ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+      return NULL;
+    }
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = pbuf_pool_alloc();
+      if (q == NULL) {
+       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
+#if PBUF_STATS
+        ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      q->tot_len = rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
+      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = PBUF_FLAG_RAM;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u) == %p\n", length, (void *)p));
+  return p;
+}
+
+
+#if PBUF_STATS
+#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
+#else /* PBUF_STATS */
+#define DEC_PBUF_STATS
+#endif /* PBUF_STATS */
+
+#define PBUF_POOL_FAST_FREE(p)  do {                                    \
+                                  p->next = pbuf_pool;                  \
+                                  pbuf_pool = p;                        \
+                                  DEC_PBUF_STATS;                       \
+                                } while (0)
+
+#if SYS_LIGHTWEIGHT_PROT
+#define PBUF_POOL_FREE(p)  do {                                         \
+                                SYS_ARCH_DECL_PROTECT(old_level);       \
+                                SYS_ARCH_PROTECT(old_level);            \
+                                PBUF_POOL_FAST_FREE(p);                 \
+                                SYS_ARCH_UNPROTECT(old_level);          \
+                               } while (0)
+#else /* SYS_LIGHTWEIGHT_PROT */
+#define PBUF_POOL_FREE(p)  do {                                         \
+                             sys_sem_wait(pbuf_pool_free_sem);          \
+                             PBUF_POOL_FAST_FREE(p);                    \
+                             sys_sem_signal(pbuf_pool_free_sem);        \
+                           } while (0)
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @bug Cannot grow the size of a pbuf (chain) (yet).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s16_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
+              p->flags == PBUF_FLAG_ROM ||
+              p->flags == PBUF_FLAG_RAM ||
+              p->flags == PBUF_FLAG_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    q->tot_len += grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param hdr_size_inc Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  void *payload;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL)) return 0;
+ 
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload,
+        (void *)(p + 1)));\
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%d)\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param pbuf The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t count;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  /* if assertions are disabled, proceed with debug output */
+  if (p == NULL) {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane flags",
+    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
+    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
+
+  count = 0;
+  /* Since decrementing ref cannot be guaranteed to be a single machine operation
+   * we must protect it. Also, the later test of ref must be protected.
+   */
+  SYS_ARCH_PROTECT(old_level);
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    p->ref--;
+    /* this pbuf is no longer referenced to? */
+    if (p->ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
+      /* is this a pbuf from the pool? */
+      if (p->flags == PBUF_FLAG_POOL) {
+        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
+        PBUF_POOL_FREE(p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* p->flags == PBUF_FLAG_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %u, ending here.\n", (void *)p, (unsigned int)p->ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
+  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
+  if ((h == NULL) || (t == NULL)) return;
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/* For packet queueing. Note that queued packets MUST be dequeued first
+ * using pbuf_dequeue() before calling other pbuf_() functions. */
+#if ARP_QUEUEING
+/**
+ * Add a packet to the end of a queue.
+ *
+ * @param q pointer to first packet on the queue
+ * @param n packet to be queued
+ *
+ * Both packets MUST be given, and must be different.
+ */
+void
+pbuf_queue(struct pbuf *p, struct pbuf *n)
+{
+#if PBUF_DEBUG /* remember head of queue */
+  struct pbuf *q = p;
+#endif
+  /* programmer stupidity checks */
+  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
+  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
+  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
+  if ((p == NULL) || (n == NULL) || (p == n)){
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"))
+    return;
+  }
+
+  /* iterate through all packets on queue */
+  while (p->next != NULL) {
+/* be very picky about pbuf chain correctness */
+#if PBUF_DEBUG
+    /* iterate through all pbufs in packet */
+    while (p->tot_len != p->len) {
+      /* make sure invariant condition holds */
+      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+      /* make sure each packet is complete */
+      LWIP_ASSERT("p->next != NULL", p->next != NULL);
+      p = p->next;
+      /* { p->tot_len == p->len => p is last pbuf of a packet } */
+    }
+    /* { p is last pbuf of a packet } */
+    /* proceed to next packet on queue */
+#endif
+    /* proceed to next pbuf */
+    if (p->next != NULL) p = p->next;
+  }
+  /* { p->tot_len == p->len and p->next == NULL } ==>
+   * { p is last pbuf of last packet on queue } */
+  /* chain last pbuf of queue with n */
+  p->next = n;
+  /* n is now referenced to by the (packet p in the) queue */
+  pbuf_ref(n);
+#if PBUF_DEBUG
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
+    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
+    (void *)n, (void *)p, (void *)q));
+#endif
+}
+
+/**
+ * Remove a packet from the head of a queue.
+ *
+ * The caller MUST reference the remainder of the queue (as returned). The
+ * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
+ * from p.
+ * 
+ * @param p pointer to first packet on the queue which will be dequeued.
+ * @return first packet on the remaining queue (NULL if no further packets).
+ *
+ */
+struct pbuf *
+pbuf_dequeue(struct pbuf *p)
+{
+  struct pbuf *q;
+  LWIP_ASSERT("p != NULL", p != NULL);
+
+  /* iterate through all pbufs in packet p */
+  while (p->tot_len != p->len) {
+    /* make sure invariant condition holds */
+    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+    /* make sure each packet is complete */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+    p = p->next;
+  }
+  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
+  /* remember next packet on queue in q */
+  q = p->next;
+  /* dequeue packet p from queue */
+  p->next = NULL;
+  /* any next packet on queue? */
+  if (q != NULL) {
+    /* although q is no longer referenced by p, it MUST be referenced by
+     * the caller, who is maintaining this packet queue. So, we do not call
+     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
+  } else {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
+  }
+  return q;
+}
+#endif
+
+/**
+ *
+ * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * Go through a pbuf chain and replace any PBUF_REF buffers
+ * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
+ * the referenced data.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ * The pbuf you give as argument, may have been replaced
+ * by a (differently located) copy through pbuf_take()!
+ *
+ * @note Any replaced pbufs will be freed through pbuf_free().
+ * This may deallocate them if they become no longer referenced.
+ *
+ * @param p Head of pbuf chain to process
+ *
+ * @return Pointer to head of pbuf chain
+ */
+struct pbuf *
+pbuf_take(struct pbuf *p)
+{
+  struct pbuf *q , *prev, *head;
+  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
+
+  prev = NULL;
+  head = p;
+  /* iterate through pbuf chain */
+  do
+  {
+    /* pbuf is of type PBUF_REF? */
+    if (p->flags == PBUF_FLAG_REF) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
+      /* allocate a pbuf (w/ payload) fully in RAM */
+      /* PBUF_POOL buffers are faster if we can use them */
+      if (p->len <= PBUF_POOL_BUFSIZE) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
+        }
+      } else {
+        /* no replacement pbuf yet */
+        q = NULL;
+        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
+      }
+      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
+      if (q == NULL) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
+        }
+      }
+      /* replacement pbuf could be allocated? */
+      if (q != NULL)
+      {
+        /* copy p to q */
+        /* copy successor */
+        q->next = p->next;
+        /* remove linkage from original pbuf */
+        p->next = NULL;
+        /* remove linkage to original pbuf */
+        if (prev != NULL) {
+          /* prev->next == p at this point */
+          LWIP_ASSERT("prev->next == p", prev->next == p);
+          /* break chain and insert new pbuf instead */
+          prev->next = q;
+        /* prev == NULL, so we replaced the head pbuf of the chain */
+        } else {
+          head = q;
+        }
+        /* copy pbuf payload */
+        memcpy(q->payload, p->payload, p->len);
+        q->tot_len = p->tot_len;
+        q->len = p->len;
+        /* in case p was the first pbuf, it is no longer refered to by
+         * our caller, as the caller MUST do p = pbuf_take(p);
+         * in case p was not the first pbuf, it is no longer refered to
+         * by prev. we can safely free the pbuf here.
+         * (note that we have set p->next to NULL already so that
+         * we will not free the rest of the chain by accident.)
+         */
+        pbuf_free(p);
+        /* do not copy ref, since someone else might be using the old buffer */
+        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
+        p = q;
+      } else {
+        /* deallocate chain */
+        pbuf_free(head);
+        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
+        return NULL;
+      }
+    /* p->flags != PBUF_FLAG_REF */
+    } else {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
+    }
+    /* remember this pbuf */
+    prev = p;
+    /* proceed to next pbuf in original chain */
+    p = p->next;
+  } while (p);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
+
+  return head;
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return (tail_gone > 0? NULL: q);
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
new file mode 100644
index 000000000..5f1f5b24e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
@@ -0,0 +1,328 @@
+/**
+ * @file
+ * 
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_RAW
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs = NULL;
+
+void
+raw_init(void)
+{
+  raw_pcbs = NULL;
+}
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param pbuf pbuf to be demultiplexed to a RAW PCB.
+ * @param netif network interface on which the datagram was received.
+ * @Return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb;
+  struct ip_hdr *iphdr;
+  int proto;
+  u8_t eaten = 0;
+
+  ( void ) inp;
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        /* the receive callback function did not eat the packet? */
+        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
+        {
+          /* receive function ate the packet */
+          p = NULL;
+          eaten = 1;
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+      /* drop the packet */
+    }
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    pbuf_header(q, -IP_HLEN);
+  }
+  
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%lx\n", ipaddr->addr));
+#if RAW_STATS
+    /*    ++lwip_stats.raw.rterr;*/
+#endif /* RAW_STATS */
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in raw_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u16_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
new file mode 100644
index 000000000..56768896b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+
+#if LWIP_STATS
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+  memset(&lwip_stats, 0, sizeof(struct stats_));
+}
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %d\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("rexmit: %d\n\t", proto->rexmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %d\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %d\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %d\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %d\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %d\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %d\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %d\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %d\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %d\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %d\n", proto->cachehit)); 
+}
+
+void
+stats_display_pbuf(struct stats_pbuf *pbuf)
+{
+  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
+  LWIP_PLATFORM_DIAG(("avail: %d\n\t", pbuf->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %d\n\t", pbuf->used)); 
+  LWIP_PLATFORM_DIAG(("max: %d\n\t", pbuf->max)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n\t", pbuf->err)); 
+  LWIP_PLATFORM_DIAG(("alloc_locked: %d\n\t", pbuf->alloc_locked)); 
+  LWIP_PLATFORM_DIAG(("refresh_locked: %d\n", pbuf->refresh_locked)); 
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %d\n\t", mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %d\n\t", mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %d\n\t", mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n", mem->err));
+  
+}
+
+void
+stats_display(void)
+{
+  int i;
+  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
+	  		"TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
+  stats_display_proto(&lwip_stats.link, "LINK");
+  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+  stats_display_proto(&lwip_stats.ip, "IP");
+  stats_display_proto(&lwip_stats.icmp, "ICMP");
+  stats_display_proto(&lwip_stats.udp, "UDP");
+  stats_display_proto(&lwip_stats.tcp, "TCP");
+  stats_display_pbuf(&lwip_stats.pbuf);
+  stats_display_mem(&lwip_stats.mem, "HEAP");
+  for (i = 0; i < MEMP_MAX; i++) {
+    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+  }
+	
+}
+#endif /* LWIP_STATS_DISPLAY */
+#endif /* LWIP_STATS */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
new file mode 100644
index 000000000..a07a839a6
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+
+#if (NO_SYS == 0)
+
+struct sswt_cb
+{
+    int timeflag;
+    sys_sem_t *psem;
+};
+
+
+
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_mbox_fetch(mbox, msg, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
+      	h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
+      return;*/
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
+        h(arg);
+      }
+
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%lu h=%p arg=%p\n",
+    (void *)timeout, msecs, (void *)h, (void *)arg));
+
+  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+
+}
+
+/* Go through timeout list (for this task only) and remove the first matching entry,
+   even though the timeout has not triggered yet.
+*/
+
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+    struct sys_timeouts *timeouts;
+    struct sys_timeout *prev_t, *t;
+
+    timeouts = sys_arch_timeouts();
+
+    if (timeouts->next == NULL)
+        return;
+
+    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
+    {
+        if ((t->h == h) && (t->arg == arg))
+        {
+            /* We have a match */
+            /* Unlink from previous in list */
+            if (prev_t == NULL)
+                timeouts->next = t->next;
+            else
+                prev_t->next = t->next;
+            /* If not the last one, add time of this one back to next */
+            if (t->next != NULL)
+                t->next->time += t->time;
+            memp_free(MEMP_SYS_TIMEOUT, t);
+            return;
+        }
+    }
+    return;
+}
+
+
+
+
+
+static void
+sswt_handler(void *arg)
+{
+    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+    /* Timeout. Set flag to TRUE and signal semaphore */
+    sswt_cb->timeflag = 1;
+    sys_sem_signal(*(sswt_cb->psem));
+}
+
+/* Wait for a semaphore with timeout (specified in ms) */
+/* timeout = 0: wait forever */
+/* Returns 0 on timeout. 1 otherwise */
+
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+    struct sswt_cb sswt_cb;
+
+    sswt_cb.psem = &sem;
+    sswt_cb.timeflag = 0;
+
+    /* If timeout is zero, then just wait forever */
+    if (timeout > 0)
+        /* Create a timer and pass it the address of our flag */
+        sys_timeout(timeout, sswt_handler, &sswt_cb);
+    sys_sem_wait(sem);
+    /* Was it a timeout? */
+    if (sswt_cb.timeflag)
+    {
+        /* timeout */
+        return 0;
+    } else {
+        /* Not a timeout. Remove timeout entry */
+        sys_untimeout(sswt_handler, &sswt_cb);
+        return 1;
+    }
+
+}
+
+
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
new file mode 100644
index 000000000..b36b79416
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
@@ -0,0 +1,1263 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/tcp.h"
+#if LWIP_TCP
+
+/* Incremented every coarse grained timer shot
+   (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;  
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Initializes the TCP layer.
+ */
+void
+tcp_init(void)
+{
+  /* Clear globals. */
+  tcp_listen_pcbs.listen_pcbs = NULL;
+  tcp_active_pcbs = NULL;
+  tcp_tw_pcbs = NULL;
+  tcp_tmp_pcb = NULL;
+  
+  /* initialize timer */
+  tcp_ticks = 0;
+  tcp_timer = 0;
+  
+}
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));
+  tcp_debug_print_state(pcb->state);
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+#endif /* TCP_DEBUG */
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case SYN_RCVD:
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    err = tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Aborts a connection by sending a RST to the remote host and deletes
+ * the local protocol control block. This is done when a connection is
+ * killed because of shortage of memory.
+ *
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
+    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ */
+
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+#if SO_REUSE
+  int reuse_port_all_set = 1;
+#endif /* SO_REUSE */
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+#if SO_REUSE == 0
+  /* Check if the address already is in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+        ip_addr_isany(ipaddr) ||
+        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+          return ERR_USE;
+      }
+    }
+  }
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+   ip_addr_isany(ipaddr) ||
+   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+  return ERR_USE;
+      }
+    }
+  }
+#else /* SO_REUSE */
+  /* Search through list of PCB's in LISTEN state. 
+     
+  If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
+  or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
+  the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
+  But no two PCB's bound to same local port and same local address is valid.
+  
+  If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+  all PCB's must have the SOF_REUSEPORT option set.
+  
+  When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+  address is already in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }      
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
+        }     
+      }
+    }
+  }
+
+  /* Search through list of PCB's in a state in which they can accept or send data. Same decription as for 
+     PCB's in state LISTEN applies to this PCB's regarding the options SOF_REUSEADDR and SOF_REUSEPORT. */
+  for(cpcb = tcp_active_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }   
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
+        }        
+      }
+    }
+  }
+
+  /* Search through list of PCB's in TIME_WAIT state. If SO_REUSEADDR is set a bound combination [IP, port} 
+     can be rebound. The same applies when SOF_REUSEPORT is set. 
+     
+     If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+     all PCB's must have the SOF_REUSEPORT option set.
+     
+     When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+     address is already in use. */
+  for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT or SO_REUSEADDR not set and same address.\n"));
+          return ERR_USE;
+        }
+        else if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+      }
+    }
+  }
+
+  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
+     {IP, port} can't be reused. */
+  if(!reuse_port_all_set) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: not all sockets have SO_REUSEPORT set.\n"));
+    return ERR_USE;
+  }
+#endif /* SO_REUSE */
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %u\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  (void)arg;
+  (void)pcb;
+  (void)err;
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ */
+struct tcp_pcb *
+tcp_listen(struct tcp_pcb *pcb)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+  } else {
+    pcb->rcv_wnd += len;
+  }
+  if (!(pcb->flags & TF_ACK_DELAY) &&
+     !(pcb->flags & TF_ACK_NOW)) {
+    /*
+     * We send an ACK here (if one is not already pending, hence
+     * the above tests) as tcp_recved() implies that the application
+     * has processed some data, and so we can open the receiver's
+     * window to allow more to be transmitted.  This could result in
+     * two ACKs being sent for each received packet in some limited cases
+     * (where the application is only receiving data, and is slow to
+     * process it) but it is necessary to guarantee that the sender can
+     * continue to transmit.
+     */
+    tcp_ack(pcb);
+  } 
+  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
+    /* If we can send a window update such that there is a full
+     * segment available in the window, do so now.  This is sort of
+     * nagle-like in its goals, and tries to hit a compromise between
+     * sending acks each time the window is updated, and only sending
+     * window updates when a timer expires.  The "threshold" used
+     * above (currently TCP_WND/2) can be tuned to be more or less
+     * aggressive  */
+    tcp_ack_now(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %u bytes, wnd %u (%u).\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  u32_t optdata;
+  err_t ret;
+  u32_t iss;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %u\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->snd_wnd = TCP_WND;
+  pcb->mss = TCP_MSS;
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API  
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */  
+  TCP_REG(&tcp_active_pcbs, pcb);
+  
+  /* Build an MSS option */
+  optdata = htonl(((u32_t)2 << 24) | 
+      ((u32_t)4 << 16) | 
+      (((u32_t)pcb->mss / 256) << 8) |
+      (pcb->mss & 255));
+
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
+  if (ret == ERR_OK) { 
+    tcp_output(pcb);
+  }
+  return ret;
+} 
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u32_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      ++pcb->rtime;
+      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+
+        /* Time for a retransmission. */
+        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %u pcb->rto %u\n",
+          pcb->rtime, pcb->rto));
+
+        /* Double retransmission time-out unless we are trying to
+         * connect to somebody (i.e., we are in SYN_SENT). */
+        if (pcb->state != SYN_SENT) {
+          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+        }
+        /* Reduce congestion window and ssthresh. */
+        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+        pcb->ssthresh = eff_wnd >> 1;
+        if (pcb->ssthresh < pcb->mss) {
+          pcb->ssthresh = pcb->mss * 2;
+        }
+        pcb->cwnd = pcb->mss;
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %u ssthresh %u\n",
+                                pcb->cwnd, pcb->ssthresh));
+ 
+        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
+        tcp_rexmit_rto(pcb);
+     }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+   /* Check if KEEPALIVE should be sent */
+   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
+         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %u.%u.%u.%u.\n",
+                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+         tcp_abort(pcb);
+      }
+      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
+         tcp_keepalive(pcb);
+         pcb->keep_cnt++;
+      }
+   }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL &&
+       (u32_t)tcp_ticks - pcb->tmr >=
+       pcb->rto * (u32_t)TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+   TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+      
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;    
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  /* send delayed ACKs */  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment.
+ *
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ *
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  memcpy((char *)cseg, (const char *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+static err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  arg = arg;
+  if (p != NULL) {
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than
+     prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%ld)\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%ld)\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      tcp_kill_prio(prio);    
+      pcb = memp_malloc(MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    pcb->mss = TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = 0;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->snd_max = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keepalive = TCP_KEEPDEFAULT;
+    pcb->keep_cnt = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. We can then implement port reservation using
+ * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
+ */
+
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/*
+ * tcp_arg():
+ *
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ */ 
+
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ */ 
+
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  ((struct tcp_pcb_listen *)pcb)->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
+ *
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+    
+    if (pcb->unsent != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+    
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }  
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5u      |    %5u      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2u |   |%u%u%u%u%u%u|     %5u     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04x     |     %5u     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
+  switch (s) {
+  case CLOSED:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
+    break;
+ case LISTEN:
+   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
+   break;
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
+    break;
+  case SYN_RCVD:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
+    break;
+  case ESTABLISHED:
+    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
+    break;
+  case FIN_WAIT_1:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
+    break;
+  case FIN_WAIT_2:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
+    break;
+  case CLOSE_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
+    break;
+  case CLOSING:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
+    break;
+  case LAST_ACK:
+    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
+    break;
+  case TIME_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
+   break;
+  }
+}
+
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+}
+
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+int
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
new file mode 100644
index 000000000..c050a05ae
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
@@ -0,0 +1,1240 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of TCP.
+ *
+ * These functions are generally called in the order (ip_input() ->) tcp_input() ->
+ * tcp_process() -> tcp_receive() (-> application).
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#if LWIP_TCP
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+
+/* tcp_input:
+ *
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ */
+
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+#if SO_REUSE
+  struct tcp_pcb *pcb_temp;
+  int reuse = 0;
+  int reuse_port = 0;
+#endif /* SO_REUSE */
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%u bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04x\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  pbuf_header(p, -(hdrlen * 4));
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+#if SO_REUSE
+  pcb_temp = tcp_active_pcbs;
+  
+ again_1:
+  
+  /* Iterate through the TCP pcb list for a fully matching pcb */
+  for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+#if SO_REUSE
+      if(pcb->so_options & SOF_REUSEPORT) {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG,("tcp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+        } else {
+          /* First PCB with this address */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: first PCB and SOF_REUSEPORT set.\n"));
+          reuse = 1;
+        }
+        
+        reuse_port = 1; 
+        p->ref++;
+        
+        /* We want to search on next socket after receiving */
+        pcb_temp = pcb->next;
+        
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: reference counter on PBUF set to %i\n", p->ref));
+      } else  {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+        }
+      }
+#endif /* SO_REUSE */
+
+      /* Move this PCB to the front of the list so that subsequent
+   lookups will be faster (we exploit locality in TCP segment
+   arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+  prev->next = pcb->next;
+  pcb->next = tcp_active_pcbs;
+  tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+   pcb->local_port == tcphdr->dest &&
+   ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+  /* We don't really care enough to move this PCB to the front
+     of the list since we are not very likely to receive that
+     many segments for connections in TIME-WAIT. */
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+  tcp_timewait_input(pcb);
+  pbuf_free(p);
+  return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+    ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+   lpcb->local_port == tcphdr->dest) {
+  /* Move this PCB to the front of the list so that subsequent
+     lookups will be faster (we exploit locality in TCP segment
+     arrivals). */
+  if (prev != NULL) {
+    ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+          /* our successor is the remainder of the listening list */
+    lpcb->next = tcp_listen_pcbs.listen_pcbs;
+          /* put this listening pcb at the head of the listening list */
+    tcp_listen_pcbs.listen_pcbs = lpcb;
+  }
+
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+  tcp_listen_input(lpcb);
+  pbuf_free(p);
+  return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    tcp_input_pcb = NULL;
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+  /* TF_RESET means that the connection was reset by the other
+     end. We then call the error callback to inform the
+     application that the connection is dead before we
+     deallocate the PCB. */
+  TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+  /* The connection has been closed and we will deallocate the
+     PCB. */
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+  err = ERR_OK;
+  /* If the application has registered a "sent" function to be
+     called when new send buffer space is available, we call it
+     now. */
+  if (pcb->acked > 0) {
+    TCP_EVENT_SENT(pcb, pcb->acked, err);
+  }
+
+  if (recv_data != NULL) {
+    /* Notify application that data has been received. */
+    TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+  }
+
+  /* If a FIN segment was received, we call the callback
+     function with a NULL buffer to indicate EOF. */
+  if (recv_flags & TF_GOT_FIN) {
+    TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+  }
+  /* If there were no errors, we try to send something out. */
+  if (err == ERR_OK) {
+    tcp_output(pcb);
+  }
+      }
+    }
+
+
+    /* We deallocate the incoming pbuf. If it was buffered by the
+       application, the application should have called pbuf_ref() to
+       increase the reference counter in the pbuf. If so, the buffer
+       isn't actually deallocated by the call to pbuf_free(), only the
+       reference count is decreased. */
+    if (inseg.p != NULL) pbuf_free(inseg.p);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+#if SO_REUSE
+    /* First socket should receive now */
+    if(reuse_port) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: searching next PCB.\n"));
+      reuse_port = 0;
+      
+      /* We are searching connected sockets */
+      goto again_1;
+    }
+#endif /* SO_REUSE */
+
+  } else {
+#if SO_REUSE
+    if(reuse) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+      pbuf_free(p);
+      goto end;
+    }
+#endif /* SO_REUSE */
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+#if SO_REUSE
+ end:
+#endif /* SO_REUSE */
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/* tcp_listen_input():
+ *
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection.
+ */
+
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t optdata;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %u -> %u.\n", tcphdr->src, tcphdr->dest));
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+
+    /* Build an MSS option. */
+    optdata = htonl(((u32_t)2 << 24) |
+        ((u32_t)4 << 16) |
+        (((u32_t)npcb->mss / 256) << 8) |
+        (npcb->mss & 255));
+    /* Send a SYN|ACK together with the MSS option. */
+    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/* tcp_timewait_input():
+ *
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ */
+
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+    pcb->rcv_nxt = seqno + tcplen;
+  }
+  if (tcplen > 0) {
+    tcp_ack_now(pcb);
+  }
+  return tcp_output(pcb);
+}
+
+/* tcp_process
+ *
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ */
+
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
+      */
+      if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)){
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags = TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt = 0;
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %lu pcb->snd_nxt %lu unacked %lu\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf ++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+      pcb->cwnd = pcb->mss;
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %u\n", (unsigned int)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+      tcp_seg_free(rseg);
+
+      /* Parse any options in the SYNACK. */
+      tcp_parseopt(pcb);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack(pcb);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK &&
+       !(flags & TCP_RST)) {
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_nxt)) { */
+      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+        pcb->cwnd = pcb->mss;
+      }
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+        LWIP_DEBUGF(TCP_DEBUG,
+         ("TCP connection closed %d -> %d.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+  tcp_ack_now(pcb);
+  tcp_pcb_purge(pcb);
+  TCP_RMV(&tcp_active_pcbs, pcb);
+  pcb->state = TIME_WAIT;
+  TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+  tcp_ack_now(pcb);
+  pcb->state = CLOSING;
+      }
+    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      pcb->state = CLOSED;
+      recv_flags = TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+
+  return ERR_OK;
+}
+
+/* tcp_receive:
+ *
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ */
+
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  int m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %lu\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %lu snd_max %lu ackno %lu wl1 %lu seqno %lu wl2 %lu\n",
+                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+
+    if (pcb->lastack == ackno) {
+      pcb->acked = 0;
+
+      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+        ++pcb->dupacks;
+        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+          if (!(pcb->flags & TF_INFR)) {
+            /* This is fast retransmit. Retransmit the first unacked segment. */
+            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %u (%lu), fast retransmit %lu\n",
+                                       (unsigned int)pcb->dupacks, pcb->lastack,
+                                       ntohl(pcb->unacked->tcphdr->seqno)));
+            tcp_rexmit(pcb);
+            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+                                      pcb->lastack) / 2,
+                                      2 * pcb->mss);*/
+            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
+            if(pcb->cwnd > pcb->snd_wnd)
+              pcb->ssthresh = pcb->snd_wnd / 2;
+            else
+              pcb->ssthresh = pcb->cwnd / 2;
+
+            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+            pcb->flags |= TF_INFR;
+          } else {
+            /* Inflate the congestion window, but not if it means that
+               the value overflows. */
+            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+              pcb->cwnd += pcb->mss;
+            }
+          }
+        }
+      } else {
+        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %lu %lu\n",
+                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+      }
+    } else
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
+      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+      /* We come here when the ACK acknowledges new data. */
+      
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. */
+      pcb->acked = ackno - pcb->lastack;
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %u\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %u\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %lu, unacked->seqno %lu:%lu\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unacked)\n", (unsigned int)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+      pcb->polltmr = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+           ) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unsent)\n", (unsigned int)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+
+      if (pcb->unsent != NULL) {
+        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %u rtseq %lu ackno %lu\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      m = tcp_ticks - pcb->rttest;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %u ticks (%u msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %u (%u miliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+         
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+         
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+      
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      if (inseg.p->len < off) {
+        new_tot_len = inseg.p->tot_len - off;
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        pbuf_header(p, -off);
+      } else {
+        pbuf_header(inseg.p, -off);
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= pcb->rcv_nxt - seqno;
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else{
+      if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+        
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %lu\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL &&
+            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+          /* We have to trim the second edge of the incoming
+             segment. */
+          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
+          pbuf_realloc(inseg.p, inseg.len);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        tcplen = TCP_TCPLEN(&inseg);
+
+        pcb->rcv_nxt += tcplen;
+
+        /* Update the receiver's (our) window. */
+        if (pcb->rcv_wnd < tcplen) {
+          pcb->rcv_wnd = 0;
+        } else {
+          pcb->rcv_wnd -= tcplen;
+        }
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags = TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_wnd = 0;
+          } else {
+            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+          }
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags = TF_GOT_FIN;
+          }
+
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace the old segment with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next->next;
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+
+                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    inseg.len = next->tcphdr->seqno - seqno;
+                    pbuf_realloc(inseg.p, inseg.len);
+                  }
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    cseg->next = next;
+                    pcb->ooseq = cseg;
+                  }
+                  break;
+                }
+              } else 
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+                /* The sequence number of the incoming segment is in
+                   between the sequence numbers of the previous and
+                   the next segment on ->ooseq. We trim and insert the
+                   incoming segment and trim the previous segment, if
+                   needed. */
+                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                  /* We need to trim the incoming segment. */
+                  inseg.len = next->tcphdr->seqno - seqno;
+                  pbuf_realloc(inseg.p, inseg.len);
+                }
+
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next;
+                  prev->next = cseg;
+                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                    /* We need to trim the prev segment. */
+                    prev->len = seqno - prev->tcphdr->seqno;
+                    pbuf_realloc(prev->p, prev->len);
+                  }
+                }
+                break;
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = seqno - next->tcphdr->seqno;
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+        tcp_ack_now(pcb);
+      }
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+/*
+ * tcp_parseopt:
+ *
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ */
+
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t c;
+  u8_t *opts, opt;
+  u16_t mss;
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+      opt = opts[c];
+      if (opt == 0x00) {
+        /* End of options. */
+  break;
+      } else if (opt == 0x01) {
+        ++c;
+        /* NOP option. */
+      } else if (opt == 0x02 &&
+        opts[c + 1] == 0x04) {
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+        /* And we are done processing options. */
+        break;
+      } else {
+  if (opts[c + 1] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+#endif /* LWIP_TCP */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
new file mode 100644
index 000000000..a2ecb2faa
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
@@ -0,0 +1,724 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include 
+
+#if LWIP_TCP
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
+  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
+ * 
+ * @see tcp_write()
+ */
+
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%u, copy=%d)\n", (void *)pcb,
+    arg, len, (unsigned int)copy));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue either data or TCP options (but not both) for tranmission
+ * 
+ * 
+ * 
+ * @arg pcb Protocol control block for the TCP connection to enqueue data for.
+ * @arg arg Pointer to the data to be enqueued for sending.
+ * @arg len Data length in bytes
+ * @arg flags
+ * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
+ * referenced.
+ * @arg optdata
+ * @arg optlen
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+  u8_t flags, u8_t copy,
+  u8_t *optdata, u8_t optlen)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue=NULL;
+  u32_t left, seqno;
+  u16_t seglen;
+  void *ptr;
+  u8_t queuelen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%u, flags=%x, copy=%u)\n",
+    (void *)pcb, arg, len, (unsigned int)flags, (unsigned int)copy));
+  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
+      len == 0 || optlen == 0);
+  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
+      arg == NULL || optdata == NULL);
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%u > snd_buf=%u)\n", len, pcb->snd_buf));
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %u\n", (unsigned int)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  if (queuelen >= TCP_SND_QUEUELEN) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %u (max %u)\n", queuelen, TCP_SND_QUEUELEN));
+    goto memerr;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = NULL;
+  queue = NULL;
+  seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+
+    /* The segment length should be the MSS if the data to be enqueued
+     * is larger than the MSS. */
+    seglen = left > pcb->mss? pcb->mss: left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied. If
+     * optdata is != NULL, we have options instead of data. */
+     
+    /* options? */
+    if (optdata != NULL) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        goto memerr;
+      }
+      ++queuelen;
+      seg->dataptr = seg->p->payload;
+    }
+    /* copy from volatile memory? */
+    else if (copy) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %u\n", seglen));
+        goto memerr;
+      }
+      ++queuelen;
+      if (arg != NULL) {
+        memcpy(seg->p->payload, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+      /* reference the non-volatile payload data */
+      p->payload = ptr;
+      seg->dataptr = ptr;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(seg->p/*header*/, p/*data*/);
+      p = NULL;
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum. */
+    if (queuelen > TCP_SND_QUEUELEN) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %u (%u)\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    /* Copy the options into the header, if they are present. */
+    if (optdata == NULL) {
+      TCPH_HDRLEN_SET(seg->tcphdr, 5);
+    }
+    else {
+      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+      /* Copy options into data portion of segment.
+       Options can thus only be sent in non data carrying
+       segments such as SYN|ACK. */
+      memcpy(seg->dataptr, optdata, optlen);
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %lu:%lu (0x%x)\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((char *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    !(flags & (TCP_SYN | TCP_FIN)) &&
+    /* fit within max seg size */
+    useg->len + queue->len <= pcb->mss) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    pbuf_header(queue->p, -TCP_HLEN);
+    pbuf_cat(useg->p, queue->p);
+    useg->len += queue->len;
+    useg->next = queue->next;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %u\n", useg->len));
+    if (seg == queue) {
+      seg = NULL;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  pcb->snd_lbb += len;
+  pcb->snd_buf -= len;
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %d (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+  memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %d (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/* find out what we can send and send it */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg, *useg;
+  u32_t wnd;
+#if TCP_CWND_DEBUG
+  int i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }                                                                             
+   
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+    if (p == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+      return ERR_BUF;
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %lu\n", pcb->rcv_nxt));
+    /* remove ACK flags from the PCB, as we send an empty ACK now */
+    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+    tcphdr = p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = htonl(pcb->snd_nxt);
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_wnd);
+    tcphdr->urgp = 0;
+    TCPH_HDRLEN_SET(tcphdr, 5);
+
+    tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+          IP_PROTO_TCP, p->tot_len);
+#endif
+    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+        IP_PROTO_TCP);
+    pbuf_free(p);
+
+    return ERR_OK;
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, seg == NULL, ack %lu\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu, i%d\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
+      pcb->snd_max = pcb->snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather at the head. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to head of unacked list */
+          seg->next = pcb->unacked;
+          pcb->unacked = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Actually send a TCP segment over IP
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* silly window avoidance */
+  if (pcb->rcv_wnd < pcb->mss) {
+    seg->tcphdr->wnd = 0;
+  } else {
+    /* advertise our receive window size in this TCP segment */
+    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
+  }
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %lu\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %lu:%lu\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+}
+
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %lu ackno %lu.\n", seqno, ackno));
+}
+
+/* requeue all unacked segments for retransmission */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  seg = pcb->unacked->next;
+  pcb->unacked->next = pcb->unsent;
+  pcb->unsent = pcb->unacked;
+  pcb->unacked = seg;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  tcp_output(pcb);
+
+}
+
+
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+   struct pbuf *p;
+   struct tcp_hdr *tcphdr;
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %u.%u.%u.%u\n",
+                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %lu   pcb->tmr %lu  pcb->keep_cnt %u\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
+   
+   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+
+   if(p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
+      return;
+   }
+
+   tcphdr = p->payload;
+   tcphdr->src = htons(pcb->local_port);
+   tcphdr->dest = htons(pcb->remote_port);
+   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
+   tcphdr->ackno = htonl(pcb->rcv_nxt);
+   tcphdr->wnd = htons(pcb->rcv_wnd);
+   tcphdr->urgp = 0;
+   TCPH_HDRLEN_SET(tcphdr, 5);
+   
+   tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+   /* Send output to IP */
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %lu ackno %lu.\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
new file mode 100644
index 000000000..8343d34dc
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
@@ -0,0 +1,801 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP.
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/icmp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+/* The list of UDP PCBs */
+#if LWIP_UDP
+/* was static, but we may want to access this from a socket layer */
+struct udp_pcb *udp_pcbs = NULL;
+
+static struct udp_pcb *pcb_cache = NULL;
+
+
+void
+udp_init(void)
+{
+  udp_pcbs = pcb_cache = NULL;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and
+ *
+ * @param pbuf pbuf to be demultiplexed to a UDP PCB.
+ * @param netif network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+
+#if SO_REUSE
+  struct udp_pcb *pcb_temp;
+  int reuse = 0;
+  int reuse_port_1 = 0;
+  int reuse_port_2 = 0;
+#endif /* SO_REUSE */
+  
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %u\n", p->tot_len));
+
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG, ("udp (%u.%u.%u.%u, %u) <-- (%u.%u.%u.%u, %u)\n",
+    ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+    ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+    ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+    ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+#if SO_REUSE
+  pcb_temp = udp_pcbs;
+  
+ again_1:
+  
+  /* Iterate through the UDP pcb list for a fully matching pcb */
+  for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */ 
+  /* Iterate through the UDP pcb list for a fully matching pcb */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */ 
+    /* print the PCB local and remote address */
+    LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+      ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+      ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+      ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+      ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+       /* PCB remote port matches UDP source port? */
+    if ((pcb->remote_port == src) &&
+       /* PCB local port matches UDP destination port? */
+       (pcb->local_port == dest) &&
+       /* accepting from any remote (source) IP address? or... */
+       (ip_addr_isany(&pcb->remote_ip) ||
+       /* PCB remote IP address matches UDP source IP address? */
+        ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src))) &&
+       /* accepting on any local (netif) IP address? or... */
+       (ip_addr_isany(&pcb->local_ip) ||
+       /* PCB local IP address matches UDP destination IP address? */
+        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+      if (pcb->so_options & SOF_REUSEPORT) {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+        } else {
+          /* First PCB with this address */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+          reuse = 1;
+        }
+        
+        reuse_port_1 = 1; 
+        p->ref++;
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+      } else {
+        if (reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+        }
+      }
+#endif /* SO_REUSE */
+      break;
+    }
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+    /* Iterate through the UDP PCB list for a pcb that matches
+       the local address. */
+
+#if SO_REUSE
+    pcb_temp = udp_pcbs;
+    
+  again_2:
+
+    for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */ 
+    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */ 
+      LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+        ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+        ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+        ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+        ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+      /* unconnected? */
+      if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) &&
+         /* destination port matches? */
+        (pcb->local_port == dest) &&
+        /* not bound to a specific (local) interface address? or... */
+        (ip_addr_isany(&pcb->local_ip) ||
+        /* ...matching interface address? */
+        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+        if (pcb->so_options & SOF_REUSEPORT) {
+          if (reuse) {
+            /* We processed one PCB already */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+          } else {
+            /* First PCB with this address */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+            reuse = 1;
+          }
+          
+          reuse_port_2 = 1; 
+          p->ref++;
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+        } else {
+          if (reuse) {
+            /* We processed one PCB already */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+          }
+        }
+#endif /* SO_REUSE */
+        break;
+      }
+    }
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL  || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
+    {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
+    pbuf_header(p, UDP_HLEN);
+#ifdef IPv6
+    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
+#else
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+#endif /* IPv4 */
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+         (struct ip_addr *)&(iphdr->dest),
+         IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
+  LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+  UDP_STATS_INC(udp.chkerr);
+  UDP_STATS_INC(udp.drop);
+  snmp_inc_udpinerrors();
+  pbuf_free(p);
+  goto end;
+      }
+#endif
+    } else {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+       (struct ip_addr *)&(iphdr->dest),
+        IP_PROTO_UDP, p->tot_len) != 0) {
+    LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
+
+    UDP_STATS_INC(udp.chkerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+      }
+#endif
+    }
+    pbuf_header(p, -UDP_HLEN);
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+#if SO_REUSE
+      /* First socket should receive now */
+      if(reuse_port_1 || reuse_port_2) {
+        /* We want to search on next socket after receiving */
+        pcb_temp = pcb->next;
+        
+        if(reuse_port_1) {
+          /* We are searching connected sockets */
+          reuse_port_1 = 0;
+          reuse_port_2 = 0;
+          goto again_1;
+        } else {
+          /* We are searching unconnected sockets */
+          reuse_port_1 = 0;
+          reuse_port_2 = 0;
+          goto again_2;
+        }
+      }
+#endif /* SO_REUSE */ 
+    } else {
+#if SO_REUSE
+      if(reuse) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+        pbuf_free(p);
+        goto end;
+      }
+#endif /* SO_REUSE */
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
+
+      /* No match was found, send ICMP destination port unreachable unless
+      destination address was broadcast/multicast. */
+
+      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+
+  /* adjust pbuf pointer */
+  p->payload = iphdr;
+  icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+    snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+  end:
+
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  err_t err;
+  /* temporary space for current PCB remote address */
+  struct ip_addr pcb_remote_ip;
+  u16_t pcb_remote_port;
+  /* remember current remote peer address of PCB */
+  pcb_remote_ip.addr = pcb->remote_ip.addr;
+  pcb_remote_port = pcb->remote_port;
+  /* copy packet destination address to PCB remote peer address */
+  pcb->remote_ip.addr = dst_ip->addr;
+  pcb->remote_port = dst_port;
+  /* send to the packet destination address */
+  err = udp_send(pcb, p);
+  /* restore PCB remote peer address */
+  pcb->remote_ip.addr = pcb_remote_ip.addr;
+  pcb->remote_port = pcb_remote_port;
+  return err;
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  struct udp_hdr *udphdr;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a seperate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  /* adding a header within p succeeded */
+  } else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  /* { q now represents the packet to be sent } */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(pcb->remote_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* find the outgoing network interface for this packet */
+  netif = ip_route(&(pcb->remote_ip));
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%lx\n", pcb->remote_ip.addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %u\n", q->tot_len));
+
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %u\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    udphdr->len = htons(pcb->chksum_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
+          IP_PROTO_UDP, pcb->chksum_len);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+    err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
+  /* UDP */
+  } else {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %u\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04x\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a seperate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q); q = NULL;
+    /* { p is still referenced by the caller, and will live on } */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+#if SO_REUSE
+  int reuse_port_all_set = 1;
+#endif /* SO_REUSE */
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %u)\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+#if SO_REUSE == 0
+/* this code does not allow upper layer to share a UDP port for
+   listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+   SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+   combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else if ((ipcb->local_port == port) &&
+       /* IP address matches, or one is IP_ADDR_ANY? */
+       (ip_addr_isany(&(ipcb->local_ip)) ||
+       ip_addr_isany(ipaddr) ||
+       ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+      /* other PCB already binds to this local IP and port */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %u already bound by another pcb\n", port));
+      return ERR_USE;
+    }
+#endif
+
+#else /* SO_REUSE */
+      /* Search through list of PCB's. 
+         
+      If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
+      or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
+      the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
+      But no two PCB's bound to same local port and same local address is valid.
+      
+      If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+      all PCB's must have the SOF_REUSEPORT option set.
+      
+      When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+      address is already in use. */
+    else if (ipcb->local_port == port) {
+      if(ip_addr_cmp(&(ipcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (ipcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(ipcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(ipcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }           
+      }
+    }
+#endif /* SO_REUSE */
+
+  }
+
+#if SO_REUSE
+  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
+     {IP, port} can't be reused. */
+  if(!reuse_port_all_set) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: not all sockets have SO_REUSEPORT set.\n"));
+    return ERR_USE;
+  }
+#endif /* SO_REUSE */
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        port++;
+        ipcb = udp_pcbs;
+      } else
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %u.%u.%u.%u, port %u\n",
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+        UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %u.%u.%u.%u, port %u\n",
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+void
+udp_recv(struct udp_pcb *pcb,
+   void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+           struct ip_addr *addr, u16_t port),
+   void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+  /* pcb not 1st in list */
+  } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in udp_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void) {
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  
+  
+  return pcb;
+}
+
+#if UDP_DEBUG
+int
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     %5u     | (src port, dest port)\n",
+         ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     0x%04x    | (len, chksum)\n",
+         ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  return 0;
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
+
+
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 000000000..634405b71
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_dur_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_te_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
new file mode 100644
index 000000000..beab85183
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
new file mode 100644
index 000000000..4c15e1a0e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+
+void ip_init(void);
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		   u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define	SOF_DEBUG	    (u16_t)0x0001U		/* turn on debugging info recording */
+#define	SOF_ACCEPTCONN	(u16_t)0x0002U		/* socket has had listen() */
+#define	SOF_REUSEADDR	(u16_t)0x0004U		/* allow local address reuse */
+#define	SOF_KEEPALIVE	(u16_t)0x0008U		/* keep connections alive */
+#define	SOF_DONTROUTE	(u16_t)0x0010U		/* just use interface addresses */
+#define	SOF_BROADCAST	(u16_t)0x0020U		/* permit sending of broadcast msgs */
+#define	SOF_USELOOPBACK	(u16_t)0x0040U		/* bypass hardware when possible */
+#define	SOF_LINGER	    (u16_t)0x0080U		/* linger on close if data present */
+#define	SOF_OOBINLINE	(u16_t)0x0100U		/* leave received OOB data in line */
+#define	SOF_REUSEPORT	(u16_t)0x0200U		/* allow local address & port reuse */
+
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 000000000..0ef99937b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE    ((u32_t) 0xffffffff)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK    ((u32_t) 0x7f000001)  /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define  IN_CLASSA(a)    ((((u32_t)(a)) & 0x80000000) == 0)
+#define  IN_CLASSA_NET    0xff000000
+#define  IN_CLASSA_NSHIFT  24
+#define  IN_CLASSA_HOST    (0xffffffff & ~IN_CLASSA_NET)
+#define  IN_CLASSA_MAX    128
+
+#define  IN_CLASSB(a)    ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
+#define  IN_CLASSB_NET    0xffff0000
+#define  IN_CLASSB_NSHIFT  16
+#define  IN_CLASSB_HOST    (0xffffffff & ~IN_CLASSB_NET)
+#define  IN_CLASSB_MAX    65536
+
+#define  IN_CLASSC(a)    ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
+#define  IN_CLASSC_NET    0xffffff00
+#define  IN_CLASSC_NSHIFT  8
+#define  IN_CLASSC_HOST    (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
+#define IN_CLASSD_NET       0xf0000000  /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28      /* net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff  /* routing needn't know.    */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+
+#define IN_LOOPBACKNET      127         /* official! */
+
+
+#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
+                                                         ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
+
+
+#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%u.%u.%u.%u", \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
+        ipaddr?(unsigned int)ntohl((ipaddr)->addr) & 0xff:0U))
+
+/* cast to unsigned int, as it is used as argument to printf functions
+ * which expect integer arguments */
+#define ip4_addr1(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr)) & 0xff)
+#endif /* __LWIP_IP_ADDR_H__ */
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 000000000..654b4d7f8
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+
+struct pbuf * ip_reass(struct pbuf *);
+err_t ip_frag(struct pbuf *, struct netif *, struct ip_addr *);
+
+#endif /* __LWIP_IP_FRAG_H__ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 000000000..2b6adb122
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/netif.h"
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
new file mode 100644
index 000000000..3cdd7407a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
new file mode 100644
index 000000000..432ca36e0
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP 58
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         unsigned char ttl, unsigned char proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      unsigned char ttl, unsigned char proto,
+      struct netif *netif);
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 000000000..08e962ddd
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#define IP_ADDR_ANY 0
+
+struct ip_addr {
+  u32_t addr[4];
+};
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+int ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+int ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+int ip_addr_isany(struct ip_addr *addr);
+
+
+#if IP_DEBUG
+void ip_addr_debug_print(struct ip_addr *addr);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
new file mode 100644
index 000000000..7f0ad5966
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/err.h"
+
+#define NETCONN_NOCOPY 0x00
+#define NETCONN_COPY   0x01
+
+enum netconn_type {
+  NETCONN_TCP,
+  NETCONN_UDP,
+  NETCONN_UDPLITE,
+  NETCONN_UDPNOCHKSUM,
+  NETCONN_RAW
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_ACCEPT,
+  NETCONN_RECV,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *fromaddr;
+  u16_t fromport;
+  err_t err;
+};
+
+struct netconn {
+  enum netconn_type type;
+  enum netconn_state state;
+  union {
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  err_t err;
+  sys_mbox_t mbox;
+  sys_mbox_t recvmbox;
+  sys_mbox_t acceptmbox;
+  sys_sem_t sem;
+  int socket;
+  u16_t recv_avail;
+  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+void              netbuf_ref      (struct netbuf *buf,
+           void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+void              netbuf_copy     (struct netbuf *buf,
+           void *dataptr, u16_t len);
+void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
+              u16_t len, u16_t offset);
+struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
+u16_t             netbuf_fromport (struct netbuf *buf);
+
+/* Network connection functions: */
+struct netconn *  netconn_new     (enum netconn_type type);
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+err_t             netconn_delete  (struct netconn *conn);
+enum netconn_type netconn_type    (struct netconn *conn);
+err_t             netconn_peer    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t *port);
+err_t             netconn_addr    (struct netconn *conn,
+           struct ip_addr **addr,
+           u16_t *port);
+err_t             netconn_bind    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen  (struct netconn *conn);
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_send    (struct netconn *conn,
+           struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+           void *dataptr, u16_t size,
+           u8_t copy);
+err_t             netconn_close   (struct netconn *conn);
+
+err_t             netconn_err     (struct netconn *conn);
+
+#endif /* __LWIP_API_H__ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
new file mode 100644
index 000000000..1957abc5e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/api.h"
+
+enum api_msg_type {
+  API_MSG_NEWCONN,
+  API_MSG_DELCONN,
+  
+  API_MSG_BIND,
+  API_MSG_CONNECT,
+  API_MSG_DISCONNECT,
+
+  API_MSG_LISTEN,
+  API_MSG_ACCEPT,
+
+  API_MSG_SEND,
+  API_MSG_RECV,
+  API_MSG_WRITE,
+
+  API_MSG_CLOSE,
+  
+  API_MSG_MAX
+};
+
+struct api_msg_msg {
+  struct netconn *conn;
+  enum netconn_type conntype;
+  union {
+    struct pbuf *p;   
+    struct  {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    struct {
+      void *dataptr;
+      u16_t len;
+      unsigned char copy;
+    } w;    
+    sys_mbox_t mbox;
+    u16_t len;
+  } msg;
+};
+
+struct api_msg {
+  enum api_msg_type type;
+  struct api_msg_msg msg;
+};
+
+void api_msg_input(struct api_msg *msg);
+void api_msg_post(struct api_msg *msg);
+
+#endif /* __LWIP_API_MSG_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
new file mode 100644
index 000000000..e0d622a4b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define	ENSROK		0	/* DNS server returned answer with no data */
+#define	ENSRNODATA	160	/* DNS server returned answer with no data */
+#define	ENSRFORMERR	161	/* DNS server claims query was misformatted */
+#define	ENSRSERVFAIL 162	/* DNS server returned general failure */
+#define	ENSRNOTFOUND 163	/* Domain name not found */
+#define	ENSRNOTIMP	164	/* DNS server does not implement requested operation */
+#define	ENSRREFUSED	165	/* DNS server refused query */
+#define	ENSRBADQUERY 166	/* Misformatted DNS query */
+#define	ENSRBADNAME	167	/* Misformatted domain name */
+#define	ENSRBADFAMILY 168	/* Unsupported address family */
+#define	ENSRBADRESP	169	/* Misformatted DNS reply */
+#define	ENSRCONNREFUSED	170	/* Could not contact DNS servers */
+#define	ENSRTIMEOUT	171	/* Timeout while contacting DNS servers */
+#define	ENSROF		172	/* End of file */
+#define	ENSRFILE	173	/* Error reading file */
+#define	ENSRNOMEM	174	/* Out of memory */
+#define	ENSRDESTRUCTION	175	/* Application terminated lookup */
+#define	ENSRQUERYDOMAINTOOLONG	176	/* Domain name is too long */
+#define	ENSRCNAMELOOP	177	/* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
new file mode 100644
index 000000000..4d3425c07
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "arch/cc.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+
+#define DBG_LEVEL_OFF     0
+#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
+#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
+#define DBG_LEVEL_SEVERE  3  /* */ 
+#define DBG_MASK_LEVEL    3
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define DBG_ON  0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define DBG_OFF 0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define DBG_TRACE   0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define DBG_STATE   0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define DBG_FRESH   0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define DBG_HALT    0x08U
+
+#ifndef LWIP_NOASSERT
+#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else
+#  define LWIP_ASSERT(x,y) 
+#endif
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least DBG_LEVEL
+ */
+#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((int)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
+#else /* LWIP_DEBUG */
+#  define LWIP_DEBUGF(debug,x) 
+#  define LWIP_ERROR(x)  
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
new file mode 100644
index 000000000..eba9b8774
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "arch/cc.h"
+
+#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
+#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
new file mode 100644
index 000000000..bfe753f26
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
@@ -0,0 +1,223 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+struct dhcp
+{
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** (first) pbuf of incoming msg */
+  struct pbuf *p;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  struct dhcp_msg *options_in; 
+  /** ingoing msg options length */
+  u16_t options_in_len;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)  
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68  
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+ 
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
new file mode 100644
index 000000000..c92cb26d7
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#include "arch/cc.h"
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK    0      /* No error, everything OK. */
+#define ERR_MEM  -1      /* Out of memory error.     */
+#define ERR_BUF  -2      /* Buffer error.            */
+
+
+#define ERR_ABRT -3      /* Connection aborted.      */
+#define ERR_RST  -4      /* Connection reset.        */
+#define ERR_CLSD -5      /* Connection closed.       */
+#define ERR_CONN -6      /* Not connected.           */
+
+#define ERR_VAL  -7      /* Illegal value.           */
+
+#define ERR_ARG  -8      /* Illegal argument.        */
+
+#define ERR_RTE  -9      /* Routing problem.         */
+
+#define ERR_USE  -10     /* Address in use.          */
+
+#define ERR_IF   -11     /* Low-level netif error    */
+#define ERR_ISCONN -12   /* Already connected.       */
+
+
+#ifdef LWIP_DEBUG
+extern char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_ERR_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
new file mode 100644
index 000000000..ee6fea7d8
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+
+void mem_init(void);
+
+void *mem_malloc(mem_size_t size);
+void mem_free(void *mem);
+void *mem_realloc(void *mem, mem_size_t size);
+void *mem_reallocm(void *mem, mem_size_t size);
+
+#ifndef MEM_ALIGN_SIZE
+#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef MEM_ALIGN
+#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#endif /* __LWIP_MEM_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
new file mode 100644
index 000000000..1cd46fa3f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+typedef enum {
+  MEMP_PBUF,
+  MEMP_RAW_PCB,
+  MEMP_UDP_PCB,
+  MEMP_TCP_PCB,
+  MEMP_TCP_PCB_LISTEN,
+  MEMP_TCP_SEG,
+
+  MEMP_NETBUF,
+  MEMP_NETCONN,
+  MEMP_API_MSG,
+  MEMP_TCPIP_MSG,
+
+  MEMP_SYS_TIMEOUT,
+  
+  MEMP_MAX
+} memp_t;
+
+void memp_init(void);
+
+void *memp_malloc(memp_t type);
+void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
+void memp_free(memp_t type, void *mem);
+
+#endif /* __LWIP_MEMP_H__  */
+    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
new file mode 100644
index 000000000..d0bda2df9
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP 0x1U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST 0x2U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x4U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP 0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP 0x10U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif
+  /** number of bytes used in hwaddr */
+  unsigned char hwaddr_len;
+  /** link level hardware address of this interface */
+  unsigned char hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** link type */
+  u8_t link_type;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+};
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+/* netif_init() must be called first. */
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
new file mode 100644
index 000000000..8e3910d52
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK		0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG              8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ * 
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS                      1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ *  fragments, note that these are orthogonal, one dealing with incoming
+ *  packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL                        255
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL                        255
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             1
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL                         255
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL                         255
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif 
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS                         128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF		1
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif 
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
+#ifndef SO_REUSE
+# define SO_REUSE 0
+#endif                                                                        
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS	1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS	1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS	1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS	1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS	1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS	1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS	1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS	1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS	1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS	1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS	0
+#endif
+
+#else
+
+#define LINK_STATS	0
+#define IP_STATS	0
+#define IPFRAG_STATS	0
+#define ICMP_STATS	0
+#define UDP_STATS	0
+#define TCP_STATS	0
+#define MEM_STATS	0
+#define MEMP_STATS	0
+#define PBUF_STATS	0
+#define SYS_STATS	0
+#define RAW_STATS	0
+#define LWIP_STATS_DISPLAY	0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0      /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT 
+
+#define NUM_PPP                         1      /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0      /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0      /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL                0
+#else
+#define LCP_ECHOINTERVAL                10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS                3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG                 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#define PPP_DEFMRU                      296             /* Try for this */
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON                    0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG                      DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG                        DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG 
+#define PPP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG 
+#define SLIP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG 
+#define DHCP_DEBUG                      DBG_OFF
+#endif
+
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
new file mode 100644
index 000000000..546aa3035
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "arch/cc.h"
+
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM,
+  PBUF_ROM,
+  PBUF_REF,
+  PBUF_POOL
+} pbuf_flag;
+
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
+#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
+#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
+#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
+#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
+
+/** indicates this packet was broadcast on the link */
+#define PBUF_FLAG_LINK_BROADCAST 0x80U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+  
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+  
+  /** length of this buffer */
+  u16_t len;  
+
+  /** flags telling the type of pbuf, see PBUF_FLAG_ */
+  u16_t flags;
+  
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+};
+
+void pbuf_init(void);
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *h, struct pbuf *t);
+void pbuf_chain(struct pbuf *h, struct pbuf *t);
+struct pbuf *pbuf_take(struct pbuf *f);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+void pbuf_queue(struct pbuf *p, struct pbuf *n);
+struct pbuf * pbuf_dequeue(struct pbuf *p);
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
new file mode 100644
index 000000000..6f7a98717
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u16_t protocol;
+
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u16_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t              raw_input      (struct pbuf *p, struct netif *inp);
+void             raw_init       (void);
+
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
new file mode 100644
index 000000000..8a37aa35a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "arch/cc.h"
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
new file mode 100644
index 000000000..7d160aaa4
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+
+/* SNMP support available? */
+#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
+
+/* network interface */
+void snmp_add_ifinoctets(unsigned long value); 
+void snmp_inc_ifinucastpkts(void);
+void snmp_inc_ifinnucastpkts(void);
+void snmp_inc_ifindiscards(void);
+void snmp_add_ifoutoctets(unsigned long value);
+void snmp_inc_ifoutucastpkts(void);
+void snmp_inc_ifoutnucastpkts(void);
+void snmp_inc_ifoutdiscards(void);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipunknownprotos(void);
+void snmp_inc_ipnoroutes(void);
+void snmp_inc_ipforwdatagrams(void);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpcurrestab(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* network interface */
+#define snmp_add_ifinoctets(value) 
+#define snmp_inc_ifinucastpkts()
+#define snmp_inc_ifinnucastpkts()
+#define snmp_inc_ifindiscards()
+#define snmp_add_ifoutoctets(value)
+#define snmp_inc_ifoutucastpkts()
+#define snmp_inc_ifoutnucastpkts()
+#define snmp_inc_ifoutdiscards()
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipunknownprotos()
+#define snmp_inc_ipnoroutes()
+#define snmp_inc_ipforwdatagrams()
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpcurrestab()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
new file mode 100644
index 000000000..d5f8ccf74
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+#include "lwip/ip_addr.h"
+
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t int
+#endif
+
+
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket.
+ */
+#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
+#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
+#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
+#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
+#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
+#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
+#define  SO_LINGER  0x0080    /* linger on close if data present */
+#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
+#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
+
+#define SO_DONTLINGER   (int)(~SO_LINGER)
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF  0x1001    /* send buffer size */
+#define SO_RCVBUF  0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define  SO_ERROR  0x1007    /* get error status and clear */
+#define  SO_TYPE    0x1008    /* get socket type */
+
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+
+#define INADDR_ANY      0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS       1
+#define IP_TTL       2
+
+
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (hopefully unused)
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ *
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000      /* no parameters */
+#define IOC_OUT         0x40000000      /* copy out parameters */
+#define IOC_IN          0x80000000      /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  #define FD_SETSIZE    16
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+/* 
+ * only define this in sockets.c so it does not interfere
+ * with other projects namespaces where timeval is present
+ */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+  struct timeval {
+    long    tv_sec;         /* seconds */
+    long    tv_usec;        /* and microseconds */
+  };
+#endif
+
+#endif
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
+    struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define close(s)              lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define read(a,b,c)           lwip_read(a,b,c)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* __LWIP_SOCKETS_H__ */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
new file mode 100644
index 000000000..71acfd068
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#if LWIP_STATS
+
+struct stats_proto {
+  u16_t xmit;    /* Transmitted packets. */
+  u16_t rexmit;  /* Retransmitted packets. */
+  u16_t recv;    /* Received packets. */
+  u16_t fw;      /* Forwarded packets. */
+  u16_t drop;    /* Dropped packets. */
+  u16_t chkerr;  /* Checksum error. */
+  u16_t lenerr;  /* Invalid length error. */
+  u16_t memerr;  /* Out of memory error. */
+  u16_t rterr;   /* Routing error. */
+  u16_t proterr; /* Protocol error. */
+  u16_t opterr;  /* Error in options. */
+  u16_t err;     /* Misc error. */
+  u16_t cachehit;
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;  
+  mem_size_t err;
+};
+
+struct stats_pbuf {
+  u16_t avail;
+  u16_t used;
+  u16_t max;  
+  u16_t err;
+
+  u16_t alloc_locked;
+  u16_t refresh_locked;
+};
+
+struct stats_syselem {
+  u16_t used;
+  u16_t max;
+  u16_t err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+  struct stats_proto link;
+  struct stats_proto ip_frag;
+  struct stats_proto ip;
+  struct stats_proto icmp;
+  struct stats_proto udp;
+  struct stats_proto tcp;
+  struct stats_pbuf pbuf;
+  struct stats_mem mem;
+  struct stats_mem memp[MEMP_MAX];
+  struct stats_sys sys;
+};
+
+extern struct stats_ lwip_stats;
+
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif
+
+#endif /* __LWIP_STATS_H__ */
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
new file mode 100644
index 000000000..68926e954
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "arch/cc.h"
+
+#include "lwip/opt.h"
+
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeout {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_free(s)
+#define sys_mbox_new() 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(t,a,p)
+
+#else /* NO_SYS */
+
+#include "arch/sys_arch.h"
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffff
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeout {
+  struct sys_timeout *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeout *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(void);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
+
+/* The following functions are used only in Unix code, and
+   can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
new file mode 100644
index 000000000..301a3f023
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+
+#include "lwip/err.h"
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Must be called first to
+           initialize TCP. */
+void             tcp_tmr     (void);  /* Must be called every
+           TCP_TMR_INTERVAL
+           ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+          struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+               u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+            u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+            void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port, err_t (* connected)(void *arg,
+                    struct tcp_pcb *tpcb,
+                    err_t err));
+struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
+void             tcp_abort   (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+            u8_t copy);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
+                                       milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
+                                       milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
+                                       milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6 /* x RTO */
+
+#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
+
+/*
+ * User-settable options (used with setsockopt).
+ */
+#define	TCP_NODELAY	   0x01	   /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
+
+/* Keepalive values */
+#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
+#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
+#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
+#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  struct tcp_pcb *next; /* for the linked list */
+  enum tcp_state state; /* TCP state */
+  u8_t prio;
+  void *callback_arg;
+
+  u16_t local_port;
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
+#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window */
+  
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  u16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  u16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt,       /* next seqno to be sent */
+    snd_max,       /* Highest seqno sent. */
+    snd_wnd,       /* sender window */
+    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+       window update. */
+    snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+  
+  
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+  
+  /* Function to be called when (in-sequence) data has arrived. */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up. */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+  /* Function which is called periodically. */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs. */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keepalive;
+  
+  /* KEEPALIVE counter */
+  u8_t keep_cnt;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+  struct tcp_pcb_listen *next;   /* for the linked list */
+  
+  /* Even if state is obviously LISTEN this is here for
+   * field compatibility with tpc_pcb to which it is cast sometimes
+   * Until a cleaner solution emerges this is here.FIXME
+   */ 
+  enum tcp_state state;   /* TCP state */
+
+  u8_t prio;
+  void *callback_arg;
+  
+  u16_t local_port; 
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
+                        if((pcb)->accept != NULL) \
+                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+                        if((pcb)->sent != NULL) \
+                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+                        if((pcb)->recv != NULL) \
+                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+                          if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+                        if((pcb)->connected != NULL) \
+                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+                        if((pcb)->poll != NULL) \
+                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+                        if((errf) != NULL) \
+                        (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
+                            (pcb)->flags &= ~TF_ACK_DELAY; \
+                            (pcb)->flags |= TF_ACK_NOW; \
+                            tcp_output(pcb); \
+                         } else { \
+                            (pcb)->flags |= TF_ACK_DELAY; \
+                         }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+                         tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+    u8_t flags, u8_t copy,
+                u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+int tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+	struct tcp_pcb_listen *listen_pcbs; 
+	struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+                            npcb->next = *pcbs; \
+                            *(pcbs) = npcb; \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            if(*(pcbs) == npcb) { \
+                               (*(pcbs)) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            } while(0)
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_TCP_H__ */
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
new file mode 100644
index 000000000..316ae4fc5
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/api_msg.h"
+#include "lwip/pbuf.h"
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+void tcpip_apimsg(struct api_msg *apimsg);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
+
+void tcpip_tcp_timer_needed(void);
+
+enum tcpip_msg_type {
+  TCPIP_MSG_API,
+  TCPIP_MSG_INPUT,
+  TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+    struct api_msg *apimsg;
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+  } msg;
+};
+
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
new file mode 100644
index 000000000..c54859476
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+#define UDP_HLEN 8
+
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  u16_t local_port, remote_port;
+  
+  u16_t chksum_len;
+  
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  void *recv_arg;  
+};
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+void             udp_init       (void);
+
+#if UDP_DEBUG
+int udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+#endif /* __LWIP_UDP_H__ */
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
new file mode 100644
index 000000000..08437afe5
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[6]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr eth);
+  PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP 0x0806
+#define ETHTYPE_IP  0x0800
+
+void etharp_init(void);
+void etharp_tmr(void);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+         struct pbuf *q);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
new file mode 100644
index 000000000..97b3c6764
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+
+err_t loopif_init(struct netif *netif);
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
new file mode 100644
index 000000000..bf70046a9
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+err_t slipif_init(struct netif * netif);
+ 
+#endif 
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
new file mode 100644
index 000000000..825d40715
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
@@ -0,0 +1,27 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          An example network interface that shows how a "loopback"
+          interface would work. This is not really intended for actual
+          use, but as a very basic example of how initialization and
+          output functions work.
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+	  
+ppp/      Point-to-Point Protocol stack
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
new file mode 100644
index 000000000..11f4973bd
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
@@ -0,0 +1,828 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+
+/* ARP needs to inform DHCP of any ARP replies? */
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+#  include "lwip/dhcp.h"
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ * (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ * (2 * 5) seconds = 10 seconds.
+ * 
+ * @internal Keep this number at least 2, otherwise it might
+ * run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+/** ARP message types */
+#define ARP_REQUEST 1
+#define ARP_REPLY 2
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE,
+  /** @internal transitional state used in etharp_tmr() for convenience*/
+  ETHARP_STATE_EXPIRED
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** 
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+   struct pbuf *p;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+/**
+ * Initializes ARP module.
+ */
+void
+etharp_init(void)
+{
+  u8_t i;
+  /* clear ARP entries */
+  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].state = ETHARP_STATE_EMPTY;
+#if ARP_QUEUEING
+    arp_table[i].p = NULL;
+#endif
+    arp_table[i].ctime = 0;
+  }
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    /* stable entry? */
+    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         /* entry has become old? */
+        (arp_table[i].ctime >= ARP_MAXAGE)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %u.\n", i));
+      arp_table[i].state = ETHARP_STATE_EXPIRED;
+    /* pending entry? */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* entry unresolved/pending for too long? */
+      if (arp_table[i].ctime >= ARP_MAXPENDING) {
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %u.\n", i));
+        arp_table[i].state = ETHARP_STATE_EXPIRED;
+#if ARP_QUEUEING
+      } else if (arp_table[i].p != NULL) {
+        /* resend an ARP query here */
+#endif
+      }
+    }
+    /* clean up entries that have just been expired */
+    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].p != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));
+        pbuf_free(arp_table[i].p);
+        arp_table[i].p = NULL;
+      }
+#endif
+      /* recycle entry for re-use */      
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %d\n", i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %d\n", i));
+        /* found exact IP address match, simply bail out */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].p != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }        
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %d\n", i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* no empty entry found and not allowed to recycle? */
+  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+  {
+  	return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry without queued packets
+   * 
+   * { ETHARP_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %d\n", i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %d\n", i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d (without queue)\n", i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", i, (void *)(arp_table[i].p)));
+    pbuf_free(arp_table[i].p);
+    arp_table[i].p = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+  return (err_t)i;
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i, k;
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %u.%u.%u.%u - %02x:%02x:%02x:%02x:%02x:%02x\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, flags);
+  /* bail out if no entry could be found */
+  if (i < 0) return (err_t)i;
+  
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %u\n", i));
+  /* update address */
+  for (k = 0; k < netif->hwaddr_len; ++k) {
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+/* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].p != NULL) {
+    /* get the first packet on the queue */
+    struct pbuf *p = arp_table[i].p;
+    /* Ethernet header */
+    struct eth_hdr *ethhdr = p->payload;
+    /* remember (and reference) remainder of queue */
+    /* note: this will also terminate the p pbuf chain */
+    arp_table[i].p = pbuf_dequeue(p);
+    /* fill-in Ethernet header */
+    for (k = 0; k < netif->hwaddr_len; ++k) {
+      ethhdr->dest.addr[k] = ethaddr->addr[k];
+      ethhdr->src.addr[k] = netif->hwaddr[k];
+    }
+    ethhdr->type = htons(ETHTYPE_IP);
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
+    /* send the queued IP packet */
+    netif->linkoutput(netif, p);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param pbuf The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct ethip_hdr *hdr;
+
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  hdr = p->payload;
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
+ * @param ethaddr Ethernet address of netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+
+  /* drop short ARP packets */
+  if (p->tot_len < sizeof(struct etharp_hdr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%d/%d)\n", p->tot_len, sizeof(struct etharp_hdr)));
+    pbuf_free(p);
+    return;
+  }
+
+  hdr = p->payload;
+ 
+  /* get aligned copies of addresses */
+  *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;
+  *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* re-use pbuf to send ARP reply */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+      for(i = 0; i < netif->hwaddr_len; ++i) {
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
+        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
+      }
+
+      hdr->hwtype = htons(HWTYPE_ETHERNET);
+      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+      hdr->proto = htons(ETHTYPE_IP);
+      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+
+      hdr->ethhdr.type = htons(ETHTYPE_ARP);
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* When unconfigured, DHCP wants to know about ARP replies from the
+     * address offered to us, as that means someone else uses it already! */
+    if (netif->ip_addr.addr == 0) dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %d\n", htons(hdr->opcode)));
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param ipaddr The IP address of the packet destination.
+ * @param pbuf The pbuf(s) containing the IP packet to be sent.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or netif->linkoutput().
+ */
+err_t
+etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr *dest, *srcaddr, mcastaddr;
+  struct eth_hdr *ethhdr;
+  u8_t i;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  srcaddr = (struct eth_addr *)netif->hwaddr;
+  ethhdr = q->payload;
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    ethhdr->dest.addr[i] = dest->addr[i];
+    ethhdr->src.addr[i] = srcaddr->addr[i];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  /* send packet directly on the link */
+  return netif->linkoutput(netif, q);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+  u8_t k; /* Ethernet address octet index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+
+  /* could not find or create entry? */
+  if (i < 0)
+  {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+	#ifdef LWIP_DEBUG
+    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
+	#endif
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+  }
+  
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping,
+       * fill in the Ethernet header for the outgoing packet */
+      struct eth_hdr *ethhdr = q->payload;
+      for(k = 0; k < netif->hwaddr_len; k++) {
+        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
+        ethhdr->src.addr[k]  = srcaddr->addr[k];
+      }
+      ethhdr->type = htons(ETHTYPE_IP);
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
+      /* send the packet */
+      result = netif->linkoutput(netif, q);
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
+      /* (the caller of lwIP assumes the referenced payload can be
+       * freed after it returns from the lwIP call that brought us here) */
+      p = pbuf_take(q);
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        if (arp_table[i].p == NULL) {
+        	/* ... in the empty queue */
+        	pbuf_ref(p);
+        	arp_table[i].p = p;
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */
+        } else {
+        	/* ... at tail of non-empty queue */
+          pbuf_queue(arp_table[i].p, p);
+#endif
+        }
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %d\n", (void *)q, i));
+        result = ERR_OK;
+      } else {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p != NULL) {
+    struct etharp_hdr *hdr = p->payload;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+    hdr->opcode = htons(ARP_REQUEST);
+    for (k = 0; k < netif->hwaddr_len; k++)
+    {
+      hdr->shwaddr.addr[k] = srcaddr->addr[k];
+      /* the hardware address is what we ask for, in
+       * a request it is a don't-care value, we use zeroes */
+      hdr->dhwaddr.addr[k] = 0x00;
+    }
+    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
+    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+    hdr->hwtype = htons(HWTYPE_ETHERNET);
+    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+    hdr->proto = htons(ETHTYPE_IP);
+    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+    for (k = 0; k < netif->hwaddr_len; ++k)
+    {
+      /* broadcast to all network interfaces on the local network */
+      hdr->ethhdr.dest.addr[k] = 0xff;
+      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
+    }
+    hdr->ethhdr.type = htons(ETHTYPE_ARP);
+    /* send ARP query */
+    result = netif->linkoutput(netif, p);
+    /* free ARP query packet */
+    pbuf_free(p);
+    p = NULL;
+  /* could not allocate pbuf for ARP request */
+  } else {
+    result = ERR_MEM;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
+  }
+  return result;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
new file mode 100644
index 000000000..7d4719ec9
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* lwIP includes. */
+#include 
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include "netif/etharp.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "SAM7_EMAC.h"
+#include "Emac.h"
+
+#define netifMTU							( 1500 )
+#define netifINTERFACE_TASK_STACK_SIZE		( 350 )
+#define netifINTERFACE_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define netifGUARD_BLOCK_TIME				( 250 )
+#define IFNAME0 'e'
+#define IFNAME1 'm'
+
+/* lwIP definitions. */
+struct ethernetif
+{
+	struct eth_addr *ethaddr;
+};
+static const struct eth_addr    ethbroadcast = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
+static struct netif *xNetIf = NULL;
+
+/* Forward declarations. */
+static void ethernetif_input( void * );
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr );
+err_t ethernetif_init( struct netif *netif );
+
+
+/*-----------------------------------------------------------*/
+
+static void low_level_init( struct netif *netif )
+{
+unsigned portBASE_TYPE uxPriority;
+
+	/* set MAC hardware address length */
+	netif->hwaddr_len = 6;
+
+	/* set MAC hardware address */
+	netif->hwaddr[0] = emacETHADDR0;
+	netif->hwaddr[1] = emacETHADDR1;
+	netif->hwaddr[2] = emacETHADDR2;
+	netif->hwaddr[3] = emacETHADDR3;
+	netif->hwaddr[4] = emacETHADDR4;
+	netif->hwaddr[5] = emacETHADDR5;
+
+	/* maximum transfer unit */
+	netif->mtu = netifMTU;
+
+	/* broadcast capability */
+	netif->flags = NETIF_FLAG_BROADCAST;
+
+	xNetIf = netif;
+
+	/* Initialise the EMAC.  This routine contains code that polls status bits.  
+	If the Ethernet cable is not plugged in then this can take a considerable 
+	time.  To prevent this starving lower priority tasks of processing time we
+	lower our priority prior to the call, then raise it back again once the
+	initialisation is complete. */
+	uxPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+	while( xEMACInit() == NULL )
+	{
+		__asm( "NOP" );
+	}
+	vTaskPrioritySet( NULL, uxPriority );
+
+	/* Create the task that handles the EMAC. */
+	xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * low_level_output(): Should do the actual transmission of the packet. The 
+ * packet is contained in the pbuf that is passed to the function. This pbuf 
+ * might be chained.
+ */
+static err_t low_level_output( struct netif *netif, struct pbuf *p )
+{
+struct pbuf *q;
+static xSemaphoreHandle xTxSemaphore = NULL;
+err_t xReturn = ERR_OK;
+
+	/* Parameter not used. */
+	( void ) netif;
+
+	if( xTxSemaphore == NULL )
+	{
+		vSemaphoreCreateBinary( xTxSemaphore );
+	}
+
+	#if ETH_PAD_SIZE
+		pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+	#endif
+
+	/* Access to the EMAC is guarded using a semaphore. */
+	if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )
+	{
+		for( q = p; q != NULL; q = q->next )
+		{
+			/* Send the data from the pbuf to the interface, one pbuf at a 
+			time. The size of the data in each pbuf is kept in the ->len 
+			variable.  if q->next == NULL then this is the last pbuf in the
+			chain. */
+			if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )
+			{
+				xReturn = ~ERR_OK;
+			}
+		}
+
+        xSemaphoreGive( xTxSemaphore );
+	}
+	
+
+	#if ETH_PAD_SIZE
+		pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+	#endif
+
+	#if LINK_STATS
+		lwip_stats.link.xmit++;
+	#endif /* LINK_STATS */
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * low_level_input(): Should allocate a pbuf and transfer the bytes of the 
+ * incoming packet from the interface into the pbuf. 
+ */
+static struct pbuf *low_level_input( struct netif *netif )
+{
+struct pbuf         *p = NULL, *q;
+u16_t               len = 0;
+static xSemaphoreHandle xRxSemaphore = NULL;
+
+	/* Parameter not used. */
+	( void ) netif;
+
+	if( xRxSemaphore == NULL )
+	{
+		vSemaphoreCreateBinary( xRxSemaphore );
+	}
+
+	/* Access to the emac is guarded using a semaphore. */
+   	if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )
+	{
+		/* Obtain the size of the packet. */
+		len = ulEMACInputLength();
+	
+		if( len )
+		{
+			#if ETH_PAD_SIZE
+				len += ETH_PAD_SIZE;    /* allow room for Ethernet padding */
+			#endif
+	
+			/* We allocate a pbuf chain of pbufs from the pool. */
+			p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );
+		
+			if( p != NULL )
+			{
+				#if ETH_PAD_SIZE
+					pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+				#endif
+		
+				/* Let the driver know we are going to read a new packet. */
+				vEMACRead( NULL, 0, len );
+					
+				/* We iterate over the pbuf chain until we have read the entire
+				packet into the pbuf. */				
+				for( q = p; q != NULL; q = q->next )
+				{
+					/* Read enough bytes to fill this pbuf in the chain. The 
+					available data in the pbuf is given by the q->len variable. */
+					vEMACRead( q->payload, q->len, len );
+				}
+		
+				#if ETH_PAD_SIZE
+					pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+				#endif
+				#if LINK_STATS
+					lwip_stats.link.recv++;
+				#endif /* LINK_STATS */
+			}
+			else
+			{
+				#if LINK_STATS
+					lwip_stats.link.memerr++;
+					lwip_stats.link.drop++;
+				#endif /* LINK_STATS */
+			}
+		}
+
+		xSemaphoreGive( xRxSemaphore );
+	}
+
+	return p;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * ethernetif_output(): This function is called by the TCP/IP stack when an 
+ * IP packet should be sent. It calls the function called low_level_output() 
+ * to do the actual transmission of the packet.
+ */
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr )
+{
+    /* resolve hardware address, then send (or queue) packet */
+    return etharp_output( netif, ipaddr, p );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * ethernetif_input(): This function should be called when a packet is ready to 
+ * be read from the interface. It uses the function low_level_input() that 
+ * should handle the actual reception of bytes from the network interface.
+ */
+static void ethernetif_input( void * pvParameters )
+{
+struct ethernetif   *ethernetif;
+struct eth_hdr      *ethhdr;
+struct pbuf         *p;
+
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		do
+		{
+			ethernetif = xNetIf->state;
+
+			/* move received packet into a new pbuf */
+			p = low_level_input( xNetIf );
+
+			if( p == NULL )
+			{
+				/* No packet could be read.  Wait a for an interrupt to tell us 
+				there is more data available. */
+				vEMACWaitForInput();
+			}
+
+		} while( p == NULL );
+	
+		/* points to packet payload, which starts with an Ethernet header */
+		ethhdr = p->payload;
+	
+		#if LINK_STATS
+			lwip_stats.link.recv++;
+		#endif /* LINK_STATS */
+	
+		ethhdr = p->payload;
+	
+		switch( htons( ethhdr->type ) )
+		{
+			/* IP packet? */
+			case ETHTYPE_IP:
+				/* update ARP table */
+				etharp_ip_input( xNetIf, p );
+		
+				/* skip Ethernet header */
+				pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
+		
+				/* pass to network layer */
+				xNetIf->input( p, xNetIf );
+				break;
+		
+			case ETHTYPE_ARP:
+				/* pass p to ARP module */
+				etharp_arp_input( xNetIf, ethernetif->ethaddr, p );
+				break;
+		
+			default:
+				pbuf_free( p );
+				p = NULL;
+				break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void arp_timer( void *arg )
+{
+	( void ) arg;
+
+    etharp_tmr();
+    sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+}
+/*-----------------------------------------------------------*/
+
+err_t ethernetif_init( struct netif *netif )
+{
+struct ethernetif   *ethernetif;
+
+	ethernetif = mem_malloc( sizeof(struct ethernetif) );
+
+	if( ethernetif == NULL )
+	{
+		LWIP_DEBUGF( NETIF_DEBUG, ("ethernetif_init: out of memory\n") );
+		return ERR_MEM;
+	}
+
+	netif->state = ethernetif;
+	netif->name[0] = IFNAME0;
+	netif->name[1] = IFNAME1;
+	netif->output = ethernetif_output;
+	netif->linkoutput = low_level_output;
+
+	ethernetif->ethaddr = ( struct eth_addr * ) &( netif->hwaddr[0] );
+
+	low_level_init( netif );
+	etharp_init();
+	sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+
+	return ERR_OK;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
new file mode 100644
index 000000000..f5bcc07cf
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/mem.h"
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+#include "netif/tcpdump.h"
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+#include "lwip/tcp.h"
+#include "lwip/ip.h"
+
+static void
+loopif_input( void * arg )
+{
+	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
+	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
+
+	mem_free( arg );
+	netif -> input( r, netif );
+}
+
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+  struct pbuf *q, *r;
+  char *ptr;
+  void **arg;
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+  tcpdump(p);
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+  
+  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (r != NULL) {
+    ptr = r->payload;
+    
+    for(q = p; q != NULL; q = q->next) {
+      memcpy(ptr, q->payload, q->len);
+      ptr += q->len;
+    }
+
+    arg = mem_malloc( sizeof( void *[2]));
+	if( NULL == arg ) {
+		return ERR_MEM;
+	}
+	
+	arg[0] = netif;
+	arg[1] = r;
+	/**
+	 * workaround (patch #1779) to try to prevent bug #2595:
+	 * When connecting to "localhost" with the loopif interface,
+	 * tcp_output doesn't get the opportunity to finnish sending the
+	 * segment before tcp_process gets it, resulting in tcp_process
+	 * referencing pcb->unacked-> which still is NULL.
+	 * 
+	 * TODO: Is there still a race condition here? Leon
+	 */
+	sys_timeout( 1, loopif_input, arg );
+	
+    return ERR_OK;    
+  }
+  return ERR_MEM;
+}
+
+err_t
+loopif_init(struct netif *netif)
+{
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+#if 0 /** TODO: I think this should be enabled, or not? Leon */
+  netif->input = loopif_input;
+#endif
+  netif->output = loopif_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+
+
+
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
new file mode 100644
index 000000000..333496402
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
@@ -0,0 +1,927 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT > 0
+#include "cbcp.h"
+#endif
+
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER    2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER   8
+
+
+                                                                    
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+    struct wordlist *next;
+    char        word[1];
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif
+#if CBCP_SUPPORT > 0
+static void callback_phase (int);
+#endif
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void link_required(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+    
+    if (lcp_phase[unit] == PHASE_DEAD)
+        return;
+    if (logged_in)
+        logout();
+    lcp_phase[unit] = PHASE_DEAD;
+    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+	pppMainWakeup(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(int unit)
+{
+    int i;
+    struct protent *protp;
+    
+    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+    if (did_authup) {
+        /* XXX Do link down processing. */
+        did_authup = 0;
+    }
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (!protp->enabled_flag)
+            continue;
+        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+            (*protp->lowerdown)(unit);
+        if (protp->protocol < 0xC000 && protp->close != NULL)
+            (*protp->close)(unit, "LCP down");
+    }
+    num_np_open = 0;
+    num_np_up = 0;
+    if (lcp_phase[unit] != PHASE_DEAD)
+        lcp_phase[unit] = PHASE_TERMINATE;
+	pppMainWakeup(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(int unit)
+{
+    int auth;
+    int i;
+    struct protent *protp;
+    lcp_options *wo = &lcp_wantoptions[unit];
+    lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+    lcp_options *ho = &lcp_hisoptions[unit];
+#endif
+    
+    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+    /*
+     * Tell higher-level protocols that LCP is up.
+     */
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol != PPP_LCP && protp->enabled_flag
+                && protp->lowerup != NULL)
+            (*protp->lowerup)(unit);
+    
+    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+        /*
+         * We wanted the peer to authenticate itself, and it refused:
+         * treat it as though it authenticated with PAP using a username
+         * of "" and a password of "".  If that's not OK, boot it out.
+         */
+        if (!wo->neg_upap || !null_login(unit)) {
+            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+            lcp_close(unit, "peer refused to authenticate");
+            return;
+        }
+    }
+    
+    lcp_phase[unit] = PHASE_AUTHENTICATE;
+    auth = 0;
+#if CHAP_SUPPORT > 0
+    if (go->neg_chap) {
+        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+        auth |= CHAP_PEER;
+    } 
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (go->neg_upap) {
+        upap_authpeer(unit);
+        auth |= PAP_PEER;
+    }
+#endif
+#if CHAP_SUPPORT > 0
+    if (ho->neg_chap) {
+        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+        auth |= CHAP_WITHPEER;
+    }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (ho->neg_upap) {
+        if (ppp_settings.passwd[0] == 0) {
+            passwd_from_file = 1;
+            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
+                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+        }
+        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+        auth |= PAP_WITHPEER;
+    }
+#endif
+    auth_pending[unit] = auth;
+    
+    if (!auth)
+        network_phase(unit);
+}
+
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(int unit, u16_t protocol)
+{
+    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+    /*
+     * Authentication failure: take the link down
+     */
+    lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_PEER;
+        break;
+    case PPP_PAP:
+        pbit = PAP_PEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        return;
+    }
+    
+    /*
+     * Save the authenticated name of the peer for later.
+     */
+    if (namelen > sizeof(peer_authname) - 1)
+        namelen = sizeof(peer_authname) - 1;
+    BCOPY(name, peer_authname, namelen);
+    peer_authname[namelen] = 0;
+    
+    /*
+     * If there is no more authentication still to be done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(int unit, u16_t protocol)
+{
+    int errCode = PPPERR_AUTHFAIL;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+    if (passwd_from_file)
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+    /* 
+     * XXX Warning: the unit number indicates the interface which is
+     * not necessarily the PPP connection.  It works here as long
+     * as we are only supporting PPP interfaces.
+     */
+    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+    /*
+     * We've failed to authenticate ourselves to our peer.
+     * He'll probably take the link down, and there's not much
+     * we can do except wait for that.
+     */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(int unit, u16_t protocol)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_WITHPEER;
+        break;
+    case PPP_PAP:
+        if (passwd_from_file)
+            BZERO(ppp_settings.passwd, MAXSECRETLEN);
+        pbit = PAP_WITHPEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        pbit = 0;
+    }
+    
+    /*
+     * If there is no more authentication still being done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+#endif
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+    if (num_np_up == 0) {
+	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+        /*
+         * At this point we consider that the link has come up successfully.
+         */
+        if (ppp_settings.idle_time_limit > 0)
+            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+        
+        /*
+         * Set a timeout to close the connection once the maximum
+         * connect time has expired.
+         */
+        if (ppp_settings.maxconnect > 0)
+            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+    ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+        UNTIMEOUT(check_idle, NULL);
+    }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+    if (--num_np_open <= 0) {
+        /* no further use for the link: shut up shop. */
+        lcp_close(0, "No network protocols running");
+    }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void auth_reset(int unit)
+{
+    lcp_options *go = &lcp_gotoptions[unit];
+    lcp_options *ao = &lcp_allowoptions[0];
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+    
+    if (go->neg_upap && !have_pap_secret())
+        go->neg_upap = 0;
+    if (go->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
+            go->neg_chap = 0;
+    }
+}
+
+
+#if PAP_SUPPORT > 0
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int check_passwd(
+	int unit,
+	char *auser,
+	int userlen,
+	char *apasswd,
+	int passwdlen,
+	char **msg,
+	int *msglen
+)
+{
+#if 1
+	*msg = (char *) 0;
+	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+    int ret = 0;
+    struct wordlist *addrs = NULL;
+    char passwd[256], user[256];
+    char secret[MAXWORDLEN];
+    static u_short attempts = 0;
+    
+    /*
+     * Make copies of apasswd and auser, then null-terminate them.
+     */
+    BCOPY(apasswd, passwd, passwdlen);
+    passwd[passwdlen] = '\0';
+    BCOPY(auser, user, userlen);
+    user[userlen] = '\0';
+    *msg = (char *) 0;
+
+    /* XXX Validate user name and password. */
+    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+        
+    if (ret == UPAP_AUTHNAK) {
+        if (*msg == (char *) 0)
+            *msg = "Login incorrect";
+        *msglen = strlen(*msg);
+        /*
+         * Frustrate passwd stealer programs.
+         * Allow 10 tries, but start backing off after 3 (stolen from login).
+         * On 10'th, drop the connection.
+         */
+        if (attempts++ >= 10) {
+            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+            /*ppp_panic("Excess Bad Logins");*/
+        }
+        if (attempts > 3) {
+            sys_msleep((attempts - 3) * 5);
+        }
+        if (addrs != NULL) {
+            free_wordlist(addrs);
+        }
+    } else {
+        attempts = 0;           /* Reset count */
+        if (*msg == (char *) 0)
+            *msg = "Login ok";
+        *msglen = strlen(*msg);
+        set_allowed_addrs(unit, addrs);
+    }
+    
+    BZERO(passwd, sizeof(passwd));
+    BZERO(secret, sizeof(secret));
+    
+    return ret;
+#endif
+}
+#endif
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int auth_ip_addr(int unit, u32_t addr)
+{
+    return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int bad_ip_adrs(u32_t addr)
+{
+    addr = ntohl(addr);
+    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT > 0
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(
+    int unit,
+    char *client,
+    char *server,
+    char *secret,
+    int *secret_len,
+    int save_addrs
+)
+{
+#if 1
+    int len;
+    struct wordlist *addrs;
+    
+    addrs = NULL;
+
+    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+	return 0;
+    }
+
+    len = strlen(ppp_settings.passwd);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(ppp_settings.passwd, secret, len);
+    *secret_len = len;
+    
+    return 1;
+#else
+    int ret = 0, len;
+    struct wordlist *addrs;
+    char secbuf[MAXWORDLEN];
+    
+    addrs = NULL;
+    secbuf[0] = 0;
+
+    /* XXX Find secret. */  
+    if (ret < 0)
+        return 0;
+    
+    if (save_addrs)
+        set_allowed_addrs(unit, addrs);
+    
+    len = strlen(secbuf);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(secbuf, secret, len);
+    BZERO(secbuf, sizeof(secbuf));
+    *secret_len = len;
+    
+    return 1;
+#endif
+}
+#endif
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void auth_check_options(void)
+{
+    lcp_options *wo = &lcp_wantoptions[0];
+    int can_auth;
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    /* Default our_name to hostname, and user to our_name */
+    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
+        strcpy(ppp_settings.our_name, ppp_settings.hostname);
+    if (ppp_settings.user[0] == 0)
+        strcpy(ppp_settings.user, ppp_settings.our_name);
+    
+    /* If authentication is required, ask peer for CHAP or PAP. */
+    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+        wo->neg_chap = 1;
+        wo->neg_upap = 1;
+    }
+    
+    /*
+     * Check whether we have appropriate secrets to use
+     * to authenticate the peer.
+     */
+    can_auth = wo->neg_upap && have_pap_secret();
+    if (!can_auth && wo->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+    }
+    
+    if (ppp_settings.auth_required && !can_auth) {
+        ppp_panic("No auth secret");
+    }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(int unit)
+{
+    int i;
+    struct protent *protp;
+    lcp_options *go = &lcp_gotoptions[unit];
+    
+    /*
+     * If the peer had to authenticate, run the auth-up script now.
+     */
+    if ((go->neg_chap || go->neg_upap) && !did_authup) {
+        /* XXX Do setup for peer authentication. */
+        did_authup = 1;
+    }
+    
+#if CBCP_SUPPORT > 0
+    /*
+     * If we negotiated callback, do it now.
+     */
+    if (go->neg_cbcp) {
+        lcp_phase[unit] = PHASE_CALLBACK;
+        (*cbcp_protent.open)(unit);
+        return;
+    }
+#endif
+    
+    lcp_phase[unit] = PHASE_NETWORK;
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol < 0xC000 && protp->enabled_flag
+                && protp->open != NULL) {
+            (*protp->open)(unit);
+            if (protp->protocol != PPP_CCP)
+                ++num_np_open;
+        }
+    
+    if (num_np_open == 0)
+        /* nothing to do */
+        lcp_close(0, "No network protocols running");
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg)
+{
+    struct ppp_idle idle;
+    u_short itime;
+    
+	(void)arg;
+    if (!get_idle_time(0, &idle))
+        return;
+    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+    if (itime >= ppp_settings.idle_time_limit) {
+        /* link is idle: shut it down. */
+        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+        lcp_close(0, "Link inactive");
+    } else {
+        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+    }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg)
+{
+	(void)arg;
+
+    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+    lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int login(char *user, char *passwd, char **msg, int *msglen)
+{
+    /* XXX Fail until we decide that we want to support logins. */
+    return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void logout(void)
+{
+    logged_in = 0;
+}
+
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int null_login(int unit)
+{
+	(void)unit;
+    /* XXX Fail until we decide that we want to support logins. */
+    return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int get_pap_passwd(int unit, char *user, char *passwd)
+{
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+    if(user)
+    	strcpy(user,   "none");
+    if(passwd)
+    	strcpy(passwd, "none");
+
+    return 1;
+}
+
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int have_pap_secret(void)
+{
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int have_chap_secret(char *client, char *server, u32_t remote)
+{
+	(void)client;
+	(void)server;
+	(void)remote;
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+    if (addresses[unit] != NULL)
+        free_wordlist(addresses[unit]);
+    addresses[unit] = addrs;
+
+#if 0
+    /*
+     * If there's only one authorized address we might as well
+     * ask our peer for that one right away
+     */
+    if (addrs != NULL && addrs->next == NULL) {
+        char *p = addrs->word;
+        struct ipcp_options *wo = &ipcp_wantoptions[unit];
+        u32_t a;
+        struct hostent *hp;
+        
+        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
+                && strchr(p, '/') == NULL) {
+            hp = gethostbyname(p);
+            if (hp != NULL && hp->h_addrtype == AF_INET)
+                a = *(u32_t *)hp->h_addr;
+            else
+                a = inet_addr(p);
+            if (a != (u32_t) -1)
+                wo->hisaddr = a;
+        }
+    }
+#endif
+}
+#endif
+
+static int ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+    
+    /* don't allow loopback or multicast address */
+    if (bad_ip_adrs(addr))
+        return 0;
+    
+    if (addrs == NULL)
+        return !ppp_settings.auth_required;      /* no addresses authorized */
+    
+    /* XXX All other addresses allowed. */
+    return 1;
+}
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void free_wordlist(struct wordlist *wp)
+{
+    struct wordlist *next;
+    
+    while (wp != NULL) {
+        next = wp->next;
+        free(wp);
+        wp = next;
+    }
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
new file mode 100644
index 000000000..d6a5de5b7
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+void link_required (int);		/* we are starting to use the link */
+void link_terminated (int);	/* we are finished with the link */
+void link_down (int);			/* the LCP layer has left the Opened state */
+void link_established (int);	/* the link is up; authenticate now */
+void np_up (int, u16_t);			/* a network protocol has come up */
+void np_down (int, u16_t);		/* a network protocol has gone down */
+void np_finished (int, u16_t);	/* a network protocol no longer needs link */
+void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+void auth_reset (int);			/* check what secrets we have */
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+
+#endif /* AUTH_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
new file mode 100644
index 000000000..4d1dc0d24
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
@@ -0,0 +1,872 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "magic.h"
+
+#if CHAP_SUPPORT > 0
+
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+static int  ChapPrintPkt (u_char *, int,
+			      void (*) (void *, char *, ...), void *);
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+    PPP_CHAP,
+    ChapInit,
+    ChapInput,
+    ChapProtocolReject,
+    ChapLowerUp,
+    ChapLowerDown,
+    NULL,
+    NULL,
+#if 0
+    ChapPrintPkt,
+    NULL,
+#endif
+    1,
+    "CHAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char *ChapCodenames[] = {
+	"Challenge", "Response", "Success", "Failure"
+};
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->resp_name = our_name;
+	cstate->resp_type = digest;
+	
+	if (cstate->clientstate == CHAPCS_INITIAL ||
+			cstate->clientstate == CHAPCS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->clientstate = CHAPCS_PENDING;
+		return;
+	}
+	
+	/*
+	 * We get here as a result of LCP coming up.
+	 * So even if CHAP was open before, we will 
+	 * have to re-authenticate ourselves.
+	 */
+	cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void ChapAuthPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->chal_name = our_name;
+	cstate->chal_type = digest;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->serverstate = CHAPSS_PENDING;
+		return;
+	}
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);		/* crank it up dude! */
+	cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void ChapInit(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	BZERO(cstate, sizeof(*cstate));
+	cstate->unit = unit;
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+	cstate->timeouttime = CHAP_DEFTIMEOUT;
+	cstate->max_transmits = CHAP_DEFTRANSMITS;
+	/* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void ChapChallengeTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending challenges, don't worry.  then again we */
+	/* probably shouldn't be here either */
+	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+			cstate->serverstate != CHAPSS_RECHALLENGE)
+		return;
+	
+	if (cstate->chal_transmits >= cstate->max_transmits) {
+		/* give up on peer */
+		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+		return;
+	}
+	
+	ChapSendChallenge(cstate);		/* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void ChapResponseTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->clientstate != CHAPCS_RESPONSE)
+		return;
+	
+	ChapSendResponse(cstate);		/* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void ChapRechallenge(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->serverstate != CHAPSS_OPEN)
+		return;
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);
+	cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void ChapLowerUp(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->clientstate == CHAPCS_INITIAL)
+		cstate->clientstate = CHAPCS_CLOSED;
+	else if (cstate->clientstate == CHAPCS_PENDING)
+		cstate->clientstate = CHAPCS_LISTEN;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL)
+		cstate->serverstate = CHAPSS_CLOSED;
+	else if (cstate->serverstate == CHAPSS_PENDING) {
+		ChapGenChallenge(cstate);
+		ChapSendChallenge(cstate);
+		cstate->serverstate = CHAPSS_INITIAL_CHAL;
+	}
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void ChapLowerDown(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	/* Timeout(s) pending?  Cancel if so. */
+	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+			cstate->serverstate == CHAPSS_RECHALLENGE)
+		UNTIMEOUT(ChapChallengeTimeout, cstate);
+	else if (cstate->serverstate == CHAPSS_OPEN
+			&& cstate->chal_interval != 0)
+		UNTIMEOUT(ChapRechallenge, cstate);
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void ChapProtocolReject(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->serverstate != CHAPSS_INITIAL &&
+			cstate->serverstate != CHAPSS_CLOSED)
+		auth_peer_fail(unit, PPP_CHAP);
+	if (cstate->clientstate != CHAPCS_INITIAL &&
+			cstate->clientstate != CHAPCS_CLOSED)
+		auth_withpeer_fail(unit, PPP_CHAP);
+	ChapLowerDown(unit);		/* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+	chap_state *cstate = &chap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (packet_len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > packet_len) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+		return;
+	}
+	len -= CHAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code (as in fact it usually does :-).
+	 */
+	switch (code) {
+	case CHAP_CHALLENGE:
+		ChapReceiveChallenge(cstate, inp, id, len);
+		break;
+	
+	case CHAP_RESPONSE:
+		ChapReceiveResponse(cstate, inp, id, len);
+		break;
+	
+	case CHAP_FAILURE:
+		ChapReceiveFailure(cstate, inp, id, len);
+		break;
+	
+	case CHAP_SUCCESS:
+		ChapReceiveSuccess(cstate, inp, id, len);
+		break;
+	
+	default:				/* Need code reject? */
+		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+		break;
+	}
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+	int rchallenge_len;
+	u_char *rchallenge;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[256];
+	MD5_CTX mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+	if (cstate->clientstate == CHAPCS_CLOSED ||
+		cstate->clientstate == CHAPCS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	
+	GETCHAR(rchallenge_len, inp);
+	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	rchallenge = inp;
+	INCPTR(rchallenge_len, inp);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
+	       rhostname));
+	
+	/* Microsoft doesn't send their name back in the PPP packet */
+	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+		rhostname[sizeof(rhostname) - 1] = 0;
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
+			   rhostname));
+	}
+	
+	/* get secret for authenticating ourselves with the specified host */
+	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+			    secret, &secret_len, 0)) {
+		secret_len = 0;		/* assume null secret if can't find one */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+	}
+	
+	/* cancel response send timeout if necessary */
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->resp_id = id;
+	cstate->resp_transmits = 0;
+	
+	/*  generate MD based on negotiated type */
+	switch (cstate->resp_type) { 
+	
+	case CHAP_DIGEST_MD5:
+		MD5Init(&mdContext);
+		MD5Update(&mdContext, &cstate->resp_id, 1);
+		MD5Update(&mdContext, (u_char*)secret, secret_len);
+		MD5Update(&mdContext, rchallenge, rchallenge_len);
+		MD5Final(hash, &mdContext);
+		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+		cstate->resp_length = MD5_SIGNATURE_SIZE;
+		break;
+	
+#ifdef CHAPMS
+	case CHAP_MICROSOFT:
+		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+		break;
+#endif
+	
+	default:
+		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+		return;
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+	u_char *remmd, remmd_len;
+	int secret_len, old_state;
+	int code;
+	char rhostname[256];
+	MD5_CTX mdContext;
+	char secret[MAXSECRETLEN];
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+	
+	if (cstate->serverstate == CHAPSS_CLOSED ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+		cstate->serverstate));
+		return;
+	}
+	
+	if (id != cstate->chal_id)
+		return;			/* doesn't match ID of last challenge */
+	
+	/*
+	* If we have received a duplicate or bogus Response,
+	* we have to send the same answer (Success/Failure)
+	* as we did for the first Response we saw.
+	*/
+	if (cstate->serverstate == CHAPSS_OPEN) {
+		ChapSendStatus(cstate, CHAP_SUCCESS);
+		return;
+	}
+	if (cstate->serverstate == CHAPSS_BADAUTH) {
+		ChapSendStatus(cstate, CHAP_FAILURE);
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(remmd_len, inp);		/* get length of MD */
+	remmd = inp;			/* get pointer to MD */
+	INCPTR(remmd_len, inp);
+	
+	len -= sizeof (u_char) + remmd_len;
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	
+	UNTIMEOUT(ChapChallengeTimeout, cstate);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
+				rhostname));
+	
+	/*
+	* Get secret for authenticating them with us,
+	* do the hash ourselves, and compare the result.
+	*/
+	code = CHAP_FAILURE;
+	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+	secret, &secret_len, 1)) {
+/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+		rhostname));
+	} else {
+	
+		/*  generate MD based on negotiated type */
+		switch (cstate->chal_type) { 
+		
+		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
+			if (remmd_len != MD5_SIGNATURE_SIZE)
+				break;			/* it's not even the right length */
+			MD5Init(&mdContext);
+			MD5Update(&mdContext, &cstate->chal_id, 1);
+			MD5Update(&mdContext, (u_char*)secret, secret_len);
+			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+			MD5Final(hash, &mdContext); 
+			
+			/* compare local and remote MDs and send the appropriate status */
+			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
+				code = CHAP_SUCCESS;	/* they are the same! */
+			break;
+		
+		default:
+			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+		}
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendStatus(cstate, code);
+	
+	if (code == CHAP_SUCCESS) {
+		old_state = cstate->serverstate;
+		cstate->serverstate = CHAPSS_OPEN;
+		if (old_state == CHAPSS_INITIAL_CHAL) {
+			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+		}
+		if (cstate->chal_interval != 0)
+			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+	} else {
+		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+	}
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+
+	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate == CHAPCS_OPEN)
+		/* presumably an answer to a duplicate response */
+		return;
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	cstate->clientstate = CHAPCS_OPEN;
+	
+	auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+	auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void ChapSendChallenge(chap_state *cstate)
+{
+	u_char *outp;
+	int chal_len, name_len;
+	int outlen;
+	
+	chal_len = cstate->chal_len;
+	name_len = strlen(cstate->chal_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
+	
+	PUTCHAR(CHAP_CHALLENGE, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	
+	PUTCHAR(chal_len, outp);		/* put length of challenge */
+	BCOPY(cstate->challenge, outp, chal_len);
+	INCPTR(chal_len, outp);
+	
+	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
+	
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+	
+	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+	++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void ChapSendStatus(chap_state *cstate, int code)
+{
+	u_char *outp;
+	int outlen, msglen;
+	char msg[256];
+	
+	if (code == CHAP_SUCCESS)
+		strcpy(msg, "Welcome!");
+	else
+		strcpy(msg, "I don't like you.  Go 'way.");
+	msglen = strlen(msg);
+	
+	outlen = CHAP_HEADERLEN + msglen;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
+	       cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void ChapGenChallenge(chap_state *cstate)
+{
+	int chal_len;
+	u_char *ptr = cstate->challenge;
+	int i;
+	
+	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+	   MAX_CHALLENGE_LENGTH */  
+	chal_len = (unsigned)
+				((((magic() >> 16) *
+			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+			     + MIN_CHALLENGE_LENGTH);
+	cstate->chal_len = chal_len;
+	cstate->chal_id = ++cstate->id;
+	cstate->chal_transmits = 0;
+	
+	/* generate a random string */
+	for (i = 0; i < chal_len; i++ )
+		*ptr++ = (char) (magic() & 0xff);
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void ChapSendResponse(chap_state *cstate)
+{
+	u_char *outp;
+	int outlen, md_len, name_len;
+	
+	md_len = cstate->resp_length;
+	name_len = strlen(cstate->resp_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);
+	
+	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
+	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
+	PUTSHORT(outlen, outp);			/* packet length */
+	
+	PUTCHAR(md_len, outp);			/* length of MD */
+	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
+	INCPTR(md_len, outp);
+	
+	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
+	
+	/* send the packet */
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	cstate->clientstate = CHAPCS_RESPONSE;
+	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+	++cstate->resp_transmits;
+}
+
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int ChapPrintPkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len;
+	int clen, nlen;
+	u_char x;
+	
+	if (plen < CHAP_HEADERLEN)
+		return 0;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < CHAP_HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
+		printer(arg, " %s", ChapCodenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= CHAP_HEADERLEN;
+	switch (code) {
+	case CHAP_CHALLENGE:
+	case CHAP_RESPONSE:
+		if (len < 1)
+			break;
+		clen = p[0];
+		if (len < clen + 1)
+			break;
+		++p;
+		nlen = len - clen - 1;
+		printer(arg, " <");
+		for (; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, "%.2x", x);
+		}
+		printer(arg, ">, name = %.*Z", nlen, p);
+		break;
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		printer(arg, " %.*Z", len, p);
+		break;
+	default:
+		for (clen = len; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, " %.2x", x);
+		}
+	}
+	
+	return len + CHAP_HEADERLEN;
+}
+
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
new file mode 100644
index 000000000..6fd972752
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN		4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE		1
+#define CHAP_RESPONSE		2
+#define CHAP_SUCCESS		3
+#define CHAP_FAILURE    	4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH	32
+#define MAX_CHALLENGE_LENGTH	64
+#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
+#define CHAPCS_LISTEN		3	/* Listening for a challenge */
+#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
+#define CHAPCS_OPEN		5	/* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPSS_PENDING		2	/* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
+#define CHAPSS_OPEN		4	/* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
+#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+    int unit;			/* Interface unit number */
+    int clientstate;		/* Client state */
+    int serverstate;		/* Server state */
+    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+    u_char chal_len;		/* challenge length */
+    u_char chal_id;		/* ID of last challenge */
+    u_char chal_type;		/* hash algorithm for challenges */
+    u_char id;			/* Current id */
+    char *chal_name;		/* Our name to use with challenge */
+    int chal_interval;		/* Time until we challenge peer again */
+    int timeouttime;		/* Timeout time in seconds */
+    int max_transmits;		/* Maximum # of challenge transmissions */
+    int chal_transmits;		/* Number of transmissions of challenge */
+    int resp_transmits;		/* Number of transmissions of response */
+    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
+    u_char resp_length;		/* length of response */
+    u_char resp_id;		/* ID for response messages */
+    u_char resp_type;		/* hash algorithm for responses */
+    char *resp_name;		/* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
new file mode 100644
index 000000000..01755ba39
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
@@ -0,0 +1,398 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+
+#include "ppp.h"
+
+#if MSCHAP_SUPPORT > 0
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT;		/* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void	DesEncrypt (u_char *, u_char *, u_char *);
+static void	MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void	Expand (u_char *, u_char *);
+static void	Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+);
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+);
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void ChapMS(
+	chap_state *cstate,
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len
+)
+{
+	MS_ChapResponse	response;
+#ifdef MSLANMAN
+	extern int ms_lanman;
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+	BZERO(&response, sizeof(response));
+	
+	/* Calculate both always */
+	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+#ifdef MSLANMAN
+	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+	/* prefered method is set by option  */
+	response.UseNT = !ms_lanman;
+#else
+	response.UseNT = 1;
+#endif
+	
+	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+)
+{
+	char    ZPasswordHash[21];
+	
+	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+	BCOPY(pwHash, ZPasswordHash, 16);
+	
+#if 0
+	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+	
+	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+	
+#if 0
+	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	u_char des_key[8];
+	u_char crypt_key[66];
+	u_char des_input[66];
+	
+	MakeKey(key, des_key);
+	
+	Expand(des_key, crypt_key);
+	setkey(crypt_key);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	Expand(clear, des_input);
+	encrypt(des_input, 0);
+	Collapse(des_input, cipher);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	des_cblock		des_key;
+	des_key_schedule	key_schedule;
+	
+	MakeKey(key, des_key);
+	
+	des_set_key(&des_key, key_schedule);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+)
+{
+	register unsigned int	word;
+	
+	word  = (unsigned)input[startBit / 8] << 8;
+	word |= (unsigned)input[startBit / 8 + 1];
+	
+	word >>= 15 - (startBit % 8 + 7);
+	
+	return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void Expand(u_char *in, u_char *out)
+{
+	int j, c;
+	int i;
+	
+	for(i = 0; i < 64; in++){
+		c = *in;
+		for(j = 7; j >= 0; j--)
+			*out++ = (c >> j) & 01;
+		i += 8;
+	}
+}
+
+/* The inverse of Expand
+ */
+static void Collapse(u_char *in, u_char *out)
+{
+	int j;
+	int i;
+	unsigned int c;
+	
+	for (i = 0; i < 64; i += 8, out++) {
+		c = 0;
+		for (j = 7; j >= 0; j--, in++)
+			c |= *in << j;
+		*out = c & 0xff;
+	}
+}
+#endif
+
+static void MakeKey(
+	u_char *key,		/* IN  56 bit DES key missing parity bits */
+	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
+)
+{
+	des_key[0] = Get7Bits(key,  0);
+	des_key[1] = Get7Bits(key,  7);
+	des_key[2] = Get7Bits(key, 14);
+	des_key[3] = Get7Bits(key, 21);
+	des_key[4] = Get7Bits(key, 28);
+	des_key[5] = Get7Bits(key, 35);
+	des_key[6] = Get7Bits(key, 42);
+	des_key[7] = Get7Bits(key, 49);
+	
+#ifndef USE_CRYPT
+	des_set_odd_parity((des_cblock *)des_key);
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+)
+{
+	int			i;
+	MDstruct	md4Context;
+	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
+	static int	low_byte_first = -1;
+	
+	/* Initialize the Unicode version of the secret (== password). */
+	/* This implicitly supports 8-bit ISO8859/1 characters. */
+	BZERO(unicodePassword, sizeof(unicodePassword));
+	for (i = 0; i < secret_len; i++)
+		unicodePassword[i * 2] = (u_char)secret[i];
+	
+	MDbegin(&md4Context);
+	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
+	
+	if (low_byte_first == -1)
+		low_byte_first = (htons((unsigned short int)1) != 1);
+	if (low_byte_first == 0)
+		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+	
+	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
+	
+	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static ChapMS_LANMan(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse	*response
+)
+{
+	int			i;
+	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+	u_char		PasswordHash[16];
+	
+	/* LANMan password is case insensitive */
+	BZERO(UcasePassword, sizeof(UcasePassword));
+	for (i = 0; i < secret_len; i++)
+		UcasePassword[i] = (u_char)toupper(secret[i]);
+	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
new file mode 100644
index 000000000..c58447215
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
new file mode 100644
index 000000000..fe8b38a93
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
@@ -0,0 +1,838 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f)	((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f)
+{
+	f->state = INITIAL;
+	f->flags = 0;
+	f->id = 0;				/* XXX Start with random id? */
+	f->timeouttime = FSM_DEFTIMEOUT;
+	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+	f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f)
+{
+	int oldState = f->state;
+
+	switch( f->state ){
+	case INITIAL:
+		f->state = CLOSED;
+		break;
+	
+	case STARTING:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+	break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+	case CLOSED:
+		f->state = INITIAL;
+		break;
+	
+	case STOPPED:
+		f->state = STARTING;
+		if( f->callbacks->starting )
+			(*f->callbacks->starting)(f);
+		break;
+	
+	case CLOSING:
+		f->state = INITIAL;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = STARTING;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		f->state = STARTING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+		case INITIAL:
+			f->state = STARTING;
+			if( f->callbacks->starting )
+				(*f->callbacks->starting)(f);
+			break;
+		
+		case CLOSED:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+		break;
+	
+	case CLOSING:
+		f->state = STOPPING;
+		/* fall through */
+	case STOPPED:
+	case OPENED:
+		if( f->flags & OPT_RESTART ){
+			fsm_lowerdown(f);
+			fsm_lowerup(f);
+		}
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the CLOSED state.
+ */
+void fsm_close(fsm *f, char *reason)
+{
+	int oldState = f->state;
+	
+	f->term_reason = reason;
+	f->term_reason_len = (reason == NULL? 0: strlen(reason));
+	switch( f->state ){
+	case STARTING:
+		f->state = INITIAL;
+		break;
+	case STOPPED:
+		f->state = CLOSED;
+		break;
+	case STOPPING:
+		f->state = CLOSING;
+		break;
+	
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+	case OPENED:
+		if( f->state != OPENED )
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		else if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = CLOSING;
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
+			PROTO_NAME(f), reason, oldState, f->state));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(
+	fsm *f,
+	u_char code, 
+	u_char id,
+	u_char *data,
+	int datalen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	/* Adjust length to be smaller than MTU */
+	outp = outpacket_buf[f->unit];
+	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
+		datalen = peer_mru[f->unit] - HEADERLEN;
+	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
+		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+	outlen = datalen + HEADERLEN;
+	MAKEHEADER(outp, f->protocol);
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+				PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l)
+{
+	u_char *inp = inpacket;
+	u_char code, id;
+	int len;
+	
+	/*
+	* Parse header (code, id and length).
+	* If packet too short, drop it.
+	*/
+	if (l < HEADERLEN) {
+		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+					f->protocol));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+				f->protocol));
+		return;
+	}
+	if (len > l) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+				f->protocol));
+		return;
+	}
+	len -= HEADERLEN;		/* subtract header length */
+	
+	if( f->state == INITIAL || f->state == STARTING ){
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
+				f->protocol, f->state));
+		return;
+	}
+	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case CONFREQ:
+		fsm_rconfreq(f, id, inp, len);
+		break;
+	
+	case CONFACK:
+		fsm_rconfack(f, id, inp, len);
+		break;
+	
+	case CONFNAK:
+	case CONFREJ:
+		fsm_rconfnakrej(f, code, id, inp, len);
+		break;
+	
+	case TERMREQ:
+		fsm_rtermreq(f, id, inp, len);
+		break;
+	
+	case TERMACK:
+		fsm_rtermack(f);
+		break;
+	
+	case CODEREJ:
+		fsm_rcoderej(f, inp, len);
+		break;
+	
+	default:
+		if( !f->callbacks->extcode
+				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
+			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+		break;
+	}
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f)
+{
+	switch( f->state ){
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case CLOSED:
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case STOPPED:
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = STOPPING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
+					PROTO_NAME(f), f->state));
+	}
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg)
+{
+    fsm *f = (fsm *) arg;
+
+    switch (f->state) {
+    case CLOSING:
+    case STOPPING:
+		if( f->retransmits <= 0 ){
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /*
+		     * We've waited for an ack long enough.  Peer probably heard us.
+		     */
+		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
+		    if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /* Send Terminate-Request */
+		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+			      (u_char *) f->term_reason, f->term_reason_len);
+		    TIMEOUT(fsm_timeout, f, f->timeouttime);
+		    --f->retransmits;
+		}
+		break;
+
+    case REQSENT:
+    case ACKRCVD:
+    case ACKSENT:
+		if (f->retransmits <= 0) {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    f->state = STOPPED;
+		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+				(*f->callbacks->finished)(f);
+	
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    /* Retransmit the configure-request */
+		    if (f->callbacks->retransmit)
+				(*f->callbacks->retransmit)(f);
+		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
+		    if( f->state == ACKRCVD )
+				f->state = REQSENT;
+		}
+		break;
+
+    default:
+		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
+				  PROTO_NAME(f), f->state));
+	    }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+	int code, reject_if_disagree;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
+				PROTO_NAME(f), id, f->state));
+	switch( f->state ){
+	case CLOSED:
+		/* Go away, we're closed */
+		fsm_sdata(f, TERMACK, id, NULL, 0);
+		return;
+	case CLOSING:
+	case STOPPING:
+		return;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		break;
+	
+	case STOPPED:
+		/* Negotiation started by our peer */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+	
+	/*
+	* Pass the requested configuration options
+	* to protocol-specific code for checking.
+	*/
+	if (f->callbacks->reqci){		/* Check CI */
+		reject_if_disagree = (f->nakloops >= f->maxnakloops);
+		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+	} 
+	else if (len)
+		code = CONFREJ;			/* Reject all CI */
+	else
+		code = CONFACK;
+	
+	/* send the Ack, Nak or Rej to the peer */
+	fsm_sdata(f, (u_char)code, id, inp, len);
+	
+	if (code == CONFACK) {
+		if (f->state == ACKRCVD) {
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+			f->state = OPENED;
+			if (f->callbacks->up)
+				(*f->callbacks->up)(f);	/* Inform upper layers */
+		} 
+		else
+			f->state = ACKSENT;
+		f->nakloops = 0;
+	} 
+	else {
+		/* we sent CONFACK or CONFREJ */
+		if (f->state != ACKRCVD)
+			f->state = REQSENT;
+		if( code == CONFNAK )
+			++f->nakloops;
+	}
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)		/* Expected id? */
+		return;					/* Nope, toss... */
+	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+								(len == 0)) ){
+		/* Ack is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+					PROTO_NAME(f), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+		f->state = ACKRCVD;
+		f->retransmits = f->maxconfreqtransmits;
+		break;
+	
+	case ACKRCVD:
+		/* Huh? an extra valid Ack? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		f->state = OPENED;
+		f->retransmits = f->maxconfreqtransmits;
+		if (f->callbacks->up)
+			(*f->callbacks->up)(f);	/* Inform upper layers */
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+	int (*proc) (fsm *, u_char *, int);
+	int ret;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)	/* Expected id? */
+		return;				/* Nope, toss... */
+	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+	if (!proc || !(ret = proc(f, inp, len))) {
+		/* Nak/reject is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+	case ACKSENT:
+		/* They didn't agree to what we wanted - try another request */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		if (ret < 0)
+			f->state = STOPPED;		/* kludge for stopping CCP */
+		else
+			fsm_sconfreq(f, 0);		/* Send Configure-Request */
+		break;
+	
+	case ACKRCVD:
+		/* Got a Nak/reject when we had already had an Ack?? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	switch (f->state) {
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = REQSENT;		/* Start over but keep trying */
+		break;
+	
+	case OPENED:
+		if (len > 0) {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+		} else {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+		}
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		f->retransmits = 0;
+		f->state = STOPPING;
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		break;
+	}
+	
+	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	switch (f->state) {
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	case STOPPING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case ACKRCVD:
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);
+		break;
+	}
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+	u_char code, id;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+				PROTO_NAME(f), code, id));
+	
+	if( f->state == ACKRCVD )
+		f->state = REQSENT;
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit)
+{
+	u_char *outp;
+	int cilen;
+	
+	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
+		/* Not currently negotiating - reset options */
+		if( f->callbacks->resetci )
+			(*f->callbacks->resetci)(f);
+		f->nakloops = 0;
+		}
+	
+	if( !retransmit ){
+		/* New request - reset retransmission counter, use new ID */
+		f->retransmits = f->maxconfreqtransmits;
+		f->reqid = ++f->id;
+	}
+	
+	f->seen_ack = 0;
+	
+	/*
+	 * Make up the request packet
+	 */
+	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+	if( f->callbacks->cilen && f->callbacks->addci ){
+		cilen = (*f->callbacks->cilen)(f);
+		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
+			cilen = peer_mru[f->unit] - HEADERLEN;
+		if (f->callbacks->addci)
+			(*f->callbacks->addci)(f, outp, &cilen);
+	} else
+		cilen = 0;
+	
+	/* send the request to our peer */
+	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+	
+	/* start the retransmit timer */
+	--f->retransmits;
+	TIMEOUT(fsm_timeout, f, f->timeouttime);
+	
+	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+				PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
new file mode 100644
index 000000000..0e1d9f61a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1		/* Configuration Request */
+#define CONFACK		2		/* Configuration Ack */
+#define CONFNAK		3		/* Configuration Nak */
+#define CONFREJ		4		/* Configuration Reject */
+#define TERMREQ		5		/* Termination Request */
+#define TERMACK		6		/* Termination Ack */
+#define CODEREJ		7		/* Code Reject */
+
+/*
+ * Link states.
+ */
+#define INITIAL		0		/* Down, hasn't been opened */
+#define STARTING	1		/* Down, been opened */
+#define CLOSED		2		/* Up, hasn't been opened */
+#define STOPPED		3		/* Open, waiting for down event */
+#define CLOSING		4		/* Terminating the connection, not open */
+#define STOPPING	5		/* Terminating, but open */
+#define REQSENT		6		/* We've sent a Config Request */
+#define ACKRCVD		7		/* We've received a Config Ack */
+#define ACKSENT		8		/* We've sent a Config Ack */
+#define OPENED		9		/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
+#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4		/* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    int unit;				/* Interface unit number */
+    u_short protocol;		/* Data Link Layer Protocol field value */
+    int state;				/* State */
+    int flags;				/* Contains option bits */
+    u_char id;				/* Current id */
+    u_char reqid;			/* Current request id */
+    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+    int timeouttime;		/* Timeout time in milliseconds */
+    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
+    int retransmits;		/* Number of retransmissions left */
+    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
+    int nakloops;			/* Number of nak loops since last ack */
+    int maxnakloops;		/* Maximum number of nak loops tolerated */
+    struct fsm_callbacks* callbacks;/* Callback routines */
+    char* term_reason;		/* Reason for closing protocol */
+    int term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)			/* Reset our Configuration Information */
+		(fsm*);
+    int  (*cilen)			/* Length of our Configuration Information */
+		(fsm*);
+    void (*addci) 			/* Add our Configuration Information */
+		(fsm*, u_char*, int*);
+    int  (*ackci)			/* ACK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*nakci)			/* NAK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*rejci)			/* Reject our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*reqci)			/* Request peer's Configuration Information */
+		(fsm*, u_char*, int*, int);
+    void (*up)				/* Called when fsm reaches OPENED state */
+		(fsm*);
+    void (*down)			/* Called when fsm leaves OPENED state */
+		(fsm*);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm*);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm*);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm*);
+    int  (*extcode)			/* Called when unknown code received */
+		(fsm*, int, u_char, u_char*, int);
+    char *proto_name;		/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+#endif /* FSM_H */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
new file mode 100644
index 000000000..d5b251880
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
@@ -0,0 +1,1377 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include 
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
+#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR	6	/* new-style single address option */
+#define CILEN_ADDRS	10	/* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);	/* Reset our CI */
+static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);		/* We're UP */
+static void ipcp_down (fsm *);		/* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);	/* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+    PPP_IPCP,
+    ipcp_init,
+    ipcp_input,
+    ipcp_protrej,
+    ipcp_lowerup,
+    ipcp_lowerdown,
+    ipcp_open,
+    ipcp_close,
+#if 0
+    ipcp_printpkt,
+    NULL,
+#endif
+    1,
+    "IPCP",
+#if 0
+    ip_check_options,
+    NULL,
+    ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
+static int default_route_set[NUM_PPP];	/* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+    ipcp_resetci,		/* Reset our Configuration Information */
+    ipcp_cilen,			/* Length of our Configuration Information */
+    ipcp_addci,			/* Add our Configuration Information */
+    ipcp_ackci,			/* ACK our Configuration Information */
+    ipcp_nakci,			/* NAK our Configuration Information */
+    ipcp_rejci,			/* Reject our Configuration Information */
+    ipcp_reqci,			/* Request peer's Configuration Information */
+    ipcp_up,			/* Called when fsm reaches OPENED state */
+    ipcp_down,			/* Called when fsm leaves OPENED state */
+    NULL,				/* Called when we want the lower layer up */
+    ipcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    NULL,				/* Called to handle protocol-specific codes */
+    "IPCP"				/* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */ 
+
+char * _inet_ntoa(u32_t n)
+{
+	struct in_addr ia;
+	ia.s_addr = n;
+	return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(int unit)
+{
+	fsm *f = &ipcp_fsm[unit];
+	ipcp_options *wo = &ipcp_wantoptions[unit];
+	ipcp_options *ao = &ipcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_IPCP;
+	f->callbacks = &ipcp_callbacks;
+	fsm_init(&ipcp_fsm[unit]);
+	
+	memset(wo, 0, sizeof(*wo));
+	memset(ao, 0, sizeof(*ao));
+	
+	wo->neg_addr = 1;
+	wo->ouraddr = 0;
+#if VJ_SUPPORT > 0
+	wo->neg_vj = 1;
+#else
+	wo->neg_vj = 0;
+#endif
+	wo->vj_protocol = IPCP_VJ_COMP;
+	wo->maxslotindex = MAX_SLOTS - 1;
+	wo->cflag = 0;
+	
+	wo->default_route = 1;
+	
+	ao->neg_addr = 1;
+#if VJ_SUPPORT > 0
+	ao->neg_vj = 1;
+#else
+	ao->neg_vj = 0;
+#endif
+	ao->maxslotindex = MAX_SLOTS - 1;
+	ao->cflag = 1;
+	
+	ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(int unit)
+{
+	fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(int unit, char *reason)
+{
+	fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(int unit)
+{
+	fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(int unit, u_char *p, int len)
+{
+	fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void ipcp_resetci(fsm *f)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+	if (wo->ouraddr == 0)
+		wo->accept_local = 1;
+	if (wo->hisaddr == 0)
+		wo->accept_remote = 1;
+	/* Request DNS addresses from the peer */
+	wo->req_dns1 = ppp_settings.usepeerdns;
+	wo->req_dns2 = ppp_settings.usepeerdns;
+	ipcp_gotoptions[f->unit] = *wo;
+	cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int ipcp_cilen(fsm *f)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	
+#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
+	
+	/*
+	 * First see if we want to change our options to the old
+	 * forms because we have received old forms from the peer.
+	 */
+	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+		/* use the old style of address negotiation */
+		go->neg_addr = 1;
+		go->old_addrs = 1;
+	}
+	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+		/* try an older style of VJ negotiation */
+		if (cis_received[f->unit] == 0) {
+			/* keep trying the new style until we see some CI from the peer */
+			go->neg_vj = 1;
+		} else {
+			/* use the old style only if the peer did */
+			if (ho->neg_vj && ho->old_vj) {
+				go->neg_vj = 1;
+				go->old_vj = 1;
+				go->vj_protocol = ho->vj_protocol;
+			}
+		}
+	}
+	
+	return (LENCIADDR(go->neg_addr, go->old_addrs)
+			+ LENCIVJ(go->neg_vj, go->old_vj) +
+			LENCIDNS(go->req_dns1) +
+			LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	int len = *lenp;
+	
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if (len >= vjlen) { \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(vjlen, ucp); \
+			PUTSHORT(val, ucp); \
+			if (!old) { \
+				PUTCHAR(maxslotindex, ucp); \
+				PUTCHAR(cflag, ucp); \
+			} \
+			len -= vjlen; \
+		} else \
+			neg = 0; \
+	}
+	
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		if (len >= addrlen) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(addrlen, ucp); \
+			l = ntohl(val1); \
+			PUTLONG(l, ucp); \
+			if (old) { \
+				l = ntohl(val2); \
+				PUTLONG(l, ucp); \
+			} \
+			len -= addrlen; \
+		} else \
+			neg = 0; \
+	}
+
+#define ADDCIDNS(opt, neg, addr) \
+	if (neg) { \
+		if (len >= CILEN_ADDR) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(CILEN_ADDR, ucp); \
+			l = ntohl(addr); \
+			PUTLONG(l, ucp); \
+			len -= CILEN_ADDR; \
+		} else \
+			neg = 0; \
+	}
+	
+	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	*lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_short cilen, citype, cishort;
+	u32_t cilong;
+	u_char cimaxslotindex, cicflag;
+	
+	/*
+	 * CIs must be in exactly the same order that we sent...
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+	
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if ((len -= vjlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != vjlen || \
+				citype != opt)  \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslotindex) \
+				goto bad; \
+			GETCHAR(cicflag, p); \
+			if (cicflag != cflag) \
+				goto bad; \
+		} \
+	}
+	
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		u32_t l; \
+		if ((len -= addrlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != addrlen || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (val1 != cilong) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			if (val2 != cilong) \
+				goto bad; \
+		} \
+	}
+
+#define ACKCIDNS(opt, neg, addr) \
+	if (neg) { \
+		u32_t l; \
+		if ((len -= CILEN_ADDR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_ADDR || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (addr != cilong) \
+			goto bad; \
+	}
+	
+	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	return (1);
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+	return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, cicflag;
+	u_char citype, cilen, *next;
+	u_short cishort;
+	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+	ipcp_options no;		/* options we've seen Naks for */
+	ipcp_options try;		/* options to request next time */
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	 * Any Nak'd CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define NAKCIADDR(opt, neg, old, code) \
+	if (go->neg && \
+			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		ciaddr1 = htonl(l); \
+		if (old) { \
+			GETLONG(l, p); \
+			ciaddr2 = htonl(l); \
+			no.old_addrs = 1; \
+		} else \
+			ciaddr2 = 0; \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIVJ(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIDNS(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cidnsaddr = htonl(l); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	 * Accept the peer's idea of {our,his} address, if different
+	 * from our idea, only if the accept_{local,remote} flag is set.
+	 */
+	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
+		  try.ouraddr = ciaddr1;
+		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+			     inet_ntoa(ciaddr1)));
+	  }
+	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
+		  try.hisaddr = ciaddr2;
+		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+			     inet_ntoa(ciaddr2)));
+	  }
+	);
+	
+	/*
+	 * Accept the peer's value of maxslotindex provided that it
+	 * is less than what we asked for.  Turn off slot-ID compression
+	 * if the peer wants.  Send old-style compress-type option if
+	 * the peer wants.
+	 */
+	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+		if (cilen == CILEN_VJ) {
+			GETCHAR(cimaxslotindex, p);
+			GETCHAR(cicflag, p);
+			if (cishort == IPCP_VJ_COMP) {
+				try.old_vj = 0;
+				if (cimaxslotindex < go->maxslotindex)
+					try.maxslotindex = cimaxslotindex;
+				if (!cicflag)
+					try.cflag = 0;
+			} else {
+				try.neg_vj = 0;
+			}
+		} else {
+			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+				try.old_vj = 1;
+				try.vj_protocol = cishort;
+			} else {
+				try.neg_vj = 0;
+			}
+		}
+	);
+	
+	NAKCIDNS(CI_MS_DNS1, req_dns1,
+			try.dnsaddr[0] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	NAKCIDNS(CI_MS_DNS2, req_dns2,
+			try.dnsaddr[1] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If they want to negotiate about IP addresses, we comply.
+	* If they want us to ask for compression, we refuse.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if( (len -= cilen) < 0 )
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_COMPRESSTYPE:
+			if (go->neg_vj || no.neg_vj ||
+					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+				goto bad;
+			no.neg_vj = 1;
+			break;
+		case CI_ADDRS:
+			if ((go->neg_addr && go->old_addrs) || no.old_addrs
+					|| cilen != CILEN_ADDRS)
+				goto bad;
+			try.neg_addr = 1;
+			try.old_addrs = 1;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			GETLONG(l, p);
+			ciaddr2 = htonl(l);
+			if (ciaddr2 && go->accept_remote)
+				try.hisaddr = ciaddr2;
+			no.old_addrs = 1;
+			break;
+		case CI_ADDR:
+			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+				goto bad;
+			try.old_addrs = 0;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			if (try.ouraddr != 0)
+				try.neg_addr = 1;
+			no.neg_addr = 1;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	 * OK, the Nak is good.  Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, ciflag, cilen;
+	u_short cishort;
+	u32_t cilong;
+	ipcp_options try;		/* options to request next time */
+	
+	try = *go;
+	/*
+	 * Any Rejected CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+	if (go->neg && \
+			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != val1) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			/* Check rejected value. */ \
+			if (cilong != val2) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+	if (go->neg && \
+			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+			len >= p[1] && \
+			p[0] == opt) { \
+		len -= p[1]; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */  \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslot) \
+				goto bad; \
+			GETCHAR(ciflag, p); \
+			if (ciflag != cflag) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIDNS(opt, neg, dnsaddr) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != dnsaddr) \
+			goto bad; \
+		try.neg = 0; \
+	}
+
+	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	/*
+	 * Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int ipcp_reqci(
+	fsm *f,
+	u_char *inp,		/* Requested CIs */
+	int *len,			/* Length of requested CIs */
+	int reject_if_disagree
+)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+	u_char *cip, *next;				/* Pointer to current and next CIs */
+	u_short cilen, citype;			/* Parsed len, type */
+	u_short cishort;				/* Parsed short value */
+	u32_t tl, ciaddr1;			/* Parsed address values */
+#ifdef OLD_CI_ADDRS
+	u32_t ciaddr2;				/* Parsed address values */
+#endif
+	int rc = CONFACK;				/* Final packet return code */
+	int orc;						/* Individual option return code */
+	u_char *p;						/* Pointer to next char to parse */
+	u_char *ucp = inp;				/* Pointer to current output char */
+	int l = *len;					/* Length left */
+	u_char maxslotindex, cflag;
+	int d;
+	
+	cis_received[f->unit] = 1;
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	while (l) {
+		orc = CONFACK;				/* Assume success */
+		cip = p = next;				/* Remember begining of CI */
+		if (l < 2 ||				/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;			/* Reject bad CI */
+			cilen = l;				/* Reject till end of packet */
+			l = 0;					/* Don't loop again */
+			goto endswitch;
+		}
+		GETCHAR(citype, p);			/* Parse CI type */
+		GETCHAR(cilen, p);			/* Parse CI length */
+		l -= cilen;					/* Adjust remaining length */
+		next += cilen;				/* Step to next CI */
+
+		switch (citype) {			/* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+		case CI_ADDRS:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+			if (!ao->neg_addr ||
+					cilen != CILEN_ADDRS) {	/* Check CI length */
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);		/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * If neither we nor he knows his address, reject the option.
+				 */
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			/*
+			 * If he doesn't know our address, or if we both have our address
+			 * but disagree about it, then NAK it with our idea.
+			 */
+			GETLONG(tl, p);		/* Parse desination address (ours) */
+			ciaddr2 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+			if (ciaddr2 != wo->ouraddr) {
+				if (ciaddr2 == 0 || !wo->accept_local) {
+					orc = CONFNAK;
+					if (!reject_if_disagree) {
+						DECPTR(sizeof(u32_t), p);
+						tl = ntohl(wo->ouraddr);
+						PUTLONG(tl, p);
+					}
+				} else {
+					go->ouraddr = ciaddr2;	/* accept peer's idea */
+				}
+			}
+			
+			ho->neg_addr = 1;
+			ho->old_addrs = 1;
+			ho->hisaddr = ciaddr1;
+			ho->ouraddr = ciaddr2;
+			break;
+#endif
+		
+		case CI_ADDR:
+			if (!ao->neg_addr) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);	/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * Don't ACK an address of 0.0.0.0 - reject it instead.
+				 */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			ho->neg_addr = 1;
+			ho->hisaddr = ciaddr1;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+			break;
+		
+		case CI_MS_DNS1:
+		case CI_MS_DNS2:
+			/* Microsoft primary or secondary DNS request */
+			d = citype == CI_MS_DNS2;
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->dnsaddr[d] == 0 ||
+					cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->dnsaddr[d]) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+							d+1, inet_ntoa(tl)));
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->dnsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+			break;
+		
+		case CI_MS_WINS1:
+		case CI_MS_WINS2:
+			/* Microsoft primary or secondary WINS request */
+			d = citype == CI_MS_WINS2;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->winsaddr[d] == 0 ||
+				cilen != CILEN_ADDR) {	/* Check CI length */
+				orc = CONFREJ;			/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->winsaddr[d]) {
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->winsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			break;
+		
+		case CI_COMPRESSTYPE:
+			if (!ao->neg_vj) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			if (!(cishort == IPCP_VJ_COMP ||
+					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+				orc = CONFREJ;
+				break;
+			}
+			
+			ho->neg_vj = 1;
+			ho->vj_protocol = cishort;
+			if (cilen == CILEN_VJ) {
+				GETCHAR(maxslotindex, p);
+				if (maxslotindex > ao->maxslotindex) { 
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(ao->maxslotindex, p);
+					}
+				}
+				GETCHAR(cflag, p);
+				if (cflag && !ao->cflag) {
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(wo->cflag, p);
+					}
+				}
+				ho->maxslotindex = maxslotindex;
+				ho->cflag = cflag;
+			} else {
+				ho->old_vj = 1;
+				ho->maxslotindex = MAX_SLOTS - 1;
+				ho->cflag = 1;
+			}
+			IPCPDEBUG((LOG_INFO, 
+						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+			break;
+			
+		default:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+			orc = CONFREJ;
+			break;
+		}
+		
+endswitch:
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;				/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+				orc = CONFREJ;		/* Get tough if so */
+			} else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+					rc = CONFNAK;	/* Not anymore... */
+					ucp = inp;		/* Backup */
+				}
+			}
+		}
+		
+		if (orc == CONFREJ &&		/* Reject this CI */
+				rc != CONFREJ) {	/*  but no prior ones? */
+			rc = CONFREJ;
+			ucp = inp;				/* Backup */
+		}
+		
+		/* Need to move CI? */
+		if (ucp != cip)
+			BCOPY(cip, ucp, cilen);	/* Move it */
+		
+		/* Update output pointer */
+		INCPTR(cilen, ucp);
+	}
+	
+	/*
+	 * If we aren't rejecting this packet, and we want to negotiate
+	 * their address, and they didn't send their address, then we
+	 * send a NAK with a CI_ADDR option appended.  We assume the
+	 * input buffer is long enough that we can append the extra
+	 * option safely.
+	 */
+	if (rc != CONFREJ && !ho->neg_addr &&
+			wo->req_addr && !reject_if_disagree) {
+		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+		if (rc == CONFACK) {
+			rc = CONFNAK;
+			ucp = inp;				/* reset pointer */
+			wo->req_addr = 0;		/* don't ask again */
+		}
+		PUTCHAR(CI_ADDR, ucp);
+		PUTCHAR(CILEN_ADDR, ucp);
+		tl = ntohl(wo->hisaddr);
+		PUTLONG(tl, ucp);
+	}
+	
+	*len = (int)(ucp - inp);		/* Compute output length */
+	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ip_check_options(u_long localAddr)
+{
+	ipcp_options *wo = &ipcp_wantoptions[0];
+
+	/*
+	 * Load our default IP address but allow the remote host to give us
+	 * a new address.
+	 */
+	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+		wo->accept_local = 1;	/* don't insist on this default value */
+		wo->ouraddr = htonl(localAddr);
+	}
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f)
+{
+	u32_t mask;
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	np_up(f->unit, PPP_IP);
+	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+	
+	/*
+	 * We must have a non-zero IP address for both ends of the link.
+	 */
+	if (!ho->neg_addr)
+		ho->hisaddr = wo->hisaddr;
+	
+	if (ho->hisaddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+		ipcp_close(f->unit, "Could not determine remote IP address");
+		return;
+	}
+	if (go->ouraddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+		ipcp_close(f->unit, "Could not determine local IP address");
+		return;
+	}
+	
+	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+	}
+
+	/*
+	 * Check that the peer is allowed to use the IP address it wants.
+	 */
+	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+				inet_ntoa(ho->hisaddr)));
+		ipcp_close(f->unit, "Unauthorized remote IP address");
+		return;
+	}
+	
+	/* set tcp compression */
+	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+	
+	/*
+	 * Set IP addresses and (if specified) netmask.
+	 */
+	mask = GetMask(go->ouraddr);
+	
+	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	/* bring the interface up for IP */
+	if (!sifup(f->unit)) {
+		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+	
+	/* assign a default route through the interface if required */
+	if (ipcp_wantoptions[f->unit].default_route) 
+		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
+			default_route_set[f->unit] = 1;
+	
+	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+	if (go->dnsaddr[0]) {
+		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+	}
+	if (go->dnsaddr[1]) {
+		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+	}
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f)
+{
+	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+	np_down(f->unit, PPP_IP);
+	sifvjcomp(f->unit, 0, 0, 0);
+	
+	sifdown(f->unit);
+	ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void ipcp_clear_addrs(int unit)
+{
+	u32_t ouraddr, hisaddr;
+	
+	ouraddr = ipcp_gotoptions[unit].ouraddr;
+	hisaddr = ipcp_hisoptions[unit].hisaddr;
+	if (default_route_set[unit]) {
+		cifdefaultroute(unit, ouraddr, hisaddr);
+		default_route_set[unit] = 0;
+	}
+	cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f)
+{
+	np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int ipcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN	20	/* bytes */
+#define IP_OFFMASK	0x1fff
+#define IPPROTO_TCP	6
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)	(((x)[0] << 8) + (x)[1])
+#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)	(((unsigned char *)(x))[9])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int ip_active_pkt(u_char *pkt, int len)
+{
+	u_char *tcp;
+	int hlen;
+	
+	len -= PPP_HDRLEN;
+	pkt += PPP_HDRLEN;
+	if (len < IP_HDRLEN)
+		return 0;
+	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+		return 0;
+	if (get_ipproto(pkt) != IPPROTO_TCP)
+		return 1;
+	hlen = get_iphl(pkt) * 4;
+	if (len < hlen + TCP_HDRLEN)
+		return 0;
+	tcp = pkt + hlen;
+	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+		return 0;
+	return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
new file mode 100644
index 000000000..416aa79a2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS	1			/* IP Addresses */
+#define CI_COMPRESSTYPE	2		/* Compression Type */
+#define	CI_ADDR		3
+
+#define CI_MS_WINS1	128			/* Primary WINS value */
+#define CI_MS_DNS1	129			/* Primary DNS value */
+#define CI_MS_WINS2	130			/* Secondary WINS value */
+#define CI_MS_DNS2	131			/* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+								/* compression option*/ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+    u_int neg_addr : 1;			/* Negotiate IP Address? */
+    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
+    u_int req_addr : 1;			/* Ask peer to send IP address? */
+    u_int default_route : 1;		/* Assign default route through interface? */
+    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
+    u_int neg_vj : 1;				/* Van Jacobson Compression? */
+    u_int old_vj : 1;				/* use old (short) form of VJ option? */
+    u_int accept_local : 1;		/* accept peer's value for ouraddr */
+    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
+    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
+    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
+    u_short vj_protocol;		/* protocol value to use in VJ option */
+    u_char maxslotindex;		/* VJ slots - 1. */
+    u_char cflag;				/* VJ slot compression flag. */
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
+    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+
+#endif /* IPCP_H */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
new file mode 100644
index 000000000..e974a2d44
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
@@ -0,0 +1,1991 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID	2
+#define CILEN_CHAR	3
+#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP	3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);	        /* Reset our CI */
+static int  lcp_cilen (fsm*);		        /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
+static void lcp_up (fsm*);		            /* We're UP */
+static void lcp_down (fsm*);	    	    /* We're DOWN */
+static void lcp_starting (fsm*);   	    /* We need lower layer up */
+static void lcp_finished (fsm*);	        /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
+static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
+static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
+    lcp_resetci,		/* Reset our Configuration Information */
+    lcp_cilen,			/* Length of our Configuration Information */
+    lcp_addci,			/* Add our Configuration Information */
+    lcp_ackci,			/* ACK our Configuration Information */
+    lcp_nakci,			/* NAK our Configuration Information */
+    lcp_rejci,			/* Reject our Configuration Information */
+    lcp_reqci,			/* Request peer's Configuration Information */
+    lcp_up,				/* Called when fsm reaches OPENED state */
+    lcp_down,			/* Called when fsm leaves OPENED state */
+    lcp_starting,		/* Called when we want the lower layer up */
+    lcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    lcp_extcode,		/* Called to handle LCP-specific codes */
+    "LCP"				/* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void lcp_init(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	lcp_options *ao = &lcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_LCP;
+	f->callbacks = &lcp_callbacks;
+	
+	fsm_init(f);
+	
+	wo->passive = 0;
+	wo->silent = 0;
+	wo->restart = 0;			/* Set to 1 in kernels or multi-line
+								 * implementations */
+	wo->neg_mru = 1;
+	wo->mru = PPP_DEFMRU;
+	wo->neg_asyncmap = 1;
+	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	wo->neg_chap = 0;			/* Set to 1 on server */
+	wo->neg_upap = 0;			/* Set to 1 on server */
+	wo->chap_mdtype = CHAP_DIGEST_MD5;
+	wo->neg_magicnumber = 1;
+	wo->neg_pcompression = 1;
+	wo->neg_accompression = 1;
+	wo->neg_lqr = 0;			/* no LQR implementation yet */
+	wo->neg_cbcp = 0;
+	
+	ao->neg_mru = 1;
+	ao->mru = PPP_MAXMRU;
+	ao->neg_asyncmap = 1;
+	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	ao->neg_chap = (CHAP_SUPPORT != 0);
+	ao->chap_mdtype = CHAP_DIGEST_MD5;
+	ao->neg_upap = (PAP_SUPPORT != 0);
+	ao->neg_magicnumber = 1;
+	ao->neg_pcompression = 1;
+	ao->neg_accompression = 1;
+	ao->neg_lqr = 0;			/* no LQR implementation yet */
+	ao->neg_cbcp = (CBCP_SUPPORT != 0);
+
+	/* 
+	 * Set transmit escape for the flag and escape characters plus anything
+	 * set for the allowable options.
+	 */
+	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+	xmit_accm[unit][15] = 0x60;
+	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
+	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
+	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
+	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
+	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+				xmit_accm[unit][0],
+				xmit_accm[unit][1],
+				xmit_accm[unit][2],
+				xmit_accm[unit][3]));
+	
+	lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	f->flags = 0;
+	if (wo->passive)
+		f->flags |= OPT_PASSIVE;
+	if (wo->silent)
+		f->flags |= OPT_SILENT;
+	fsm_open(f);
+	
+	lcp_phase[unit] = PHASE_ESTABLISH; 
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(int unit, char *reason)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_phase[unit] != PHASE_DEAD)
+		lcp_phase[unit] = PHASE_TERMINATE;
+	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+		/*
+		 * This action is not strictly according to the FSM in RFC1548,
+		 * but it does mean that the program terminates if you do an
+		 * lcp_close() in passive/silent mode when a connection hasn't
+		 * been established.
+		 */
+		f->state = CLOSED;
+		lcp_finished(f);
+	}
+	else
+		fsm_close(&lcp_fsm[unit], reason);
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(int unit)
+{
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	/*
+	* Don't use A/C or protocol compression on transmission,
+	* but accept A/C and protocol compressed packets
+	* if we are going to ask for A/C and protocol compression.
+	*/
+	ppp_set_xaccm(unit, &xmit_accm[unit]);
+	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+					wo->neg_pcompression, wo->neg_accompression);
+	peer_mru[unit] = PPP_MRU;
+	lcp_allowoptions[unit].asyncmap 
+		= (u_long)xmit_accm[unit][0]
+			| ((u_long)xmit_accm[unit][1] << 8)
+			| ((u_long)xmit_accm[unit][2] << 16)
+			| ((u_long)xmit_accm[unit][3] << 24);
+	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+				xmit_accm[unit][3],
+				xmit_accm[unit][2],
+				xmit_accm[unit][1],
+				xmit_accm[unit][0]));
+	
+	fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(int unit, u_char *p, int len)
+{
+	/*
+	* Send back the protocol and the information field of the
+	* rejected packet.  We only get here if LCP is in the OPENED state.
+	*/
+
+	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
+				p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(int unit, u_char *p, int len)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+	u_char *magp;
+	
+	switch( code ){
+	case PROTREJ:
+		lcp_rprotrej(f, inp, len);
+		break;
+	
+	case ECHOREQ:
+		if (f->state != OPENED)
+			break;
+		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+		magp = inp;
+		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+		fsm_sdata(f, ECHOREP, id, inp, len);
+		break;
+	
+	case ECHOREP:
+		lcp_received_echo_reply(f, id, inp, len);
+		break;
+	
+	case DISCREQ:
+		break;
+	
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+    
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+	int i;
+	struct protent *protp;
+	u_short prot;
+	
+	if (len < sizeof (u_short)) {
+		LCPDEBUG((LOG_INFO,
+				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+		return;
+	}
+	
+	GETSHORT(prot, inp);
+	
+	LCPDEBUG((LOG_INFO,
+			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
+			prot));
+	
+	/*
+	* Protocol-Reject packets received in any state other than the LCP
+	* OPENED state SHOULD be silently discarded.
+	*/
+	if( f->state != OPENED ){
+		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
+				f->state));
+		return;
+	}
+	
+	/*
+	* Upcall the proper Protocol-Reject routine.
+	*/
+	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+		if (protp->protocol == prot && protp->enabled_flag) {
+			(*protp->protrej)(f->unit);
+			return;
+		}
+	
+	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
+			prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void lcp_protrej(int unit)
+{
+	(void)unit;
+	/*
+	* Can't reject LCP!
+	*/
+	LCPDEBUG((LOG_WARNING,
+			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
+	fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f)
+{
+	lcp_wantoptions[f->unit].magicnumber = magic();
+	lcp_wantoptions[f->unit].numloops = 0;
+	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+	peer_mru[f->unit] = PPP_MRU;
+	auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
+	/*
+	* NB: we only ask for one of CHAP and UPAP, even if we will
+	* accept either.
+	*/
+	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+		LENCICHAP(go->neg_chap) +
+		LENCISHORT(!go->neg_chap && go->neg_upap) +
+		LENCILQR(go->neg_lqr) +
+		LENCICBCP(go->neg_cbcp) +
+		LENCILONG(go->neg_magicnumber) +
+		LENCIVOID(go->neg_pcompression) +
+		LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char *start_ucp = ucp;
+	
+#define ADDCIVOID(opt, neg) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_VOID, ucp); \
+	}
+#define ADDCISHORT(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_SHORT, ucp); \
+		PUTSHORT(val, ucp); \
+	}
+#define ADDCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAP, ucp); \
+		PUTSHORT(val, ucp); \
+		PUTCHAR(digest, ucp); \
+	}
+#define ADDCILONG(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LONG, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCILQR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LQR, ucp); \
+		PUTSHORT(PPP_LQR, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCICHAR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAR, ucp); \
+		PUTCHAR(val, ucp); \
+	}
+	
+	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	if (ucp - start_ucp != *lenp) {
+		/* this should never happen, because peer_mtu should be 1500 */
+		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+	}
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cilen, citype, cichar;
+	u_short cishort;
+	u32_t cilong;
+	
+	/*
+	* CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define ACKCIVOID(opt, neg) \
+	if (neg) { \
+		if ((len -= CILEN_VOID) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_VOID || \
+				citype != opt) \
+			goto bad; \
+	}
+#define ACKCISHORT(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_SHORT) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_SHORT || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+	}
+#define ACKCICHAR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_CHAR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAR || \
+				citype != opt) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != val) \
+			goto bad; \
+	}
+#define ACKCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+		if ((len -= CILEN_CHAP) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAP || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != digest) \
+			goto bad; \
+	}
+#define ACKCILONG(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LONG) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LONG || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+#define ACKCILQR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LQR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LQR || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != PPP_LQR) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+	
+	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+	return (1);
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+	return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	u_char citype, cichar, *next;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options no;		/* options we've seen Naks for */
+	lcp_options try;		/* options to request next time */
+	int looped_back = 0;
+	int cilen;
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	* Any Nak'd CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define NAKCIVOID(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAP(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAR && \
+			p[1] == CILEN_CHAR && \
+			p[0] == opt) { \
+		len -= CILEN_CHAR; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCISHORT(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILONG(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILQR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	* We don't care if they want to send us smaller packets than
+	* we want.  Therefore, accept any MRU less than what we asked for,
+	* but then ignore the new value when setting the MRU in the kernel.
+	* If they send us a bigger MRU than what we asked, accept it, up to
+	* the limit of the default MRU we'd get if we didn't negotiate.
+	*/
+	if (go->neg_mru && go->mru != PPP_DEFMRU) {
+		NAKCISHORT(CI_MRU, neg_mru,
+			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
+				try.mru = cishort;
+		);
+	}
+	
+	/*
+	* Add any characters they want to our (receive-side) asyncmap.
+	*/
+	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+			try.asyncmap = go->asyncmap | cilong;
+		);
+	}
+	
+	/*
+	* If they've nak'd our authentication-protocol, check whether
+	* they are proposing a different protocol, or a different
+	* hash algorithm for CHAP.
+	*/
+	if ((go->neg_chap || go->neg_upap)
+			&& len >= CILEN_SHORT
+			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+		cilen = p[1];
+	len -= cilen;
+	no.neg_chap = go->neg_chap;
+	no.neg_upap = go->neg_upap;
+	INCPTR(2, p);
+	GETSHORT(cishort, p);
+	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+		/*
+		 * If we were asking for CHAP, they obviously don't want to do it.
+		 * If we weren't asking for CHAP, then we were asking for PAP,
+		 * in which case this Nak is bad.
+		 */
+		if (!go->neg_chap)
+			goto bad;
+		try.neg_chap = 0;
+	
+	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+		GETCHAR(cichar, p);
+		if (go->neg_chap) {
+			/*
+			 * We were asking for CHAP/MD5; they must want a different
+			 * algorithm.  If they can't do MD5, we'll have to stop
+			 * asking for CHAP.
+			 */
+			if (cichar != go->chap_mdtype)
+				try.neg_chap = 0;
+		} else {
+			/*
+			 * Stop asking for PAP if we were asking for it.
+			 */
+			try.neg_upap = 0;
+		}
+	
+	} else {
+		/*
+		 * We don't recognize what they're suggesting.
+		 * Stop asking for what we were asking for.
+		 */
+		if (go->neg_chap)
+			try.neg_chap = 0;
+		else
+			try.neg_upap = 0;
+		p += cilen - CILEN_SHORT;
+	}
+	}
+	
+	/*
+	* If they can't cope with our link quality protocol, we'll have
+	* to stop asking for LQR.  We haven't got any other protocol.
+	* If they Nak the reporting period, take their value XXX ?
+	*/
+	NAKCILQR(CI_QUALITY, neg_lqr,
+		if (cishort != PPP_LQR)
+			try.neg_lqr = 0;
+		else
+			try.lqr_period = cilong;
+	);
+	
+	/*
+	* Only implementing CBCP...not the rest of the callback options
+	*/
+	NAKCICHAR(CI_CALLBACK, neg_cbcp,
+		try.neg_cbcp = 0;
+	);
+	
+	/*
+	* Check for a looped-back line.
+	*/
+	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+		try.magicnumber = magic();
+		looped_back = 1;
+	);
+	
+	/*
+	* Peer shouldn't send Nak for protocol compression or
+	* address/control compression requests; they should send
+	* a Reject instead.  If they send a Nak, treat it as a Reject.
+	*/
+	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+		try.neg_pcompression = 0;
+	);
+	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+		try.neg_accompression = 0;
+	);
+	
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If we see an option that we requested, or one we've already seen
+	* in this packet, then this packet is bad.
+	* If we wanted to respond by starting to negotiate on the requested
+	* option(s), we could, but we don't, because except for the
+	* authentication type and quality protocol, if we are not negotiating
+	* an option, it is because we were told not to.
+	* For the authentication type, the Nak from the peer means
+	* `let me authenticate myself with you' which is a bit pointless.
+	* For the quality protocol, the Nak means `ask me to send you quality
+	* reports', but if we didn't ask for them, we don't want them.
+	* An option we don't recognize represents the peer asking to
+	* negotiate some option we don't support, so ignore it.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if (cilen < CILEN_VOID || (len -= cilen) < 0)
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_MRU:
+			if ((go->neg_mru && go->mru != PPP_DEFMRU)
+					|| no.neg_mru || cilen != CILEN_SHORT)
+				goto bad;
+			GETSHORT(cishort, p);
+			if (cishort < PPP_DEFMRU)
+				try.mru = cishort;
+			break;
+		case CI_ASYNCMAP:
+			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+					|| no.neg_asyncmap || cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_AUTHTYPE:
+			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
+				goto bad;
+			break;
+		case CI_MAGICNUMBER:
+			if (go->neg_magicnumber || no.neg_magicnumber ||
+					cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_PCOMPRESSION:
+			if (go->neg_pcompression || no.neg_pcompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_ACCOMPRESSION:
+			if (go->neg_accompression || no.neg_accompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_QUALITY:
+			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+				goto bad;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	* OK, the Nak is good.  Now we can update state.
+	*/
+	if (f->state != OPENED) {
+		if (looped_back) {
+			if (++try.numloops >= lcp_loopbackfail) {
+				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+				lcp_close(f->unit, "Loopback detected");
+			}
+		} 
+		else
+			try.numloops = 0;
+		*go = try;
+	}
+	
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Reject was bad.
+ *	1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cichar;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options try;		/* options to request next time */
+	
+	try = *go;
+	
+	/*
+	* Any Rejected CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define REJCIVOID(opt, neg) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+	}
+#define REJCISHORT(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */ \
+		if (cishort != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+	}
+#define REJCICHAP(opt, neg, val, digest) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cishort != val || cichar != digest) \
+			goto bad; \
+		try.neg = 0; \
+		try.neg_upap = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+	}
+#define REJCILONG(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+	}
+#define REJCILQR(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cishort != PPP_LQR || cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+	}
+#define REJCICBCP(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_CBCP && \
+			p[1] == CILEN_CBCP && \
+			p[0] == opt) { \
+		len -= CILEN_CBCP; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cichar != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+	}
+	
+	REJCISHORT(CI_MRU, neg_mru, go->mru);
+	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+	if (!go->neg_chap) {
+		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+	}
+	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+	
+	/*
+	* If there are any remaining CIs, then this packet is bad.
+	*/
+	if (len != 0)
+		goto bad;
+	/*
+	* Now we can update state.
+	*/
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int lcp_reqci(fsm *f, 
+						u_char *inp,		/* Requested CIs */
+						int *lenp,			/* Length of requested CIs */
+						int reject_if_disagree)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	u_char *cip, *next;			/* Pointer to current and next CIs */
+	int cilen, citype, cichar;	/* Parsed len, type, char value */
+	u_short cishort;			/* Parsed short value */
+	u32_t cilong;			/* Parse long value */
+	int rc = CONFACK;			/* Final packet return code */
+	int orc;					/* Individual option return code */
+	u_char *p;					/* Pointer to next char to parse */
+	u_char *rejp;				/* Pointer to next char in reject frame */
+	u_char *nakp;				/* Pointer to next char in Nak frame */
+	int l = *lenp;				/* Length left */
+#if TRACELCP > 0
+	char traceBuf[80];
+	int traceNdx = 0;
+#endif
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	nakp = nak_buffer;
+	rejp = inp;
+	while (l) {
+		orc = CONFACK;			/* Assume success */
+		cip = p = next;			/* Remember begining of CI */
+		if (l < 2 ||			/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;		/* Reject bad CI */
+			cilen = l;			/* Reject till end of packet */
+			l = 0;			/* Don't loop again */
+			citype = 0;
+			goto endswitch;
+		}
+		GETCHAR(citype, p);		/* Parse CI type */
+		GETCHAR(cilen, p);		/* Parse CI length */
+		l -= cilen;			/* Adjust remaining length */
+		next += cilen;			/* Step to next CI */
+		
+		switch (citype) {		/* Check CI type */
+		case CI_MRU:
+			if (!ao->neg_mru) {		/* Allow option? */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			GETSHORT(cishort, p);	/* Parse MRU */
+			
+			/*
+			 * He must be able to receive at least our minimum.
+			 * No need to check a maximum.  If he sends a large number,
+			 * we'll just ignore it.
+			 */
+			if (cishort < PPP_MINMRU) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+				orc = CONFNAK;		/* Nak CI */
+				PUTCHAR(CI_MRU, nakp);
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
+				break;
+			}
+			ho->neg_mru = 1;		/* Remember he sent MRU */
+			ho->mru = cishort;		/* And remember value */
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " MRU %d", cishort);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_ASYNCMAP:
+			if (!ao->neg_asyncmap) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_LONG) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+			
+			/*
+			 * Asyncmap must have set at least the bits
+			 * which are set in lcp_allowoptions[unit].asyncmap.
+			 */
+			if ((ao->asyncmap & ~cilong) != 0) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+							cilong, ao->asyncmap));
+				orc = CONFNAK;
+				PUTCHAR(CI_ASYNCMAP, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(ao->asyncmap | cilong, nakp);
+				break;
+			}
+			ho->neg_asyncmap = 1;
+			ho->asyncmap = cilong;
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " ASYNCMAP=%lX", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_AUTHTYPE:
+			if (cilen < CILEN_SHORT) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+				orc = CONFREJ;
+				break;
+			} else if (!(ao->neg_upap || ao->neg_chap)) {
+				/*
+				 * Reject the option if we're not willing to authenticate.
+				 */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			/*
+			 * Authtype must be UPAP or CHAP.
+			 *
+			 * Note: if both ao->neg_upap and ao->neg_chap are set,
+			 * and the peer sends a Configure-Request with two
+			 * authenticate-protocol requests, one for CHAP and one
+			 * for UPAP, then we will reject the second request.
+			 * Whether we end up doing CHAP or UPAP depends then on
+			 * the ordering of the CIs in the peer's Configure-Request.
+			 */
+			
+			if (cishort == PPP_PAP) {
+				if (ho->neg_chap) {	/* we've already accepted CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_SHORT) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_upap) {	/* we don't want to do PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest CHAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+				ho->neg_upap = 1;
+#if TRACELCP > 0
+				sprintf(&traceBuf[traceNdx], " PAP (%X)", cishort);
+				traceNdx = strlen(traceBuf);
+#endif
+				break;
+			}
+			if (cishort == PPP_CHAP) {
+				if (ho->neg_upap) {	/* we've already accepted PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_CHAP) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_chap) {	/* we don't want to do CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest PAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_SHORT, nakp);
+					PUTSHORT(PPP_PAP, nakp);
+					break;
+				}
+				GETCHAR(cichar, p);	/* get digest type*/
+				if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+						&& cichar != CHAP_MICROSOFT
+#endif
+				) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+					orc = CONFNAK;
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+#if TRACELCP > 0
+				sprintf(&traceBuf[traceNdx], " CHAP %X,%d", cishort, cichar);
+				traceNdx = strlen(traceBuf);
+#endif
+				ho->chap_mdtype = cichar; /* save md type */
+				ho->neg_chap = 1;
+				break;
+			}
+			
+			/*
+			 * We don't recognize the protocol they're asking for.
+			 * Nak it with something we're willing to do.
+			 * (At this point we know ao->neg_upap || ao->neg_chap.)
+			 */
+			orc = CONFNAK;
+			PUTCHAR(CI_AUTHTYPE, nakp);
+			if (ao->neg_chap) {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+				PUTCHAR(CILEN_CHAP, nakp);
+				PUTSHORT(PPP_CHAP, nakp);
+				PUTCHAR(ao->chap_mdtype, nakp);
+			} 
+			else {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_PAP, nakp);
+			}
+			break;
+		
+		case CI_QUALITY:
+			GETSHORT(cishort, p);
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			if (!ao->neg_lqr ||
+					cilen != CILEN_LQR) {
+				orc = CONFREJ;
+				break;
+			}
+			
+			/*
+			 * Check the protocol and the reporting period.
+			 * XXX When should we Nak this, and what with?
+			 */
+			if (cishort != PPP_LQR) {
+				orc = CONFNAK;
+				PUTCHAR(CI_QUALITY, nakp);
+				PUTCHAR(CILEN_LQR, nakp);
+				PUTSHORT(PPP_LQR, nakp);
+				PUTLONG(ao->lqr_period, nakp);
+				break;
+			}
+			break;
+		
+		case CI_MAGICNUMBER:
+			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+					cilen != CILEN_LONG) {
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " MAGICNUMBER (%lX)", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			/*
+			 * He must have a different magic number.
+			 */
+			if (go->neg_magicnumber &&
+					cilong == go->magicnumber) {
+				cilong = magic();	/* Don't put magic() inside macro! */
+				orc = CONFNAK;
+				PUTCHAR(CI_MAGICNUMBER, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(cilong, nakp);
+				break;
+			}
+			ho->neg_magicnumber = 1;
+			ho->magicnumber = cilong;
+			break;
+		
+		
+		case CI_PCOMPRESSION:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " PCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_pcompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_pcompression = 1;
+			break;
+		
+		case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " ACCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_accompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_accompression = 1;
+			break;
+		
+		case CI_MRRU:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_MRRU");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_SSNHF:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_SSNHF");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_EPDISC:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_EPDISC");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		default:
+#if TRACELCP
+			sprintf(&traceBuf[traceNdx], " unknown %d", citype);
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		}
+		
+	endswitch:
+#if TRACELCP
+		if (traceNdx >= 80 - 32) {
+			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+			traceNdx = 0;
+		}
+#endif
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;			/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
+					&& citype != CI_MAGICNUMBER) {
+				orc = CONFREJ;		/* Get tough if so */
+			} 
+			else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				rc = CONFNAK;
+			}
+		}
+		if (orc == CONFREJ) {		/* Reject this CI */
+			rc = CONFREJ;
+			if (cip != rejp)		/* Need to move rejected CI? */
+				BCOPY(cip, rejp, cilen); /* Move it */
+			INCPTR(cilen, rejp);	/* Update output pointer */
+		}
+	}
+	
+	/*
+	 * If we wanted to send additional NAKs (for unsent CIs), the
+	 * code would go here.  The extra NAKs would go at *nakp.
+	 * At present there are no cases where we want to ask the
+	 * peer to negotiate an option.
+	 */
+	
+	switch (rc) {
+	case CONFACK:
+		*lenp = (int)(next - inp);
+		break;
+	case CONFNAK:
+		/*
+		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+		 */
+		*lenp = (int)(nakp - nak_buffer);
+		BCOPY(nak_buffer, inp, *lenp);
+		break;
+	case CONFREJ:
+		*lenp = (int)(rejp - inp);
+		break;
+	}
+	
+#if TRACELCP > 0
+	if (traceNdx > 0) {
+		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+	}
+#endif
+	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f)
+{
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	
+	if (!go->neg_magicnumber)
+		go->magicnumber = 0;
+	if (!ho->neg_magicnumber)
+		ho->magicnumber = 0;
+	
+	/*
+	* Set our MTU to the smaller of the MTU we wanted and
+	* the MRU our peer wanted.  If we negotiated an MRU,
+	* set our MRU to the larger of value we wanted and
+	* the value we got in the negotiation.
+	*/
+	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+				ho->neg_pcompression, ho->neg_accompression);
+	/*
+	* If the asyncmap hasn't been negotiated, we really should
+	* set the receive asyncmap to ffffffff, but we set it to 0
+	* for backwards contemptibility.
+	*/
+	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	
+	if (ho->neg_mru)
+		peer_mru[f->unit] = ho->mru;
+	
+	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
+	
+	link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	
+	lcp_echo_lowerdown(f->unit);
+	
+	link_down(f->unit);
+	
+	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(f->unit, PPP_MRU,
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f)
+{
+	link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f)
+{
+	link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void print_string(
+    char *p,
+    int len,
+    void (*printer) (void *, char *, ...),
+    void *arg
+)
+{
+    int c;
+    
+    printer(arg, "\"");
+    for (; len > 0; --len) {
+        c = *p++;
+        if (' ' <= c && c <= '~') {
+            if (c == '\\' || c == '"')
+                printer(arg, "\\");
+            printer(arg, "%c", c);
+        } else {
+            switch (c) {
+            case '\n':
+                printer(arg, "\\n");
+                break;
+            case '\r':
+                printer(arg, "\\r");
+                break;
+            case '\t':
+                printer(arg, "\\t");
+                break;
+            default:
+                printer(arg, "\\%.3o", c);
+            }
+        }
+    }
+    printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
+	"TermReq", "TermAck", "CodeRej", "ProtRej",
+	"EchoReq", "EchoRep", "DiscReq"
+};
+
+static int lcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len, olen;
+	u_char *pstart, *optend;
+	u_short cishort;
+	u32_t cilong;
+	
+	if (plen < HEADERLEN)
+		return 0;
+	pstart = p;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
+		printer(arg, " %s", lcp_codenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= HEADERLEN;
+	switch (code) {
+	case CONFREQ:
+	case CONFACK:
+	case CONFNAK:
+	case CONFREJ:
+		/* print option list */
+		while (len >= 2) {
+			GETCHAR(code, p);
+			GETCHAR(olen, p);
+			p -= 2;
+			if (olen < 2 || olen > len) {
+				break;
+			}
+			printer(arg, " <");
+			len -= olen;
+			optend = p + olen;
+			switch (code) {
+			case CI_MRU:
+				if (olen == CILEN_SHORT) {
+					p += 2;
+					GETSHORT(cishort, p);
+					printer(arg, "mru %d", cishort);
+				}
+				break;
+			case CI_ASYNCMAP:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "asyncmap 0x%lx", cilong);
+				}
+				break;
+			case CI_AUTHTYPE:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "auth ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_PAP:
+						printer(arg, "pap");
+						break;
+					case PPP_CHAP:
+						printer(arg, "chap");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_QUALITY:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "quality ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_LQR:
+						printer(arg, "lqr");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_CALLBACK:
+				if (olen >= CILEN_CHAR) {
+					p += 2;
+					printer(arg, "callback ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case CBCP_OPT:
+						printer(arg, "CBCP");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_MAGICNUMBER:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "magic 0x%x", cilong);
+				}
+				break;
+			case CI_PCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "pcomp");
+				}
+				break;
+			case CI_ACCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "accomp");
+				}
+				break;
+			}
+			while (p < optend) {
+				GETCHAR(code, p);
+				printer(arg, " %.2x", code);
+			}
+			printer(arg, ">");
+		}
+		break;
+	
+	case TERMACK:
+	case TERMREQ:
+		if (len > 0 && *p >= ' ' && *p < 0x7f) {
+			printer(arg, " ");
+			print_string((char*)p, len, printer, arg);
+			p += len;
+			len = 0;
+		}
+		break;
+	
+	case ECHOREQ:
+	case ECHOREP:
+	case DISCREQ:
+		if (len >= 4) {
+			GETLONG(cilong, p);
+			printer(arg, " magic=0x%x", cilong);
+			p += 4;
+			len -= 4;
+		}
+		break;
+	}
+	
+	/* print the rest of the bytes in the packet */
+	for (; len > 0; --len) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	}
+	
+	return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure (fsm *f)
+{
+	if (f->state == OPENED) {
+		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+		lcp_close(f->unit, "Peer not responding");
+	}
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck (fsm *f)
+{
+	LcpSendEchoRequest (f);
+	
+	/*
+	 * Start the timer for the next interval.
+	 */
+	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+	lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout (void *arg)
+{
+	if (lcp_echo_timer_running != 0) {
+		lcp_echo_timer_running = 0;
+		LcpEchoCheck ((fsm *) arg);
+	}
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+	u32_t magic;
+	
+	(void)id;
+
+	/* Check the magic number - don't count replies from ourselves. */
+	if (len < 4) {
+		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+		return;
+	}
+	GETLONG(magic, inp);
+	if (lcp_gotoptions[f->unit].neg_magicnumber
+			&& magic == lcp_gotoptions[f->unit].magicnumber) {
+		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+		return;
+	}
+	
+	/* Reset the number of outstanding echo frames */
+	lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest (fsm *f)
+{
+	u32_t lcp_magic;
+	u_char pkt[4], *pktp;
+	
+	/*
+	* Detect the failure of the peer at this point.
+	*/
+	if (lcp_echo_fails != 0) {
+		if (lcp_echos_pending++ >= lcp_echo_fails) {
+			LcpLinkFailure(f);
+			lcp_echos_pending = 0;
+		}
+	}
+	
+	/*
+	* Make and send the echo request frame.
+	*/
+	if (f->state == OPENED) {
+		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+		pktp = pkt;
+		PUTLONG(lcp_magic, pktp);
+		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+	}
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	/* Clear the parameters for generating echo frames */
+	lcp_echos_pending      = 0;
+	lcp_echo_number        = 0;
+	lcp_echo_timer_running = 0;
+	
+	/* If a timeout interval is specified then start the timer */
+	if (lcp_echo_interval != 0)
+		LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_echo_timer_running != 0) {
+		UNTIMEOUT (LcpEchoTimeout, f);
+		lcp_echo_timer_running = 0;
+	}
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
new file mode 100644
index 000000000..3876d39ae
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive : 1;			/* Don't die if we don't get a response */
+    u_int silent : 1;				/* Wait for the other end to start first */
+    u_int restart : 1;			/* Restart vs. exit after close */
+    u_int neg_mru : 1;			/* Negotiate the MRU? */
+    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
+    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
+    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
+    u_int neg_magicnumber : 1;	/* Ask for magic number? */
+    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
+    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
+    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
+    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
+#endif
+    u_short mru;			/* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;			/* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
+    u32_t asyncmap;			/* Value of async map */
+    u32_t magicnumber;
+    int numloops;				/* Number of loops during magic number neg. */
+    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;	/* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+	PHASE_DEAD = 0,
+	PHASE_INITIALIZE,
+	PHASE_ESTABLISH,
+	PHASE_AUTHENTICATE,
+	PHASE_CALLBACK,
+	PHASE_NETWORK,
+	PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init (int);
+void lcp_open (int);
+void lcp_close (int, char *);
+void lcp_lowerup (int);
+void lcp_lowerdown (int);
+void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+
+#endif /* LCP_H */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
new file mode 100644
index 000000000..427401691
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+	return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+    return avRandom();
+}
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
new file mode 100644
index 000000000..7574f32b9
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+void magicInit(void);   /* Initialize the magic number generator */
+u32_t magic(void);  /* Returns the next magic number */
+
+#endif /* MAGIC_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
new file mode 100644
index 000000000..e077cdea5
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
@@ -0,0 +1,306 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "ppp.h"
+#include "md5.h"
+#include "pppdebug.h"
+
+#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x)	x##UL
+#else
+#ifdef WIN32
+#define UL(x)	x##UL
+#else
+#define UL(x)	x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants.
+   */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
+    mdContext->i[1]++;
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4)
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+				(((u32_t)mdContext->in[ii+1]) << 8) |
+                ((u32_t)mdContext->in[ii]);
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4)
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8) |
+            ((u32_t)mdContext->in[ii]);
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
+	mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  memcpy(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
new file mode 100644
index 000000000..0e81cdc34
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];                                    /* scratch buffer */
+  unsigned char in[64];                              /* input buffer */
+  unsigned char digest[16];     /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init (MD5_CTX *mdContext);
+void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
new file mode 100644
index 000000000..23e438ff2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
@@ -0,0 +1,608 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "auth.h"
+#include "pap.h"
+#include "pppdebug.h"
+
+
+#if PAP_SUPPORT > 0
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init (int);
+static void upap_lowerup (int);
+static void upap_lowerdown (int);
+static void upap_input (int, u_char *, int);
+static void upap_protrej (int);
+
+static void upap_timeout (void *);
+static void upap_reqtimeout (void *);
+static void upap_rauthreq (upap_state *, u_char *, int, int);
+static void upap_rauthack (upap_state *, u_char *, int, int);
+static void upap_rauthnak (upap_state *, u_char *, int, int);
+static void upap_sauthreq (upap_state *);
+static void upap_sresp (upap_state *, u_char, u_char, char *, int);
+
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+    PPP_PAP,
+    upap_init,
+    upap_input,
+    upap_protrej,
+    upap_lowerup,
+    upap_lowerdown,
+    NULL,
+    NULL,
+#if 0
+    upap_printpkt,
+    NULL,
+#endif
+    1,
+    "PAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Save the username and password we're given */
+	u->us_user = luser;
+	u->us_userlen = strlen(luser);
+	u->us_passwd = lpassword;
+	u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(int unit, char *user, char *password)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+				unit, user, password, u->us_clientstate));
+	
+	upap_setloginpasswd(unit, user, password);
+
+	u->us_transmits = 0;
+	
+	/* Lower layer up yet? */
+	if (u->us_clientstate == UPAPCS_INITIAL ||
+			u->us_clientstate == UPAPCS_PENDING) {
+		u->us_clientstate = UPAPCS_PENDING;
+		return;
+	}
+	
+	upap_sauthreq(u);			/* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Lower layer up yet? */
+	if (u->us_serverstate == UPAPSS_INITIAL ||
+			u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_PENDING;
+		return;
+	}
+	
+	u->us_serverstate = UPAPSS_LISTEN;
+	if (u->us_reqtimeout > 0)
+		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(int unit)
+{
+	upap_state *u = &upap[unit];
+
+	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
+	u->us_unit = unit;
+	u->us_user = NULL;
+	u->us_userlen = 0;
+	u->us_passwd = NULL;
+	u->us_passwdlen = 0;
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+	u->us_id = 0;
+	u->us_timeouttime = UPAP_DEFTIMEOUT;
+	u->us_maxtransmits = 10;
+	u->us_reqtimeout = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+				u->us_unit, u->us_timeouttime, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ)
+		return;
+	
+	if (u->us_transmits >= u->us_maxtransmits) {
+		/* give up in disgust */
+		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+		u->us_clientstate = UPAPCS_BADAUTH;
+		auth_withpeer_fail(u->us_unit, PPP_PAP);
+		return;
+	}
+	
+	upap_sauthreq(u);		/* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	if (u->us_serverstate != UPAPSS_LISTEN)
+		return;			/* huh?? */
+	
+	auth_peer_fail(u->us_unit, PPP_PAP);
+	u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_INITIAL)
+		u->us_clientstate = UPAPCS_CLOSED;
+	else if (u->us_clientstate == UPAPCS_PENDING) {
+		upap_sauthreq(u);	/* send an auth-request */
+	}
+	
+	if (u->us_serverstate == UPAPSS_INITIAL)
+		u->us_serverstate = UPAPSS_CLOSED;
+	else if (u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_LISTEN;
+		if (u->us_reqtimeout > 0)
+			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+	}
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
+		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
+	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+	
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void upap_protrej(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+		auth_withpeer_fail(unit, PPP_PAP);
+	}
+	if (u->us_serverstate == UPAPSS_LISTEN) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+		auth_peer_fail(unit, PPP_PAP);
+	}
+	upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(int unit, u_char *inpacket, int l)
+{
+	upap_state *u = &upap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (l < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > l) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+		return;
+	}
+	len -= UPAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case UPAP_AUTHREQ:
+		upap_rauthreq(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHACK:
+		upap_rauthack(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHNAK:
+		upap_rauthnak(u, inp, id, len);
+		break;
+	
+	default:				/* XXX Need code reject */
+		break;
+	}
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(
+	upap_state *u, 
+	u_char *inp, 
+	int id,
+	int len
+)
+{
+	u_char ruserlen, rpasswdlen;
+	char *ruser, *rpasswd;
+	int retcode;
+	char *msg;
+	int msglen;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+	
+	if (u->us_serverstate < UPAPSS_LISTEN)
+		return;
+	
+	/*
+	 * If we receive a duplicate authenticate-request, we are
+	 * supposed to return the same status as for the first request.
+	 */
+	if (u->us_serverstate == UPAPSS_OPEN) {
+		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
+		return;
+	}
+	if (u->us_serverstate == UPAPSS_BADAUTH) {
+		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
+		return;
+	}
+	
+	/*
+	 * Parse user/passwd.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(ruserlen, inp);
+	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+	if (len < 0) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	ruser = (char *) inp;
+	INCPTR(ruserlen, inp);
+	GETCHAR(rpasswdlen, inp);
+	if (len < rpasswdlen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	rpasswd = (char *) inp;
+	
+	/*
+	 * Check the username and password given.
+	 */
+	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
+			   rpasswdlen, &msg, &msglen);
+	BZERO(rpasswd, rpasswdlen);
+	
+	upap_sresp(u, retcode, id, msg, msglen);
+	
+	if (retcode == UPAP_AUTHACK) {
+		u->us_serverstate = UPAPSS_OPEN;
+		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+	} else {
+		u->us_serverstate = UPAPSS_BADAUTH;
+		auth_peer_fail(u->us_unit, PPP_PAP);
+	}
+	
+	if (u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_OPEN;
+	
+	auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void upap_rauthnak(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_BADAUTH;
+	
+	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+	auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(upap_state *u)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+			+ u->us_userlen + u->us_passwdlen;
+	outp = outpacket_buf[u->us_unit];
+	
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(UPAP_AUTHREQ, outp);
+	PUTCHAR(++u->us_id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(u->us_userlen, outp);
+	BCOPY(u->us_user, outp, u->us_userlen);
+	INCPTR(u->us_userlen, outp);
+	PUTCHAR(u->us_passwdlen, outp);
+	BCOPY(u->us_passwd, outp, u->us_passwdlen);
+	
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+	
+	TIMEOUT(upap_timeout, u, u->us_timeouttime);
+	++u->us_transmits;
+	u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(
+	upap_state *u,
+	u_char code, 
+	u_char id,
+	char *msg,
+	int msglen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+	outp = outpacket_buf[u->us_unit];
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(msglen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
+				code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+#endif
+
+#endif /* PAP_SUPPORT */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
new file mode 100644
index 000000000..215c8a4f2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef PAP_H
+#define PAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN		4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN		4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+    int us_unit;			/* Interface unit number */
+    const char *us_user;	/* User */
+    int us_userlen;			/* User length */
+    const char *us_passwd;	/* Password */
+    int us_passwdlen;		/* Password length */
+    int us_clientstate;		/* Client state */
+    int us_serverstate;		/* Server state */
+    u_char us_id;			/* Current id */
+    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
+    int us_transmits;		/* Number of auth-reqs sent */
+    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
+    int us_reqtimeout;		/* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer (int, char *, char *);
+void upap_authpeer (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_H */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
new file mode 100644
index 000000000..df402189e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
@@ -0,0 +1,1623 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT > 0
+#include "pap.h"
+#endif
+#if CHAP_SUPPORT > 0
+#include "chap.h"
+#endif
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT > 0
+#include "vj.h"
+#endif
+
+#include "pppdebug.h"
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+    PDIDLE = 0,                 /* Idle state - waiting. */
+    PDSTART,                    /* Process start flag. */
+    PDADDRESS,                  /* Process address field. */
+    PDCONTROL,                  /* Process control field. */
+    PDPROTOCOL1,                /* Process protocol field 1. */
+    PDPROTOCOL2,                /* Process protocol field 2. */
+    PDDATA                      /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+    char openFlag;                      /* True when in use. */
+    char oldFrame;                      /* Old framing character for fd. */
+    sio_fd_t fd;                    /* File device ID of port. */
+    int  kill_link;                     /* Shut the link down. */
+    int  sig_hup;                       /* Carrier lost. */
+    int  if_up;                         /* True when the interface is up. */
+    int  errCode;                       /* Code indicating why interface is down. */
+    struct pbuf *inHead, *inTail;       /* The input packet. */
+    PPPDevStates inState;               /* The input process state. */
+    char inEscaped;                     /* Escape next character. */
+    u16_t inProtocol;                   /* The input protocol code. */
+    u16_t inFCS;                        /* Input Frame Check Sequence value. */
+    int  mtu;                           /* Peer's mru */
+    int  pcomp;                         /* Does peer accept protocol compression? */
+    int  accomp;                        /* Does peer accept addr/ctl compression? */
+    u_long lastXMit;                    /* Time of last transmission. */
+    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
+    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
+#if VJ_SUPPORT > 0
+    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
+    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
+#endif
+
+    struct netif netif;
+
+    struct ppp_addrs addrs;
+
+    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+    void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+    int     protocol;           /* PPP procotol, e.g. PPP_IP */
+    enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+    &lcp_protent,
+#if PAP_SUPPORT > 0
+    &pap_protent,
+#endif
+#if CHAP_SUPPORT > 0
+    &chap_protent,
+#endif
+#if CBCP_SUPPORT > 0
+    &cbcp_protent,
+#endif
+    &ipcp_protent,
+#if CCP_SUPPORT > 0
+    &ccp_protent,
+#endif
+    NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+    0x01,
+    0x02,
+    0x04,
+    0x08,
+    0x10,
+    0x20,
+    0x40,
+    0x80
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void pppInit(void)
+{
+    struct protent *protp;
+    int i, j;
+    
+	memset(&ppp_settings, 0, sizeof(ppp_settings));
+	ppp_settings.usepeerdns = 1;
+	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+	magicInit();
+
+    for (i = 0; i < NUM_PPP; i++) {
+        pppControl[i].openFlag = 0;
+
+		subnetMask = htonl(0xffffff00);
+    
+        /*
+         * Initialize to the standard option set.
+         */
+        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
+            (*protp->init)(i);
+    }
+
+#if LINK_STATS
+    /* Clear the statistics. */
+    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif
+}
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+    switch(authType) {
+	case PPPAUTHTYPE_NONE:
+	default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+	    ppp_settings.refuse_pap = 1;
+#else
+	    /* some providers request pap and accept an empty login/pw */
+	    ppp_settings.refuse_pap = 0;
+#endif
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_ANY:
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+	case PPPAUTHTYPE_PAP:
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_CHAP:
+	    ppp_settings.refuse_pap = 1;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+    }
+
+    if(user) {
+	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+    } else
+	ppp_settings.user[0] = '\0';
+
+    if(passwd) {
+	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+    } else
+	ppp_settings.passwd[0] = '\0';
+}
+
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+    PPPControl *pc;
+    int pd;
+
+    /* Find a free PPP session descriptor. Critical region? */
+    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+    if (pd >= NUM_PPP)
+        pd = PPPERR_OPEN;
+    else
+        pppControl[pd].openFlag = !0;
+
+    /* Launch a deamon thread. */
+    if (pd >= 0) {
+
+        pppControl[pd].openFlag = 1;
+
+        lcp_init(pd);
+        pc = &pppControl[pd];
+        pc->fd = fd;
+        pc->kill_link = 0;
+        pc->sig_hup = 0;
+        pc->if_up = 0;
+        pc->errCode = 0;
+        pc->inState = PDIDLE;
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+        pc->inEscaped = 0;
+        pc->lastXMit = 0;
+
+#if VJ_SUPPORT > 0
+        pc->vjEnabled = 0;
+        vj_compress_init(&pc->vjComp);
+#endif
+
+        /* 
+         * Default the in and out accm so that escape and flag characters
+         * are always escaped. 
+         */
+        memset(pc->inACCM, 0, sizeof(ext_accm));
+        pc->inACCM[15] = 0x60;
+        memset(pc->outACCM, 0, sizeof(ext_accm));
+        pc->outACCM[15] = 0x60;
+
+	pc->linkStatusCB = linkStatusCB;
+	pc->linkStatusCtx = linkStatusCtx;
+
+	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
+	if(!linkStatusCB) {
+		while(pd >= 0 && !pc->if_up) {
+			sys_msleep(500);
+			if (lcp_phase[pd] == PHASE_DEAD) {
+				pppClose(pd);
+				if (pc->errCode)
+					pd = pc->errCode;
+				else
+					pd = PPPERR_CONNECT;
+			}
+		}
+	}
+    }
+    return pd;
+}
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int pppClose(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    /* Disconnect */
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+    
+    if(!pc->linkStatusCB) {
+	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+		    sys_msleep(500);
+		    break;
+	    }
+    }
+    return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void pppSigHUP(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+}
+
+static void nPut(PPPControl *pc, struct pbuf *nb)
+{
+	struct pbuf *b;
+	int c;
+
+	for(b = nb; b != NULL; b = b->next) {
+	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+		PPPDEBUG((LOG_WARNING,
+			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+#if LINK_STATS
+		lwip_stats.link.err++;
+#endif /* LINK_STATS */
+		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+		break;
+	    }
+	}
+	pbuf_free(nb);
+
+#if LINK_STATS
+	lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+    struct pbuf *tb = nb;
+    
+    /* Make sure there is room for the character and an escape code.
+     * Sure we don't quite fill the buffer if the character doesn't
+     * get escaped but is one character worth complicating this? */
+    /* Note: We assume no packet header. */
+    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+	if (tb) {
+	    nb->next = tb;
+        }
+#if LINK_STATS
+	else {
+	    lwip_stats.link.memerr++;
+	}
+#endif /* LINK_STATS */
+	nb = tb;
+    }
+    if (nb) {
+	if (outACCM && ESCAPE_P(*outACCM, c)) {
+            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+        }
+        else
+            *((u_char*)nb->payload + nb->len++) = c;
+    }
+        
+    return tb;
+}
+
+/* Send a packet on the given connection. */
+static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+    int pd = (int)netif->state;
+    u_short protocol = PPP_IP;
+    PPPControl *pc = &pppControl[pd];
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+    u_char c;
+
+    (void)ipaddr;
+
+    /* Validate parameters. */
+    /* We let any protocol value go through - it can't hurt us
+     * and the peer will just drop it if it's not accepting it. */
+	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+                    pd, protocol, pb));
+#if LINK_STATS
+		lwip_stats.link.opterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_ARG;
+	}
+
+    /* Check that the link is up. */
+	if (lcp_phase[pd] == PHASE_DEAD) {
+        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+#if LINK_STATS
+		lwip_stats.link.rterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_RTE;
+	}
+
+    /* Grab an output buffer. */
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+        return ERR_MEM;
+    }
+        
+#if VJ_SUPPORT > 0
+    /* 
+     * Attempt Van Jacobson header compression if VJ is configured and
+     * this is an IP packet. 
+     */
+    if (protocol == PPP_IP && pc->vjEnabled) {
+        switch (vj_compress_tcp(&pc->vjComp, pb)) {
+        case TYPE_IP:
+            /* No change...
+            protocol = PPP_IP_PROTOCOL;
+             */
+            break;
+        case TYPE_COMPRESSED_TCP:
+            protocol = PPP_VJC_COMP;
+            break;
+        case TYPE_UNCOMPRESSED_TCP:
+            protocol = PPP_VJC_UNCOMP;
+            break;
+        default:
+            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+#if LINK_STATS
+			lwip_stats.link.proterr++;
+			lwip_stats.link.drop++;
+#endif
+        	pbuf_free(headMB);
+            return ERR_VAL;
+        }
+    }
+#endif
+        
+    tailMB = headMB;
+        
+    /* Build the PPP header. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+    if (!pc->accomp) {
+        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+        fcsOut = PPP_FCS(fcsOut, PPP_UI);
+        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+    }
+    if (!pc->pcomp || protocol > 0xFF) {
+        c = (protocol >> 8) & 0xFF;
+        fcsOut = PPP_FCS(fcsOut, c);
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    c = protocol & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    
+    /* Load packet. */
+	for(p = pb; p; p = p->next) {
+    	int n;
+    	u_char *sPtr;
+
+        sPtr = (u_char*)p->payload;
+        n = p->len;
+        while (n-- > 0) {
+            c = *sPtr++;
+            
+            /* Update FCS before checking for special characters. */
+            fcsOut = PPP_FCS(fcsOut, c);
+            
+            /* Copy to output buffer escaping special characters. */
+            tailMB = pppAppend(c, tailMB, &pc->outACCM);
+        }
+    }
+
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away. */
+    if (!tailMB) {
+        PPPDEBUG((LOG_WARNING,
+                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+                    pd, protocol));
+        pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif
+        return ERR_MEM;
+    }
+
+	/* Send it. */
+    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+    nPut(pc, headMB);
+
+    return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int  pppIOCtl(int pd, int cmd, void *arg)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    if (pd < 0 || pd >= NUM_PPP)
+        st = PPPERR_PARAM;
+    else {
+        switch(cmd) {
+        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+            if (arg) 
+                *(int *)arg = (int)(pc->if_up);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+            if (arg) 
+                pc->errCode = *(int *)arg;
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+            if (arg) 
+                *(int *)arg = (int)(pc->errCode);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_FD:
+            if (arg) 
+                *(sio_fd_t *)arg = pc->fd;
+            else
+                st = PPPERR_PARAM;
+            break;
+        default:
+            st = PPPERR_PARAM;
+            break;
+        }
+    }
+    
+    return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_int st;
+    
+    /* Validate parameters. */
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
+        st = 0;
+    else
+        st = pc->mtu;
+        
+    return st;
+}
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_char c;
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB;
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+    }
+
+    tailMB = headMB;
+        
+    /* If the link has been idle, we'll send a fresh flag character to
+     * flush any noise. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+     
+    /* Load output buffer. */
+    while (n-- > 0) {
+        c = *s++;
+        
+        /* Update FCS before checking for special characters. */
+        fcsOut = PPP_FCS(fcsOut, c);
+        
+        /* Copy to output buffer escaping special characters. */
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away.
+     * Otherwise send it. */
+    if (!tailMB) {
+		PPPDEBUG((LOG_WARNING,
+                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+		pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+	}
+
+    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    nPut(pc, headMB);
+
+    return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void ppp_send_config(
+    int unit, 
+    int mtu,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+    pc->mtu = mtu;
+    pc->pcomp = pcomp;
+    pc->accomp = accomp;
+    
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32/8; i++)
+        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void ppp_set_xaccm(int unit, ext_accm *accm)
+{
+    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pppControl[unit].outACCM[0],
+                pppControl[unit].outACCM[1],
+                pppControl[unit].outACCM[2],
+                pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void ppp_recv_config(
+    int unit, 
+    int mru,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+	(void)accomp;
+	(void)pcomp;
+	(void)mru;
+
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32 / 8; i++)
+        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+                unit,
+                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int ccp_test(
+    int unit, 
+    int opt_len, 
+    int for_transmit,
+    u_char *opt_ptr
+)
+{
+    return 0;   /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void ccp_flags_set(int unit, int isopen, int isup)
+{
+    /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int ccp_fatal_error(int unit)
+{
+    /* XXX */
+    return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(int u, struct ppp_idle *ip)
+{   
+    /* XXX */
+	(void)u;
+	(void)ip;
+
+    return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t GetMask(u32_t addr)
+{
+    u32_t mask, nmask;
+    
+    htonl(addr);
+    if (IN_CLASSA(addr))    /* determine network mask for address class */
+        nmask = IN_CLASSA_NET;
+    else if (IN_CLASSB(addr))
+        nmask = IN_CLASSB_NET;
+    else
+        nmask = IN_CLASSC_NET;
+    /* class D nets are disallowed by bad_ip_adrs */
+    mask = subnetMask | htonl(nmask);
+    
+    /* XXX
+     * Scan through the system's network interfaces.
+     * Get each netmask and OR them into our mask.
+     */
+    
+    return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(
+    int pd, 
+    int vjcomp, 
+    int cidcomp, 
+    int maxcid
+)
+{
+#if VJ_SUPPORT > 0
+    PPPControl *pc = &pppControl[pd];
+    
+    pc->vjEnabled = vjcomp;
+    pc->vjComp.compressSlot = cidcomp;
+    pc->vjComp.maxSlotIndex = maxcid;
+    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+                vjcomp, cidcomp, maxcid));
+#endif
+
+    return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t pppifNetifInit(struct netif *netif)
+{
+	netif->name[0] = 'p';
+	netif->name[1] = 'p';
+	netif->output = pppifOutput;
+	netif->mtu = pppMTU((int)netif->state);
+	return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_remove(&pc->netif);
+		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+        		pc->if_up = 1;
+        		pc->errCode = PPPERR_NONE;
+
+			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+			if(pc->linkStatusCB)
+				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+		} else {
+        	st = 0;
+        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+		}
+    }
+
+    return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(int u, int proto, enum NPmode mode)
+{
+	(void)u;
+	(void)proto;
+	(void)mode;
+    return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int sifdown(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+    } else {
+        pc->if_up = 0;
+	netif_remove(&pc->netif);
+	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+	if(pc->linkStatusCB)
+		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+	}
+    return st;
+}
+
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(
+    int pd,             /* Interface unit ??? */
+    u32_t o,        /* Our IP address ??? */
+    u32_t h,        /* His IP address ??? */
+    u32_t m,        /* IP subnet mask ??? */
+    u32_t ns1,      /* Primary DNS */
+    u32_t ns2       /* Secondary DNS */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
+		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
+		memcpy(&pc->addrs.netmask, &m, sizeof(m));
+		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
+		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
+    }
+    return st;
+}
+
+/*
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(
+    int pd,         /* Interface unit ??? */
+    u32_t o,    /* Our IP address ??? */
+    u32_t h     /* IP broadcast address ??? */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)o;
+	(void)h;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+    }
+    return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(&pc->netif);
+    }
+
+    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+    return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(NULL);
+    }
+
+    return st;
+}
+
+void
+pppMainWakeup(int pd)
+{
+	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+	sio_read_abort(pppControl[pd].fd);
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+    lcp_lowerup(pd);
+    lcp_open(pd);      /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+    lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+    lcp_lowerdown(pd);
+    link_terminated(pd);
+}
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void pppMain(void *arg)
+{
+    int pd = (int)arg;
+    struct pbuf *p;
+    PPPControl* pc;
+
+    pc = &pppControl[pd];
+
+    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+    if(!p) {
+		LWIP_ASSERT("p != NULL", p);
+		pc->errCode = PPPERR_ALLOC;
+		goto out;
+    }
+
+    /*
+     * Start the connection and handle incoming events (packet or timeout).
+     */
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, arg);
+    while (lcp_phase[pd] != PHASE_DEAD) {
+        if (pc->kill_link) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
+		pc->errCode = PPPERR_USER;
+		/* This will leave us at PHASE_DEAD. */
+    		tcpip_callback(pppStopCB, arg);
+		pc->kill_link = 0;
+        }
+        else if (pc->sig_hup) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
+		pc->sig_hup = 0;
+    		tcpip_callback(pppHupCB, arg);
+        } else {
+		int c = sio_read(pc->fd, p->payload, p->len);
+		if(c > 0) {
+			pppInProc(pd, p->payload, c);
+		} else {
+		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+		    sys_msleep(1); /* give other tasks a chance to run */
+		}
+        }
+    }
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+    pbuf_free(p);
+
+out:
+	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB)
+	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+
+    pc->openFlag = 0;
+}
+
+static struct pbuf *pppSingleBuf(struct pbuf *p)
+{
+	struct pbuf *q, *b;
+	u_char *pl;
+
+	if(p->tot_len == p->len)
+		return p;
+
+	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+	if(!q) {
+		PPPDEBUG((LOG_ERR,
+                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+		return p; /* live dangerously */
+	}
+
+	for(b = p, pl = q->payload; b != NULL; b = b->next) {
+		memcpy(pl, b->payload, b->len);
+		pl += b->len;
+	}
+
+	pbuf_free(p);
+
+	return q;
+}
+
+struct pppInputHeader {
+	int unit;
+	u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void pppInput(void *arg)
+{
+	struct pbuf *nb = (struct pbuf *)arg;
+    u16_t protocol;
+    int pd;
+
+	pd = ((struct pppInputHeader *)nb->payload)->unit;
+	protocol = ((struct pppInputHeader *)nb->payload)->proto;
+
+    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+    /*
+     * Toss all non-LCP packets unless LCP is OPEN.
+     * Until we get past the authentication phase, toss all packets
+     * except LCP, LQR and authentication packets.
+     */
+    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+		goto drop;
+	    }
+    }
+
+    switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+         * pass the result to IP.
+         */
+        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Process the TCP/IP header for VJ header compression and then pass
+         * the packet to IP.
+         */
+        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO,
+                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_IP:            /* Internet Protocol */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+		return;
+    default:
+	{
+		struct protent *protp;
+		int i;
+
+		/*
+		 * Upcall the proper protocol input routine.
+		 */
+		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+			if (protp->protocol == protocol && protp->enabled_flag) {
+				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+				nb = pppSingleBuf(nb);
+				(*protp->input)(pd, nb->payload, nb->len);
+				goto out;
+			}
+		}
+
+		/* No handler for this protocol so reject the packet. */
+		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+		pbuf_header(nb, sizeof(protocol));
+#if BYTE_ORDER == LITTLE_ENDIAN
+		protocol = htons(protocol);
+		memcpy(nb->payload, &protocol, sizeof(protocol));
+#endif
+		lcp_sprotrej(pd, nb->payload, nb->len);
+	}
+	break;
+    }
+
+drop:
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif
+
+out:
+    pbuf_free(nb);
+    return;
+}
+
+
+/*
+ * Drop the input packet.
+ */
+static void pppDrop(PPPControl *pc)
+{
+    if (pc->inHead != NULL) {
+#if 0	    
+        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif	
+        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+	if (pc->inTail && (pc->inTail != pc->inHead))
+	    pbuf_free(pc->inTail);
+        pbuf_free(pc->inHead);
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+    }
+#if VJ_SUPPORT > 0
+    vj_uncompress_err(&pc->vjComp);
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+}
+
+
+/*
+ * Process a received octet string.
+ */
+static void pppInProc(int pd, u_char *s, int l)
+{
+    PPPControl *pc = &pppControl[pd];
+    struct pbuf *nextNBuf;
+    u_char curChar;
+
+    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+    while (l-- > 0) {
+        curChar = *s++;
+        
+        /* Handle special characters. */
+        if (ESCAPE_P(pc->inACCM, curChar)) {
+            /* Check for escape sequences. */
+            /* XXX Note that this does not handle an escaped 0x5d character which
+             * would appear as an escape character.  Since this is an ASCII ']'
+             * and there is no reason that I know of to escape it, I won't complicate
+             * the code to handle this case. GLL */
+            if (curChar == PPP_ESCAPE)
+                pc->inEscaped = 1;
+            /* Check for the flag character. */
+            else if (curChar == PPP_FLAG) {
+                /* If this is just an extra flag character, ignore it. */
+                if (pc->inState <= PDADDRESS)
+                    ;
+                /* If we haven't received the packet header, drop what has come in. */
+                else if (pc->inState < PDDATA) {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                                pd, pc->inState));
+#if LINK_STATS
+					lwip_stats.link.lenerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* If the fcs is invalid, drop the packet. */
+                else if (pc->inFCS != PPP_GOODFCS) {
+                    PPPDEBUG((LOG_INFO,
+                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                                pd, pc->inFCS, pc->inProtocol));
+#if LINK_STATS
+					lwip_stats.link.chkerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* Otherwise it's a good packet so pass it on. */
+                else {
+                    
+                    /* Trim off the checksum. */
+		    if(pc->inTail->len >= 2) {
+			pc->inTail->len -= 2;
+
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    } else {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+
+			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+		    }
+
+                    /* Dispatch the packet thereby consuming it. */
+		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+                    	PPPDEBUG((LOG_ERR,
+				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+			pbuf_free(pc->inHead);
+#if LINK_STATS
+			lwip_stats.link.drop++;
+#endif
+		    }
+                    pc->inHead = NULL;
+                    pc->inTail = NULL;
+                }
+                    
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+                pc->inState = PDADDRESS;
+                pc->inEscaped = 0;
+            }
+            /* Other characters are usually control characters that may have
+             * been inserted by the physical layer so here we just drop them. */
+            else {
+                PPPDEBUG((LOG_WARNING,
+                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+            }
+        }
+        /* Process other characters. */
+        else {
+            /* Unencode escaped characters. */
+            if (pc->inEscaped) {
+                pc->inEscaped = 0;
+                curChar ^= PPP_TRANS;
+            }
+            
+            /* Process character relative to current state. */
+            switch(pc->inState) {
+            case PDIDLE:                    /* Idle state - waiting. */
+                /* Drop the character if it's not 0xff
+                 * we would have processed a flag character above. */
+                if (curChar != PPP_ALLSTATIONS) {
+                	break;
+				}
+
+				/* Fall through */
+            case PDSTART:                   /* Process start flag. */
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+
+				/* Fall through */
+            case PDADDRESS:                 /* Process address field. */
+                if (curChar == PPP_ALLSTATIONS) {
+                    pc->inState = PDCONTROL;
+                    break;
+                }
+                /* Else assume compressed address and control fields so
+                 * fall through to get the protocol... */
+            case PDCONTROL:                 /* Process control field. */
+                /* If we don't get a valid control code, restart. */
+                if (curChar == PPP_UI) {
+                    pc->inState = PDPROTOCOL1;
+                	break;
+                }
+#if 0
+                else {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                    pc->inState = PDSTART;
+                }
+#endif
+            case PDPROTOCOL1:               /* Process protocol field 1. */
+                /* If the lower bit is set, this is the end of the protocol
+                 * field. */
+                if (curChar & 1) {
+                    pc->inProtocol = curChar;
+                    pc->inState = PDDATA;
+                }
+                else {
+                    pc->inProtocol = (u_int)curChar << 8;
+                    pc->inState = PDPROTOCOL2;
+                }
+                break;
+            case PDPROTOCOL2:               /* Process protocol field 2. */
+                pc->inProtocol |= curChar;
+                pc->inState = PDDATA;
+                break;
+            case PDDATA:                    /* Process data byte. */
+                /* Make space to receive processed data. */
+                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+		    if(pc->inTail) {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    }
+                    /* If we haven't started a packet, we need a packet header. */
+                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+                    if (nextNBuf == NULL) {
+                        /* No free buffers.  Drop the input packet and let the
+                         * higher layers deal with it.  Continue processing
+                         * the received pbuf chain in case a new packet starts. */
+                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+#if LINK_STATS
+						lwip_stats.link.memerr++;
+#endif /* LINK_STATS */
+                        pppDrop(pc);
+                        pc->inState = PDSTART;  /* Wait for flag sequence. */
+			break;
+                    }
+		    if (pc->inHead == NULL) {
+			struct pppInputHeader *pih = nextNBuf->payload;
+
+			pih->unit = pd;
+			pih->proto = pc->inProtocol;
+
+			nextNBuf->len += sizeof(*pih);
+
+			pc->inHead = nextNBuf;
+		    }
+		    pc->inTail = nextNBuf;
+                }
+                /* Load character into buffer. */
+                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+                break;
+            }
+
+            /* update the frame check sequence number. */
+            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+        }
+    }
+	avRandomize();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
new file mode 100644
index 000000000..dbe12171e
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT > 0
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+# ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN  4       /* octets for standard ppp header */
+#define PPP_FCSLEN  2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS 0xffff  /* Initial FCS value */
+#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,        /* pass the packet through */
+    NPMODE_DROP,        /* silently drop the packet */
+    NPMODE_ERROR,       /* return an error */
+    NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp)++ << 8; \
+    (s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp)++ << 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      memcpy((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else
+#define PRINTMSG(m, l)
+#endif
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE 0				/* No error. */
+#define PPPERR_PARAM -1				/* Invalid parameter. */
+#define PPPERR_OPEN -2				/* Unable to open PPP session. */
+#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
+#define PPPERR_USER -5				/* User interrupt. */
+#define PPPERR_CONNECT -6			/* Connection lost. */
+#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE 101		/* Set the error code */
+#define PPPCTLG_ERRCODE 102		/* Get the error code */
+#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    u_short xmit_idle;      /* seconds since last NP packet sent */
+    u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
+	u_int  auth_required : 1;      /* Peer is required to authenticate */
+	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
+	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
+	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
+	u_int  usehostname : 1;        /* Use hostname for our_name */
+	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
+
+	u_short idle_time_limit; /* Shut down link if idle for this long */
+	int  maxconnect;         /* Maximum connect time (seconds) */
+
+	char user[MAXNAMELEN + 1];/* Username for PAP */
+	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
+	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
+	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ *	RETURN: >= 0 Number of characters written
+ *		 	 -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);		
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);	
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
new file mode 100644
index 000000000..de1478cee
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+	LOG_CRITICAL = 0,
+	LOG_ERR = 1,
+	LOG_NOTICE = 2,
+	LOG_WARNING = 3,
+	LOG_INFO = 5,
+	LOG_DETAIL = 6,
+	LOG_DEBUG = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ *	ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#if PPP_DEBUG > 0
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a) ppp_trace a
+#define FSMDEBUG(a) ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a) ppp_trace a
+
+#define TRACELCP 1
+
+#else
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+
+#define PPPDEBUG(a)
+
+#define TRACELCP 0
+
+#endif
+
+#endif /* PPPDEBUG_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
new file mode 100644
index 000000000..05eeb4410
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "md5.h"
+#include "randm.h"
+
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT>0   /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void avRandomInit()
+{
+    avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void avChurnRand(char *randData, u32_t randLen)
+{
+    MD5_CTX md5;
+
+/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    if (randData)
+        MD5Update(&md5, (u_char *)randData, randLen);
+    else {
+        struct {
+            /* INCLUDE fields for any system sources of randomness */
+            char foobar;
+        } sysData;
+
+        /* Load sysData fields here. */
+        ;
+        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+    }
+    MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void avGenRand(char *buf, u32_t bufLen)
+{
+    MD5_CTX md5;
+    u_char tmp[16];
+    u32_t n;
+
+    while (bufLen > 0) {
+        n = LWIP_MIN(bufLen, RANDPOOLSZ);
+        MD5Init(&md5);
+        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+        MD5Final(tmp, &md5);
+        randCount++;
+        memcpy(buf, tmp, n);
+        buf += n;
+        bufLen -= n;
+    }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom()
+{
+    u32_t newRand;
+
+    avGenRand((char *)&newRand, sizeof(newRand));
+
+    return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void avRandomInit()
+{
+#if 0
+    /* Get a pointer into the last 4 bytes of clockBuf. */
+    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+    /*
+     * Initialize our seed using the real-time clock, the idle
+     * counter, the millisecond timer, and the hardware timer
+     * tick counter.  The real-time clock and the hardware
+     * tick counter are the best sources of randomness but
+     * since the tick counter is only 16 bit (and truncated
+     * at that), the idle counter and millisecond timer
+     * (which may be small values) are added to help
+     * randomize the lower 16 bits of the seed.
+     */
+    readClk();
+    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+    avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+        
+    /* Initialize the Borland random number generator. */
+    srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void avRandomize(void)
+{
+    static u32_t last_jiffies;
+
+    if (!avRandomized) {
+        avRandomized = !0;
+        avRandomInit();
+        /* The initialization function also updates the seed. */
+    } else {
+/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
+    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+    }
+    last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t avRandom()
+{
+    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+
+
+#endif /* MD5_SUPPORT */
+#endif /* PPP_SUPPORT */
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
new file mode 100644
index 000000000..baa42f0c2
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*	Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *	on random and semi-random system events to build randomness in time for
+ *	usage.  For randomly timed events, pass a null pointer and a zero length
+ *	and this will use the system timer and other sources to add randomness.
+ *	If new random data is available, pass a pointer to that and it will be
+ *	included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize()	avChurnRand(NULL, 0)
+#else
+void avRandomize(void);
+#endif
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *	random when used faster than randomness is supplied using churnRand().
+ *	Thus it's important to make sure that the results of this are not
+ *	published directly because one could predict the next result to at
+ *	least some degree.  Also, it's important to get a good seed before
+ *	the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
new file mode 100644
index 000000000..0636ee11b
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
@@ -0,0 +1,633 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include 
+
+#include "ppp.h"
+#include "vj.h"
+#include "pppdebug.h"
+
+#if VJ_SUPPORT > 0
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)	((base).ip_hl_v&0xf)
+#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)	((base).ip_hl)
+#define getth_off(base)	((base).th_off)
+#endif
+
+void vj_compress_init(struct vjcompress *comp)
+{
+	register u_int i;
+	register struct cstate *tstate = comp->tstate;
+	
+#if MAX_SLOTS == 0
+	memset((char *)comp, 0, sizeof(*comp));
+#endif
+	comp->maxSlotIndex = MAX_SLOTS - 1;
+	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
+	for (i = MAX_SLOTS - 1; i > 0; --i) {
+		tstate[i].cs_id = i;
+		tstate[i].cs_next = &tstate[i - 1];
+	}
+	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+	tstate[0].cs_id = 0;
+	comp->last_cs = &tstate[0];
+	comp->last_recv = 255;
+	comp->last_xmit = 255;
+	comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+	if ((u_short)(n) >= 256) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+#define ENCODEZ(n) { \
+	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+
+#define DECODEL(f) { \
+	if (*cp == 0) {\
+		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+		(f) = htonl(tmp); \
+		cp += 3; \
+	} else { \
+		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+		(f) = htonl(tmp); \
+	} \
+}
+
+#define DECODES(f) { \
+	if (*cp == 0) {\
+		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+		(f) = htons(tmp); \
+		cp += 3; \
+	} else { \
+		u_short tmp = ntohs(f) + (u_short)*cp++; \
+		(f) = htons(tmp); \
+	} \
+}
+
+#define DECODEU(f) { \
+	if (*cp == 0) {\
+		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+		cp += 3; \
+	} else { \
+		(f) = htons((u_short)*cp++); \
+	} \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int vj_compress_tcp(
+	struct vjcompress *comp,
+	struct pbuf *pb
+)
+{
+	register struct ip *ip = (struct ip *)pb->payload;
+	register struct cstate *cs = comp->last_cs->cs_next;
+	register u_short hlen = getip_hl(*ip);
+	register struct tcphdr *oth;
+	register struct tcphdr *th;
+	register u_short deltaS, deltaA;
+	register u_long deltaL;
+	register u_int changes = 0;
+	u_char new_seq[16];
+	register u_char *cp = new_seq;
+
+	/*	
+	 * Check that the packet is IP proto TCP.
+	 */
+	if (ip->ip_p != IPPROTO_TCP)
+		return (TYPE_IP);
+		
+	/*
+	 * Bail if this is an IP fragment or if the TCP packet isn't
+	 * `compressible' (i.e., ACK isn't set or some other control bit is
+	 * set).  
+	 */
+	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
+		return (TYPE_IP);
+	th = (struct tcphdr *)&((long *)ip)[hlen];
+	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
+		return (TYPE_IP);
+		
+	/*
+	 * Packet is compressible -- we're going to send either a
+	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+	 * to locate (or create) the connection state.  Special case the
+	 * most recently used connection since it's most likely to be used
+	 * again & we don't have to do any reordering if it's used.
+	 */
+	INCR(vjs_packets);
+	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+		/*
+		 * Wasn't the first -- search for it.
+		 *
+		 * States are kept in a circularly linked list with
+		 * last_cs pointing to the end of the list.  The
+		 * list is kept in lru order by moving a state to the
+		 * head of the list whenever it is referenced.  Since
+		 * the list is short and, empirically, the connection
+		 * we want is almost always near the front, we locate
+		 * states via linear search.  If we don't find a state
+		 * for the datagram, the oldest state is (re-)used.
+		 */
+		register struct cstate *lcs;
+		register struct cstate *lastcs = comp->last_cs;
+		
+		do {
+			lcs = cs; cs = cs->cs_next;
+			INCR(vjs_searches);
+			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
+				goto found;
+		} while (cs != lastcs);
+		
+		/*
+		 * Didn't find it -- re-use oldest cstate.  Send an
+		 * uncompressed packet that tells the other side what
+		 * connection number we're using for this conversation.
+		 * Note that since the state list is circular, the oldest
+		 * state points to the newest and we only need to set
+		 * last_cs to update the lru linkage.
+		 */
+		INCR(vjs_misses);
+		comp->last_cs = lcs;
+		hlen += getth_off(*th);
+		hlen <<= 2;
+		/* Check that the IP/TCP headers are contained in the first buffer. */
+		if (hlen > pb->len)
+			return (TYPE_IP);
+		goto uncompressed;
+		
+		found:
+		/*
+		 * Found it -- move to the front on the connection list.
+		 */
+		if (cs == lastcs)
+			comp->last_cs = lcs;
+		else {
+			lcs->cs_next = cs->cs_next;
+			cs->cs_next = lastcs->cs_next;
+			lastcs->cs_next = cs;
+		}
+	}
+	
+	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+	deltaS = hlen;
+	hlen += getth_off(*th);
+	hlen <<= 2;
+	/* Check that the IP/TCP headers are contained in the first buffer. */
+	if (hlen > pb->len) {
+		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
+					hlen));
+		return (TYPE_IP);
+	}
+	
+	/*
+	 * Make sure that only what we expect to change changed. The first
+	 * line of the `if' checks the IP protocol version, header length &
+	 * type of service.  The 2nd line checks the "Don't fragment" bit.
+	 * The 3rd line checks the time-to-live and protocol (the protocol
+	 * check is unnecessary but costless).  The 4th line checks the TCP
+	 * header length.  The 5th line checks IP options, if any.  The 6th
+	 * line checks TCP options, if any.  If any of these things are
+	 * different between the previous & current datagram, we send the
+	 * current datagram `uncompressed'.
+	 */
+	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+			|| getth_off(*th) != getth_off(*oth) 
+			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
+		goto uncompressed;
+	
+	/*
+	 * Figure out which of the changing fields changed.  The
+	 * receiver expects changes in the order: urgent, window,
+	 * ack, seq (the order minimizes the number of temporaries
+	 * needed in this section of code).
+	 */
+	if (th->th_flags & TCP_URG) {
+		deltaS = ntohs(th->th_urp);
+		ENCODEZ(deltaS);
+		changes |= NEW_U;
+	} else if (th->th_urp != oth->th_urp)
+		/* argh! URG not set but urp changed -- a sensible
+		 * implementation should never do this but RFC793
+		 * doesn't prohibit the change so we have to deal
+		 * with it. */
+		goto uncompressed;
+	
+	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+		ENCODE(deltaS);
+		changes |= NEW_W;
+	}
+	
+	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaA = (u_short)deltaL;
+		ENCODE(deltaA);
+		changes |= NEW_A;
+	}
+	
+	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaS = (u_short)deltaL;
+		ENCODE(deltaS);
+		changes |= NEW_S;
+	}
+	
+	switch(changes) {
+	
+	case 0:
+		/*
+		 * Nothing changed. If this packet contains data and the
+		 * last one didn't, this is probably a data packet following
+		 * an ack (normal on an interactive connection) and we send
+		 * it compressed.  Otherwise it's probably a retransmit,
+		 * retransmitted ack or window probe.  Send it uncompressed
+		 * in case the other side missed the compressed version.
+		 */
+		if (ip->ip_len != cs->cs_ip.ip_len &&
+			ntohs(cs->cs_ip.ip_len) == hlen)
+		break;
+	
+	/* (fall through) */
+	
+	case SPECIAL_I:
+	case SPECIAL_D:
+		/*
+		 * actual changes match one of our special case encodings --
+		 * send packet uncompressed.
+		 */
+		goto uncompressed;
+	
+	case NEW_S|NEW_A:
+		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for echoed terminal traffic */
+			changes = SPECIAL_I;
+			cp = new_seq;
+		}
+		break;
+	
+	case NEW_S:
+		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for data xfer */
+			changes = SPECIAL_D;
+			cp = new_seq;
+		}
+		break;
+	}
+	
+	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+	if (deltaS != 1) {
+		ENCODEZ(deltaS);
+		changes |= NEW_I;
+	}
+	if (th->th_flags & TCP_PSH)
+	changes |= TCP_PUSH_BIT;
+	/*
+	 * Grab the cksum before we overwrite it below.  Then update our
+	 * state with this packet's header.
+	 */
+	deltaA = ntohs(th->th_sum);
+	BCOPY(ip, &cs->cs_ip, hlen);
+	
+	/*
+	 * We want to use the original packet as our compressed packet.
+	 * (cp - new_seq) is the number of bytes we need for compressed
+	 * sequence numbers.  In addition we need one byte for the change
+	 * mask, one for the connection id and two for the tcp checksum.
+	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+	 * many bytes of the original packet to toss so subtract the two to
+	 * get the new packet size.
+	 */
+	deltaS = (u_short)(cp - new_seq);
+	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+		comp->last_xmit = cs->cs_id;
+		hlen -= deltaS + 4;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes | NEW_C;
+		*cp++ = cs->cs_id;
+	} else {
+		hlen -= deltaS + 3;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes;
+	}
+	*cp++ = deltaA >> 8;
+	*cp++ = deltaA;
+	BCOPY(new_seq, cp, deltaS);
+	INCR(vjs_compressed);
+	return (TYPE_COMPRESSED_TCP);
+
+	/*
+	 * Update connection state cs & send uncompressed packet (that is,
+	 * a regular ip/tcp packet but with the 'conversation id' we hope
+	 * to use on future compressed packets in the protocol field).
+	 */
+uncompressed:
+	BCOPY(ip, &cs->cs_ip, hlen);
+	ip->ip_p = cs->cs_id;
+	comp->last_xmit = cs->cs_id;
+	return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void vj_uncompress_err(struct vjcompress *comp)
+{
+    comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int vj_uncompress_uncomp(
+	struct pbuf *nb,
+	struct vjcompress *comp
+)
+{
+	register u_int hlen;
+	register struct cstate *cs;
+	register struct ip *ip;
+	
+	ip = (struct ip *)nb->payload;
+	hlen = getip_hl(*ip) << 2;
+	if (ip->ip_p >= MAX_SLOTS
+			|| hlen + sizeof(struct tcphdr) > nb->len
+			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+			    > nb->len
+			|| hlen > MAX_HDR) {
+		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+					ip->ip_p, hlen, nb->len));
+		comp->flags |= VJF_TOSS;
+		INCR(vjs_errorin);
+		return -1;
+	}
+	cs = &comp->rstate[comp->last_recv = ip->ip_p];
+	comp->flags &=~ VJF_TOSS;
+	ip->ip_p = IPPROTO_TCP;
+	BCOPY(ip, &cs->cs_ip, hlen);
+	cs->cs_hlen = hlen;
+	INCR(vjs_uncompressedin);
+	return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int vj_uncompress_tcp(
+	struct pbuf **nb,
+	struct vjcompress *comp
+)
+{
+	u_char *cp;
+	struct tcphdr *th;
+	struct cstate *cs;
+	u_short *bp;
+	struct pbuf *n0 = *nb;
+	u32_t tmp;
+	u_int vjlen, hlen, changes;
+	
+	INCR(vjs_compressedin);
+	cp = (u_char *)n0->payload;
+	changes = *cp++;
+	if (changes & NEW_C) {
+		/* 
+		 * Make sure the state index is in range, then grab the state.
+		 * If we have a good state index, clear the 'discard' flag. 
+		 */
+		if (*cp >= MAX_SLOTS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+			goto bad;
+		}
+		
+		comp->flags &=~ VJF_TOSS;
+		comp->last_recv = *cp++;
+	} else {
+		/* 
+		 * this packet has an implicit state index.  If we've
+		 * had a line error since the last time we got an
+		 * explicit state index, we have to toss the packet. 
+		 */
+		if (comp->flags & VJF_TOSS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+			INCR(vjs_tossed);
+			return (-1);
+		}
+	}
+	cs = &comp->rstate[comp->last_recv];
+	hlen = getip_hl(cs->cs_ip) << 2;
+	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+	th->th_sum = htons((*cp << 8) | cp[1]);
+	cp += 2;
+	if (changes & TCP_PUSH_BIT)
+		th->th_flags |= TCP_PSH;
+	else
+		th->th_flags &=~ TCP_PSH;
+	
+	switch (changes & SPECIALS_MASK) {
+	case SPECIAL_I:
+		{
+			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+			/* some compilers can't nest inline assembler.. */
+			tmp = ntohl(th->th_ack) + i;
+			th->th_ack = htonl(tmp);
+			tmp = ntohl(th->th_seq) + i;
+			th->th_seq = htonl(tmp);
+		}
+		break;
+	
+	case SPECIAL_D:
+		/* some compilers can't nest inline assembler.. */
+		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+		th->th_seq = htonl(tmp);
+		break;
+	
+	default:
+		if (changes & NEW_U) {
+			th->th_flags |= TCP_URG;
+			DECODEU(th->th_urp);
+		} else
+			th->th_flags &=~ TCP_URG;
+		if (changes & NEW_W)
+			DECODES(th->th_win);
+		if (changes & NEW_A)
+			DECODEL(th->th_ack);
+		if (changes & NEW_S)
+			DECODEL(th->th_seq);
+		break;
+	}
+	if (changes & NEW_I) {
+		DECODES(cs->cs_ip.ip_id);
+	} else {
+		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+	}
+	
+	/*
+	 * At this point, cp points to the first byte of data in the
+	 * packet.  Fill in the IP total length and update the IP
+	 * header checksum.
+	 */
+	vjlen = (u_short)(cp - (u_char*)n0->payload);
+	if (n0->len < vjlen) {
+		/* 
+		 * We must have dropped some characters (crc should detect
+		 * this but the old slip framing won't) 
+		 */
+		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+				  n0->len, vjlen));
+		goto bad;
+	}
+	
+#if BYTE_ORDER == LITTLE_ENDIAN
+	tmp = n0->tot_len - vjlen + cs->cs_hlen;
+	cs->cs_ip.ip_len = htons(tmp);
+#else
+	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+	
+	/* recompute the ip header checksum */
+	bp = (u_short *) &cs->cs_ip;
+	cs->cs_ip.ip_sum = 0;
+	for (tmp = 0; hlen > 0; hlen -= 2)
+		tmp += *bp++;
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	cs->cs_ip.ip_sum = (u_short)(~tmp);
+	
+	/* Remove the compressed header and prepend the uncompressed header. */
+	pbuf_header(n0, -vjlen);
+
+	if(MEM_ALIGN(n0->payload) != n0->payload) {
+		struct pbuf *np, *q;
+		u8_t *bufptr;
+
+		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+
+		pbuf_header(np, -cs->cs_hlen);
+
+		bufptr = n0->payload;
+		for(q = np; q != NULL; q = q->next) {
+			memcpy(q->payload, bufptr, q->len);
+			bufptr += q->len;
+		}
+
+		if(n0->next) {
+			pbuf_chain(np, n0->next);
+			pbuf_dechain(n0);
+		}
+		pbuf_free(n0);
+		n0 = np;
+	}
+
+	if(pbuf_header(n0, cs->cs_hlen)) {
+		struct pbuf *np;
+
+		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+		pbuf_cat(np, n0);
+		n0 = np;
+	}
+	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+	*nb = n0;
+
+	return vjlen;
+	
+bad:
+	comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+	return (-1);
+}
+
+#endif
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
new file mode 100644
index 000000000..717208145
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS	16			/* must be > 2 and < 256 */
+#define MAX_HDR		128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C	0x40	/* flag bits for what changed in a packet */
+#define NEW_I	0x20
+#define NEW_S	0x08
+#define NEW_A	0x04
+#define NEW_W	0x02
+#define NEW_U	0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+    struct cstate *cs_next;	/* next most recently used state (xmit only) */
+    u_short cs_hlen;		/* size of hdr (receive only) */
+    u_char cs_id;			/* connection # associated with this state */
+    u_char cs_filler;
+    union {
+		char csu_hdr[MAX_HDR];
+		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
+    } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+    unsigned long vjs_packets;			/* outbound packets */
+    unsigned long vjs_compressed;		/* outbound compressed packets */
+    unsigned long vjs_searches;			/* searches for connection state */
+    unsigned long vjs_misses;			/* times couldn't find conn. state */
+    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
+    unsigned long vjs_compressedin;		/* inbound compressed packets */
+    unsigned long vjs_errorin;			/* inbound unknown type packets */
+    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+    struct cstate *last_cs;	/* most recently used tstate */
+    u_char last_recv;		/* last rcvd conn. id */
+    u_char last_xmit;		/* last sent conn. id */
+    u_short flags;
+    u_char maxSlotIndex;
+    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+    struct vjstat stats;
+#endif
+    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
+    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init (struct vjcompress *comp);
+extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
new file mode 100644
index 000000000..a089352ad
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,76 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned ip_hl:4,				/* header length */
+		ip_v:4;						/* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+	unsigned ip_v:4,					/* version */
+		ip_hl:4;					/* header length */
+#else
+	COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+	u_char	ip_tos;					/* type of service */
+	u_short	ip_len;					/* total length */
+	u_short	ip_id;					/* identification */
+	u_short	ip_off;					/* fragment offset field */
+#define	IP_DF 0x4000				/* dont fragment flag */
+#define	IP_MF 0x2000				/* more fragments flag */
+#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
+	u_char	ip_ttl;					/* time to live */
+	u_char	ip_p;					/* protocol */
+	u_short	ip_sum;					/* checksum */
+	struct	in_addr ip_src,ip_dst;	/* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr  
+{
+	u_short	th_sport;		/* source port */
+	u_short	th_dport;		/* destination port */
+	tcp_seq	th_seq;			/* sequence number */
+	tcp_seq	th_ack;			/* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+	u_char th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned	th_x2:4,		/* (unused) */
+			th_off:4;		/* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+	unsigned	th_off:4,		/* data offset */
+			th_x2:4;		/* (unused) */
+#endif
+#endif
+	u_char	th_flags;
+	u_short	th_win;			/* window */
+	u_short	th_sum;			/* checksum */
+	u_short	th_urp;			/* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
new file mode 100644
index 000000000..776c13f7a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be provided 
+ * by another file.They are sio_open, sio_recv and sio_send
+ */ 
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+#define MAX_SIZE     1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send() 
+ */ 
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct pbuf *q;
+  int i;
+  u8_t c;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, netif->state);
+
+  for(q = p; q != NULL; q = q->next) {
+    for(i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+  sio_send(SLIP_ESC, netif->state);
+  sio_send(SLIP_ESC_END, netif->state);
+  break;
+      case SLIP_ESC:
+  sio_send(SLIP_ESC, netif->state);
+  sio_send(SLIP_ESC_ESC, netif->state);
+  break;
+      default:
+  sio_send(c, netif->state);
+  break;
+      }
+    }
+  }
+  sio_send(SLIP_END, netif->state);
+  return 0;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ * 
+ * @return The IP packet when SLIP_END is received 
+ */ 
+static struct pbuf *
+slipif_input( struct netif * netif )
+{
+  u8_t c;
+  struct pbuf *p, *q;
+  int recved;
+  int i;
+
+  q = p = NULL;
+  recved = i = 0;
+  c = 0;
+
+  while (1) {
+    c = sio_recv(netif->state);
+    switch (c) {
+    case SLIP_END:
+      if (recved > 0) {
+  /* Received whole packet. */
+  pbuf_realloc(q, recved);
+  
+  LINK_STATS_INC(link.recv);
+  
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+  return q;
+      }
+      break;
+
+    case SLIP_ESC:
+      c = sio_recv(netif->state);
+      switch (c) {
+      case SLIP_ESC_END:
+  c = SLIP_END;
+  break;
+      case SLIP_ESC_ESC:
+  c = SLIP_ESC;
+  break;
+      }
+      /* FALLTHROUGH */
+      
+    default:
+      if (p == NULL) {
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+  p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+  if (p == NULL) {
+    LINK_STATS_INC(link.drop);
+    LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+  }
+  
+  if (q != NULL) {
+    pbuf_cat(q, p);
+  } else {
+    q = p;
+  }
+      }
+      if (p != NULL && recved < MAX_SIZE) {
+  ((u8_t *)p->payload)[i] = c;
+  recved++;
+  i++;
+  if (i >= p->len) {
+    i = 0;
+    p = NULL;
+  }
+      }
+      break;
+    }
+    
+  }
+  return NULL;
+}
+
+/**
+ * The SLIP input thread 
+ *
+ * Feed the IP layer with incoming packets
+ */ 
+static void
+slipif_loop(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif);
+    netif->input(p, netif);
+  }
+}
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ */ 
+err_t
+slipif_init(struct netif *netif)
+{
+  
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%x\n", (int)netif->num));
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = 1500;  
+  netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+  netif->state = sio_open(netif->num);
+  if (!netif->state)
+      return ERR_IF;
+
+  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h b/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
new file mode 100644
index 000000000..fd7cc2c0a
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
+#define SYS_LIGHTWEIGHT_PROT            1
+
+#define TCPIP_THREAD_PRIO	3
+
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                2000
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           20
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#define MEMP_NUM_UDP_PCB        4
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        10
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        8
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    3
+
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         4
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        4
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        8
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      8
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+#define PBUF_POOL_SIZE          16
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+#define PBUF_POOL_BUFSIZE       512
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 512
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             512
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+/* TCP receive window. */
+#define TCP_WND                 512
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ---------- ARP options ---------- */
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 1
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              1
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+/* ---------- UDP options ---------- */
+#define LWIP_UDP                1
+#define UDP_TTL                 255
+
+
+/* ---------- Statistics options ---------- */
+#define STATS
+
+#ifdef STATS
+#define LINK_STATS 1
+#define IP_STATS   1
+#define ICMP_STATS 1
+#define UDP_STATS  1
+#define TCP_STATS  1
+#define MEM_STATS  1
+#define MEMP_STATS 1
+#define PBUF_STATS 1
+#define SYS_STATS  1
+#endif /* STATS */
+
+#define LWIP_PROVIDE_ERRNO 1
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/main.c b/Demo/lwIP_Demo_Rowley_ARM7/main.c
new file mode 100644
index 000000000..566eb161f
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/main.c
@@ -0,0 +1,298 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the application tasks, then starts the scheduler.
+ *
+ * A task defined by the function vBasicWEBServer is created.  This executes 
+ * the lwIP stack and basic WEB server sample.  A task defined by the function
+ * vUSBCDCTask.  This executes the USB to serial CDC example.  All the other 
+ * tasks are from the set of standard demo tasks.  The WEB documentation 
+ * provides more details of the standard demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three
+ * seconds but has the highest priority so is guaranteed to get processor time.
+ * Its main function is to check the status of all the other demo application
+ * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
+ * should no error conditions be detected in any of the standard demo tasks.
+ * The toggle rate increasing to 500ms indicates that at least one error has
+ * been detected.
+ *
+ * Main.c includes an idle hook function that simply periodically sends data
+ * to the USB task for transmission.
+ */
+
+/*
+	Changes from V3.2.2
+
+	+ Modified the stack sizes used by some tasks to permit use of the 
+	  command line GCC tools.
+*/
+
+/* Library includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "PollQ.h"
+#include "semtest.h"
+#include "flash.h"
+#include "integer.h"
+#include "BlockQ.h"
+#include "BasicWEB.h"
+#include "USB-CDC.h"
+
+/* lwIP includes. */
+#include "lwip/api.h" 
+
+/* Hardware specific headers. */
+#include "Board.h"
+#include "AT91SAM7X256.h"
+
+/* Priorities/stacks for the various tasks within the demo application. */
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainWEBSERVER_PRIORITY      ( tskIDLE_PRIORITY + 2 )
+#define mainUSB_PRIORITY			( tskIDLE_PRIORITY + 1 )
+#define mainUSB_TASK_STACK			( 200 )
+
+/* The rate at which the on board LED will toggle when there is/is not an
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The rate at which the idle hook sends data to the USB port. */
+#define mainUSB_TX_FREQUENCY		( 100 / portTICK_RATE_MS )
+
+/* The string that is transmitted down the USB port. */
+#define mainFIRST_TX_CHAR			'a'
+#define mainLAST_TX_CHAR			'z'
+
+/* The LED used by the check task to indicate the system status. */
+#define mainCHECK_LED 				( 3 )
+/*-----------------------------------------------------------*/
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * The task that executes at the highest priority and calls
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Atmel demo board.  This is very
+ * minimal as most of the setup is performed in the startup code.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * The idle hook is just used to stream data to the USB port.
+ */
+void vApplicationIdleHook( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup hardware then start all the demo application tasks.
+ */
+int main( void )
+{
+	/* Setup the ports. */
+	prvSetupHardware();
+
+	/* Setup the IO required for the LED's. */
+	vParTestInitialise();
+
+	/* Setup lwIP. */
+    vlwIPInit();
+
+	/* Create the lwIP task.  This uses the lwIP RTOS abstraction layer.*/
+    sys_thread_new( vBasicWEBServer, ( void * ) NULL, mainWEBSERVER_PRIORITY );
+
+	/* Create the demo USB CDC task. */
+	xTaskCreate( vUSBCDCTask, ( signed portCHAR * ) "USB", mainUSB_TASK_STACK, NULL, mainUSB_PRIORITY, NULL );
+
+	/* Create the standard demo application tasks. */
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartLEDFlashTasks( mainFLASH_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */	
+    xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Finally, start the scheduler. 
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+	vTaskStartScheduler();
+
+	/* Should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+
+static void prvSetupHardware( void )
+{
+	/* When using the JTAG debugger the hardware is not always initialised to
+	the correct default state.  This line just ensures that this does not
+	cause all interrupts to be masked at the start. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+	
+	/* Most setup is performed by the low level init function called from the
+	startup asm file.
+
+	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
+	well as the UART Tx line. */
+	AT91C_BASE_PIOB->PIO_PER = LED_MASK; // Set in PIO mode
+	AT91C_BASE_PIOB->PIO_OER = LED_MASK; // Configure in Output
+
+
+	/* Enable the peripheral clock. */
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+portTickType xLastWakeTime;
+
+	/* The parameters are not used. */
+	( void ) pvParameters;
+
+	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
+	functions correctly. */
+	xLastWakeTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the Check LED flash rate will increase. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again.  The delay period is
+		shorter following an error. */
+		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without
+		error.  */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+static portTickType xLastTx = 0;
+portCHAR cTxByte;
+
+	/* The idle hook simply sends a string of characters to the USB port.
+	The characters will be buffered and sent once the port is connected. */
+	if( ( xTaskGetTickCount() - xLastTx ) > mainUSB_TX_FREQUENCY )
+	{
+		xLastTx = xTaskGetTickCount();
+		for( cTxByte = mainFIRST_TX_CHAR; cTxByte <= mainLAST_TX_CHAR; cTxByte++ )
+		{
+			vUSBSendByte( cTxByte );
+		}		
+	}
+}
+
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/makefile b/Demo/lwIP_Demo_Rowley_ARM7/makefile
new file mode 100644
index 000000000..132af20ce
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/makefile
@@ -0,0 +1,158 @@
+#	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+#
+#	This file is part of the FreeRTOS distribution.
+#
+#	FreeRTOS is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+CC=arm-elf-gcc
+OBJCOPY=arm-elf-objcopy
+ARCH=arm-elf-ar
+CRT0=boot.s
+DEBUG=
+OPTIM=-Os
+LDSCRIPT=atmel-rom.ld
+
+#
+# CFLAGS common to both the THUMB and ARM mode builds
+#
+
+CFLAGS= \
+-I.  \
+-I./EMAC  \
+-I../Common/include  \
+-I./USB  \
+-I./lwip-1.1.0/src/include  \
+-I./lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X  \
+-I../../Source/include  \
+-I../../Source/portable/GCC/ARM7_AT91SAM7S  \
+-I./lwip-1.1.0/src/include/ipv4 \
+-Wall  \
+-Wextra  \
+-Wstrict-prototypes  \
+-Wmissing-prototypes  \
+-Wmissing-declarations  \
+-Wno-strict-aliasing  \
+-D SAM7_GCC  \
+-D THUMB_INTERWORK \
+-mthumb-interwork \
+-mcpu=arm7tdmi  \
+-T$(LDSCRIPT) \
+$(DEBUG)  \
+$(OPTIM)
+
+THUMB_FLAGS=-mthumb
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
+
+#
+# Source files that can be built to THUMB mode.
+#
+FREERTOS_THUMB_SRC= \
+  ../../Source/tasks.c \
+  ../../Source/queue.c \
+  ../../Source/list.c \
+  ../../Source/portable/GCC/ARM7_AT91SAM7S/port.c
+
+DEMO_APP_THMUB_SRC= \
+  ../../Source/portable/MemMang/heap_2.c \
+  ParTest/ParTest.c \
+  main.c \
+  ../Common/Minimal/flash.c \
+  ../Common/Minimal/BlockQ.c \
+  ../Common/Minimal/integer.c \
+  ../Common/Minimal/PollQ.c \
+  ../Common/Minimal/semtest.c \
+  BasicWEB.c \
+  USB/USB-CDC.c 
+
+LWIP_THUMB_SRC= \
+  lwip-1.1.0/src/core/tcp_out.c \
+  lwip-1.1.0/src/core/inet.c \
+  lwip-1.1.0/src/core/mem.c \
+  lwip-1.1.0/src/core/memp.c \
+  lwip-1.1.0/src/core/netif.c \
+  lwip-1.1.0/src/core/pbuf.c \
+  lwip-1.1.0/src/core/raw.c \
+  lwip-1.1.0/src/core/stats.c \
+  lwip-1.1.0/src/core/sys.c \
+  lwip-1.1.0/src/core/tcp.c \
+  lwip-1.1.0/src/core/tcp_in.c \
+  lwip-1.1.0/src/core/ipv4/ip.c \
+  lwip-1.1.0/src/core/ipv4/ip_addr.c \
+  lwip-1.1.0/src/core/ipv4/icmp.c \
+  lwip-1.1.0/src/api/tcpip.c \
+  lwip-1.1.0/src/api/api_msg.c \
+  lwip-1.1.0/src/api/err.c \
+  lwip-1.1.0/src/api/api_lib.c \
+  lwip-1.1.0/src/netif/etharp.c \
+  lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c \
+  lwip-1.1.0/src/netif/ethernetif.c \
+  EMAC/SAM7_EMAC.c \
+  lwip-1.1.0/src/core/udp.c \
+  lwip-1.1.0/src/core/ipv4/ip_frag.c
+
+#
+# Source files that must be built to ARM mode.
+#
+ARM_SRC= \
+  ../../Source/portable/GCC/ARM7_AT91SAM7S/portISR.c \
+  EMAC/SAM7_EMAC_ISR.c \
+  USB/USBIsr.c \
+  Cstartup_SAM7.c  
+
+
+#
+# Define all object files.
+#
+ARM_OBJ = $(ARM_SRC:.c=.o)
+FREERTOS_THUMB_OBJ = $(FREERTOS_THUMB_SRC:.c=.o)
+DEMO_APP_THMUB_OBJ = $(DEMO_APP_THMUB_SRC:.c=.o)
+LWIP_THUMB_OBJ = $(LWIP_THUMB_SRC:.c=.o)
+
+rtosdemo.bin : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O binary rtosdemo.bin
+
+rtosdemo.hex : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
+
+rtosdemo.elf : $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) $(CRT0) Makefile FreeRTOSConfig.h
+	$(CC) $(CFLAGS) $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
+
+$(DEMO_APP_THMUB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(LWIP_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(FREERTOS_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(CFLAGS) $< -o $@
+
+clean :
+	touch Makefile
+
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
new file mode 100644
index 000000000..8b5dad655
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
@@ -0,0 +1,84 @@
+
+
+  
+    
+    
+    
+    
+      
+      
+        
+        
+        
+        
+          
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+          
+          
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+          
+        
+        
+        
+      
+    
+    
+      
+      
+      
+        
+      
+      
+      
+        
+      
+    
+    
+  
+  
+  
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
new file mode 100644
index 000000000..9a2732c91
--- /dev/null
+++ b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
@@ -0,0 +1,60 @@
+
+
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+   
+   
+   
+   
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+
diff --git a/Demo/msp430_CrossWorks/FreeRTOSConfig.h b/Demo/msp430_CrossWorks/FreeRTOSConfig.h
new file mode 100644
index 000000000..1c159dd3e
--- /dev/null
+++ b/Demo/msp430_CrossWorks/FreeRTOSConfig.h
@@ -0,0 +1,77 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			1
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
+#define configMAX_TASK_NAME_LEN		( 8 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		1
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		0
+#define INCLUDE_uxTaskPriorityGet		0
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			0
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/msp430_CrossWorks/ParTest/ParTest.c b/Demo/msp430_CrossWorks/ParTest/ParTest.c
new file mode 100644
index 000000000..9907e1e0c
--- /dev/null
+++ b/Demo/msp430_CrossWorks/ParTest/ParTest.c
@@ -0,0 +1,210 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
+ * is really operating on the LCD display.
+ *-----------------------------------------------------------*/
+
+/*
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * There is a single genuine on board LED referenced as LED 10.
+ */
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Constants required to setup the LCD. */
+#define LCD_DIV_64 5
+
+/* Constants required to access the "LED's".  The LED segments are turned on
+and off to generate '*' characters. */
+#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
+#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
+#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
+
+/* The LED number of the real on board LED, rather than a simulated LED. */
+#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
+#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
+
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
+																( unsigned portCHAR * )0xa2, 
+																( unsigned portCHAR * )0xa0, 
+																( unsigned portCHAR * )0x9e,
+																( unsigned portCHAR * )0x9c,
+																( unsigned portCHAR * )0x9a };
+
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
+																( unsigned portCHAR * )0xa1, 
+																( unsigned portCHAR * )0x9f, 
+																( unsigned portCHAR * )0x9d,
+																( unsigned portCHAR * )0x9b,
+																( unsigned portCHAR * )0x99 };
+
+/*
+ * Toggle the single genuine built in LED.
+ */
+static void prvToggleOnBoardLED( void );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* Initialise the LCD hardware. */
+
+	/* Used for the onboard LED. */
+	P1DIR = 0x01;
+
+	// Setup Basic Timer for LCD operation
+	BTCTL = (LCD_DIV_64+0x23);
+
+	// Setup port functions
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+	
+	/* Initialise all segments to off. */
+	LCDM1 = partstSEGMENTS_OFF;	
+	LCDM2 = partstSEGMENTS_OFF;	
+	LCDM3 = partstSEGMENTS_OFF;	
+	LCDM4 = partstSEGMENTS_OFF;	
+	LCDM5 = partstSEGMENTS_OFF;	
+	LCDM6 = partstSEGMENTS_OFF;	
+	LCDM7 = partstSEGMENTS_OFF;	
+	LCDM8 = partstSEGMENTS_OFF;	
+	LCDM9 = partstSEGMENTS_OFF;	
+	LCDM10 = partstSEGMENTS_OFF;	
+	LCDM11 = partstSEGMENTS_OFF;	
+	LCDM12 = partstSEGMENTS_OFF;	
+	LCDM13 = partstSEGMENTS_OFF;	
+	LCDM14 = partstSEGMENTS_OFF;	
+	LCDM15 = partstSEGMENTS_OFF;	
+	LCDM16 = partstSEGMENTS_OFF;	
+	LCDM17 = partstSEGMENTS_OFF;	
+	LCDM18 = partstSEGMENTS_OFF;	
+	LCDM19 = partstSEGMENTS_OFF;	
+	LCDM20 = partstSEGMENTS_OFF;	
+
+	/* Setup LCD control. */
+	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	/* Set or clear the output [in this case show or hide the '*' character. */
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			if( xValue )
+			{
+				/* Turn on the segments required to show the '*'. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+			else
+			{
+				/* Turn off all the segments. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			/* If the '*' is already showing - hide it.  If it is not already
+			showing then show it. */
+			if( *( ucRHSSegments[ uxLED ] ) )
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+			else
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+		}
+		xTaskResumeAll();
+	}
+	else
+	{
+		if( uxLED == partstON_BOARD_LED )
+		{
+			/* The request related to the genuine on board LED. */
+			prvToggleOnBoardLED();
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static void prvToggleOnBoardLED( void )
+{
+static unsigned portSHORT sState = pdFALSE;
+
+	/* Toggle the state of the single genuine on board LED. */
+	if( sState )	
+	{
+		P1OUT |= mainON_BOARD_LED_BIT;
+	}
+	else
+	{
+		P1OUT &= ~mainON_BOARD_LED_BIT;
+	}
+
+	sState = !sState;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/Demo/msp430_CrossWorks/RTOSDemo.hzp b/Demo/msp430_CrossWorks/RTOSDemo.hzp
new file mode 100644
index 000000000..94acc5011
--- /dev/null
+++ b/Demo/msp430_CrossWorks/RTOSDemo.hzp
@@ -0,0 +1,34 @@
+
+
+  
+    
+    
+      
+      
+        
+      
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+  
+  
+
diff --git a/Demo/msp430_CrossWorks/RTOSDemo.hzs b/Demo/msp430_CrossWorks/RTOSDemo.hzs
new file mode 100644
index 000000000..c4dc21923
--- /dev/null
+++ b/Demo/msp430_CrossWorks/RTOSDemo.hzs
@@ -0,0 +1,57 @@
+
+
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+  
+  
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+ 
+ 
+
diff --git a/Demo/msp430_CrossWorks/main.c b/Demo/msp430_CrossWorks/main.c
new file mode 100644
index 000000000..9dc8b9875
--- /dev/null
+++ b/Demo/msp430_CrossWorks/main.c
@@ -0,0 +1,293 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * Main. c also creates a task called 'Check'.  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.  
+ * Each task that does not flash an LED maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * 'check' task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles an LED with a three second period.  Should any task contain an error 
+ * at any time the LED toggle rate will increase to 500ms.
+ *
+ * Please read the documentation for the MSP430 port available on
+ * http://www.FreeRTOS.org.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "comtest2.h"
+#include "PollQ.h"
+
+/* Constants required for hardware setup. */
+#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
+#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
+
+/* Constants that define the LED's used by the various tasks. [in this case
+the '*' characters on the LCD represent LED's] */
+#define mainCHECK_LED			( 4 )
+#define mainCOM_TEST_LED		( 10 )
+
+/* Demo task priorities. */
+#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the COM test tasks. */
+#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
+
+/* The frequency at which the 'Check' tasks executes.  See the comments at the 
+top of the page.  When the system is operating error free the 'Check' task
+toggles an LED every three seconds.  If an error is discovered in any task the
+rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
+LCD represent LED's]*/
+#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The constants used in the calculation. */
+#define intgCONST1				( ( portLONG ) 123 )
+#define intgCONST2				( ( portLONG ) 234567 )
+#define intgCONST3				( ( portLONG ) -3 )
+#define intgCONST4				( ( portLONG ) 7 )
+#define intgEXPECTED_ANSWER		( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
+
+/* 
+ * The function that implements the Check task.  See the comments at the head
+ * of the page for implementation details.
+ */ 
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Called by the Check task.  Returns pdPASS if all the other tasks are found
+ * to be operating without error - otherwise returns pdFAIL.
+ */
+static portSHORT prvCheckOtherTasksAreStillRunning( void );
+
+/* 
+ * Perform the hardware setup required by the ES449 in order to run the demo
+ * application.
+ */
+static void prvSetupHardware( void );
+
+
+portBASE_TYPE xLocalError = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Start the demo application tasks - then start the real time scheduler.
+ */
+int main( void )
+{
+	/* Setup the hardware ready for the demo. */
+	prvSetupHardware();
+	vParTestInitialise();
+
+	/* Start the standard demo application tasks. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+
+	/* Start the 'Check' task which is defined in this file. */
+	xTaskCreate( vErrorChecks, ( const signed portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* As the scheduler has been started the demo applications tasks will be
+	executing and we should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vErrorChecks, pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error. */
+	for( ;; )
+	{
+		/* Wait until it is time to check again.  The time we wait here depends
+		on whether an error has been detected or not.  When an error is 
+		detected the time is shortened resulting in a faster LED flash rate. */
+		vTaskDelay( xDelayPeriod );
+
+		/* See if the other tasks are all ok. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error occurred in one of the tasks so shorten the delay 
+			period - which has the effect of increasing the frequency of the
+			LED toggle. */
+			xDelayPeriod = mainERROR_CHECK_DELAY;
+		}
+
+		/* Flash! */
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portSHORT prvCheckOtherTasksAreStillRunning( void )
+{
+static portSHORT sNoErrorFound = pdTRUE;
+
+	/* The demo tasks maintain a count that increments every cycle of the task
+	provided that the task has never encountered an error.  This function 
+	checks the counts maintained by the tasks to ensure they are still being
+	incremented.  A count remaining at the same value between calls therefore
+	indicates that an error has been detected.  Only tasks that do not flash
+	an LED are checked. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xLocalError == pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	return sNoErrorFound;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Stop the watchdog. */
+	WDTCTL = WDTPW + WDTHOLD;
+
+	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
+	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
+
+	/* X2 DCO frequency, 8MHz nominal DCO */
+	SCFI0 |= FN_4;                  
+
+	/* (121+1) x 32768 x 2 = 7.99 Mhz */
+	SCFQCTL = mainMAX_FREQUENCY;
+
+	/* Setup the IO.  This is just copied from the demo supplied by SoftBaugh
+	 for the ES449 demo board. */
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+}
+/*-----------------------------------------------------------*/
+
+/* The idle hook is just a copy of the standard integer maths tasks.  See
+Demo/Common/integer.c for rationale. */
+
+void vApplicationIdleHook( void ) __toplevel
+{
+/* These variables are all effectively set to constants so they are volatile to
+ensure the compiler does not just get rid of them. */
+volatile portLONG lValue;
+volatile signed portBASE_TYPE *pxTaskHasExecuted;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		/* Perform the calculation.  This will store partial value in
+		registers, resulting in a good test of the context switch mechanism. */
+		lValue = intgCONST1;
+		lValue += intgCONST2;
+
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+
+		/* Finish off the calculation. */
+		lValue *= intgCONST3;
+		lValue /= intgCONST4;
+
+		/* If the calculation is found to be incorrect we stop setting the 
+		TaskHasExecuted variable so the check task can see an error has 
+		occurred. */
+		if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
+		{
+			/* Don't bother with mutual exclusion - it is only read from the
+			check task and never written. */
+			xLocalError = pdTRUE;
+		}
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+	}
+}
+
+
+
+
+
diff --git a/Demo/msp430_CrossWorks/serial/serial.c b/Demo/msp430_CrossWorks/serial/serial.c
new file mode 100644
index 000000000..54b34d595
--- /dev/null
+++ b/Demo/msp430_CrossWorks/serial/serial.c
@@ -0,0 +1,280 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
+ * 
+ * This file only supports UART 1
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Constants required to setup the hardware. */
+#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
+
+/* Misc. constants. */
+#define serNO_BLOCK				( ( portTickType ) 0 )
+
+/* Enable the UART Tx interrupt. */
+#define vInterruptOn() IFG2 |= UTXIFG1
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars; 
+
+/* The queue used to hold characters waiting transmission. */
+static xQueueHandle xCharsForTx; 
+
+static volatile portSHORT sTHREEmpty;
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulBaudRateCount;
+
+	/* Initialise the hardware. */
+
+	/* Generate the baud rate constants for the wanted baud rate. */
+	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
+
+	portENTER_CRITICAL();
+	{
+		/* Create the queues used by the com test task. */
+		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+		/* Reset UART. */
+		UCTL1 |= SWRST;
+
+		/* Set pin function. */
+		P4SEL |= serTX_AND_RX;
+
+		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
+		LOOPBACK MODE!*/
+		U1CTL |= CHAR + LISTEN;
+		U1TCTL |= SSEL1;
+
+		/* Setup baud rate low byte. */
+		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Setup baud rate high byte. */
+		ulBaudRateCount >>= 8UL;
+		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Enable ports. */
+		ME2 |= UTXE1 + URXE1;
+
+		/* Set. */
+		UCTL1 &= ~SWRST;
+
+		/* Nothing in the buffer yet. */
+		sTHREEmpty = pdTRUE;
+
+		/* Enable interrupts. */
+		IE2 |= URXIE1 + UTXIE1;
+	}
+	portEXIT_CRITICAL();
+	
+	/* Unlike other ports, this serial code does not allow for more than one
+	com port.  We therefore don't return a pointer to a port structure and can
+	instead just return NULL. */
+	return NULL;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* Transmit a character. */
+
+	portENTER_CRITICAL();
+	{
+		if( sTHREEmpty == pdTRUE )
+		{
+			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
+			there are no characters queued to be transmitted - so we can
+			write the character directly to the shift Tx register. */
+			sTHREEmpty = pdFALSE;
+			U1TXBUF = cOutChar;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* sTHREEmpty is false, so there are still characters waiting to be
+			transmitted.  We have to queue this character so it gets 
+			transmitted	in turn. */
+
+			/* Return false if after the block time there is no room on the Tx 
+			queue.  It is ok to block inside a critical section as each task
+			maintains it's own critical section status. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we 
+			were blocked waiting to post on the queue interrupts were not 
+			disabled.  It is possible that the serial ISR has emptied the 
+			Tx queue, in which case we need to start the Tx off again
+			writing directly to the Tx register. */
+			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
+			{
+				/* Get back the character we just posted. */
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				sTHREEmpty = pdFALSE;
+				U1TXBUF = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#ifdef MSP_ROWLEY_RB_PORT
+
+/* Serial interrupt service routines for the RB port. */
+
+	/*
+	 * UART RX interrupt service routine.
+	 */
+	void vRxISR( void ) __interrupt[ UART1RX_VECTOR ]
+	{
+	signed portCHAR cChar;
+	
+		/* Get the character from the UART and post it on the queue of Rxed 
+		characters. */
+		cChar = U1RXBUF;
+	
+		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+		{
+			/*If the post causes a task to wake force a context switch 
+			as the woken task may have a higher priority than the task we have 
+			interrupted. */
+			taskYIELD();
+		}
+	}
+	/*-----------------------------------------------------------*/
+	
+	/*
+	 * UART Tx interrupt service routine.
+	 */
+	void vTxISR( void ) __interrupt[ UART1TX_VECTOR ]
+	{
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWoken;
+	
+		/* The previous character has been transmitted.  See if there are any
+		further characters waiting transmission. */
+	
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+		{
+			/* There was another character queued - transmit it now. */
+			U1TXBUF = cChar;
+		}
+		else
+		{
+			/* There were no other characters to transmit. */
+			sTHREEmpty = pdTRUE;
+		}
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#ifdef MSP_ROWLEY_MP_PORT
+
+/* Serial port interrupts for the alternative port code. */
+
+	void ISRCom1Rx( void )
+	{
+	signed portCHAR cChar;
+	
+		/* Get the character from the UART and post it on the queue of Rxed 
+		characters. */
+		cChar = U1RXBUF;
+	
+		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+		{
+			/*If the post causes a task to wake force a context switch 
+			as the woken task may have a higher priority than the task we have 
+			interrupted. */
+			portEXIT_SWITCHING_ISR( pdTRUE );
+		}
+	}
+	/*-----------------------------------------------------------*/
+	
+	void ISRCom1Tx( void )
+	{
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWoken;
+	
+		/* The previous character has been transmitted.  See if there are any
+		further characters waiting transmission. */
+	
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+		{
+			/* There was another character queued - transmit it now. */
+			U1TXBUF = cChar;
+		}
+		else
+		{
+			/* There were no other characters to transmit. */
+			sTHREEmpty = pdTRUE;
+		}
+	}
+
+#endif
+/*-----------------------------------------------------------*/
diff --git a/Demo/msp430_GCC/FreeRTOSConfig.h b/Demo/msp430_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..ed2fff261
--- /dev/null
+++ b/Demo/msp430_GCC/FreeRTOSConfig.h
@@ -0,0 +1,82 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
+#define configMAX_TASK_NAME_LEN		( 8 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		1
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		0
+#define INCLUDE_uxTaskPriorityGet		0
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			0
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+
+
+
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/msp430_GCC/ParTest/ParTest.c b/Demo/msp430_GCC/ParTest/ParTest.c
new file mode 100644
index 000000000..a8101c36d
--- /dev/null
+++ b/Demo/msp430_GCC/ParTest/ParTest.c
@@ -0,0 +1,212 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
+ * is really operating on the LCD display.
+ *-----------------------------------------------------------*/
+
+/*
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * There is a single genuine on board LED referenced as LED 10.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Constants required to setup the LCD. */
+#define LCD_DIV_64 5
+
+/* Constants required to access the "LED's".  The LED segments are turned on
+and off to generate '*' characters. */
+#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
+#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
+#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
+
+/* The LED number of the real on board LED, rather than a simulated LED. */
+#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
+#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
+
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
+																( unsigned portCHAR * )0xa2, 
+																( unsigned portCHAR * )0xa0, 
+																( unsigned portCHAR * )0x9e,
+																( unsigned portCHAR * )0x9c,
+																( unsigned portCHAR * )0x9a };
+
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
+																( unsigned portCHAR * )0xa1, 
+																( unsigned portCHAR * )0x9f, 
+																( unsigned portCHAR * )0x9d,
+																( unsigned portCHAR * )0x9b,
+																( unsigned portCHAR * )0x99 };
+
+/*
+ * Toggle the single genuine built in LED.
+ */
+static void prvToggleOnBoardLED( void );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* Initialise the LCD hardware. */
+
+	/* Used for the onboard LED. */
+	P1DIR = 0x01;
+
+	// Setup Basic Timer for LCD operation
+	BTCTL = (LCD_DIV_64+0x23);
+
+	// Setup port functions
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+	
+	/* Initialise all segments to off. */
+	LCDM1 = partstSEGMENTS_OFF;	
+	LCDM2 = partstSEGMENTS_OFF;	
+	LCDM3 = partstSEGMENTS_OFF;	
+	LCDM4 = partstSEGMENTS_OFF;	
+	LCDM5 = partstSEGMENTS_OFF;	
+	LCDM6 = partstSEGMENTS_OFF;	
+	LCDM7 = partstSEGMENTS_OFF;	
+	LCDM8 = partstSEGMENTS_OFF;	
+	LCDM9 = partstSEGMENTS_OFF;	
+	LCDM10 = partstSEGMENTS_OFF;	
+	LCDM11 = partstSEGMENTS_OFF;	
+	LCDM12 = partstSEGMENTS_OFF;	
+	LCDM13 = partstSEGMENTS_OFF;	
+	LCDM14 = partstSEGMENTS_OFF;	
+	LCDM15 = partstSEGMENTS_OFF;	
+	LCDM16 = partstSEGMENTS_OFF;	
+	LCDM17 = partstSEGMENTS_OFF;	
+	LCDM18 = partstSEGMENTS_OFF;	
+	LCDM19 = partstSEGMENTS_OFF;	
+	LCDM20 = partstSEGMENTS_OFF;	
+
+	/* Setup LCD control. */
+	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	/* Set or clear the output [in this case show or hide the '*' character. */
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			if( xValue )
+			{
+				/* Turn on the segments required to show the '*'. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+			else
+			{
+				/* Turn off all the segments. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			/* If the '*' is already showing - hide it.  If it is not already
+			showing then show it. */
+			if( *( ucRHSSegments[ uxLED ] ) )
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+			else
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+		}
+		xTaskResumeAll();
+	}
+	else
+	{
+		if( uxLED == partstON_BOARD_LED )
+		{
+			/* The request related to the genuine on board LED. */
+			prvToggleOnBoardLED();
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static void prvToggleOnBoardLED( void )
+{
+static unsigned portSHORT sState = pdFALSE;
+
+	/* Toggle the state of the single genuine on board LED. */
+	if( sState )	
+	{
+		P1OUT |= mainON_BOARD_LED_BIT;
+	}
+	else
+	{
+		P1OUT &= ~mainON_BOARD_LED_BIT;
+	}
+
+	sState = !sState;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/Demo/msp430_GCC/gdb.ini b/Demo/msp430_GCC/gdb.ini
new file mode 100644
index 000000000..ff3ac1401
--- /dev/null
+++ b/Demo/msp430_GCC/gdb.ini
@@ -0,0 +1,8 @@
+target remote localhost:3333
+kill
+target remote localhost:3333
+b main
+c
+
+
+
diff --git a/Demo/msp430_GCC/main.c b/Demo/msp430_GCC/main.c
new file mode 100644
index 000000000..587b95846
--- /dev/null
+++ b/Demo/msp430_GCC/main.c
@@ -0,0 +1,242 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * Main. c also creates a task called 'Check'.  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.  
+ * Each task that does not flash an LED maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * 'check' task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles an LED with a three second period.  Should any task contain an error 
+ * at any time the LED toggle rate will increase to 500ms.
+ *
+ * Please read the documentation for the MSP430 port available on
+ * http://www.FreeRTOS.org.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "comtest2.h"
+#include "PollQ.h"
+
+/* Constants required for hardware setup. */
+#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
+#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
+
+/* Constants that define the LED's used by the various tasks. [in this case
+the '*' characters on the LCD represent LED's] */
+#define mainCHECK_LED			( 4 )
+#define mainCOM_TEST_LED		( 10 )
+
+/* Demo task priorities. */
+#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the COM test tasks. */
+#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
+
+/* The frequency at which the 'Check' tasks executes.  See the comments at the 
+top of the page.  When the system is operating error free the 'Check' task
+toggles an LED every three seconds.  If an error is discovered in any task the
+rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
+LCD represent LED's]*/
+#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* 
+ * The function that implements the Check task.  See the comments at the head
+ * of the page for implementation details.
+ */ 
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Called by the Check task.  Returns pdPASS if all the other tasks are found
+ * to be operating without error - otherwise returns pdFAIL.
+ */
+static portSHORT prvCheckOtherTasksAreStillRunning( void );
+
+/* 
+ * Perform the hardware setup required by the ES449 in order to run the demo
+ * application.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Start the demo application tasks - then start the real time scheduler.
+ */
+int main( void )
+{
+	/* Setup the hardware ready for the demo. */
+	prvSetupHardware();
+	vParTestInitialise();
+
+	/* Start the standard demo application tasks. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+
+	/* Start the 'Check' task which is defined in this file. */
+	xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* As the scheduler has been started the demo applications tasks will be
+	executing and we should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+static volatile unsigned portLONG ulDummyVariable = 3UL;
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error. */
+	for( ;; )
+	{
+		/* Wait until it is time to check again.  The time we wait here depends
+		on whether an error has been detected or not.  When an error is 
+		detected the time is shortened resulting in a faster LED flash rate. */
+		vTaskDelay( xDelayPeriod );
+
+		/* Perform a bit of 32bit maths to ensure the registers used by the 
+		integer tasks get some exercise outside of the integer tasks 
+		themselves. The result here is not important we are just deliberately
+		changing registers used by other tasks to ensure that their context
+		switch is operating as required. - see the demo application 
+		documentation for more info. */
+		ulDummyVariable *= 3UL;
+		
+		/* See if the other tasks are all ok. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error occurred in one of the tasks so shorten the delay 
+			period - which has the effect of increasing the frequency of the
+			LED toggle. */
+			xDelayPeriod = mainERROR_CHECK_DELAY;
+		}
+
+		/* Flash! */
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portSHORT prvCheckOtherTasksAreStillRunning( void )
+{
+static portSHORT sNoErrorFound = pdTRUE;
+
+	/* The demo tasks maintain a count that increments every cycle of the task
+	provided that the task has never encountered an error.  This function 
+	checks the counts maintained by the tasks to ensure they are still being
+	incremented.  A count remaining at the same value between calls therefore
+	indicates that an error has been detected.  Only tasks that do not flash
+	an LED are checked. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	return sNoErrorFound;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Stop the watchdog. */
+	WDTCTL = WDTPW + WDTHOLD;
+
+	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
+	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
+
+	/* X2 DCO frequency, 8MHz nominal DCO */
+	SCFI0 |= FN_4;                  
+
+	/* (121+1) x 32768 x 2 = 7.99 Mhz */
+	SCFQCTL = mainMAX_FREQUENCY;
+
+	/* Setup the IO as per the SoftBaugh demo for the same target hardware. */
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
diff --git a/Demo/msp430_GCC/makefile b/Demo/msp430_GCC/makefile
new file mode 100644
index 000000000..dcc6fb9a6
--- /dev/null
+++ b/Demo/msp430_GCC/makefile
@@ -0,0 +1,87 @@
+#	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+#
+#	This file is part of the FreeRTOS distribution.
+#
+#	FreeRTOS is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+
+CC=msp430-gcc
+OBJCOPY=msp430-objcopy
+DEBUG=-g
+OPT=-Os
+WARNINGS=-Wall -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
+		-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
+
+CFLAGS=-mmcu=msp430x449 $(OPT) $(DEBUG) -I. -I../../Source/include -I../Common/include -DGCC_MSP430 $(WARNINGS)
+
+# Setup paths to source code
+SOURCE_PATH = ../../Source
+PORT_PATH = ../../Source/portable/GCC/MSP430F449
+DEMO_PATH = ../Common/Minimal
+
+#
+# Source files that can be built to THUMB mode.
+#
+SRC = \
+main.c \
+ParTest/ParTest.c \
+serial/serial.c \
+$(SOURCE_PATH)/tasks.c \
+$(SOURCE_PATH)/list.c \
+$(SOURCE_PATH)/queue.c \
+$(SOURCE_PATH)/portable/MemMang/heap_1.c \
+$(PORT_PATH)/port.c \
+$(DEMO_PATH)/flash.c \
+$(DEMO_PATH)/integer.c \
+$(DEMO_PATH)/comtest.c \
+$(DEMO_PATH)/PollQ.c
+
+#
+# Define all object files.
+#
+OBJ = $(SRC:.c=.o)
+
+a.out : $(OBJ) makefile
+	$(CC) $(OBJ) $(CFLAGS)
+
+$(OBJ) : %.o : %.c makefile
+	$(CC) -c $(CFLAGS) $< -o $@	
+	
+clean :
+	touch makefile
+	
+
+
+
+
+
+
+
+
+	
+
+
diff --git a/Demo/msp430_GCC/serial/serial.c b/Demo/msp430_GCC/serial/serial.c
new file mode 100644
index 000000000..d1020a9e4
--- /dev/null
+++ b/Demo/msp430_GCC/serial/serial.c
@@ -0,0 +1,234 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
+ * 
+ * This file only supports UART 1
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Constants required to setup the hardware. */
+#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
+
+/* Misc. constants. */
+#define serNO_BLOCK				( ( portTickType ) 0 )
+
+/* Enable the UART Tx interrupt. */
+#define vInterruptOn() IFG2 |= UTXIFG1
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars; 
+
+/* The queue used to hold characters waiting transmission. */
+static xQueueHandle xCharsForTx; 
+
+static volatile portSHORT sTHREEmpty;
+
+/* Interrupt service routines. */
+interrupt (UART1RX_VECTOR) vRxISR( void );
+interrupt (UART1TX_VECTOR) vTxISR( void );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulBaudRateCount;
+
+	/* Initialise the hardware. */
+
+	/* Generate the baud rate constants for the wanted baud rate. */
+	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
+
+	portENTER_CRITICAL();
+	{
+		/* Create the queues used by the com test task. */
+		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+		/* Reset UART. */
+		UCTL1 |= SWRST;
+
+		/* Set pin function. */
+		P4SEL |= serTX_AND_RX;
+
+		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
+		LOOPBACK MODE!*/
+		U1CTL |= CHAR + LISTEN;
+		U1TCTL |= SSEL1;
+
+		/* Setup baud rate low byte. */
+		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Setup baud rate high byte. */
+		ulBaudRateCount >>= 8UL;
+		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Enable ports. */
+		ME2 |= UTXE1 + URXE1;
+
+		/* Set. */
+		UCTL1 &= ~SWRST;
+
+		/* Nothing in the buffer yet. */
+		sTHREEmpty = pdTRUE;
+
+		/* Enable interrupts. */
+		IE2 |= URXIE1 + UTXIE1;
+	}
+	portEXIT_CRITICAL();
+	
+	/* Unlike other ports, this serial code does not allow for more than one
+	com port.  We therefore don't return a pointer to a port structure and can
+	instead just return NULL. */
+	return NULL;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* Transmit a character. */
+
+	portENTER_CRITICAL();
+	{
+		if( sTHREEmpty == pdTRUE )
+		{
+			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
+			there are no characters queued to be transmitted - so we can
+			write the character directly to the shift Tx register. */
+			sTHREEmpty = pdFALSE;
+			U1TXBUF = cOutChar;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* sTHREEmpty is false, so there are still characters waiting to be
+			transmitted.  We have to queue this character so it gets 
+			transmitted	in turn. */
+
+			/* Return false if after the block time there is no room on the Tx 
+			queue.  It is ok to block inside a critical section as each task
+			maintains it's own critical section status. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we 
+			were blocked waiting to post on the queue interrupts were not 
+			disabled.  It is possible that the serial ISR has emptied the 
+			Tx queue, in which case we need to start the Tx off again
+			writing directly to the Tx register. */
+			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
+			{
+				/* Get back the character we just posted. */
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				sTHREEmpty = pdFALSE;
+				U1TXBUF = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * UART RX interrupt service routine.
+ */
+interrupt (UART1RX_VECTOR) vRxISR( void )
+{
+signed portCHAR cChar;
+
+	/* Get the character from the UART and post it on the queue of Rxed 
+	characters. */
+	cChar = U1RXBUF;
+
+	if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+	{
+		/*If the post causes a task to wake force a context switch 
+		as the woken task may have a higher priority than the task we have 
+		interrupted. */
+		taskYIELD();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * UART Tx interrupt service routine.
+ */
+interrupt (UART1TX_VECTOR) vTxISR( void )
+{
+signed portCHAR cChar;
+portBASE_TYPE xTaskWoken;
+
+	/* The previous character has been transmitted.  See if there are any
+	further characters waiting transmission. */
+
+	if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+	{
+		/* There was another character queued - transmit it now. */
+		U1TXBUF = cChar;
+	}
+	else
+	{
+		/* There were no other characters to transmit. */
+		sTHREEmpty = pdTRUE;
+	}
+}
+
diff --git a/Demo/readme.txt b/Demo/readme.txt
new file mode 100644
index 000000000..813c257cc
--- /dev/null
+++ b/Demo/readme.txt
@@ -0,0 +1,16 @@
+Each RTOS port has a demo application to demonstrate it's use.
+
++ The Demo/Common directory contains the demo application files as described on 
+the http://www.FreeRTOS.org WEB site.  Each file creates one or more tasks.
+The files in the Demo/Common directory are used by every demo application for
+every port.
+
++ All the other directories contain a project or makefile for the demo
+application targeted at a particular microcontroller.  
+
+
+For example, if you are interested in the ATMega323 demo application for
+the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the 
+relevant makefile.  The makefile includes files from the Demo/ATMega323 
+and the Demo/Common directories.  If this is the only port you are 
+interested in then all the other directories can be ignored.
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 b/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
new file mode 100644
index 000000000..9c2c1ed40
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
@@ -0,0 +1,56 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+		RSEG ICODE:CODE
+		CODE32
+
+		EXTERN vEMACISR
+		PUBLIC vEMACISREntry
+
+; Wrapper for the EMAC interrupt service routine.  This can cause a
+; context switch so requires an assembly wrapper.
+
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
+#include "ISR_Support.h"
+
+vEMACISREntry:
+
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	bl	vEMACISR				; Call the ISR routine.
+
+	portRESTORE_CONTEXT			; Restore the context of the current task -
+								; which may be different to the task that
+								; was interrupted.
+
+		END
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
new file mode 100644
index 000000000..233ed0a42
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
@@ -0,0 +1,694 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * Basic interrupt driven driver for the EMAC peripheral.  This driver is not
+ * reentrant as with uIP the buffers are only ever accessed from a single task.
+ *
+ * The simple buffer management used within uIP allows the EMAC driver to also
+ * be simplistic.  The driver contained within the lwIP demo is more
+ * comprehensive.
+ */
+
+
+/*
+Changes from V3.2.2
+
+	+ Corrected the byte order when writing the MAC address to the MAC.
+	+ Support added for MII interfaces.  Previously only RMII was supported.
+
+Changes from V3.2.3
+
+	+ The MII interface is now the default.
+	+ Modified the initialisation sequence slightly to allow auto init more
+	  time to complete.
+
+Changes from V3.2.4
+
+	+ Also read the EMAC_RSR register in the EMAC ISR as a work around the 
+	  the EMAC bug that can reset the RX bit in EMAC_ISR register before the
+	  bit has been read.
+*/
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* uIP includes. */
+#include "uip.h"
+
+/* Hardware specific includes. */
+#include "emac.h"
+#include "mii.h"
+
+
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define USE_RMII_INTERFACE 0
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last few bits are zero.  These bits have special meaning for the EMAC
+peripheral and cannot be used as part of the address. */
+#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
+
+/* Bit used within the Tx descriptor status to indicate whether the
+descriptor is under the control of the EMAC or the software. */
+#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
+#define emacBUFFER_WAIT_DELAY		( 2 )
+#define emacMAX_WAIT_CYCLES			( configTICK_RATE_HZ / 40 )
+
+/* Misc defines. */
+#define emacINTERRUPT_LEVEL			( 5 )
+#define emacNO_DELAY				( 0 )
+#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
+#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
+#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
+#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Prototype for the EMAC interrupt asm wrapper.
+ */
+extern void vEMACISREntry( void );
+
+/*
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.
+ */
+__arm void vEMACISR( void );
+
+/*
+ * Initialise both the Tx and Rx descriptors used by the EMAC.
+ */
+static void prvSetupDescriptors(void);
+
+/*
+ * Write our MAC address into the EMAC.  The MAC address is set as one of the
+ * uip options.
+ */
+static void prvSetupMACAddress( void );
+
+/*
+ * Configure the EMAC and AIC for EMAC interrupts.
+ */
+static void prvSetupEMACInterrupt( void );
+
+/*
+ * Some initialisation functions taken from the Atmel EMAC sample code.
+ */
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
+#if USE_RMII_INTERFACE != 1
+	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
+#endif
+static portBASE_TYPE xGetLinkSpeed( void );
+static portBASE_TYPE prvProbePHY( void );
+
+/*-----------------------------------------------------------*/
+
+/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
+comment above the emacADDRESS_MASK definition. */
+#pragma data_alignment=8
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
+
+/* Buffer read by the EMAC DMA.  Must be aligned as described by he comment
+above the emacADDRESS_MASK definition. */
+#pragma data_alignment=8
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
+
+/* Descriptors used to communicate between the program and the EMAC peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers. */
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
+
+/* The IP and Ethernet addresses are read from the uIP setup. */
+const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
+const unsigned char ucIPAddress[ 4 ]  = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
+
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+
+xSemaphoreHandle xEMACInit( void )
+{
+	/* Code supplied by Atmel (modified) --------------------*/
+
+	/* disable pull up on RXDV => PHY normal mode (not in test mode),
+	PHY has internal pull down. */
+	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
+
+	#if USE_RMII_INTERFACE != 1
+	  	/* PHY has internal pull down : set MII mode. */
+	  	AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
+	#endif
+
+	/* clear PB18 <=> PHY powerdown. */
+	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
+	AT91F_PIO_ClearOutput( AT91C_BASE_PIOB,  1 << 18) ;
+
+	/* After PHY power up, hardware reset. */
+	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
+	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
+	
+	/* Wait for hardware reset end. */
+	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
+	{
+		__asm( "NOP" );
+	}
+	__asm( "NOP" );
+  	
+	/* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
+	AT91F_EMAC_CfgPIO();
+
+	/* Enable com between EMAC PHY.
+
+	Enable management port. */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+
+	/* MDC = MCK/32. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
+
+	/* Wait for PHY auto init end (rather crude delay!). */
+	vTaskDelay( emacPHY_INIT_DELAY );
+
+	/* PHY configuration. */
+	#if USE_RMII_INTERFACE != 1
+	{
+		unsigned portLONG ulControl;
+
+		/* PHY has internal pull down : disable MII isolate. */
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		ulControl &= ~BMCR_ISOLATE;
+		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
+	}
+	#endif
+
+	/* Disable management port again. */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
+
+	#if USE_RMII_INTERFACE != 1
+		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
+	#else
+		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
+		on ERFCK). */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
+	#endif
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	/* Setup the buffers and descriptors. */
+	prvSetupDescriptors();
+	
+	/* Load our MAC address into the EMAC. */
+	prvSetupMACAddress();
+
+	/* Try to connect. */
+	if( prvProbePHY() )
+	{
+		/* Enable the interrupt! */
+		prvSetupEMACInterrupt();
+	}
+
+	return xSemaphore;
+}
+/*-----------------------------------------------------------*/
+
+portLONG lEMACSend( void )
+{
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;
+portBASE_TYPE xWaitCycles = 0;
+portLONG lReturn = pdPASS;
+portCHAR *pcBuffer;
+
+	/* Is a buffer available? */
+	while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
+	{
+		/* There is no room to write the Tx data to the Tx buffer.  Wait a
+		short while, then try again. */
+		xWaitCycles++;
+		if( xWaitCycles > emacMAX_WAIT_CYCLES )
+		{
+			/* Give up. */
+			lReturn = pdFAIL;
+			break;
+		}
+		else
+		{
+			vTaskDelay( emacBUFFER_WAIT_DELAY );
+		}
+	}
+
+	/* lReturn will only be pdPASS if a buffer is available. */
+	if( lReturn == pdPASS )
+	{
+		/* Copy the headers into the Tx buffer.  These will be in the uIP buffer. */
+		pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+		memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
+
+		/* If there is room, also copy in the application data if any. */
+		if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
+		{
+			memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
+		}
+
+		/* Send. */	
+		portENTER_CRITICAL();
+		{
+			if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
+			{
+				/* Fill out the necessary in the descriptor to get the data sent. */
+				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																		| AT91C_LAST_BUFFER
+																		| AT91C_TRANSMIT_WRAP;
+				uxTxBufferIndex = 0;
+			}
+			else
+			{
+				/* Fill out the necessary in the descriptor to get the data sent. */
+				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																		| AT91C_LAST_BUFFER;
+				uxTxBufferIndex++;
+			}
+	
+			AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
+		}
+		portEXIT_CRITICAL();
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+unsigned portLONG ulEMACPoll( void )
+{
+static unsigned portBASE_TYPE ulNextRxBuffer = 0;
+unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
+portCHAR *pcSource;
+
+	/* Skip any fragments. */
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
+	{
+		/* Mark the buffer as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* Is there a packet ready? */
+
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
+	{
+		pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+		ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_LENGTH_FRAME;
+
+		if( ulSectionLength == 0 )
+		{
+			/* The frame is longer than the buffer pointed to by this
+			descriptor so copy the entire buffer to uIP - then move onto
+			the next descriptor to get the rest of the frame. */
+			if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
+			{
+				memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
+				ulLengthSoFar += ETH_RX_BUFFER_SIZE;
+			}			
+		}
+		else
+		{
+			/* This is the last section of the frame.  Copy the section to
+			uIP. */
+			if( ulSectionLength < UIP_BUFSIZE )
+			{
+				/* The section length holds the length of the entire frame.
+				ulLengthSoFar holds the length of the frame sections already
+				copied to uIP, so the length of the final section is
+				ulSectionLength - ulLengthSoFar; */
+				if( ulSectionLength > ulLengthSoFar )
+				{
+					memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
+				}
+			}			
+
+			/* Is this the last buffer for the frame?  If not why? */
+			ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
+		}
+
+		/* Mark the buffer as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+		/* Increment to the next buffer, wrapping if necessary. */
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* If we obtained data but for some reason did not find the end of the
+	frame then discard the data as it must contain an error. */
+	if( !ulEOF )
+	{
+		ulSectionLength = 0;
+	}
+
+	return ulSectionLength;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupDescriptors(void)
+{
+unsigned portBASE_TYPE xIndex;
+unsigned portLONG ulAddress;
+
+	/* Initialise xRxDescriptors descriptor. */
+	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will place
+		the data at this address when this descriptor is being used.  Mask off
+		the bottom bits of the address as these have special meaning. */
+		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
+
+	/* Initialise xTxDescriptors. */
+	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will read
+		data from here when the descriptor is being used. */
+		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
+
+	/* Tell the EMAC where to find the descriptors. */
+	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
+	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
+	
+	/* Clear all the bits in the receive status register. */
+	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
+
+	/* Enable the copy of data into the buffers, ignore broadcasts,
+	and don't copy FCS. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
+
+	/* Enable Rx and Tx, plus the stats register. */
+	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
+}	
+/*-----------------------------------------------------------*/
+
+static void prvSetupMACAddress( void )
+{
+	/* Must be written SA1L then SA1H. */
+	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
+									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
+									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
+									cMACAddress[ 0 ];
+
+	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
+									cMACAddress[ 4 ];
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupEMACInterrupt( void )
+{
+	/* Create the semaphore used to trigger the EMAC task. */
+	vSemaphoreCreateBinary( xSemaphore );
+	if( xSemaphore )
+	{
+		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
+		first interrupt occurs. */
+		xSemaphoreTake( xSemaphore, emacNO_DELAY );
+		portENTER_CRITICAL();
+		{
+			/* We want to interrupt on Rx events. */
+			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
+
+			/* Enable the interrupts in the AIC. */
+			AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
+			AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
+		}
+		portEXIT_CRITICAL();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__arm void vEMACISR( void )
+{
+volatile unsigned portLONG ulIntStatus, ulRxStatus;
+portBASE_TYPE xSwitchRequired = pdFALSE;
+
+	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
+	ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
+
+	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
+	{
+		/* A frame has been received, signal the uIP task so it can process
+		the Rx descriptors. */
+		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
+		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
+	}
+
+	/* If a task was woken by either a character being received or a character
+	being transmitted then we may need to switch to another task. */
+	portEND_SWITCHING_ISR( xSwitchRequired );
+
+	/* Clear the interrupt. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+}
+/*-----------------------------------------------------------*/
+
+
+
+/*
+ * The following functions are initialisation functions taken from the Atmel
+ * EMAC sample code.
+ */
+
+static portBASE_TYPE prvProbePHY( void )
+{
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
+portBASE_TYPE xReturn = pdPASS;
+	
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Enable management port */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
+
+	/* Read the PHY ID. */
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
+
+	/* AMD AM79C875:
+			PHY_ID1 = 0x0022
+			PHY_ID2 = 0x5541
+			Bits 3:0 Revision Number Four bit manufacturer’s revision number.
+				0001 stands for Rev. A, etc.
+	*/
+	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
+	{
+		/* Did not expect this ID. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulStatus = xGetLinkSpeed();
+
+		if( ulStatus != pdPASS )
+		{
+			xReturn = pdFAIL;
+		}
+	}
+
+	/* Disable management port */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
+									| (2 << 16) | (2 << 28)
+									| ((ucPHYAddress & 0x1f) << 23)
+									| (ucAddress << 18);
+
+	/* Wait until IDLE bit in Network Status register is cleared. */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	}
+
+	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+/*-----------------------------------------------------------*/
+
+#if USE_RMII_INTERFACE != 1
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
+								| (2 << 16) | (1 << 28)
+								| ((ucPHYAddress & 0x1f) << 23)
+								| (ucAddress << 18))
+								| (ulValue & 0xffff);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	};
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+#endif
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xGetLinkSpeed( void )
+{
+	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
+
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Link status is latched, so read twice to get current value */
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+
+	if( !( ulBMSR & BMSR_LSTATUS ) )
+	{	
+		/* No Link. */
+		return pdFAIL;
+	}
+
+	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
+	if (ulBMCR & BMCR_ANENABLE)
+	{				
+		/* AutoNegotiation is enabled. */
+		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
+		{
+			/* Auto-negotiation in progress. */
+			return pdFAIL;				
+		}		
+
+		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
+		{
+			ulSpeed = SPEED_100;
+		}
+		else
+		{
+			ulSpeed = SPEED_10;
+		}
+
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
+		{
+			ulDuplex = DUPLEX_FULL;
+		}
+		else
+		{
+			ulDuplex = DUPLEX_HALF;
+		}
+	}
+	else
+	{
+		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
+		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* Update the MAC */
+	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
+	if( ulSpeed == SPEED_100 )
+	{
+		if( ulDuplex == DUPLEX_FULL )
+		{
+			/* 100 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		}
+		else
+		{					
+			/* 100 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
+		}
+	}
+	else
+	{
+		if (ulDuplex == DUPLEX_FULL)
+		{
+			/* 10 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
+		}
+		else
+		{
+			/* 10 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
+		}
+	}
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return pdPASS;
+}
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
new file mode 100644
index 000000000..36d6a05bc
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
@@ -0,0 +1,24 @@
+#ifndef SAM_7_EMAC_H
+#define SAM_7_EMAC_H
+
+
+/*
+ * Initialise the EMAC driver.  If successful a semaphore is returned that
+ * is used by the EMAC ISR to indicate that Rx packets have been received.
+ * If the initialisation fails then NULL is returned.
+ */
+xSemaphoreHandle xEMACInit( void );
+
+/*
+ * Send the current uIP buffer.  This copies the uIP buffer to one of the
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
+ */
+portLONG lEMACSend( void );
+
+/*
+ * Called in response to an EMAC Rx interrupt.  Copies the received frame
+ * into the uIP buffer.
+ */
+unsigned portLONG ulEMACPoll( void );
+
+#endif
diff --git a/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd b/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd
new file mode 100644
index 000000000..23f684657
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd
@@ -0,0 +1,26 @@
+This is an internal working file generated by the Source Browser.
+09:28 06s
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\BlockQ.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\Cstartup_SAM7.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\ParTest.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\PollQ.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\SAM7_EMAC.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\cgi.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\death.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\dynamic.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flash.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flop.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\fs.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\heap_2.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\httpd.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\integer.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\list.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\main.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\port.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\queue.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\semtest.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\tasks.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uIP_Task.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arch.pbi
+C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arp.pbi
diff --git a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
new file mode 100644
index 000000000..6a08a7743
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
@@ -0,0 +1,78 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+#include "board.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 100 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 22000 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c b/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
new file mode 100644
index 000000000..84c9da624
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
@@ -0,0 +1,81 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#include "FreeRTOS.h"
+#include "partest.h"
+#include "board.h"
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
+ * or toggled.
+ *-----------------------------------------------------------*/
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
+
+void vParTestInitialise( void )
+{	
+	/* Start with all LED's off. */
+	AT91F_PIO_SetOutput( AT91C_BASE_PIOB, LED_MASK );	
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( xValue )
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );
+		}
+		else
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( AT91F_PIO_GetInput( AT91C_BASE_PIOB ) & ulLED_MASK[ uxLED ] )
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
+		}
+		else
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );					
+		}
+	}
+}
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
new file mode 100644
index 000000000..0313bfdc6
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
@@ -0,0 +1,69 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7X Evaluation Board Features Definition File.
+*
+* Creation            : JG   20/Jun/2005
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include 
+#define __inline inline
+#include 
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
+
+#define  FLASH_PAGE_NB		256
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+#define LED1            (1<<19)	// PB19
+#define LED2            (1<<20)	// PB20
+#define LED3            (1<<21)	// PB21
+#define LED4            (1<<22)	// PB22
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+
+#define SW1_MASK        (1<<21)	// PA21
+#define SW2_MASK        (1<<22)	// PA22
+#define SW3_MASK        (1<<23)	// PA23
+#define SW4_MASK        (1<<24)	// PA24
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<21)	// PA21
+#define SW2 	(1<<22)	// PA22
+#define SW3 	(1<<23)	// PA23
+#define SW4 	(1<<24)	// PA24
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79 b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79
new file mode 100644
index 000000000..b875618fc
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79
@@ -0,0 +1,223 @@
+;------------------------------------------------------------------------------
+;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
+;------------------------------------------------------------------------------
+; The software is delivered "AS IS" without warranty or condition of any
+; kind, either express, implied or statutory. This includes without
+; limitation any warranty or condition with respect to merchantability or
+; fitness for any particular purpose, or against the infringements of
+; intellectual property rights of others.
+;-----------------------------------------------------------------------------
+;- File source          : Cstartup.s79
+;- Object               : Generic CStartup for IAR No Use REMAP
+;- Compilation flag     : None
+;-
+;- 1.0 15/Jun/04 JPP    : Creation
+;------------------------------------------------------------------------------
+
+#include "AT91SAM7X256_inc.h"
+
+;------------------------------------------------------------------------------
+;- Area Definition
+;------------------------------------------------------------------------------
+
+;---------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other
+; addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;-------------------------------------------------------------
+
+		PROGRAM	?RESET
+		RSEG	INTRAMSTART_REMAP
+		RSEG	INTRAMEND_REMAP
+
+		EXTERN	vPortYieldProcessor
+
+		RSEG	ICODE:CODE:ROOT(2)
+		CODE32	; Always ARM mode after reset	
+		org	0	
+reset		
+;------------------------------------------------------------------------------
+;- Exception vectors
+;--------------------
+;- These vectors can be read at address 0 or at RAM address
+;- They ABSOLUTELY requires to be in relative addresssing mode in order to
+;- guarantee a valid jump. For the moment, all are just looping.
+;- If an exception occurs before remap, this would result in an infinite loop.
+;- To ensure if a exeption occurs before start application to infinite loop.
+;------------------------------------------------------------------------------
+
+                B           InitReset           ; 0x00 Reset handler
+undefvec:
+                B           undefvec            ; 0x04 Undefined Instruction
+swivec:
+                B           vPortYieldProcessor ; 0x08 Software Interrupt
+pabtvec:
+                B           pabtvec             ; 0x0C Prefetch Abort
+dabtvec:
+                B           dabtvec             ; 0x10 Data Abort
+rsvdvec:
+                B           rsvdvec             ; 0x14 reserved
+irqvec:
+				LDR			PC, [PC, #-0xF20]	; Jump directly to the address given by the AIC
+
+fiqvec:               							; 0x1c FIQ
+
+;------------------------------------------------------------------------------
+;- Function             : FIQ_Handler_Entry
+;- Treatments           : FIQ Controller Interrupt Handler.
+;- Called Functions     : AIC_FVR[interrupt]
+;------------------------------------------------------------------------------
+
+FIQ_Handler_Entry:
+
+;- Switch in SVC/User Mode to allow User Stack access for C code
+; because the FIQ is not yet acknowledged
+
+;- Save and r0 in FIQ_Register
+            mov         r9,r0
+		    ldr         r0 , [r8, #AIC_FVR]
+            msr         CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
+
+;- Save scratch/used registers and LR in User Stack
+            stmfd       sp!, { r1-r3, r12, lr}
+
+;- Branch to the routine pointed by the AIC_FVR
+            mov         r14, pc
+            bx          r0
+
+;- Restore scratch/used registers and LR from User Stack
+            ldmia       sp!, { r1-r3, r12, lr}
+
+;- Leave Interrupts disabled and switch back in FIQ mode
+            msr         CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
+
+;- Restore the R0 ARM_MODE_SVC register
+            mov         r0,r9
+
+;- Restore the Program Counter using the LR_fiq directly in the PC
+            subs        pc,lr,#4
+
+InitReset:
+;------------------------------------------------------------------------------
+;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
+;------------------------------------------------------------------------------
+            	EXTERN   AT91F_LowLevelInit
+
+#define  __iramend 	SFB(INTRAMEND_REMAP)
+
+;- minumum C initialization
+;- call  AT91F_LowLevelInit( void)
+
+            ldr     r13,=__iramend            ; temporary stack in internal RAM
+;--Call Low level init function in ABSOLUTE through the Interworking
+		    ldr	    r0,=AT91F_LowLevelInit
+       	    mov     lr, pc
+		    bx	    r0
+;------------------------------------------------------------------------------
+;- Stack Sizes Definition
+;------------------------
+;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
+;- the vectoring. This assume that the IRQ management.
+;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
+;- Fast Interrupt not requires stack If in your application it required you must
+;- be definehere.
+;- The System stack size is not defined and is limited by the free internal
+;- SRAM.
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;- Top of Stack Definition
+;-------------------------
+;- Interrupt and Supervisor Stack are located at the top of internal memory in
+;- order to speed the exception handling context saving and restoring.
+;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
+;------------------------------------------------------------------------------
+
+IRQ_STACK_SIZE          EQU     300
+
+ARM_MODE_FIQ            EQU     0x11
+ARM_MODE_IRQ            EQU     0x12
+ARM_MODE_SVC            EQU     0x13
+
+I_BIT                   EQU     0x80
+F_BIT                   EQU     0x40
+
+;------------------------------------------------------------------------------
+;- Setup the stack for each mode
+;-------------------------------
+                ldr     r0, =__iramend
+
+;- Set up Fast Interrupt Mode and set FIQ Mode Stack
+                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
+;- Init the FIQ register
+            	ldr     r8, =AT91C_BASE_AIC
+
+;- Set up Interrupt Mode and set IRQ Mode Stack
+                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+                mov     r13, r0                     ; Init stack IRQ
+                sub     r0, r0, #IRQ_STACK_SIZE
+
+;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
+                msr     CPSR_c, #ARM_MODE_SVC
+                mov     r13, r0
+
+
+;---------------------------------------------------------------
+; ?CSTARTUP
+;---------------------------------------------------------------
+		EXTERN	__segment_init
+		EXTERN	main
+; Initialize segments.
+; __segment_init is assumed to use
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+		ldr	r0,=__segment_init
+                mov     lr, pc
+		bx	r0
+
+		PUBLIC	__main
+?jump_to_main:
+		ldr	lr,=?call_exit
+		ldr	r0,=main
+__main:
+		bx	r0
+
+;------------------------------------------------------------------------------
+;- Loop for ever
+;---------------
+;- End of application. Normally, never occur.
+;- Could jump on Software Reset ( B 0x0 ).
+;------------------------------------------------------------------------------
+?call_exit:
+End
+            b       End
+
+
+
+;---------------------------------------------------------------
+; ?EXEPTION_VECTOR
+; This module is only linked if needed for closing files.
+;---------------------------------------------------------------
+		PUBLIC	AT91F_Default_FIQ_handler
+		PUBLIC	AT91F_Default_IRQ_handler
+		PUBLIC	AT91F_Spurious_handler
+
+		CODE32	; Always ARM mode after exeption	
+
+AT91F_Default_FIQ_handler
+            b     AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+            b     AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+            b     AT91F_Spurious_handler
+
+	ENDMOD
+
+	END
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
new file mode 100644
index 000000000..a7d50f692
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
@@ -0,0 +1,94 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Cstartup_SAM7.c
+//* Object              : Low level initializations written in C for IAR
+//*                       tools
+//* 1.0   08/Sep/04 JPP	: Creation
+//* 1.10  10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
+//*----------------------------------------------------------------------------
+
+
+// Include the board file description
+#include "Board.h"
+//#include "init.h"
+#include 
+
+// The following functions must be write in ARM mode this function called directly
+// by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can be use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit( void);
+void AT91F_LowLevelInit( void ) @ "ICODE"
+{
+ int            i;
+ AT91PS_PMC     pPMC = AT91C_BASE_PMC;
+
+    //* Set Flash Waite sate
+	//  Single Cycle Access at Up to 30 MHz, or 40
+	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
+	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
+
+    //* Watchdog Disable
+        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+
+		
+	// If we are running off a j-link then the PLL will have already been setup.
+	if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) )
+	{
+		//* Set MCK at 47 923 200
+    	// 1 Enabling the Main Oscillator:
+        // SCK = 1/32768 = 30.51 uSeconde
+    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
+       	pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
+		// 2 Checking the Main Oscillator Frequency (Optional)
+		// 3 Setting PLL and divider:
+		// - div by 5 Fin = 3,6864 =(18,432 / 5)
+		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+		// for 96 MHz the erroe is 0.16%
+		//eld out NOT USED = 0 Fi
+       	pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
+                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+                         (AT91C_CKGR_MUL & (25<<16)));
+
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
+		// 4. Selection of Master Clock and Processor Clock
+        // select the PLL clock divided by 2
+
+       	pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+	
+        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+	}		
+		
+	// Set up the default interrupts handler vectors
+	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+	for (i=1;i < 31; i++)
+	{
+	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+	}
+	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
+}
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
new file mode 100644
index 000000000..7551a3648
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
@@ -0,0 +1,195 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Emac.h
+//* Object              : Emac header file
+//* Creation            : Hi   11/18/2002
+//*
+//*----------------------------------------------------------------------------
+#ifndef AT91C_EMAC_H
+#define AT91C_EMAC_H
+
+
+//* Allows to display all IP header in the main.c
+//* If not defined, only ICMP packets are displayed
+#define AT91C_DISPLAY_ALL_IPHEADER		0
+
+#define NB_RX_BUFFERS			25			//* Number of receive buffers
+#define ETH_RX_BUFFER_SIZE		128         //*
+
+#define NB_TX_BUFFERS			2		//* Number of Transmit buffers
+#define ETH_TX_BUFFER_SIZE		UIP_BUFSIZE       //*
+
+#define AT91C_NO_IPPACKET		0
+#define AT91C_IPPACKET	        1
+
+#define ARP_REQUEST				0x0001
+#define ARP_REPLY				0x0002
+#define PROT_ARP				0x0806
+#define PROT_IP					0x0800
+#define PROT_ICMP				0x01
+#define ICMP_ECHO_REQUEST		0x08
+#define ICMP_ECHO_REPLY			0x00
+
+#define AT91C_EMAC_CLKEN 0x2
+#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))
+
+#if 0
+//* Transfer descriptor structure
+typedef struct _AT91S_TdDescriptor {
+	unsigned int addr;
+	unsigned int status;
+}AT91S_TdDescriptor, *AT91PS_TdDescriptor;
+#endif
+
+//* Receive Transfer descriptor structure
+typedef struct  _AT91S_RxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:1;
+			unsigned int Rxbuf_off:2;
+			unsigned int StartOfFrame:1;
+			unsigned int EndOfFrame:1;
+			unsigned int Cfi:1;
+			unsigned int VlanPriority:3;
+			unsigned int PriorityTag:1;
+			unsigned int VlanTag:1;
+			unsigned int TypeID:1;
+			unsigned int Sa4Match:1;
+			unsigned int Sa3Match:1;
+			unsigned int Sa2Match:1;
+			unsigned int Sa1Match:1;
+			unsigned int Res1:1;
+			unsigned int ExternalAdd:1;
+			unsigned int UniCast:1;
+			unsigned int MultiCast:1;
+			unsigned int BroadCast:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
+
+
+//* Transmit Transfer descriptor structure
+typedef struct _AT91S_TxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:4;
+			unsigned int LastBuff:1;
+			unsigned int NoCrc:1;
+			unsigned int Res1:10;
+			unsigned int BufExhausted:1;
+			unsigned int TransmitUnderrun:1;
+			unsigned int TransmitError:1;
+			unsigned int Wrap:1;
+			unsigned int BuffUsed:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
+
+#define AT91C_OWNERSHIP_BIT		0x00000001
+
+/* Receive status defintion */
+#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
+#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
+#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
+#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
+#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
+#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
+#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
+#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
+#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
+#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
+#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
+#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
+#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
+#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
+#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
+#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
+#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
+#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
+#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
+#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
+#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
+
+#define ARP_ETHER	 		1		/* Ethernet  hardware address	*/
+#define ARPOP_REQUEST    	1		/* Request  to resolve  address	*/
+#define ARPOP_REPLY	    	2		/* Response to previous request	*/
+#define RARPOP_REQUEST   	3		/* Request  to resolve  address	*/
+#define RARPOP_REPLY	    4		/* Response to previous request */
+
+
+typedef struct _AT91S_EthHdr
+{
+	unsigned char		et_dest[6];	/* Destination node		*/
+	unsigned char		et_src[6];	/* Source node			*/
+	unsigned short		et_protlen;	/* Protocol or length		*/
+} AT91S_EthHdr, *AT91PS_EthHdr;
+
+typedef struct _AT91S_ArpHdr
+{
+	unsigned short		ar_hrd;		/* Format of hardware address	*/
+	unsigned short		ar_pro;		/* Format of protocol address	*/
+	unsigned char		ar_hln;		/* Length of hardware address	*/
+	unsigned char		ar_pln;		/* Length of protocol address	*/
+	unsigned short		ar_op;		/* Operation			*/
+	unsigned char		ar_sha[6];	/* Sender hardware address	*/
+	unsigned char		ar_spa[4];	/* Sender protocol address	*/
+	unsigned char		ar_tha[6];	/* Target hardware address	*/
+	unsigned char		ar_tpa[4];	/* Target protocol address	*/
+} AT91S_ArpHdr, *AT91PS_ArpHdr;
+
+//* IP Header structure
+typedef struct _AT91S_IPheader {
+	unsigned char	ip_hl_v;	/* header length and version	*/
+	unsigned char	ip_tos;		/* type of service		*/
+	unsigned short	ip_len;		/* total length			*/
+	unsigned short	ip_id;		/* identification		*/
+	unsigned short	ip_off;		/* fragment offset field	*/
+	unsigned char	ip_ttl;		/* time to live			*/
+	unsigned char	ip_p;		/* protocol			*/
+	unsigned short	ip_sum;		/* checksum			*/
+	unsigned char	ip_src[4];	/* Source IP address		*/
+	unsigned char	ip_dst[4];	/* Destination IP address	*/
+	unsigned short	udp_src;	/* UDP source port		*/
+	unsigned short	udp_dst;	/* UDP destination port		*/
+	unsigned short	udp_len;	/* Length of UDP packet		*/
+	unsigned short	udp_xsum;	/* Checksum			*/
+} AT91S_IPheader, *AT91PS_IPheader;
+
+//* ICMP echo header structure
+typedef struct _AT91S_IcmpEchoHdr {
+    unsigned char   type;       /* type of message */
+    unsigned char   code;       /* type subcode */
+    unsigned short  cksum;      /* ones complement cksum of struct */
+    unsigned short  id;         /* identifier */
+    unsigned short  seq;        /* sequence number */
+}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;
+
+
+typedef struct _AT91S_EthPack
+{
+	AT91S_EthHdr	EthHdr;
+	AT91S_ArpHdr	ArpHdr;
+} AT91S_EthPack, *AT91PS_EthPack;
+
+
+#endif //* AT91C_EMAC_H
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
new file mode 100644
index 000000000..cee31b1d5
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
@@ -0,0 +1,95 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+#include "Board.h"
+
+//*--------------------------1--------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(	char *buffer)
+{
+    AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+    unsigned int temp;
+    
+    while(*buffer != '\0') 
+    {
+        temp=0;
+        
+	while (temp==0)
+	{
+	  if ( (pDbgu->DBGU_CSR & 0x0200) == 0)
+	    temp=0;
+	  else
+	    temp=1;
+	}
+
+        pDbgu->DBGU_THR = *buffer;
+        buffer++;
+    }
+}
+
+
+void Init_DBGU_CLK(void)
+{
+  AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+void Init_DBGU_BGR(unsigned short baud)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_BRGR = (unsigned short)baud;
+}
+
+void DBGU_TX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000040;
+}
+
+void DBGU_RX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000010;
+}
+
+void DBGU_RX_TX_RST_DIS(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  pDbgu->DBGU_CR = 0x000000AC;
+}
+
+void DBGU_Parity_Cfg(unsigned int par)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_MR = par << 9;
+}
+
+
+void Init_DBGU(void)
+{ 
+  AT91F_DBGU_CfgPIO();
+  DBGU_RX_TX_RST_DIS();
+  Init_DBGU_BGR(26);  //26 <=> 115kBd
+  DBGU_Parity_Cfg(4);
+  DBGU_TX_Enable();   
+  DBGU_RX_Enable();
+}
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
new file mode 100644
index 000000000..58f50a046
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
@@ -0,0 +1,22 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+extern void APPLI_DBGU(void);   
+extern void D1_TEST_REGISTER_RESET_VALUES(void);
+extern void D2_CHIP_ID_VALUES(void);
+
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
new file mode 100644
index 000000000..cbb1ee48e
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
@@ -0,0 +1,31 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : init.c
+//* Object              : Low level initialisations written in C
+//* Creation            : ODi   06/26/2002
+//*
+//*----------------------------------------------------------------------------
+#include "board.h"
+//#include "init.h"
+#include 
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(
+	char *buffer) // \arg pointer to a string ending by \0
+{
+	while(*buffer != '\0') {
+		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
+		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
+	}
+}
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
new file mode 100644
index 000000000..df9caccb5
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
@@ -0,0 +1,4700 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X128.h
+// - Object              : AT91SAM7X128 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// - 
+// - CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X128_H
+#define AT91SAM7X128_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#ifdef __IAR_SYSTEMS_ASM__
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00008000) ;- Internal SRAM size in byte (32 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#endif /* AT91SAM7X128_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
new file mode 100644
index 000000000..742f25c6c
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
@@ -0,0 +1,4700 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X256.h
+// - Object              : AT91SAM7X256 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// - 
+// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#ifdef __IAR_SYSTEMS_ASM__
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#endif /* AT91SAM7X256_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
new file mode 100644
index 000000000..29b2f53d5
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
@@ -0,0 +1,105 @@
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_RESV                0x1c00  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+#define SPEED_10				10
+#define SPEED_100				100
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF				0x00
+#define DUPLEX_FULL				0x01
+
+/* PHY ID */
+#define MII_DM9161_ID     0x0181b8a0
+#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
+
+#define AT91C_PHY_ADDR	31
diff --git a/Demo/uIP_Demo_IAR_ARM7/main.c b/Demo/uIP_Demo_IAR_ARM7/main.c
new file mode 100644
index 000000000..c14f77d12
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/main.c
@@ -0,0 +1,252 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * Creates all the application tasks, then starts the scheduler.
+ *
+ * A task is also created called "uIP".  This executes the uIP stack and small
+ * WEB server sample.  All the other tasks are from the set of standard
+ * demo tasks.  The WEB documentation provides more details of the standard
+ * demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three
+ * seconds but has the highest priority so is guaranteed to get processor time.
+ * Its main function is to check the status of all the other demo application
+ * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
+ * should no error conditions be detected in any of the standard demo tasks.
+ * The toggle rate increasing to 500ms indicates that at least one error has
+ * been detected.
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "PollQ.h"
+#include "dynamic.h"
+#include "semtest.h"
+#include "flash.h"
+#include "integer.h"
+#include "flop.h"
+#include "BlockQ.h"
+#include "death.h"
+#include "uip_task.h"
+
+/*-----------------------------------------------------------*/
+
+/* Priorities/stacks for the demo application tasks. */
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainUIP_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainDEATH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainUIP_TASK_STACK_SIZE		( 250 )
+
+/* The rate at which the on board LED will toggle when there is/is not an
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The LED used by the check task to indicate the system status. */
+#define mainCHECK_LED 				( 3 )
+/*-----------------------------------------------------------*/
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * The task that executes at the highest priority and calls
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Atmel demo board.  This is very
+ * minimal as most of the setup is performed in the startup code.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler.
+ */
+int main( void )
+{
+	/* Configure the processor. */
+	prvSetupHardware();
+
+	/* Setup the port used to flash the LED's. */
+	vParTestInitialise();
+
+	/* Start the task that handles the TCP/IP and WEB server functionality. */
+    xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );
+	
+	/* Start the demo/test application tasks.  These are created in addition
+	to the TCP/IP task for demonstration and test purposes. */
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartLEDFlashTasks( mainFLASH_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartMathTasks( tskIDLE_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */	
+    xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Must be last to get created. */
+	vCreateSuicidalTasks( mainDEATH_PRIORITY );
+
+	/* Now all the tasks have been started - start the scheduler. */
+	vTaskStartScheduler();
+
+	/* Should never reach here because the tasks should now be executing! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* When using the JTAG debugger the hardware is not always initialised to
+	the correct default state.  This line just ensures that this does not
+	cause all interrupts to be masked at the start. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+	
+	/* Most setup is performed by the low level init function called from the
+	startup asm file.
+
+	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
+	well as the UART Tx line. */
+	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, LED_MASK );
+
+	/* Enable the peripheral clock. */
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+portTickType xLastWakeTime;
+
+	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
+	functions correctly. */
+	xLastWakeTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the Check LED flash rate will increase. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again.  The delay period is
+		shorter following an error. */
+		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without
+		error.  */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xIsCreateTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
new file mode 100644
index 000000000..277ca1f94
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
@@ -0,0 +1,194 @@
+// ---------------------------------------------------------
+//		 Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7.mac
+//
+//  1.0 08/Mar/04 JPP    : Creation
+//  1.1 23/Mar/05 JPP    : Change Variable name
+//
+//  $Revision: 1.5 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+
+execUserReset()
+{
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+}
+
+execUserPreload()
+{
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    __mac_i =__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
+    __mac_i =__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
+//* Get the chip status
+
+//* Init AIC
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+
+}
+
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+
+//-----------------------------------------------------------------------------
+// Check Remap
+//-------------
+//-----------------------------------------------------------------------------
+CheckRemap()
+{
+//* Read the value at 0x0
+    __mac_i =__readMemory32(0x00000000,"Memory");
+    __mac_i =__mac_i+1;
+    __writeMemory32(__mac_i,0x00,"Memory");
+    __mac_pt =__readMemory32(0x00000000,"Memory");
+    
+ if (__mac_i == __mac_pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+   
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+ }
+
+}
+
+
+execUserSetup()
+{
+ ini();
+     __message "-------------------------------Set PC ----------------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock  Peripheral Clock Disable Register
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+    __readMemory32(0xFFFA0020,"Memory");
+    __readMemory32(0xFFFA0060,"Memory");
+    __readMemory32(0xFFFA00A0,"Memory");
+
+    for (__mac_i=0;__mac_i < 8; __mac_i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
+__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
+__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
+
+__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
+
+}
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
new file mode 100644
index 000000000..63228c346
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
@@ -0,0 +1,227 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7_RAM.mac
+//
+//  1.0 08/Mar/05 JPP    : Creation
+//  1.1 23/Mar/05 JPP    : Change Variable name
+//
+//  $Revision: 1.6 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+__var __mac_mem;
+execUserReset()
+{
+     CheckNoRemap();
+     ini();
+     AIC();
+     __message "-------------------------------Set PC Reset ----------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+execUserPreload()
+{
+//*  __message "-------------------------------Set CPSR  ----------------------------------";  
+     __writeMemory32(0xD3,0x98,"Register"); 
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+     PllSetting();
+ //* Init AIC
+     AIC();
+
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckNoRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    __mac_i=__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
+    __mac_i=__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
+    __mac_i=__readMemory32(0xFFFFFF6C,"Memory");
+    __message " ---------------------------------------- Flash Version 0x",__mac_i:%X;  
+
+//*  Watchdog Disable
+    Watchdog();
+//*    RG();
+}
+//-----------------------------------------------------------------------------
+// PllSetting
+//-------------------------------
+// Set PLL
+//-----------------------------------------------------------------------------
+PllSetting()
+{
+// -1- Enabling the Main Oscillator:
+//*#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+//*#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+//*#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |    //0x0000 0600
+//                          AT91C_CKGR_MOSCEN ));          //0x0000 0001 
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
+
+// -2- Wait
+// -3- Setting PLL and divider:
+// - div by 5 Fin = 3,6864 =(18,432 / 5)
+// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+// for 96 MHz the erroe is 0.16%
+// Field out NOT USED = 0
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+// PLLCOUNT 28 = 0.000844 /(1/32768)
+//       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |       //0x0000 0005
+//                         (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
+//                         (AT91C_CKGR_MUL & (25<<16)));   //0x0019 0000 
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
+// -2- Wait
+// -5- Selection of Master Clock and Processor Clock
+// select the PLL clock divided by 2
+//	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |     //0x0000 0003
+//                           AT91C_PMC_PRES_CLK_2 ;      //0x0000 0004
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory");        
+       
+
+   __message "------------------------------- PLL  Enable ----------------------------------------";  
+}
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+CheckNoRemap()
+{
+//* Read the value at 0x0
+    __mac_i =__readMemory32(0x00000000,"Memory");
+    __mac_mem = __mac_i;
+    __mac_i=__mac_i+1;
+    __writeMemory32(__mac_i,0x00,"Memory");
+    __mac_pt=__readMemory32(0x00000000,"Memory");
+    
+ if (__mac_i == __mac_pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+   __writeMemory32( __mac_mem,0x00000000,"Memory");
+  
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+ }
+
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock  Peripheral Clock Disable Register
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+    __readMemory32(0xFFFA0020,"Memory");
+    __readMemory32(0xFFFA0060,"Memory");
+    __readMemory32(0xFFFA00A0,"Memory");
+    for (__mac_i=0;__mac_i < 8; __mac_i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
+__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
+__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
+
+__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
+
+}
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl b/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
new file mode 100644
index 000000000..95fa2e1de
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
@@ -0,0 +1,135 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91SAM7x256_NoRemap.xlc
+//
+//
+//  $Revision: 1.1.1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage:  xlink  -f lnkarm  
+//                -s   
+//
+// $Revision: 1.1.1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S64 Memory mapping
+// No remap
+//  ROMSTART
+//  Start address 0x0000 0000 
+//  Size  256 Kbo 0x0004 0000 
+//  RAMSTART
+//  Start address 0x0020 0000 
+//  Size  64Kbo   0x0001 0000 
+// Remap done
+//  RAMSTART
+//  Start address 0x0000 0000 
+//  Size  64Kbo   0x0001 0000 
+//  ROMSTART
+//  Start address 0x0010 0000 
+//  Size  256Kbo  0x0004 0000 
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 64K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00200000
+-Z(CONST)INTRAMEND_REMAP=0020FFFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 256K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0003FFFF
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+-DRAMSTART=00200000
+-DRAMEND=00200FFFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes, 
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+//-D_CSTACK_SIZE=(400*4)
+//-D_IRQ_STACK_SIZE=(2*8*4)
+
+//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+//   "-yn": Suppress DWARF debug output
+//   "-yp": Multiple ELF program sections
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf
diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep
new file mode 100644
index 000000000..04b6ad8ff
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep
@@ -0,0 +1,1590 @@
+
+
+
+  2
+  
+    Flash Debug
+    
+      $PROJ_DIR$\uip\uipopt.h
+      $PROJ_DIR$\uip\fsdata.h
+      $TOOLKIT_DIR$\inc\intrinsic.h
+      $PROJ_DIR$\Flash_Debug\Obj\uip_arp.r79
+      $PROJ_DIR$\Flash_Debug\Obj\queue.r79
+      $PROJ_DIR$\Flash_Debug\Obj\ParTest.r79
+      $PROJ_DIR$\Flash_Debug\Obj\list.r79
+      $PROJ_DIR$\Flash_Debug\Obj\PollQ.r79
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\lib_AT91SAM7X256.h
+      $PROJ_DIR$\uip\uip.c
+      $PROJ_DIR$\..\..\Source\tasks.c
+      $PROJ_DIR$\..\..\Source\include\semphr.h
+      $PROJ_DIR$\uip\cgi.c
+      $PROJ_DIR$\uip\fs.c
+      $PROJ_DIR$\uip\httpd.c
+      $PROJ_DIR$\Flash_Debug\Obj\death.r79
+      $PROJ_DIR$\SrcIAR\Board.h
+      $PROJ_DIR$\..\Common\include\BlockQ.h
+      $PROJ_DIR$\..\..\Source\include\portable.h
+      $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c
+      $PROJ_DIR$\SrcIAR\Cstartup.s79
+      $PROJ_DIR$\uip\uip_arp.c
+      $PROJ_DIR$\uip\uip_arch.c
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\ISR_Support.h
+      $PROJ_DIR$\Flash_Debug\Obj\BlockQ.r79
+      $PROJ_DIR$\Flash_Debug\Obj\heap_2.r79
+      $PROJ_DIR$\SrcIAR\Emac.h
+      $PROJ_DIR$\Flash_Debug\Obj\httpd.r79
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256_inc.h
+      $PROJ_DIR$\EMAC\SAM7_EMAC.h
+      $PROJ_DIR$\Flash_Debug\Obj\main.pbi
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256.h
+      $PROJ_DIR$\Flash_Debug\Obj\integer.r79
+      $PROJ_DIR$\Flash_Debug\Obj\portasm.r79
+      $PROJ_DIR$\uip\httpd.h
+      $PROJ_DIR$\Flash_Debug\Obj\SAM7_EMAC.r79
+      $PROJ_DIR$\Flash_Debug\Obj\dynamic.r79
+      $PROJ_DIR$\resource\at91SAM7X256_NoRemap.xcl
+      $PROJ_DIR$\..\Common\Minimal\death.c
+      $PROJ_DIR$\Flash_Debug\Obj\BlockQ.pbi
+      $TOOLKIT_DIR$\inc\DLib_Threads.h
+      $PROJ_DIR$\Flash_Debug\Obj\cgi.r79
+      $PROJ_DIR$\Flash_Debug\Obj\integer.pbi
+      $PROJ_DIR$\Flash_Debug\Exe\rtosdemo.sim
+      $PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.r79
+      $PROJ_DIR$\..\Common\include\death.h
+      $TOOLKIT_DIR$\inc\stddef.h
+      $PROJ_DIR$\Flash_Debug\Obj\main.r79
+      $PROJ_DIR$\Flash_Debug\Obj\port.r79
+      $PROJ_DIR$\Flash_Debug\Obj\flop.r79
+      $PROJ_DIR$\Flash_Debug\Obj\Cstartup.r79
+      $PROJ_DIR$\..\..\Source\include\croutine.h
+      $PROJ_DIR$\Flash_Debug\Obj\queue.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.pbi
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7S64_inc.h
+      $PROJ_DIR$\Flash_Debug\Obj\flash.r79
+      $PROJ_DIR$\..\Common\include\integer.h
+      $PROJ_DIR$\Flash_Debug\Obj\semtest.r79
+      $TOOLKIT_DIR$\inc\string.h
+      $PROJ_DIR$\uip\tapdev.h
+      $PROJ_DIR$\Flash_Debug\Obj\list.pbi
+      $PROJ_DIR$\..\Common\include\semtest.h
+      $PROJ_DIR$\uip\uip_arp.h
+      $PROJ_DIR$\uip\fs.h
+      $PROJ_DIR$\..\Common\include\partest.h
+      $PROJ_DIR$\..\..\Source\include\list.h
+      $TOOLKIT_DIR$\inc\stdlib.h
+      $PROJ_DIR$\Flash_Debug\Obj\fs.r79
+      $PROJ_DIR$\..\..\Source\include\task.h
+      $TOOLKIT_DIR$\inc\xencoding_limits.h
+      $PROJ_DIR$\..\Common\include\PollQ.h
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h
+      $PROJ_DIR$\Flash_Debug\Exe\rtosdemo.d79
+      $PROJ_DIR$\Flash_Debug\Obj\dynamic.pbi
+      $TOOLKIT_DIR$\lib\dl4tptinl8n.h
+      $PROJ_DIR$\..\Common\Minimal\semtest.c
+      $PROJ_DIR$\uip\fsdata.c
+      $PROJ_DIR$\Flash_Debug\Obj\fs.pbi
+      $PROJ_DIR$\Flash_Debug\List\rtosdemo.map
+      $PROJ_DIR$\Flash_Debug\Obj\uIP_Task.r79
+      $PROJ_DIR$\Flash_Debug\Obj\EMAClISR.r79
+      $PROJ_DIR$\Flash_Debug\Obj\semtest.pbi
+      $PROJ_DIR$\uip\uip.h
+      $PROJ_DIR$\ParTest\ParTest.c
+      $TOOLKIT_DIR$\inc\stdio.h
+      $PROJ_DIR$\Flash_Debug\Obj\death.pbi
+      $PROJ_DIR$\uIP_Task.c
+      $PROJ_DIR$\..\Common\Minimal\PollQ.c
+      $PROJ_DIR$\EMAC\SAM7_EMAC.c
+      $PROJ_DIR$\..\Common\include\flop.h
+      $PROJ_DIR$\..\Common\include\flash.h
+      $PROJ_DIR$\uip\cgi.h
+      $PROJ_DIR$\..\..\Source\include\FreeRTOS.h
+      $TOOLKIT_DIR$\inc\DLib_Product.h
+      $PROJ_DIR$\uIP_Task.h
+      $PROJ_DIR$\Flash_Debug\Obj\uip_arch.r79
+      $TOOLKIT_DIR$\inc\DLib_Defaults.h
+      $PROJ_DIR$\FreeRTOSConfig.h
+      $PROJ_DIR$\Flash_Debug\Obj\rtosdemo.pbd
+      $PROJ_DIR$\Flash_Debug\Obj\heap_2.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\port.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\uip.pbi
+      $TOOLKIT_DIR$\inc\yvals.h
+      $TOOLKIT_DIR$\inc\ysizet.h
+      $PROJ_DIR$\Flash_Debug\Obj\uip.r79
+      $PROJ_DIR$\uip\uip_arch.h
+      $PROJ_DIR$\..\Common\include\dynamic.h
+      $PROJ_DIR$\Flash_Debug\Obj\uip_arch.pbi
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c
+      $PROJ_DIR$\..\Common\Minimal\dynamic.c
+      $PROJ_DIR$\EMAC\EMAClISR.s79
+      $PROJ_DIR$\..\Common\Minimal\flash.c
+      $PROJ_DIR$\..\..\Source\include\projdefs.h
+      $PROJ_DIR$\Flash_Debug\Obj\flop.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\uIP_Task.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\cgi.pbi
+      $PROJ_DIR$\Flash_Debug\Obj\tasks.r79
+      $PROJ_DIR$\Flash_Debug\Obj\PollQ.pbi
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79
+      $PROJ_DIR$\Flash_Debug\Obj\httpd.pbi
+      $TOOLKIT_DIR$\inc\intrinsics.h
+      $PROJ_DIR$\Flash_Debug\Obj\flash.pbi
+      $TOOLKIT_DIR$\inc\ymath.h
+      $PROJ_DIR$\Flash_Debug\Obj\uip_arp.pbi
+      $TOOLKIT_DIR$\lib\dl4tptinl8n.r79
+      $PROJ_DIR$\..\..\Source\queue.c
+      $PROJ_DIR$\Flash_Debug\Obj\SAM7_EMAC.pbi
+      $PROJ_DIR$\..\Common\Minimal\flop.c
+      $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c
+      $PROJ_DIR$\..\Common\Minimal\integer.c
+      $PROJ_DIR$\main.c
+      $PROJ_DIR$\Flash_Debug\Obj\tasks.pbi
+      $PROJ_DIR$\..\..\Source\list.c
+      $PROJ_DIR$\Flash_Debug\Obj\ParTest.pbi
+      $PROJ_DIR$\SrcIAR\mii.h
+      $PROJ_DIR$\..\..\Source\include\queue.h
+      $TOOLKIT_DIR$\inc\math.h
+      $PROJ_DIR$\..\Common\Minimal\BlockQ.c
+    
+    
+      $PROJ_DIR$\uip\uip.c
+      
+        
+          ICCARM
+           104
+        
+        
+          BICOMP
+           101
+        
+      
+      
+        
+          ICCARM
+           82 0 34 105
+        
+        
+          BICOMP
+           82 0 34 105
+        
+      
+    
+    
+      $PROJ_DIR$\..\..\Source\tasks.c
+      
+        
+          ICCARM
+           116
+        
+        
+          BICOMP
+           131
+        
+      
+      
+        
+          ICCARM
+           84 102 96 74 93 69 103 66 58 92 46 112 97 2 16 31 8 18 71 68 65
+        
+        
+          BICOMP
+           84 102 96 93 69 40 103 66 58 92 46 112 97 2 120 16 31 8 18 71 68 65
+        
+      
+    
+    
+      $PROJ_DIR$\uip\cgi.c
+      
+        
+          ICCARM
+           41
+        
+        
+          BICOMP
+           115
+        
+      
+      
+        
+          ICCARM
+           82 0 34 91 63 84 102 96 74 93 69 103 58
+        
+        
+          BICOMP
+           82 0 34 91 63 84 102 96 93 69 40 103 58
+        
+      
+    
+    
+      $PROJ_DIR$\uip\fs.c
+      
+        
+          ICCARM
+           67
+        
+        
+          BICOMP
+           77
+        
+      
+      
+        
+          ICCARM
+           82 0 34 63 1 76
+        
+        
+          BICOMP
+           82 0 34 63 1 76
+        
+      
+    
+    
+      $PROJ_DIR$\uip\httpd.c
+      
+        
+          ICCARM
+           27
+        
+        
+          BICOMP
+           119
+        
+      
+      
+        
+          ICCARM
+           82 0 34 63 1 91
+        
+        
+          BICOMP
+           82 0 34 63 1 91
+        
+      
+    
+    
+      $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c
+      
+        
+          ICCARM
+           44
+        
+        
+          BICOMP
+           53
+        
+      
+      
+        
+          ICCARM
+           16 31 8 58 102 96 74 93 69 103
+        
+        
+          BICOMP
+           16 31 8 58 102 96 93 69 40 103
+        
+      
+    
+    
+      $PROJ_DIR$\SrcIAR\Cstartup.s79
+      
+        
+          AARM
+           50
+        
+      
+      
+        
+          AARM
+           28
+        
+      
+    
+    
+      $PROJ_DIR$\uip\uip_arp.c
+      
+        
+          ICCARM
+           3
+        
+        
+          BICOMP
+           123
+        
+      
+      
+        
+          ICCARM
+           62 82 0 34 58 102 96 74 93 69 103
+        
+        
+          BICOMP
+           62 82 0 34 58 102 96 93 69 40 103
+        
+      
+    
+    
+      $PROJ_DIR$\uip\uip_arch.c
+      
+        
+          ICCARM
+           95
+        
+        
+          BICOMP
+           107
+        
+      
+      
+        
+          ICCARM
+           82 0 34 105
+        
+        
+          BICOMP
+           82 0 34 105
+        
+      
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\death.c
+      
+        
+          ICCARM
+           15
+        
+        
+          BICOMP
+           85
+        
+      
+      
+        
+          ICCARM
+           66 102 96 74 93 69 103 92 46 112 97 2 16 31 8 18 71 68 65 45
+        
+        
+          BICOMP
+           66 102 96 93 69 40 103 92 46 112 97 2 120 16 31 8 18 71 68 65 45
+        
+      
+    
+    
+      $PROJ_DIR$\Flash_Debug\Exe\rtosdemo.d79
+      
+        
+          XLINK
+           78 43
+        
+      
+      
+        
+          XLINK
+           37 24 50 44 80 5 7 35 41 15 36 55 49 67 25 27 32 6 47 48 33 4 57 116 79 104 95 3 124
+        
+      
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\semtest.c
+      
+        
+          ICCARM
+           57
+        
+        
+          BICOMP
+           81
+        
+      
+      
+        
+          ICCARM
+           66 102 96 74 93 69 103 92 46 112 97 2 16 31 8 18 71 68 65 11 135 61
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diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd
new file mode 100644
index 000000000..88dde96a3
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd
@@ -0,0 +1,913 @@
+
+
+
+  1
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+        1
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+        1
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+
diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp
new file mode 100644
index 000000000..5d133f4b6
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp
@@ -0,0 +1,1780 @@
+
+
+
+  1
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+      $PROJ_DIR$\..\Common\Minimal\BlockQ.c
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+      $PROJ_DIR$\..\Common\Minimal\death.c
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+      $PROJ_DIR$\..\Common\Minimal\dynamic.c
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+      $PROJ_DIR$\EMAC\EMAClISR.s79
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+      $PROJ_DIR$\..\Common\Minimal\flop.c
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+      $PROJ_DIR$\ParTest\ParTest.c
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+      $PROJ_DIR$\..\Common\Minimal\PollQ.c
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+      $PROJ_DIR$\EMAC\SAM7_EMAC.c
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+      $PROJ_DIR$\..\Common\Minimal\semtest.c
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+    
+      $PROJ_DIR$\uIP_Task.c
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+  
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+    FreeRTOS Source
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+      $PROJ_DIR$\..\..\Source\list.c
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+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c
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+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79
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+      $PROJ_DIR$\..\..\Source\queue.c
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+      $PROJ_DIR$\..\..\Source\tasks.c
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+    uIP Source
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+      http
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+        $PROJ_DIR$\uip\cgi.c
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+      
+        $PROJ_DIR$\uip\fs.c
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+      
+        $PROJ_DIR$\uip\httpd.c
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+      $PROJ_DIR$\uip\uip.c
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+      $PROJ_DIR$\uip\uip_arch.c
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+      $PROJ_DIR$\uip\uip_arp.c
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+  
+  
+    $PROJ_DIR$\SrcIAR\Cstartup.s79
+  
+  
+    $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c
+  
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww
new file mode 100644
index 000000000..2294aacb5
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww
@@ -0,0 +1,10 @@
+
+
+
+  
+    $WS_DIR$\rtosdemo.ewp
+  
+  
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt b/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt
new file mode 100644
index 000000000..5085f2cdb
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt
@@ -0,0 +1,71 @@
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+    TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c010378378TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\tasks.c09393051130511TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s7904822262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s7904110571079TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h02778108450108450TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c0136532653267TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h067000100000010000001
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diff --git a/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni b/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni
new file mode 100644
index 000000000..9b68f65a8
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni
@@ -0,0 +1,23 @@
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diff --git a/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt b/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt
new file mode 100644
index 000000000..2ce5c4bb0
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+++ b/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt
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new file mode 100644
index 000000000..b1dd7f561
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diff --git a/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni b/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni
new file mode 100644
index 000000000..4bdd38699
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni
@@ -0,0 +1,25 @@
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diff --git a/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt b/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt
new file mode 100644
index 000000000..7dbc0e7fe
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diff --git a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
new file mode 100644
index 000000000..24f0bc3ee
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
@@ -0,0 +1,207 @@
+/*
+ * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $
+ *
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "SAM7_EMAC.h"
+
+/* uIP includes. */
+#undef HTONS
+#include "uip.h"
+#include "uip_arp.h"
+#include "tapdev.h"
+#include "httpd.h"
+
+/* The start of the uIP buffer, which will contain the frame headers. */
+#define pucUIP_Buffer ( ( struct uip_eth_hdr * ) &uip_buf[ 0 ] )
+
+/* uIP update frequencies. */
+#define RT_CLOCK_SECOND		( configTICK_RATE_HZ  )
+#define uipARP_FREQUENCY	( 20 )
+#define uipMAX_BLOCK_TIME	( RT_CLOCK_SECOND / 4 )
+
+/*-----------------------------------------------------------*/
+
+void vuIP_TASK( void *pvParameters )
+{
+/* The semaphore used by the EMAC ISR to indicate that an Rx frame is ready
+for processing. */
+xSemaphoreHandle xSemaphore = NULL;
+portBASE_TYPE xARPTimer;
+unsigned portBASE_TYPE uxPriority;
+static volatile portTickType xStartTime, xCurrentTime;
+
+	/* Initialize the uIP TCP/IP stack. */
+	uip_init();
+	uip_arp_init();
+	
+	/* Initialize the HTTP server. */
+	httpd_init();
+
+	/* Initialise the local timers. */
+	xStartTime = xTaskGetTickCount();
+	xARPTimer = 0;
+
+	/* Initialise the EMAC.  A semaphore will be returned when this is
+	successful. This routine contains code that polls status bits.  If the
+	Ethernet cable is not plugged in then this can take a considerable time.
+	To prevent this starving lower priority tasks of processing time we
+	lower our priority prior to the call, then raise it back again once the
+	initialisation is complete. */
+	uxPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+	while( xSemaphore == NULL )
+	{
+		xSemaphore = xEMACInit();
+	}
+	vTaskPrioritySet( NULL, uxPriority );
+
+	for( ;; )
+	{
+		/* Let the network device driver read an entire IP packet
+		into the uip_buf. If it returns > 0, there is a packet in the
+		uip_buf buffer. */
+		uip_len = ulEMACPoll();
+
+		/* Was a packet placed in the uIP buffer? */
+		if( uip_len > 0 )
+		{
+			/* A packet is present in the uIP buffer. We call the
+			appropriate ARP functions depending on what kind of packet we
+			have received. If the packet is an IP packet, we should call
+			uip_input() as well. */
+			if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_IP ) )
+			{
+				uip_arp_ipin();
+				uip_input();
+
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */
+				if( uip_len > 0 )
+				{
+					uip_arp_out();
+					lEMACSend();
+				}
+			}
+			else if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_ARP ) )
+			{
+				uip_arp_arpin();
+
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */	
+				if( uip_len > 0 )
+				{	
+					lEMACSend();
+				}
+			}
+		}
+		else
+		{
+			/* The poll function returned 0, so no packet was
+			received. Instead we check if it is time that we do the
+			periodic processing. */
+			xCurrentTime = xTaskGetTickCount();
+
+			if( ( xCurrentTime - xStartTime ) >= RT_CLOCK_SECOND )
+			{
+				portBASE_TYPE i;
+
+				/* Reset the timer. */
+				xStartTime = xCurrentTime;
+
+				/* Periodic check of all connections. */
+				for( i = 0; i < UIP_CONNS; i++ )
+				{
+					uip_periodic( i );
+
+					/* If the above function invocation resulted in data that
+					should be sent out on the network, the global variable
+					uip_len is set to a value > 0. */					
+					if( uip_len > 0 )
+					{
+						uip_arp_out();
+						lEMACSend();
+					}
+				}
+
+				#if UIP_UDP
+					for( i = 0; i < UIP_UDP_CONNS; i++ )
+					{
+						uip_udp_periodic( i );
+
+						/* If the above function invocation resulted in data that
+						should be sent out on the network, the global variable
+						uip_len is set to a value > 0. */
+						if( uip_len > 0 )
+						{
+							uip_arp_out();
+							tapdev_send();
+						}
+					}
+				#endif /* UIP_UDP */
+
+				/* Periodically call the ARP timer function. */
+				if( ++xARPTimer == uipARP_FREQUENCY )
+				{	
+					uip_arp_timer();
+					xARPTimer = 0;
+				}
+			}
+			else
+			{				
+				/* We did not receive a packet, and there was no periodic
+				processing to perform.  Block for a fixed period.  If a packet
+				is received during this period we will be woken by the ISR
+				giving us the Semaphore. */
+				xSemaphoreTake( xSemaphore, uipMAX_BLOCK_TIME );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------------------------------*/
+
+
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
new file mode 100644
index 000000000..aae424ba0
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
@@ -0,0 +1,8 @@
+#ifndef UIP_TASK_H
+#define UIP_TASK_H
+
+/* The task that handles all uIP data. */
+void vuIP_TASK( void *pvParameters );
+
+#endif
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/Makefile b/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
new file mode 100644
index 000000000..61d3a06aa
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
@@ -0,0 +1,74 @@
+# Copyright (c) 2001, Adam Dunkels.
+# All rights reserved. 
+#
+# Redistribution and use in source and binary forms, with or without 
+# modification, are permitted provided that the following conditions 
+# are met: 
+# 1. Redistributions of source code must retain the above copyright 
+#    notice, this list of conditions and the following disclaimer. 
+# 2. Redistributions in binary form must reproduce the above copyright 
+#    notice, this list of conditions and the following disclaimer in the 
+#    documentation and/or other materials provided with the distribution. 
+# 3. All advertising materials mentioning features or use of this software
+#    must display the following acknowledgement:
+#      This product includes software developed by Adam Dunkels.
+# 4. The name of the author may not be used to endorse or promote
+#    products derived from this software without specific prior
+#    written permission.  
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+#
+# This file is part of the uIP TCP/IP stack.
+#
+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $
+#
+
+CC=gcc
+CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp  -I../apps/telnet -fpack-struct
+
+%.o:
+	$(CC) $(CFLAGS) -c $(<:.o=.c)
+
+
+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o 
+
+tapdev.o: tapdev.c uipopt.h
+main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \
+ tapdev.h
+uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h 
+uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h 
+
+uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h
+	$(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c
+
+
+cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h
+fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \
+ ../apps/httpd/fsdata.c
+fsdata.o: ../apps/httpd/fsdata.c
+httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \
+ ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \
+ ../apps/httpd/fsdata.h ../apps/httpd/cgi.h
+
+clean:
+	rm -f *.o *~ *core uip
+
+
+
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
new file mode 100644
index 000000000..748cc1b5d
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
@@ -0,0 +1,225 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server script language C functions file.
+ * \author Adam Dunkels 
+ *
+ * This file contains functions that are called by the web server
+ * scripts. The functions takes one argument, and the return value is
+ * interpreted as follows. A zero means that the function did not
+ * complete and should be invoked for the next packet as well. A
+ * non-zero value indicates that the function has completed and that
+ * the web server should move along to the next script line.
+ *
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "cgi.h"
+#include "httpd.h"
+#include "fs.h"
+
+#include 
+#include 
+
+static u8_t print_stats(u8_t next);
+static u8_t file_stats(u8_t next);
+static u8_t tcp_stats(u8_t next);
+static u8_t rtos_stats(u8_t next);
+
+cgifunction cgitab[] = {
+  print_stats,   /* CGI function "a" */
+  file_stats,    /* CGI function "b" */
+  tcp_stats,      /* CGI function "c" */
+  rtos_stats	/* CGI function "d" */
+};
+
+static const char closed[] =   /*  "CLOSED",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
+ 0x44,  0};
+static const char syn_sent[] = /*  "SYN-SENT",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
+ 0x54,  0};
+static const char established[] = /*  "ESTABLISHED",*/
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
+ 0x45, 0x44, 0};
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x31, 0};
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x32, 0};
+static const char closing[] = /*  "CLOSING",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x49,
+ 0x4e, 0x47, 0};
+static const char time_wait[] = /*  "TIME-WAIT,"*/
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
+ 0x49, 0x54, 0};
+static const char last_ack[] = /*  "LAST-ACK"*/
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
+ 0x4b, 0};
+
+static const char *states[] = {
+  closed,
+  syn_rcvd,
+  syn_sent,
+  established,
+  fin_wait_1,
+  fin_wait_2,
+  closing,
+  time_wait,
+  last_ack};
+
+
+/*-----------------------------------------------------------------------------------*/
+/* print_stats:
+ *
+ * Prints out a part of the uIP statistics. The statistics data is
+ * written into the uip_appdata buffer. It overwrites any incoming
+ * packet.
+ */
+static u8_t
+print_stats(u8_t next)
+{
+#if UIP_STATISTICS
+  u16_t i, j;
+  u8_t *buf;
+  u16_t *databytes;
+
+  if(next) {
+    /* If our last data has been acknowledged, we move on the next
+       chunk of statistics. */
+    hs->count = hs->count + 4;
+    if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {
+      /* We have printed out all statistics, so we return 1 to
+	 indicate that we are done. */
+      return 1;
+    }
+  }
+
+  /* Write part of the statistics into the uip_appdata buffer. */
+  databytes = (u16_t *)&uip_stat + hs->count;
+  buf       = (u8_t *)uip_appdata;
+
+  j = 4 + 1;
+  i = hs->count;
+  while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {
+    sprintf((char *)buf, "%5u\r\n", *databytes);
+    ++databytes;
+    buf += 6;
+    ++i;
+  }
+
+  /* Send the data. */
+  uip_send(uip_appdata, buf - uip_appdata);
+
+  return 0;
+#else
+  return 1;
+#endif /* UIP_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+file_stats(u8_t next)
+{
+  /* We use sprintf() to print the number of file accesses to a
+     particular file (given as an argument to the function in the
+     script). We then use uip_send() to actually send the data. */
+  if(next) {
+    return 1;
+  }
+  uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4])));
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+tcp_stats(u8_t next)
+{
+  struct uip_conn *conn;
+
+  if(next) {
+    /* If the previously sent data has been acknowledged, we move
+       forward one connection. */
+    if(++hs->count == UIP_CONNS) {
+      /* If all connections has been printed out, we are done and
+	 return 1. */
+      return 1;
+    }
+  }
+
+  conn = &uip_conns[hs->count];
+  if((conn->tcpstateflags & TS_MASK) == CLOSED) {
+    uip_send(uip_appdata, sprintf((char *)uip_appdata,
+				  "--%u%u%c %c\r\n",
+				  conn->nrtx,
+				  conn->timer,
+				  (uip_outstanding(conn))? '*':' ',
+    				  (uip_stopped(conn))? '!':' '));
+  } else {
+    uip_send(uip_appdata, sprintf((char *)uip_appdata,
+				  "%u.%u.%u.%u:%u%s%u%u%c %c\r\n",
+				  htons(conn->ripaddr[0]) >> 8,
+				  htons(conn->ripaddr[0]) & 0xff,
+				  htons(conn->ripaddr[1]) >> 8,
+				  htons(conn->ripaddr[1]) & 0xff,
+				  htons(conn->rport),
+				  states[conn->tcpstateflags & TS_MASK],
+				  conn->nrtx,
+				  conn->timer,
+				  (uip_outstanding(conn))? '*':' ',
+    				  (uip_stopped(conn))? '!':' '));
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+
+static u8_t
+rtos_stats(u8_t next)
+{
+static char cTraceBuffer[ 1024 ];
+extern void ( vTaskList )( char * );
+
+	vTaskList( cTraceBuffer );
+	uip_send( ( void * ) cTraceBuffer, strlen( cTraceBuffer ) );
+
+	return 1;
+}
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h
new file mode 100644
index 000000000..d85389b52
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h
@@ -0,0 +1,57 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP script language header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+#ifndef __CGI_H__
+#define __CGI_H__
+
+typedef u8_t (* cgifunction)(u8_t next);
+
+/**
+ * A table containing pointers to C functions that can be called from
+ * a web server script.
+ */
+extern cgifunction cgitab[];
+
+#endif /* __CGI_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm b/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm
new file mode 100644
index 000000000..ef91f42a8
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm
@@ -0,0 +1,66 @@
+// Rowley C Compiler, runtime support.
+//
+// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited.
+//
+// This file may be distributed under the terms of the License Agreement
+// provided with this software.
+//
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+
+; Create sections
+        .data
+        .bss
+
+; Go to code section.
+        .code
+
+; Executed upon reset
+__reset proc
+
+; Turn off watchdog.  You can enable it in main() if required.
+        mov.w   #0x5a80, &0x120
+
+; Set up stack.
+        mov.w   #RAM_Start_Address+RAM_Size, sp
+
+; Copy from initialised data section to data section.
+        mov.w   #SFB(IDATA0), r15
+        mov.w   #data_init_begin, r14
+        mov.w   #data_init_end-data_init_begin, r13
+        call    #_memcpy
+
+; Zero the bss.  Ensure the stack is not allocated in the bss!
+        mov.w   #SFB(UDATA0), r15
+        mov.w   #0, r14
+        mov.w   #SFE(UDATA0)-SFB(UDATA0), r13
+        call    #_memset
+
+; Call user entry point void main(void).
+        call    #_main
+
+; If main() returns, kick off again.
+        jmp     __reset
+        endproc
+
+; Heap data structures; removed by the linker if the heap isn't used.
+        .break   
+        .data
+        align   WORD
+___heap_start__::
+        DW      0
+        DW      heap_size
+        DS      heap_size-4    
+
+; Reset vector
+        .vectors
+        .keep
+        org     0x1e
+        dw      __reset
+
+; Initialise the IDATA0 section by duplicating the contents into the
+; CONST section and copying them on startup.
+        .const
+data_init_begin:
+        .init  "IDATA0"
+data_init_end:
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs.c b/Demo/uIP_Demo_IAR_ARM7/uip/fs.c
new file mode 100644
index 000000000..a66eb8dc3
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs.c
@@ -0,0 +1,156 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server read-only file system code.
+ * \author Adam Dunkels 
+ *
+ * A simple read-only filesystem.
+ */
+
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $
+ */
+
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+#include "fsdata.h"
+
+#define NULL (void *)0
+#include "fsdata.c"
+
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+static u16_t count[FS_NUMFILES];
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+fs_strcmp(const char *str1, const char *str2)
+{
+  u8_t i;
+  i = 0;
+ loop:
+
+  if(str2[i] == 0 ||
+     str1[i] == '\r' ||
+     str1[i] == '\n') {
+    return 0;
+  }
+
+  if(str1[i] != str2[i]) {
+    return 1;
+  }
+
+
+  ++i;
+  goto loop;
+}
+/*-----------------------------------------------------------------------------------*/
+int
+fs_open(const char *name, struct fs_file *file)
+{
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t i = 0;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+  struct fsdata_file_noconst *f;
+
+  for(f = (struct fsdata_file_noconst *)FS_ROOT;
+      f != NULL;
+      f = (struct fsdata_file_noconst *)f->next) {
+
+    if(fs_strcmp(name, f->name) == 0) {
+      file->data = f->data;
+      file->len = f->len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+      ++count[i];
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+      return 1;
+    }
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+    ++i;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+void
+fs_init(void)
+{
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t i;
+  for(i = 0; i < FS_NUMFILES; i++) {
+    count[i] = 0;
+  }
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+u16_t fs_count
+(char *name)
+{
+  struct fsdata_file_noconst *f;
+  u16_t i;
+
+  i = 0;
+  for(f = (struct fsdata_file_noconst *)FS_ROOT;
+      f != NULL;
+      f = (struct fsdata_file_noconst *)f->next) {
+
+    if(fs_strcmp(name, f->name) == 0) {
+      return count[i];
+    }
+    ++i;
+  }
+  return 0;
+}
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs.h b/Demo/uIP_Demo_IAR_ARM7/uip/fs.h
new file mode 100644
index 000000000..65551ba41
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs.h
@@ -0,0 +1,80 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server read-only file system header file.
+ * \author Adam Dunkels 
+ */
+ 
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $
+ */
+#ifndef __FS_H__
+#define __FS_H__
+
+#include "uip.h"
+
+/**
+ * An open file in the read-only file system.
+ */
+struct fs_file {
+  char *data;  /**< The actual file data. */
+  int len;     /**< The length of the file data. */
+};
+
+/**
+ * Open a file in the read-only file system.
+ *
+ * \param name The name of the file.
+ *
+ * \param file The file pointer, which must be allocated by caller and
+ * will be filled in by the function.
+ */
+int fs_open(const char *name, struct fs_file *file);
+
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1  
+u16_t fs_count(char *name);
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+/**
+ * Initialize the read-only file system.
+ */
+void fs_init(void);
+
+#endif /* __FS_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html
new file mode 100644
index 000000000..8d6beec83
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html
@@ -0,0 +1 @@
+
404 - file not found

\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files
new file mode 100644
index 000000000..58c45f30f
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files
@@ -0,0 +1,26 @@
+# This script shows the access statistics for different files on the
+# web server.
+#
+# First, we include the HTML header.
+i /files_header.html
+# Print out the name of the file, and call the function that prints
+# the access statistics of that file.
+t /index.html
+c b /index.html
+t  /control.html
+c b /control.html
+t  /img/logo.png
+c b /img/logo.png
+t  /404.html
+c b /404.html
+t  /cgi/files
+c b /cgi/files
+t  /cgi/stats
+c b /cgi/stats
+t  /cgi/tcp
+c b /cgi/tcp
+t 
+# Include the HTML footer.
+i /files_footer.plain
+# End of script.
+.
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos
new file mode 100644
index 000000000..7772ea420
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos
@@ -0,0 +1,6 @@
+t uIP Open Source Embedded TCP/IP Stack On FreeRTOS KernelFreeRTOS Homepage
AT91SAM7X Embedded WEB Server Demo
Using uIP and the FreeRTOS real time kernel
These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.
The uIP stack is executing from a single task under control of the FreeRTOS real time kernel.  The table below shows the statistics for all the tasks in the demo applicaiton.
Task          State  Priority  Stack	#
************************************************

+c d
+t 

+.
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats
new file mode 100644
index 000000000..2c71c90dc
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats
@@ -0,0 +1,4 @@
+i /stats_header.html
+c a
+i /stats_footer.plain
+.
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp
new file mode 100644
index 000000000..14efd3700
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp
@@ -0,0 +1,4 @@
+i /tcp_header.html
+c c
+i /tcp_footer.plain
+.
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html
new file mode 100644
index 000000000..0d9352ce7
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html
@@ -0,0 +1,20 @@
+
+
+AT91SAM7X Embedded WEB Server using uIP and FreeRTOS
+
+
+
+
+Tasks |
+Connections |
+Files |
+Statistics

+

+
+
+
+
+
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain
new file mode 100644
index 000000000..0b6dceb4f
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain
@@ -0,0 +1,3 @@
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html
new file mode 100644
index 000000000..20cf1c961
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html
@@ -0,0 +1,4 @@
+
+
+

+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png b/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png
new file mode 100644
index 000000000..ef572dd38
Binary files /dev/null and b/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png differ
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html
new file mode 100644
index 000000000..626ff3780
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html
@@ -0,0 +1,15 @@
+
+
+
+
+ 
+  
+  
+
+
+
+<body>
+Your browser must support frames
+</body>
+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain
new file mode 100644
index 000000000..0b6dceb4f
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain
@@ -0,0 +1,3 @@
+

+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html
new file mode 100644
index 000000000..e819c3449
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html
@@ -0,0 +1,30 @@
+
+
+

+
+

+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
	     
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
new file mode 100644
index 000000000..442c17a58
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
@@ -0,0 +1,5 @@
+
+

+

+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html
new file mode 100644
index 000000000..47bdf302c
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html
@@ -0,0 +1,6 @@
+
+
+

+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c
new file mode 100644
index 000000000..6a3c5140a
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c
@@ -0,0 +1,968 @@
+static const char data_404_html[] = {
+	/* /404.html */
+	0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 
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+	0x6c, 0x3e, };
+
+static const char data_control_html[] = {
+	/* /control.html */
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+	0xa, 0xd, 0xa, 0xd, 0xa, 0xd, 0xa, 0xd, 0xa, };
+
+static const char data_files_footer_plain[] = {
+	/* /files_footer.plain */
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+
+static const char data_files_header_html[] = {
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+
+static const char data_stats_header_html[] = {
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+
+static const char data_tcp_footer_plain[] = {
+	/* /tcp_footer.plain */
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+	0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, };
+
+static const char data_tcp_header_html[] = {
+	/* /tcp_header.html */
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+	0xd, 0xa, };
+
+static const char data_img_logo_png[] = {
+	/* /img/logo.png */
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+	0xf0, 0xd9, 0xc3, 0xbf, 0x18, 0x14, 0x8, 0xf4, 0x9c, 0x94, 
+	0xde, 0xd8, 0x30, 0x14, 0x9, 0xbb, 0xc7, 0x46, 0xde, 0xe, 
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+	0x67, 0xf9, 0x6f, 0x2a, 0x60, 0x7e, 0x32, 0x3b, 0x43, 0x10, 
+	0x16, 0x80, 0xdf, 0xbf, 0xa5, 0x7f, 0x2f, 0xe9, 0x17, 0xcd, 
+	0xf4, 0x47, 0x15, 0x44, 0x8, 0xda, 0xc8, 0x7e, 0x36, 0x50, 
+	0x28, 0x6e, 0x21, 0xfe, 0x1f, 0xd2, 0xa8, 0xa2, 0x91, 0xdc, 
+	0x83, 0x90, 0x3, 00, 00, 00, 00, 0x49, 0x45, 0x4e, 
+	0x44, 0xae, 0x42, 0x60, 0x82, };
+
+static const char data_cgi_files[] = {
+	/* /cgi/files */
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+static const char data_cgi_stats[] = {
+	/* /cgi/stats */
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+static const char data_cgi_tcp[] = {
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+static const char data_cgi_rtos[] = {
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+
+static const char data_index_html[] = {
+	/* /index.html */
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+	0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 
+	0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 
+	0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 
+	0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c, 
+	0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74, 0x20, 0x63, 
+	0x6f, 0x6c, 0x73, 0x3d, 0x22, 0x2a, 0x22, 0x20, 0x72, 0x6f, 
+	0x77, 0x73, 0x3d, 0x22, 0x31, 0x32, 0x30, 0x2c, 0x2a, 0x22, 
+	0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x62, 0x6f, 0x72, 0x64, 
+	0x65, 0x72, 0x3d, 0x22, 0x6e, 0x6f, 0x22, 0x3e, 0x20, 0xd, 
+	0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20, 
+	0x73, 0x72, 0x63, 0x3d, 0x22, 0x63, 0x6f, 0x6e, 0x74, 0x72, 
+	0x6f, 0x6c, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0xd, 
+	0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20, 
+	0x73, 0x72, 0x63, 0x3d, 0x22, 0x2f, 0x63, 0x67, 0x69, 0x2f, 
+	0x72, 0x74, 0x6f, 0x73, 0x22, 0x20, 0x6e, 0x61, 0x6d, 0x65, 
+	0x3d, 0x22, 0x6d, 0x61, 0x69, 0x6e, 0x22, 0x3e, 0xd, 0xa, 
+	0x3c, 0x2f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74, 
+	0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x6e, 0x6f, 0x66, 0x72, 
+	0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x6f, 
+	0x64, 0x79, 0x3e, 0xd, 0xa, 0x59, 0x6f, 0x75, 0x72, 0x20, 
+	0x62, 0x72, 0x6f, 0x77, 0x73, 0x65, 0x72, 0x20, 0x6d, 0x75, 
+	0x73, 0x74, 0x20, 0x73, 0x75, 0x70, 0x70, 0x6f, 0x72, 0x74, 
+	0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0xd, 0xa, 0x3c, 
+	0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 
+	0x6e, 0x6f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd, 
+	0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, };
+
+const struct fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};
+
+const struct fsdata_file file_control_html[] = {{file_404_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}};
+
+const struct fsdata_file file_files_footer_plain[] = {{file_control_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}};
+
+const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}};
+
+const struct fsdata_file file_stats_footer_plain[] = {{file_files_header_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}};
+
+const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}};
+
+const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}};
+
+const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}};
+
+const struct fsdata_file file_img_logo_png[] = {{file_tcp_header_html, data_img_logo_png, data_img_logo_png + 14, sizeof(data_img_logo_png) - 14}};
+
+const struct fsdata_file file_cgi_files[] = {{file_img_logo_png, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}};
+
+const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}};
+
+const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}};
+
+const struct fsdata_file file_cgi_rtos[] = {{file_cgi_tcp, data_cgi_rtos, data_cgi_rtos + 10, sizeof(data_cgi_rtos) - 10}};
+
+const struct fsdata_file file_index_html[] = {{file_cgi_rtos, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
+
+#define FS_ROOT file_index_html
+
+#define FS_NUMFILES 14
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h
new file mode 100644
index 000000000..94086c4df
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $
+ */
+#ifndef __FSDATA_H__
+#define __FSDATA_H__
+
+#include "uipopt.h"
+
+struct fsdata_file {
+  const struct fsdata_file *next;
+  const char *name;
+  const char *data;
+  const int len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t count;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+};
+
+struct fsdata_file_noconst {
+  struct fsdata_file *next;
+  char *name;
+  char *data;
+  int len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t count;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+};
+
+#endif /* __FSDATA_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c
new file mode 100644
index 000000000..108fa26e8
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c
@@ -0,0 +1,372 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \defgroup httpd Web server
+ * @{
+ *
+ * The uIP web server is a very simplistic implementation of an HTTP
+ * server. It can serve web pages and files from a read-only ROM
+ * filesystem, and provides a very small scripting language.
+ *
+ * The script language is very simple and works as follows. Each
+ * script line starts with a command character, either "i", "t", "c",
+ * "#" or ".".  The "i" command tells the script interpreter to
+ * "include" a file from the virtual file system and output it to the
+ * web browser. The "t" command should be followed by a line of text
+ * that is to be output to the browser. The "c" command is used to
+ * call one of the C functions from the httpd-cgi.c file. A line that
+ * starts with a "#" is ignored (i.e., the "#" denotes a comment), and
+ * the "." denotes the last script line.
+ *
+ * The script that produces the file statistics page looks somewhat
+ * like this:
+ *
+ \code
+i /header.html
+t 
File statistics

RemoteStateRetransmissionsTimerFlags

+t 
/index.html
+c a /index.html
+t 
 
/cgi/files
+c a /cgi/files
+t 
 
/cgi/tcp
+c a /cgi/tcp
+t 
 
/404.html
+c a /404.html
+t 

+i /footer.plain
+.
+ \endcode
+ *
+ */
+
+
+/**
+ * \file
+ * HTTP server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+#include "fsdata.h"
+#include "cgi.h"
+
+#define NULL (void *)0
+
+/* The HTTP server states: */
+#define HTTP_NOGET        0
+#define HTTP_FILE         1
+#define HTTP_TEXT         2
+#define HTTP_FUNC         3
+#define HTTP_END          4
+
+#ifdef DEBUG
+#include 
+#define PRINT(x)
+#define PRINTLN(x)
+#else /* DEBUG */
+#define PRINT(x)
+#define PRINTLN(x)
+#endif /* DEBUG */
+
+struct httpd_state *hs;
+
+extern const struct fsdata_file file_index_html;
+extern const struct fsdata_file file_404_html;
+
+static void next_scriptline(void);
+static void next_scriptstate(void);
+
+#define ISO_G        0x47
+#define ISO_E        0x45
+#define ISO_T        0x54
+#define ISO_slash    0x2f
+#define ISO_c        0x63
+#define ISO_g        0x67
+#define ISO_i        0x69
+#define ISO_space    0x20
+#define ISO_nl       0x0a
+#define ISO_cr       0x0d
+#define ISO_a        0x61
+#define ISO_t        0x74
+#define ISO_hash     0x23
+#define ISO_period   0x2e
+
+#define httpPORT	80
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the web server.
+ *
+ * Starts to listen for incoming connection requests on TCP port 80.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+httpd_init(void)
+{
+  fs_init();
+
+  /* Listen to port 80. */
+  uip_listen(HTONS(httpPORT));
+}
+/*-----------------------------------------------------------------------------------*/
+void
+httpd_appcall(void)
+{
+  struct fs_file fsfile;
+
+  u8_t i;
+
+  switch(uip_conn->lport) {
+    /* This is the web server: */
+  case HTONS(httpPORT):
+    /* Pick out the application state from the uip_conn structure. */
+    hs = (struct httpd_state *)(uip_conn->appstate);
+
+    /* We use the uip_ test functions to deduce why we were
+       called. If uip_connected() is non-zero, we were called
+       because a remote host has connected to us. If
+       uip_newdata() is non-zero, we were called because the
+       remote host has sent us new data, and if uip_acked() is
+       non-zero, the remote host has acknowledged the data we
+       previously sent to it. */
+    if(uip_connected()) {
+      /* Since we have just been connected with the remote host, we
+         reset the state for this connection. The ->count variable
+         contains the amount of data that is yet to be sent to the
+         remote host, and the ->state is set to HTTP_NOGET to signal
+         that we haven't received any HTTP GET request for this
+         connection yet. */
+
+      hs->state = HTTP_NOGET;
+      hs->count = 0;
+      return;
+
+    } else if(uip_poll()) {
+      /* If we are polled ten times, we abort the connection. This is
+         because we don't want connections lingering indefinately in
+         the system. */
+      if(hs->count++ >= 10) {
+	uip_abort();
+      }
+      return;
+    } else if(uip_newdata() && hs->state == HTTP_NOGET) {
+      /* This is the first data we receive, and it should contain a
+	 GET. */
+
+      /* Check for GET. */
+      if(uip_appdata[0] != ISO_G ||
+	 uip_appdata[1] != ISO_E ||
+	 uip_appdata[2] != ISO_T ||
+	 uip_appdata[3] != ISO_space) {
+	/* If it isn't a GET, we abort the connection. */
+	uip_abort();
+	return;
+      }
+	
+      /* Find the file we are looking for. */
+      for(i = 4; i < 40; ++i) {
+	if(uip_appdata[i] == ISO_space ||
+	   uip_appdata[i] == ISO_cr ||
+	   uip_appdata[i] == ISO_nl) {
+	  uip_appdata[i] = 0;
+	  break;
+	}
+      }
+
+      PRINT("request for file ");
+      PRINTLN(&uip_appdata[4]);
+
+      /* Check for a request for "/". */
+      if(uip_appdata[4] == ISO_slash &&
+	 uip_appdata[5] == 0) {
+	fs_open(file_index_html.name, &fsfile);
+      } else {
+	if(!fs_open((const char *)&uip_appdata[4], &fsfile)) {
+	  PRINTLN("couldn't open file");
+	  fs_open(file_404_html.name, &fsfile);
+	}
+      }
+
+
+      if(uip_appdata[4] == ISO_slash &&
+	 uip_appdata[5] == ISO_c &&
+	 uip_appdata[6] == ISO_g &&
+	 uip_appdata[7] == ISO_i &&
+	 uip_appdata[8] == ISO_slash) {
+	/* If the request is for a file that starts with "/cgi/", we
+           prepare for invoking a script. */	
+	hs->script = fsfile.data;
+	next_scriptstate();
+      } else {
+	hs->script = NULL;
+	/* The web server is now no longer in the HTTP_NOGET state, but
+	   in the HTTP_FILE state since is has now got the GET from
+	   the client and will start transmitting the file. */
+	hs->state = HTTP_FILE;
+
+	/* Point the file pointers in the connection state to point to
+	   the first byte of the file. */
+	hs->dataptr = fsfile.data;
+	hs->count = fsfile.len;	
+      }
+    }
+
+
+    if(hs->state != HTTP_FUNC) {
+      /* Check if the client (remote end) has acknowledged any data that
+	 we've previously sent. If so, we move the file pointer further
+	 into the file and send back more data. If we are out of data to
+	 send, we close the connection. */
+      if(uip_acked()) {
+	if(hs->count >= uip_conn->len) {
+	  hs->count -= uip_conn->len;
+	  hs->dataptr += uip_conn->len;
+	} else {
+	  hs->count = 0;
+	}
+	
+	if(hs->count == 0) {
+	  if(hs->script != NULL) {
+	    next_scriptline();
+	    next_scriptstate();
+	  } else {
+	    uip_close();
+	  }
+	}
+      }
+    } else {
+      /* Call the CGI function. */
+      if(cgitab[hs->script[2] - ISO_a](uip_acked())) {
+	/* If the function returns non-zero, we jump to the next line
+           in the script. */
+	next_scriptline();
+	next_scriptstate();
+      }
+    }
+
+    if(hs->state != HTTP_FUNC && !uip_poll()) {
+      /* Send a piece of data, but not more than the MSS of the
+	 connection. */
+      uip_send(( void * ) hs->dataptr, hs->count);
+    }
+
+    /* Finally, return to uIP. Our outgoing packet will soon be on its
+       way... */
+    return;
+
+  default:
+    /* Should never happen. */
+    uip_abort();
+    break;
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/* next_scriptline():
+ *
+ * Reads the script until it finds a newline. */
+static void
+next_scriptline(void)
+{
+  /* Loop until we find a newline character. */
+  do {
+    ++(hs->script);
+  } while(hs->script[0] != ISO_nl);
+
+  /* Eat up the newline as well. */
+  ++(hs->script);
+}
+/*-----------------------------------------------------------------------------------*/
+/* next_sciptstate:
+ *
+ * Reads one line of script and decides what to do next.
+ */
+static void
+next_scriptstate(void)
+{
+  struct fs_file fsfile;
+  long i;
+
+ again:
+  switch(hs->script[0]) {
+  case ISO_t:
+    /* Send a text string. */
+    hs->state = HTTP_TEXT;
+    hs->dataptr = &hs->script[2];
+
+    /* Calculate length of string. */
+    for(i = 0; hs->dataptr[i] != ISO_nl; ++i);
+    hs->count = i;
+    break;
+  case ISO_c:
+    /* Call a function. */
+    hs->state = HTTP_FUNC;
+    hs->dataptr = NULL;
+    hs->count = 0;
+    cgitab[hs->script[2] - ISO_a](0);
+    break;
+  case ISO_i:
+    /* Include a file. */
+    hs->state = HTTP_FILE;
+    if(!fs_open(&hs->script[2], &fsfile)) {
+      uip_abort();
+    }
+    hs->dataptr = fsfile.data;
+    hs->count = fsfile.len;
+    break;
+  case ISO_hash:
+    /* Comment line. */
+    next_scriptline();
+    goto again;
+  case ISO_period:
+    /* End of script. */
+    hs->state = HTTP_END;
+    uip_close();
+    break;
+  default:
+    uip_abort();
+    break;
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_
new file mode 100644
index 000000000..fda240826
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_
@@ -0,0 +1,380 @@
+/*$T httpd.c GC 1.138 07/23/05 13:10:49 */
+
+/*
+ * \addtogroup exampleapps @{ £
+ * \defgroup httpd Web server @{ The uIP web server is a very simplistic
+ * implementation of an HTTP server. It can serve web pages and files from a
+ * read-only ROM filesystem, and provides a very small scripting language. The
+ * script language is very simple and works as follows. Each script line starts
+ * with a command character, either "i", "t", "c", "#" or ".". The "i" command
+ * tells the script interpreter to "include" a file from the virtual file system
+ * and output it to the web browser. The "t" command should be followed by a line
+ * of text that is to be output to the browser. The "c" command is used to call
+ * one of the C functions from the httpd-cgi.c file. A line that starts with a "#"
+ * is ignored (i.e., the "#" denotes a comment), and the "." denotes the last
+ * script line. The script that produces the file statistics page looks somewhat
+ * like this: \code i /header.html t 
File statistics

 t 
/index.html c a
+ * /index.html t 
 
/cgi/files c
+ * a /cgi/files t 
 
/cgi/tcp c a
+ * /cgi/tcp t 
 
/404.html c a
+ * /404.html t 
 i /footer.plain . \endcode £
+ * \file HTTP server. \author Adam Dunkels  £
+ * Copyright (c) 2001, Adam Dunkels. All rights reserved. Redistribution and use
+ * in source and binary forms, with or without modification, are permitted
+ * provided that the following conditions are met: 1. Redistributions of source
+ * code must retain the above copyright notice, this list of conditions and the
+ * following disclaimer. 2. Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution. 3. The
+ * name of the author may not be used to endorse or promote products derived from
+ * this software without specific prior written permission. THIS SOFTWARE IS
+ * PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This file is part of the uIP TCP/IP stack. $Id: httpd.c,v 1.28.2.6 2003/10/07
+ * 13:22:27 adam Exp $
+ */
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+#include "fsdata.h"
+#include "cgi.h"
+
+#define NULL    ( void * ) 0
+
+/* The HTTP server states: */
+#define HTTP_NOGET  0
+#define HTTP_FILE   1
+#define HTTP_TEXT   2
+#define HTTP_FUNC   3
+#define HTTP_END    4
+
+#ifdef DEBUG
+#include 
+#define PRINT( x )
+#define PRINTLN( x )
+#else /* DEBUG */
+#define PRINT( x )
+#define PRINTLN( x )
+#endif /* DEBUG */
+
+struct httpd_state              *hs;
+
+extern const struct fsdata_file file_index_html;
+extern const struct fsdata_file file_404_html;
+
+static void                     next_scriptline( void );
+static void                     next_scriptstate( void );
+
+#define ISO_G       0x47
+#define ISO_E       0x45
+#define ISO_T       0x54
+#define ISO_slash   0x2f
+#define ISO_c       0x63
+#define ISO_g       0x67
+#define ISO_i       0x69
+#define ISO_space   0x20
+#define ISO_nl      0x0a
+#define ISO_cr      0x0d
+#define ISO_a       0x61
+#define ISO_t       0x74
+#define ISO_hash    0x23
+#define ISO_period  0x2e
+
+#define httpPORT    80
+
+/*
+ =======================================================================================================================
+    Initialize the web server. Starts to listen for incoming connection requests on TCP port 80.
+ =======================================================================================================================
+ */
+void httpd_init( void )
+{
+    fs_init();
+
+    /* Listen to port 80. */
+    uip_listen( HTONS( httpPORT ) );
+}
+
+/*
+ =======================================================================================================================
+ =======================================================================================================================
+ */
+void httpd_appcall( void )
+{
+    /*~~~~~~~~~~~~~~~~~~~*/
+    struct fs_file  fsfile;
+    u8_t            i;
+    /*~~~~~~~~~~~~~~~~~~~*/
+
+    switch( uip_conn->lport )
+    {
+    /* This is the web server: */
+    case HTONS( httpPORT ):
+        /* Pick out the application state from the uip_conn structure. */
+        hs = ( struct httpd_state * ) ( uip_conn->appstate );
+
+        /*
+         * We use the uip_ test functions to deduce why we were called. If uip_connected()
+         * is non-zero, we were called because a remote host has connected to us. If
+         * uip_newdata() is non-zero, we were called because the remote host has sent us
+         * new data, and if uip_acked() is non-zero, the remote host has acknowledged the
+         * data we previously sent to it.
+         */
+        if( uip_connected() )
+        {
+            /*
+             * Since we have just been connected with the remote host, we reset the state for
+             * this connection. The ->count variable contains the amount of data that is yet
+             * to be sent to the remote host, and the ->state is set to HTTP_NOGET to signal
+             * that we haven't received any HTTP GET request for this connection yet.
+             */
+            hs->state = HTTP_NOGET;
+            hs->count = 0;
+            return;
+        }
+        else if( uip_poll() )
+        {
+            /*
+             * If we are polled ten times, we abort the connection. This is because we don't
+             * want connections lingering indefinately in the system.
+             */
+            if( hs->count++ >= 10 )
+            {
+                uip_abort();
+            }
+
+            return;
+        }
+        else if( uip_newdata() && hs->state == HTTP_NOGET )
+        {
+            /*
+             * This is the first data we receive, and it should contain a GET. £
+             * Check for GET.
+             */
+            if
+            (
+                uip_appdata[0] != ISO_G
+            ||  uip_appdata[1] != ISO_E
+            ||  uip_appdata[2] != ISO_T
+            ||  uip_appdata[3] != ISO_space
+            )
+            {
+                /* If it isn't a GET, we abort the connection. */
+                uip_abort();
+                return;
+            }
+
+            /* Find the file we are looking for. */
+            for( i = 4; i < 40; ++i )
+            {
+                if( uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl )
+                {
+                    uip_appdata[i] = 0;
+                    break;
+                }
+            }
+
+            PRINT( "request for file " );
+            PRINTLN( &uip_appdata[4] );
+
+            /* Check for a request for "/". */
+            if( uip_appdata[4] == ISO_slash && uip_appdata[5] == 0 )
+            {
+                fs_open( file_index_html.name, &fsfile );
+            }
+            else
+            {
+                if( !fs_open( ( const char * ) &uip_appdata[4], &fsfile ) )
+                {
+                    PRINTLN( "couldn't open file" );
+                    fs_open( file_404_html.name, &fsfile );
+                }
+            }
+
+            if
+            (
+                uip_appdata[4] == ISO_slash
+            &&  uip_appdata[5] == ISO_c
+            &&  uip_appdata[6] == ISO_g
+            &&  uip_appdata[7] == ISO_i
+            &&  uip_appdata[8] == ISO_slash
+            )
+            {
+                /*
+                 * If the request is for a file that starts with "/cgi/", we prepare for invoking
+                 * a script.
+                 */
+                hs->script = fsfile.data;
+                next_scriptstate();
+            }
+            else
+            {
+                hs->script = NULL;
+
+                /*
+                 * The web server is now no longer in the HTTP_NOGET state, but in the HTTP_FILE
+                 * state since is has now got the GET from the client and will start transmitting
+                 * the file.
+                 */
+                hs->state = HTTP_FILE;
+
+                /*
+                 * Point the file pointers in the connection state to point to the first byte of
+                 * the file.
+                 */
+                hs->dataptr = fsfile.data;
+                hs->count = fsfile.len;
+            }
+        }
+
+        if( hs->state != HTTP_FUNC )
+        {
+            /*
+             * Check if the client (remote end) has acknowledged any data that we've
+             * previously sent. If so, we move the file pointer further into the file and send
+             * back more data. If we are out of data to send, we close the connection.
+             */
+            if( uip_acked() )
+            {
+                if( hs->count >= uip_conn->len )
+                {
+                    hs->count -= uip_conn->len;
+                    hs->dataptr += uip_conn->len;
+                }
+                else
+                {
+                    hs->count = 0;
+                }
+
+                if( hs->count == 0 )
+                {
+                    if( hs->script != NULL )
+                    {
+                        next_scriptline();
+                        next_scriptstate();
+                    }
+                    else
+                    {
+                        uip_close();
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* Call the CGI function. */
+            if( cgitab[hs->script[2] - ISO_a](uip_acked()) )
+            {
+                /* If the function returns non-zero, we jump to the next line in the script. */
+                next_scriptline();
+                next_scriptstate();
+            }
+        }
+
+        if( hs->state != HTTP_FUNC && !uip_poll() )
+        {
+            /* Send a piece of data, but not more than the MSS of the connection. */
+            uip_send( ( void * ) hs->dataptr, hs->count );
+        }
+
+        /* Finally, return to uIP. Our outgoing packet will soon be on its way... */
+        return;
+
+    default:
+        /* Should never happen. */
+        uip_abort();
+        break;
+    }
+}
+
+/*
+ =======================================================================================================================
+    next_scriptline(): Reads the script until it finds a newline.
+ =======================================================================================================================
+ */
+static void next_scriptline( void )
+{
+    /* Loop until we find a newline character. */
+    do
+    {
+        ++( hs->script );
+    } while( hs->script[0] != ISO_nl );
+
+    /* Eat up the newline as well. */
+    ++( hs->script );
+}
+
+/*
+ =======================================================================================================================
+    next_sciptstate: Reads one line of script and decides what to do next.
+ =======================================================================================================================
+ */
+static void next_scriptstate( void )
+{
+    /*~~~~~~~~~~~~~~~~~~~*/
+    struct fs_file  fsfile;
+    u8_t            i;
+    /*~~~~~~~~~~~~~~~~~~~*/
+
+again:
+    switch( hs->script[0] )
+    {
+    case ISO_t:
+        /* Send a text string. */
+        hs->state = HTTP_TEXT;
+        hs->dataptr = &hs->script[2];
+
+        /* Calculate length of string. */
+        for( i = 0; hs->dataptr[i] != ISO_nl; ++i );
+        hs->count = i;
+        break;
+
+    case ISO_c:
+        /* Call a function. */
+        hs->state = HTTP_FUNC;
+        hs->dataptr = NULL;
+        hs->count = 0;
+        cgitab[hs->script[2] - ISO_a]( 0 );
+        break;
+
+    case ISO_i:
+        /* Include a file. */
+        hs->state = HTTP_FILE;
+        if( !fs_open( &hs->script[2], &fsfile ) )
+        {
+            uip_abort();
+        }
+
+        hs->dataptr = fsfile.data;
+        hs->count = fsfile.len;
+        break;
+
+    case ISO_hash:
+        /* Comment line. */
+        next_scriptline();
+        goto again;
+
+    case ISO_period:
+        /* End of script. */
+        hs->state = HTTP_END;
+        uip_close();
+        break;
+
+    default:
+        uip_abort();
+        break;
+    }
+}
+
+/*
+ * @} £
+ * @}
+ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h
new file mode 100644
index 000000000..34d6bb35f
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h
@@ -0,0 +1,77 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $
+ *
+ */
+
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+void httpd_init(void);
+void httpd_appcall(void);
+
+/* UIP_APPCALL: the name of the application function. This function
+   must return void and take no arguments (i.e., C type "void
+   appfunc(void)"). */
+#ifndef UIP_APPCALL
+#define UIP_APPCALL     httpd_appcall
+#endif
+
+struct httpd_state {
+  u8_t state; 
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+
+
+/* UIP_APPSTATE_SIZE: The size of the application-specific state
+   stored in the uip_conn structure. */
+#ifndef UIP_APPSTATE_SIZE
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+#endif
+
+#define FS_STATISTICS 1
+
+extern struct httpd_state *hs;
+
+#endif /* __HTTPD_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/main_led b/Demo/uIP_Demo_IAR_ARM7/uip/main_led
new file mode 100644
index 000000000..8fe01ea6d
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/main_led
@@ -0,0 +1,67 @@
+// Copyright (c) 2001-2004 Rowley Associates Limited.
+//
+// This file may be distributed under the terms of the License Agreement
+// provided with this software.
+//
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//                      Olimex LPC-P1  LED Example
+//
+// Description
+// -----------
+// This example demonstrates writing to the programmable peripheral interface.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include 
+
+#define LED_RED (1<<8)
+#define LED_GREEN (1<<10)
+#define LED_YELLOW (1<<11)
+
+#define LED1 LED_YELLOW
+
+static void
+ledInit()
+{
+  IODIR |= LED1;
+  IOSET = LED1;
+}
+
+static void
+ledOn(void)
+{
+  IOCLR = LED1;
+}
+
+static void
+ledOff(void)
+{
+  IOSET = LED1;
+}
+
+void
+delay(int d)
+{     
+  for(; d; --d);
+}
+ 
+int
+main(void)
+{
+  MAMCR = 2;
+  ledInit();
+  while (1)
+    {
+      ledOn();
+      delay(100000);
+      ledOff();
+      delay(100000);
+    }
+  return 0;
+}
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata b/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata
new file mode 100644
index 000000000..f5f75f174
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata
@@ -0,0 +1,93 @@
+#!/usr/bin/perl
+
+open(OUTPUT, "> fsdata.c");
+
+chdir("fs");
+open(FILES, "find . -type f |");
+
+while($file = ) {
+
+    # Do not include files in CVS directories nor backup files.
+    if($file =~ /(CVS|~)/) {
+    	next;
+    }
+    
+    chop($file);
+    
+    open(HEADER, "> /tmp/header") || die $!;
+    if($file =~ /404.html/) {
+      print(HEADER "HTTP/1.0 404 File not found\r\n");
+    } else {
+      print(HEADER "HTTP/1.0 200 OK\r\n");
+    }
+    print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n");
+    if($file =~ /\.html$/) {
+	print(HEADER "Content-type: text/html\r\n");
+    } elsif($file =~ /\.gif$/) {
+	print(HEADER "Content-type: image/gif\r\n");
+    } elsif($file =~ /\.png$/) {
+	print(HEADER "Content-type: image/png\r\n");
+    } elsif($file =~ /\.jpg$/) {
+	print(HEADER "Content-type: image/jpeg\r\n");
+    } else {
+	print(HEADER "Content-type: text/plain\r\n");
+    }
+    print(HEADER "\r\n");
+    close(HEADER);
+
+    unless($file =~ /\.plain$/ || $file =~ /cgi/) {
+	system("cat /tmp/header $file > /tmp/file");
+    } else {
+	system("cp $file /tmp/file");
+    }
+    
+    open(FILE, "/tmp/file");
+    unlink("/tmp/file");
+    unlink("/tmp/header");
+
+    $file =~ s/\.//;
+    $fvar = $file;
+    $fvar =~ s-/-_-g;
+    $fvar =~ s-\.-_-g;
+    print(OUTPUT "static const char data".$fvar."[] = {\n");
+    print(OUTPUT "\t/* $file */\n\t");
+    for($j = 0; $j < length($file); $j++) {
+	printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));
+    }
+    printf(OUTPUT "0,\n");
+    
+    
+    $i = 0;        
+    while(read(FILE, $data, 1)) {
+        if($i == 0) {
+            print(OUTPUT "\t");
+        }
+        printf(OUTPUT "%#02x, ", unpack("C", $data));
+        $i++;
+        if($i == 10) {
+            print(OUTPUT "\n");
+            $i = 0;
+        }
+    }
+    print(OUTPUT "};\n\n");
+    close(FILE);
+    push(@fvars, $fvar);
+    push(@files, $file);
+}
+
+for($i = 0; $i < @fvars; $i++) {
+    $file = $files[$i];
+    $fvar = $fvars[$i];
+
+    if($i == 0) {
+        $prevfile = "NULL";
+    } else {
+        $prevfile = "file" . $fvars[$i - 1];
+    }
+    print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");
+}
+
+print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n");
+print(OUTPUT "#define FS_NUMFILES $i");
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/memb.c b/Demo/uIP_Demo_IAR_ARM7/uip/memb.c
new file mode 100644
index 000000000..56e663446
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/memb.c
@@ -0,0 +1,152 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \file
+ * Memory block allocation routines.
+ * \author Adam Dunkels 
+ *
+ * The memory block allocation routines provide a simple yet powerful
+ * set of functions for managing a set of memory blocks of fixed
+ * size. A set of memory blocks is statically declared with the
+ * MEMB() macro. Memory blocks are allocated from the declared
+ * memory by the memb_alloc() function, and are deallocated with the
+ * memb_free() function.
+ *
+ * \note Because of namespace clashes only one MEMB() can be
+ * declared per C module, and the name scope of a MEMB() memory
+ * block is local to each C module.
+ *
+ * The following example shows how to declare and use a memory block
+ * called "cmem" which has 8 chunks of memory with each memory chunk
+ * being 20 bytes large.
+ *
+ \code
+ MEMB(cmem, 20, 8);
+
+ int main(int argc, char *argv[]) {
+    char *ptr;
+    
+    memb_init(&cmem);
+
+    ptr = memb_alloc(&cmem);
+
+    if(ptr != NULL) {
+       do_something(ptr);
+    } else {
+       printf("Could not allocate memory.\n");
+    }
+
+    if(memb_free(ptr) == 0) {
+       printf("Deallocation succeeded.\n");
+    }
+ }
+ \endcode
+ * 
+ */
+
+#include 
+
+#include "memb.h"
+
+/*------------------------------------------------------------------------------*/
+/**
+ * Initialize a memory block that was declared with MEMB().
+ *
+ * \param m A memory block previosly declared with MEMB().
+ */
+/*------------------------------------------------------------------------------*/
+void
+memb_init(struct memb_blocks *m)
+{
+  memset(m->mem, (m->size + 1) * m->num, 0);
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Allocate a memory block from a block of memory declared with MEMB().
+ *
+ * \param m A memory block previosly declared with MEMB().
+ */
+/*------------------------------------------------------------------------------*/
+char *
+memb_alloc(struct memb_blocks *m)
+{
+  int i;
+  char *ptr;
+
+  ptr = m->mem;
+  for(i = 0; i < m->num; ++i) {
+    if(*ptr == 0) {
+      /* If this block was unused, we increase the reference count to
+	 indicate that it now is used and return a pointer to the
+	 first byte following the reference counter. */
+      ++*ptr;
+      return ptr + 1;
+    }
+    ptr += m->size + 1;
+  }
+
+  /* No free block was found, so we return NULL to indicate failure to
+     allocate block. */
+  return NULL;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Deallocate a memory block from a memory block previously declared
+ * with MEMB().
+ *
+ * \param m m A memory block previosly declared with MEMB().
+ *
+ * \param ptr A pointer to the memory block that is to be deallocated.
+ *
+ * \return The new reference count for the memory block (should be 0
+ * if successfully deallocated) or -1 if the pointer "ptr" did not
+ * point to a legal memory block.
+ */
+/*------------------------------------------------------------------------------*/
+char
+memb_free(struct memb_blocks *m, char *ptr)
+{
+  int i;
+  char *ptr2;
+
+  /* Walk through the list of blocks and try to find the block to
+     which the pointer "ptr" points to. */
+  ptr2 = m->mem;
+  for(i = 0; i < m->num; ++i) {
+    
+    if(ptr2 == ptr - 1) {
+      /* We've found to block to which "ptr" points so we decrease the
+	 reference count and return the new value of it. */      
+      return --*ptr2;
+    }
+    ptr2 += m->size + 1;
+  }
+  return -1;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Increase the reference count for a memory chunk.
+ *
+ * \note No sanity checks are currently made.
+ *
+ * \param m m A memory block previosly declared with MEMB().
+ *
+ * \param ptr A pointer to the memory chunk for which the reference
+ * count should be increased.
+ *
+ * \return The new reference count.
+ */
+/*------------------------------------------------------------------------------*/
+char
+memb_ref(struct memb_blocks *m, char *ptr)
+{
+  return ++*(ptr - 1);
+}
+/*------------------------------------------------------------------------------*/
+
+
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/memb.h b/Demo/uIP_Demo_IAR_ARM7/uip/memb.h
new file mode 100644
index 000000000..505846f4d
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/memb.h
@@ -0,0 +1,43 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \file
+ * Memory block allocation routines.
+ * \author Adam Dunkels 
+ *
+ */
+
+#ifndef __MEMB_H__
+#define __MEMB_H__
+
+/**
+ * Declare a memory block.
+ *
+ * \param name The name of the memory block (later used with
+ * memb_init(), memb_alloc() and memb_free()).
+ *
+ * \param size The size of each memory chunk, in bytes.
+ *
+ * \param num The total number of memory chunks in the block.
+ *
+ */
+#define MEMB(name, size, num) \
+        static char memb_mem[(size + 1) * num]; \
+        static struct memb_blocks name = {size, num, memb_mem}
+
+struct memb_blocks {
+  unsigned short size;
+  unsigned short num;
+  char *mem;
+};
+
+void  memb_init(struct memb_blocks *m);
+char *memb_alloc(struct memb_blocks *m);
+char  memb_ref(struct memb_blocks *m, char *ptr);
+char  memb_free(struct memb_blocks *m, char *ptr);
+
+
+#endif /* __MEMB_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat b/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat
new file mode 100644
index 000000000..7f5babb3f
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat
@@ -0,0 +1 @@
+arp -s 172.25.218.210 00-bd-3b-33-05-72
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c
new file mode 100644
index 000000000..fc968c82e
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c
@@ -0,0 +1,202 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup slip Serial Line IP (SLIP) protocol
+ * @{
+ *
+ * The SLIP protocol is a very simple way to transmit IP packets over
+ * a serial line. It does not provide any framing or error control,
+ * and is therefore not very widely used today.
+ *
+ * This SLIP implementation requires two functions for accessing the
+ * serial device: slipdev_char_poll() and slipdev_char_put(). These
+ * must be implemented specifically for the system on which the SLIP
+ * protocol is to be run.
+ */
+
+/**
+ * \file
+ * SLIP protocol implementation
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $
+ *
+ */
+
+/*
+ * This is a generic implementation of the SLIP protocol over an RS232
+ * (serial) device. 
+ *
+ * Huge thanks to Ullrich von Bassewitz  of cc65 fame for
+ * and endless supply of bugfixes, insightsful comments and
+ * suggestions, and improvements to this code!
+ */
+
+#include "uip.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+static u8_t slip_buf[UIP_BUFSIZE];
+
+static u16_t len, tmplen;
+static u8_t lastc;
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Send the packet in the uip_buf and uip_appdata buffers using the
+ * SLIP protocol.
+ *
+ * The first 40 bytes of the packet (the IP and TCP headers) are read
+ * from the uip_buf buffer, and the following bytes (the application
+ * data) are read from the uip_appdata buffer.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+slipdev_send(void)
+{
+  u16_t i;
+  u8_t *ptr;
+  u8_t c;
+
+  slipdev_char_put(SLIP_END);
+
+  ptr = uip_buf;
+  for(i = 0; i < uip_len; ++i) {
+    if(i == 40) {
+      ptr = (u8_t *)uip_appdata;
+    }
+    c = *ptr++;
+    switch(c) {
+    case SLIP_END:
+      slipdev_char_put(SLIP_ESC);
+      slipdev_char_put(SLIP_ESC_END);
+      break;
+    case SLIP_ESC:
+      slipdev_char_put(SLIP_ESC);
+      slipdev_char_put(SLIP_ESC_ESC);
+      break;
+    default:
+      slipdev_char_put(c);
+      break;
+    }
+  }
+  slipdev_char_put(SLIP_END);
+}
+/*-----------------------------------------------------------------------------------*/
+/** 
+ * Poll the SLIP device for an available packet.
+ *
+ * This function will poll the SLIP device to see if a packet is
+ * available. It uses a buffer in which all avaliable bytes from the
+ * RS232 interface are read into. When a full packet has been read
+ * into the buffer, the packet is copied into the uip_buf buffer and
+ * the length of the packet is returned.
+ *
+ * \return The length of the packet placed in the uip_buf buffer, or
+ * zero if no packet is available.
+ */
+/*-----------------------------------------------------------------------------------*/
+u16_t
+slipdev_poll(void)
+{
+  u8_t c;
+  
+  while(slipdev_char_poll(c)) {
+    switch(c) {
+    case SLIP_ESC:
+      lastc = c;
+      break;
+      
+    case SLIP_END:
+      lastc = c;
+      /* End marker found, we copy our input buffer to the uip_buf
+	 buffer and return the size of the packet we copied. */
+      memcpy(uip_buf, slip_buf, len);
+      tmplen = len;
+      len = 0;
+      return tmplen;
+      
+    default:     
+      if(lastc == SLIP_ESC) {
+	lastc = c;
+	/* Previous read byte was an escape byte, so this byte will be
+	   interpreted differently from others. */
+	switch(c) {
+	case SLIP_ESC_END:
+	  c = SLIP_END;
+	  break;
+	case SLIP_ESC_ESC:
+	  c = SLIP_ESC;
+	  break;
+	}
+      } else {
+	lastc = c;
+      }
+      
+      slip_buf[len] = c;
+      ++len;
+      
+      if(len > UIP_BUFSIZE) {
+	len = 0;
+      }
+    
+      break;
+    }
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the SLIP module.
+ *
+ * This function does not initialize the underlying RS232 device, but
+ * only the SLIP part.
+ */ 
+/*-----------------------------------------------------------------------------------*/
+void
+slipdev_init(void)
+{
+  lastc = len = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h
new file mode 100644
index 000000000..3fbfe2d2d
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h
@@ -0,0 +1,88 @@
+/**
+ * \addtogroup slip
+ * @{
+ */
+
+/**
+ * \file
+ * SLIP header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $
+ *
+ */
+
+#ifndef __SLIPDEV_H__
+#define __SLIPDEV_H__
+
+#include "uip.h"
+
+/**
+ * Put a character on the serial device.
+ *
+ * This function is used by the SLIP implementation to put a character
+ * on the serial device. It must be implemented specifically for the
+ * system on which the SLIP implementation is to be run.
+ *
+ * \param c The character to be put on the serial device.
+ */
+void slipdev_char_put(u8_t c);
+
+/**
+ * Poll the serial device for a character.
+ *
+ * This function is used by the SLIP implementation to poll the serial
+ * device for a character. It must be implemented specifically for the
+ * system on which the SLIP implementation is to be run.
+ *
+ * The function should return immediately regardless if a character is
+ * available or not. If a character is available it should be placed
+ * at the memory location pointed to by the pointer supplied by the
+ * arguement c.
+ *
+ * \param c A pointer to a byte that is filled in by the function with
+ * the received character, if available.
+ *
+ * \retval 0 If no character is available.
+ * \retval Non-zero If a character is available.
+ */
+u8_t slipdev_char_poll(u8_t *c);
+
+void slipdev_init(void);
+void slipdev_send(void);
+u16_t slipdev_poll(void);
+
+#endif /* __SLIPDEV_H__ */
+
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c
new file mode 100644
index 000000000..0d23fc4d9
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ *
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ *
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef linux
+#include 
+#include 
+#include 
+#define DEVTAP "/dev/net/tun"
+#else  /* linux */
+#define DEVTAP "/dev/tap0"
+#endif /* linux */
+
+#include "uip.h"
+
+static int fd;
+
+static unsigned long lasttime;
+static struct timezone tz;
+
+/*-----------------------------------------------------------------------------------*/
+void
+tapdev_init(void)
+{
+  char buf[1024];
+  
+  fd = open(DEVTAP, O_RDWR);
+  if(fd == -1) {
+    perror("tapdev: tapdev_init: open");
+    exit(1);
+  }
+
+#ifdef linux
+  {
+    struct ifreq ifr;
+    memset(&ifr, 0, sizeof(ifr));
+    ifr.ifr_flags = IFF_TAP|IFF_NO_PI;
+    if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) {
+      perror(buf);
+      exit(1);
+    }
+  }
+#endif /* Linux */
+
+  snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d",
+	   UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3);
+  system(buf);
+
+  lasttime = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+unsigned int
+tapdev_read(void)
+{
+  fd_set fdset;
+  struct timeval tv, now;
+  int ret;
+  
+  if(lasttime >= 500000) {
+    lasttime = 0;
+    return 0;
+  }
+  
+  tv.tv_sec = 0;
+  tv.tv_usec = 500000 - lasttime;
+
+
+  FD_ZERO(&fdset);
+  FD_SET(fd, &fdset);
+
+  gettimeofday(&now, &tz);  
+  ret = select(fd + 1, &fdset, NULL, NULL, &tv);
+  if(ret == 0) {
+    lasttime = 0;    
+    return 0;
+  } 
+  ret = read(fd, uip_buf, UIP_BUFSIZE);  
+  if(ret == -1) {
+    perror("tap_dev: tapdev_read: read");
+  }
+  gettimeofday(&tv, &tz);
+  lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec);
+
+  return ret;
+}
+/*-----------------------------------------------------------------------------------*/
+void
+tapdev_send(void)
+{
+  int ret;
+  struct iovec iov[2];
+  
+#ifdef linux
+  {
+    char tmpbuf[UIP_BUFSIZE];
+    int i;
+
+    for(i = 0; i < 40 + UIP_LLH_LEN; i++) {
+      tmpbuf[i] = uip_buf[i];
+    }
+    
+    for(; i < uip_len; i++) {
+      tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN];
+    }
+    
+    ret = write(fd, tmpbuf, uip_len);
+  }  
+#else 
+
+  if(uip_len < 40 + UIP_LLH_LEN) {
+    ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN);
+  } else {
+    iov[0].iov_base = uip_buf;
+    iov[0].iov_len = 40 + UIP_LLH_LEN;
+    iov[1].iov_base = (char *)uip_appdata;
+    iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN);  
+    
+    ret = writev(fd, iov, 2);
+  }
+#endif
+  if(ret == -1) {
+    perror("tap_dev: tapdev_send: writev");
+    exit(1);
+  }
+}  
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h
new file mode 100644
index 000000000..66f1a4a71
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $
+ *
+ */
+
+#ifndef __TAPDEV_H__
+#define __TAPDEV_H__
+
+void tapdev_init(void);
+unsigned int tapdev_read(void);
+void tapdev_send(void);
+
+#endif /* __TAPDEV_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c
new file mode 100644
index 000000000..7dff714ca
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c
@@ -0,0 +1,181 @@
+/**
+ * \addtogroup telnetd
+ * @{
+ */
+
+/**
+ * \file
+ * An example telnet server shell
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the Contiki desktop OS.
+ *
+ * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "telnetd.h"
+#include 
+
+struct ptentry {
+  char c;
+  void (* pfunc)(struct telnetd_state *s, char *str);
+};
+
+/*-----------------------------------------------------------------------------------*/
+static void
+parse(struct telnetd_state *s, register char *str, struct ptentry *t)
+{
+  register struct ptentry *p;
+  char *sstr;
+
+  sstr = str;
+  
+  /* Loop over the parse table entries in t in order to find one that
+     matches the first character in str. */
+  for(p = t; p->c != 0; ++p) {
+    if(*str == p->c) {
+      /* Skip rest of the characters up to the first space. */
+      while(*str != ' ') {
+	++str;
+      }
+
+      /* Skip all spaces.*/
+      while(*str == ' ') {
+	++str;
+      }
+
+      /* Call parse table entry function and return. */
+      p->pfunc(s, str);
+      return;
+    }
+  }
+
+  /* Did not find matching entry in parse table. We just call the
+     default handler supplied by the caller and return. */
+  p->pfunc(s, str);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+exitt(struct telnetd_state *s, char *str)
+{
+  telnetd_close(s);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+inttostr(register char *str, unsigned int i)
+{
+  str[0] = '0' + i / 100;
+  if(str[0] == '0') {
+    str[0] = ' ';
+  }
+  str[1] = '0' + (i / 10) % 10;
+  if(str[1] == '0') {
+    str[1] = ' ';
+  }
+  str[2] = '0' + i % 10;
+  str[3] = ' ';
+  str[4] = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+stats(struct telnetd_state *s, char *strr)
+{
+  char str[10];
+
+  inttostr(str, uip_stat.ip.recv);
+  telnetd_output(s, "IP packets received ", str);
+  inttostr(str, uip_stat.ip.sent);
+  telnetd_output(s, "IP packets sent ", str);
+  inttostr(str, uip_stat.ip.drop);
+  telnetd_output(s, "IP packets dropped ", str);
+
+  inttostr(str, uip_stat.icmp.recv);
+  telnetd_output(s, "ICMP packets received ", str);
+  inttostr(str, uip_stat.icmp.sent);
+  telnetd_output(s, "ICMP packets sent ", str);
+  inttostr(str, uip_stat.icmp.drop);
+  telnetd_output(s, "ICMP packets dropped ", str);
+
+  inttostr(str, uip_stat.tcp.recv);
+  telnetd_output(s, "TCP packets received ", str);
+  inttostr(str, uip_stat.tcp.sent);
+  telnetd_output(s, "TCP packets sent ", str);
+  inttostr(str, uip_stat.tcp.drop);
+  telnetd_output(s, "TCP packets dropped ", str);
+  inttostr(str, uip_stat.tcp.rexmit);
+  telnetd_output(s, "TCP packets retransmitted ", str);
+  inttostr(str, uip_stat.tcp.synrst);
+  telnetd_output(s, "TCP connection attempts ", str);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+help(struct telnetd_state *s, char *str)
+{
+  telnetd_output(s, "Available commands:", "");
+  telnetd_output(s, "stats - show uIP statistics", "");
+  telnetd_output(s, "exit  - exit shell", "");  
+  telnetd_output(s, "?     - show this help", "");        
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+none(struct telnetd_state *s, char *str)
+{
+  if(strlen(str) > 0) {
+    telnetd_output(s, "Unknown command", "");
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static struct ptentry configparsetab[] =
+  {{'s', stats},
+   {'e', exitt},
+   {'?', help},
+
+   /* Default action */
+   {0, none}};
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_connected(struct telnetd_state *s)
+{
+  telnetd_output(s, "uIP command shell", "");
+  telnetd_output(s, "Type '?' for help", "");  
+  telnetd_prompt(s, "uIP-0.9> "); 
+}
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_input(struct telnetd_state *s, char *cmd)
+{
+  parse(s, cmd, configparsetab);
+  telnetd_prompt(s, "uIP-0.9> "); 
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c
new file mode 100644
index 000000000..dba522271
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c
@@ -0,0 +1,392 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \defgroup telnetd Telnet server
+ * @{
+ *
+ * The uIP telnet server provides a command based interface to uIP. It
+ * allows using the "telnet" application to access uIP, and implements
+ * the required telnet option negotiation.
+ *
+ * The code is structured in a way which makes it possible to add
+ * commands without having to rewrite the main telnet code. The main
+ * telnet code calls two callback functions, telnetd_connected() and
+ * telnetd_input(), when a telnet connection has been established and
+ * when a line of text arrives on a telnet connection. These two
+ * functions can be implemented in a way which suits the particular
+ * application or environment in which the uIP system is intended to
+ * be run.
+ *
+ * The uIP distribution contains an example telnet shell
+ * implementation that provides a basic set of commands.
+ */
+
+/**
+ * \file
+ * Implementation of the Telnet server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "memb.h"
+#include "telnetd.h"
+#include 
+
+#define ISO_nl       0x0a
+#define ISO_cr       0x0d
+
+MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES);
+
+static u8_t i;
+
+#define STATE_NORMAL 0
+#define STATE_IAC    1
+#define STATE_WILL   2
+#define STATE_WONT   3
+#define STATE_DO     4  
+#define STATE_DONT   5
+#define STATE_CLOSE  6
+
+#define TELNET_IAC   255
+#define TELNET_WILL  251
+#define TELNET_WONT  252
+#define TELNET_DO    253
+#define TELNET_DONT  254
+/*-----------------------------------------------------------------------------------*/
+static char *
+alloc_line(void)
+{  
+  return memb_alloc(&linemem);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+dealloc_line(char *line)
+{
+  memb_free(&linemem, line);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+sendline(struct telnetd_state *s, char *line)
+{
+  static unsigned int i;
+  for(i = 0; i < TELNETD_NUMLINES; ++i) {
+    if(s->lines[i] == NULL) {
+      s->lines[i] = line;
+      break;
+    }
+  }
+  if(i == TELNETD_NUMLINES) {
+    dealloc_line(line);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Close a telnet session.
+ *
+ * This function can be called from a telnet command in order to close
+ * the connection.
+ *
+ * \param s The connection which is to be closed.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_close(struct telnetd_state *s)
+{
+  s->state = STATE_CLOSE;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Print a prompt on a telnet connection.
+ *
+ * This function can be called by the telnet command shell in order to
+ * print out a command prompt.
+ *
+ * \param s A telnet connection.
+ *
+ * \param str The command prompt.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_prompt(struct telnetd_state *s, char *str)
+{
+  char *line;
+  line = alloc_line();
+  if(line != NULL) {
+    strncpy(line, str, TELNETD_LINELEN);
+    sendline(s, line);
+  }         
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Print out a string on a telnet connection.
+ *
+ * This function can be called from a telnet command parser in order
+ * to print out a string of text on the connection. The two strings
+ * given as arguments to the function will be concatenated, a carrige
+ * return and a new line character will be added, and the line is
+ * sent.
+ *
+ * \param s The telnet connection.
+ *
+ * \param str1 The first string.
+ *
+ * \param str2 The second string.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_output(struct telnetd_state *s, char *str1, char *str2)
+{
+  static unsigned len;
+  char *line;
+  
+  line = alloc_line();
+  if(line != NULL) {
+    len = strlen(str1);
+    strncpy(line, str1, TELNETD_LINELEN);
+    if(len < TELNETD_LINELEN) {
+      strncpy(line + len, str2, TELNETD_LINELEN - len);
+    }
+    len = strlen(line);
+    if(len < TELNETD_LINELEN - 2) {
+      line[len] = ISO_cr;
+      line[len+1] = ISO_nl;
+      line[len+2] = 0;
+    }
+    sendline(s, line);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the telnet server.
+ *
+ * This function will perform the necessary initializations and start
+ * listening on TCP port 23.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_init(void)
+{
+  memb_init(&linemem);
+  uip_listen(HTONS(23));
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+acked(struct telnetd_state *s)     
+{
+  dealloc_line(s->lines[0]);
+  for(i = 1; i < TELNETD_NUMLINES; ++i) {
+    s->lines[i - 1] = s->lines[i];
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+senddata(struct telnetd_state *s)    
+{
+  if(s->lines[0] != NULL) {
+    uip_send(s->lines[0], strlen(s->lines[0]));
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+getchar(struct telnetd_state *s, u8_t c)
+{
+  if(c == ISO_cr) {
+    return;
+  }
+  
+  s->buf[(int)s->bufptr] = c;  
+  if(s->buf[(int)s->bufptr] == ISO_nl ||
+     s->bufptr == sizeof(s->buf) - 1) {    
+    if(s->bufptr > 0) {
+      s->buf[(int)s->bufptr] = 0;
+    }
+    telnetd_input(s, s->buf);
+    s->bufptr = 0;
+  } else {
+    ++s->bufptr;
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+sendopt(struct telnetd_state *s, u8_t option, u8_t value)
+{
+  char *line;
+  line = alloc_line();
+  if(line != NULL) {
+    line[0] = TELNET_IAC;
+    line[1] = option;
+    line[2] = value;
+    line[3] = 0;
+    sendline(s, line);
+  }       
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+newdata(struct telnetd_state *s)
+{
+  u16_t len;
+  u8_t c;
+    
+  
+  len = uip_datalen();
+  
+  while(len > 0 && s->bufptr < sizeof(s->buf)) {
+    c = *uip_appdata;
+    ++uip_appdata;
+    --len;
+    switch(s->state) {
+    case STATE_IAC:
+      if(c == TELNET_IAC) {
+	getchar(s, c);
+	s->state = STATE_NORMAL;
+      } else {
+	switch(c) {
+	case TELNET_WILL:
+	  s->state = STATE_WILL;
+	  break;
+	case TELNET_WONT:
+	  s->state = STATE_WONT;
+	  break;
+	case TELNET_DO:
+	  s->state = STATE_DO;
+	  break;
+	case TELNET_DONT:
+	  s->state = STATE_DONT;
+	  break;
+	default:
+	  s->state = STATE_NORMAL;
+	  break;
+	}
+      }
+      break;
+    case STATE_WILL:
+      /* Reply with a DONT */
+      sendopt(s, TELNET_DONT, c);
+      s->state = STATE_NORMAL;
+      break;
+      
+    case STATE_WONT:
+      /* Reply with a DONT */
+      sendopt(s, TELNET_DONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_DO:
+      /* Reply with a WONT */
+      sendopt(s, TELNET_WONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_DONT:
+      /* Reply with a WONT */
+      sendopt(s, TELNET_WONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_NORMAL:
+      if(c == TELNET_IAC) {
+	s->state = STATE_IAC;
+      } else {
+	getchar(s, c);
+      }      
+      break;
+    } 
+
+    
+  }  
+  
+}
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_app(void)
+{
+  struct telnetd_state *s;
+
+  s = (struct telnetd_state *)uip_conn->appstate;
+  
+  if(uip_connected()) {
+
+    for(i = 0; i < TELNETD_NUMLINES; ++i) {
+      s->lines[i] = NULL;
+    }
+    s->bufptr = 0;
+    s->state = STATE_NORMAL;
+
+    telnetd_connected(s);
+    senddata(s);
+    return;
+  }
+
+  if(s->state == STATE_CLOSE) {
+    s->state = STATE_NORMAL;
+    uip_close();
+    return;
+  }
+  
+  if(uip_closed()) {
+    telnetd_output(s, "Connection closed", "");
+  }
+
+  
+  if(uip_aborted()) {
+    telnetd_output(s, "Connection reset", "");
+  }
+  
+  if(uip_timedout()) {
+    telnetd_output(s, "Connection timed out", "");
+  }
+  
+  if(uip_acked()) {
+    acked(s);
+  }
+  
+  if(uip_newdata()) {
+    newdata(s);
+  }
+  
+  if(uip_rexmit() ||
+     uip_newdata() ||
+     uip_acked()) {
+    senddata(s);
+  } else if(uip_poll()) {    
+    senddata(s);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h
new file mode 100644
index 000000000..254e44ff1
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h
@@ -0,0 +1,114 @@
+/**
+ * \addtogroup telnetd
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the telnet server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2002, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+#ifndef __TELNETD_H__
+#define __TELNETD_H__
+
+#include "uip.h"
+
+/**
+ * The maximum length of a telnet line.
+ *
+ * \hideinitializer
+ */
+#define TELNETD_LINELEN 36
+
+/**
+ * The number of output lines being buffered for all telnet
+ * connections.
+ *
+ * \hideinitializer
+ */
+#define TELNETD_NUMLINES 2
+
+/**
+ * A telnet connection structure.
+ */
+struct telnetd_state {
+  char *lines[TELNETD_NUMLINES];
+  char buf[TELNETD_LINELEN];
+  char bufptr;
+  u8_t state;
+};
+
+
+/**
+ * Callback function that is called when a telnet connection has been
+ * established.
+ *
+ * \param s The telnet connection. 
+ */
+void telnetd_connected(struct telnetd_state *s);
+
+/**
+ * Callback function that is called when a line of text has arrived on
+ * a telnet connection.
+ *
+ * \param s The telnet connection.
+ *
+ * \param cmd The line of text.
+ */
+void telnetd_input(struct telnetd_state *s, char *cmd);
+
+
+void telnetd_close(struct telnetd_state *s);
+void telnetd_output(struct telnetd_state *s, char *s1, char *s2);
+void telnetd_prompt(struct telnetd_state *s, char *str);
+
+void telnetd_app(void);
+
+#ifndef UIP_APPCALL
+#define UIP_APPCALL     telnetd_app
+#endif
+
+#ifndef UIP_APPSTATE_SIZE
+#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state))
+#endif
+
+void telnetd_init(void);
+
+
+#endif /* __TELNET_H__ */
+
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip.c
new file mode 100644
index 000000000..37f64facc
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip.c
@@ -0,0 +1,1514 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $
+ *
+ */
+
+/*
+This is a small implementation of the IP and TCP protocols (as well as
+some basic ICMP stuff). The implementation couples the IP, TCP and the
+application layers very tightly. To keep the size of the compiled code
+down, this code also features heavy usage of the goto statement.
+
+The principle is that we have a small buffer, called the uip_buf, in
+which the device driver puts an incoming packet. The TCP/IP stack
+parses the headers in the packet, and calls upon the application. If
+the remote host has sent data to the application, this data is present
+in the uip_buf and the application read the data from there. It is up
+to the application to put this data into a byte stream if needed. The
+application will not be fed with data that is out of sequence.
+
+If the application whishes to send data to the peer, it should put its
+data into the uip_buf, 40 bytes from the start of the buffer. The
+TCP/IP stack will calculate the checksums, and fill in the necessary
+header fields and finally send the packet back to the peer.
+*/
+
+#include "uip.h"
+#include "uipopt.h"
+#include "uip_arch.h"
+
+/*-----------------------------------------------------------------------------------*/
+/* Variable definitions. */
+
+
+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+const u16_t uip_hostaddr[2] =
+  {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),
+   HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};
+const u16_t uip_arp_draddr[2] =
+  {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),
+   HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};
+const u16_t uip_arp_netmask[2] =
+  {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),
+   HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};
+#else
+u16_t uip_hostaddr[2];
+u16_t uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* UIP_FIXEDADDR */
+
+u8_t uip_buf[UIP_BUFSIZE+2];   /* The packet buffer that contains
+				incoming packets. */
+volatile u8_t *uip_appdata;  /* The uip_appdata pointer points to
+				application data. */
+volatile u8_t *uip_sappdata;  /* The uip_appdata pointer points to the
+				 application data which is to be sent. */
+#if UIP_URGDATA > 0
+volatile u8_t *uip_urgdata;  /* The uip_urgdata pointer points to
+				urgent data (out-of-band data), if
+				present. */
+volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+volatile u16_t uip_len, uip_slen;
+                             /* The uip_len is either 8 or 16 bits,
+				depending on the maximum packet
+				size. */
+
+volatile u8_t uip_flags;     /* The uip_flags variable is used for
+				communication between the TCP/IP stack
+				and the application program. */
+struct uip_conn *uip_conn;   /* uip_conn always points to the current
+				connection. */
+
+struct uip_conn uip_conns[UIP_CONNS];
+                             /* The uip_conns array holds all TCP
+				connections. */
+u16_t uip_listenports[UIP_LISTENPORTS];
+                             /* The uip_listenports list all currently
+				listning ports. */
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_conn;
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+
+static u16_t ipid;           /* Ths ipid variable is an increasing
+				number that is used for the IP ID
+				field. */
+
+static u8_t iss[4];          /* The iss variable is used for the TCP
+				initial sequence number. */
+
+#if UIP_ACTIVE_OPEN
+static u16_t lastport;       /* Keeps track of the last port used for
+				a new connection. */
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+volatile u8_t uip_acc32[4];
+static u8_t c, opt;
+static u16_t tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN 0x01
+#define TCP_SYN 0x02
+#define TCP_RST 0x04
+#define TCP_PSH 0x08
+#define TCP_ACK 0x10
+#define TCP_URG 0x20
+#define TCP_CTL 0x3f
+
+#define ICMP_ECHO_REPLY 0
+#define ICMP_ECHO       8
+
+/* Macros. */
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0])
+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+#if UIP_STATISTICS == 1
+struct uip_stats uip_stat;
+#define UIP_STAT(s) s
+#else
+#define UIP_STAT(s)
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+#include 
+void uip_log(char *msg);
+#define UIP_LOG(m) uip_log(m)
+#else
+#define UIP_LOG(m)
+#endif /* UIP_LOGGING == 1 */
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_init(void)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    uip_listenports[c] = 0;
+  }
+  for(c = 0; c < UIP_CONNS; ++c) {
+    uip_conns[c].tcpstateflags = CLOSED;
+  }
+#if UIP_ACTIVE_OPEN
+  lastport = 1024;
+#endif /* UIP_ACTIVE_OPEN */
+
+#if UIP_UDP
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    uip_udp_conns[c].lport = 0;
+  }
+#endif /* UIP_UDP */
+
+
+  /* IPv4 initialization. */
+#if UIP_FIXEDADDR == 0
+  uip_hostaddr[0] = uip_hostaddr[1] = 0;
+#endif /* UIP_FIXEDADDR */
+
+}
+/*-----------------------------------------------------------------------------------*/
+#if UIP_ACTIVE_OPEN
+struct uip_conn *
+uip_connect(u16_t *ripaddr, u16_t rport)
+{
+  register struct uip_conn *conn, *cconn;
+
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  /* Check if this port is already in use, and if so try to find
+     another one. */
+  for(c = 0; c < UIP_CONNS; ++c) {
+    conn = &uip_conns[c];
+    if(conn->tcpstateflags != CLOSED &&
+       conn->lport == htons(lastport)) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    cconn = &uip_conns[c];
+    if(cconn->tcpstateflags == CLOSED) {
+      conn = cconn;
+      break;
+    }
+    if(cconn->tcpstateflags == TIME_WAIT) {
+      if(conn == 0 ||
+	 cconn->timer > uip_conn->timer) {
+	conn = cconn;
+      }
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+
+  conn->tcpstateflags = SYN_SENT;
+
+  conn->snd_nxt[0] = iss[0];
+  conn->snd_nxt[1] = iss[1];
+  conn->snd_nxt[2] = iss[2];
+  conn->snd_nxt[3] = iss[3];
+
+  conn->initialmss = conn->mss = UIP_TCP_MSS;
+
+  conn->len = 1;   /* TCP length of the SYN is one. */
+  conn->nrtx = 0;
+  conn->timer = 1; /* Send the SYN next time around. */
+  conn->rto = UIP_RTO;
+  conn->sa = 0;
+  conn->sv = 16;
+  conn->lport = htons(lastport);
+  conn->rport = rport;
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+
+  return conn;
+}
+#endif /* UIP_ACTIVE_OPEN */
+/*-----------------------------------------------------------------------------------*/
+#if UIP_UDP
+struct uip_udp_conn *
+uip_udp_new(u16_t *ripaddr, u16_t rport)
+{
+  register struct uip_udp_conn *conn;
+
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == lastport) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == 0) {
+      conn = &uip_udp_conns[c];
+      break;
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+
+  conn->lport = HTONS(lastport);
+  conn->rport = HTONS(rport);
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+
+  return conn;
+}
+#endif /* UIP_UDP */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_unlisten(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == port) {
+      uip_listenports[c] = 0;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_listen(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == 0) {
+      uip_listenports[c] = port;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/* XXX: IP fragment reassembly: not well-tested. */
+
+#if UIP_REASSEMBLY
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,
+				    0x0f, 0x07, 0x03, 0x01};
+static u16_t uip_reasslen;
+static u8_t uip_reassflags;
+#define UIP_REASS_FLAG_LASTFRAG 0x01
+static u8_t uip_reasstmr;
+
+#define IP_HLEN 20
+#define IP_MF   0x20
+
+static u8_t
+uip_reass(void)
+{
+  u16_t offset, len;
+  u16_t i;
+
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if(uip_reasstmr == 0) {
+    memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN);
+    uip_reasstmr = UIP_REASS_MAXAGE;
+    uip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0);
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&
+     BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&
+     BUF->destipaddr[0] == FBUF->destipaddr[0] &&
+     BUF->destipaddr[1] == FBUF->destipaddr[1] &&
+     BUF->ipid[0] == FBUF->ipid[0] &&
+     BUF->ipid[1] == FBUF->ipid[1]) {
+
+    len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;
+    offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if(offset > UIP_REASS_BUFSIZE ||
+       offset + len > UIP_REASS_BUFSIZE) {
+      uip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    memcpy(&uip_reassbuf[IP_HLEN + offset],
+	   (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
+	   len);
+
+    /* Update the bitmap. */
+    if(offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      /* If the two endpoints are in the same byte, we only update
+	 that byte. */
+	
+      uip_reassbitmap[offset / (8 * 8)] |=
+	     bitmap_bits[(offset / 8 ) & 7] &
+	     ~bitmap_bits[((offset + len) / 8 ) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+	 bytes in the endpoints and fill the stuff inbetween with
+	 0xff. */
+      uip_reassbitmap[offset / (8 * 8)] |=
+	bitmap_bits[(offset / 8 ) & 7];
+      for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+	uip_reassbitmap[i] = 0xff;
+      }
+      uip_reassbitmap[(offset + len) / (8 * 8)] |=
+	~bitmap_bits[((offset + len) / 8 ) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if((BUF->ipoffset[0] & IP_MF) == 0) {
+      uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+      uip_reasslen = offset + len;
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+	 the bitmap. */
+      for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {
+	if(uip_reassbitmap[i] != 0xff) {
+	  goto nullreturn;
+	}
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+	 right amount of bits. */
+      if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=
+	 (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
+	goto nullreturn;
+      }
+
+      /* If we have come this far, we have a full packet in the
+	 buffer, so we allocate a pbuf and copy the packet into it. We
+	 also reset the timer. */
+      uip_reasstmr = 0;
+      memcpy(BUF, FBUF, uip_reasslen);
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+	 from now on. */
+      BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+      BUF->len[0] = uip_reasslen >> 8;
+      BUF->len[1] = uip_reasslen & 0xff;
+      BUF->ipchksum = 0;
+      BUF->ipchksum = ~(uip_ipchksum());
+
+      return uip_reasslen;
+    }
+  }
+
+ nullreturn:
+  return 0;
+}
+#endif /* UIP_REASSEMBL */
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_add_rcv_nxt(u16_t n)
+{
+  uip_add32(uip_conn->rcv_nxt, n);
+  uip_conn->rcv_nxt[0] = uip_acc32[0];
+  uip_conn->rcv_nxt[1] = uip_acc32[1];
+  uip_conn->rcv_nxt[2] = uip_acc32[2];
+  uip_conn->rcv_nxt[3] = uip_acc32[3];
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_process(u8_t flag)
+{
+  register struct uip_conn *uip_connr = uip_conn;
+
+  uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+
+
+  /* Check if we were invoked because of the perodic timer fireing. */
+  if(flag == UIP_TIMER) {
+#if UIP_REASSEMBLY
+    if(uip_reasstmr != 0) {
+      --uip_reasstmr;
+    }
+#endif /* UIP_REASSEMBLY */
+    /* Increase the initial sequence number. */
+    if(++iss[3] == 0) {
+      if(++iss[2] == 0) {
+	if(++iss[1] == 0) {
+	  ++iss[0];
+	}
+      }
+    }
+    uip_len = 0;
+    if(uip_connr->tcpstateflags == TIME_WAIT ||
+       uip_connr->tcpstateflags == FIN_WAIT_2) {
+      ++(uip_connr->timer);
+      if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {
+	uip_connr->tcpstateflags = CLOSED;
+      }
+    } else if(uip_connr->tcpstateflags != CLOSED) {
+      /* If the connection has outstanding data, we increase the
+	 connection's timer and see if it has reached the RTO value
+	 in which case we retransmit. */
+      if(uip_outstanding(uip_connr)) {
+	if(uip_connr->timer-- == 0) {
+	  if(uip_connr->nrtx == UIP_MAXRTX ||
+	     ((uip_connr->tcpstateflags == SYN_SENT ||
+	       uip_connr->tcpstateflags == SYN_RCVD) &&
+	      uip_connr->nrtx == UIP_MAXSYNRTX)) {
+	    uip_connr->tcpstateflags = CLOSED;
+
+	    /* We call UIP_APPCALL() with uip_flags set to
+	       UIP_TIMEDOUT to inform the application that the
+	       connection has timed out. */
+	    uip_flags = UIP_TIMEDOUT;
+	    UIP_APPCALL();
+
+	    /* We also send a reset packet to the remote host. */
+	    BUF->flags = TCP_RST | TCP_ACK;
+	    goto tcp_send_nodata;
+	  }
+
+	  /* Exponential backoff. */
+	  uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
+					 4:
+					 uip_connr->nrtx);
+	  ++(uip_connr->nrtx);
+	
+	  /* Ok, so we need to retransmit. We do this differently
+	     depending on which state we are in. In ESTABLISHED, we
+	     call upon the application so that it may prepare the
+	     data for the retransmit. In SYN_RCVD, we resend the
+	     SYNACK that we sent earlier and in LAST_ACK we have to
+	     retransmit our FINACK. */
+	  UIP_STAT(++uip_stat.tcp.rexmit);
+	  switch(uip_connr->tcpstateflags & TS_MASK) {
+	  case SYN_RCVD:
+	    /* In the SYN_RCVD state, we should retransmit our
+               SYNACK. */
+	    goto tcp_send_synack;
+	
+#if UIP_ACTIVE_OPEN
+	  case SYN_SENT:
+	    /* In the SYN_SENT state, we retransmit out SYN. */
+	    BUF->flags = 0;
+	    goto tcp_send_syn;
+#endif /* UIP_ACTIVE_OPEN */
+	
+	  case ESTABLISHED:
+	    /* In the ESTABLISHED state, we call upon the application
+               to do the actual retransmit after which we jump into
+               the code for sending out the packet (the apprexmit
+               label). */
+	    uip_len = 0;
+	    uip_slen = 0;
+	    uip_flags = UIP_REXMIT;
+	    UIP_APPCALL();
+	    goto apprexmit;
+	
+	  case FIN_WAIT_1:
+	  case CLOSING:
+	  case LAST_ACK:
+	    /* In all these states we should retransmit a FINACK. */
+	    goto tcp_send_finack;
+	
+	  }
+	}
+      } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) {
+	/* If there was no need for a retransmission, we poll the
+           application for new data. */
+	uip_len = 0;
+	uip_slen = 0;
+	uip_flags = UIP_POLL;
+	UIP_APPCALL();
+	goto appsend;
+      }
+    }
+    goto drop;
+  }
+#if UIP_UDP
+  if(flag == UIP_UDP_TIMER) {
+    if(uip_udp_conn->lport != 0) {
+      uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+      uip_len = uip_slen = 0;
+      uip_flags = UIP_POLL;
+      UIP_UDP_APPCALL();
+      goto udp_send;
+    } else {
+      goto drop;
+    }
+  }
+#endif
+
+  /* This is where the input processing starts. */
+  UIP_STAT(++uip_stat.ip.recv);
+
+
+  /* Start of IPv4 input header processing code. */
+
+  /* Check validity of the IP header. */
+  if(BUF->vhl != 0x45)  { /* IP version and header length. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.vhlerr);
+    UIP_LOG("ip: invalid version or header length.");
+    goto drop;
+  }
+
+  /* Check the size of the packet. If the size reported to us in
+     uip_len doesn't match the size reported in the IP header, there
+     has been a transmission error and we drop the packet. */
+
+  if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */
+    uip_len = (uip_len & 0xff) | (BUF->len[0] << 8);
+  }
+  if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */
+    uip_len = (uip_len & 0xff00) | BUF->len[1];
+  }
+
+  /* Check the fragment flag. */
+  if((BUF->ipoffset[0] & 0x3f) != 0 ||
+     BUF->ipoffset[1] != 0) {
+#if UIP_REASSEMBLY
+    uip_len = uip_reass();
+    if(uip_len == 0) {
+      goto drop;
+    }
+#else
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.fragerr);
+    UIP_LOG("ip: fragment dropped.");
+    goto drop;
+#endif /* UIP_REASSEMBLY */
+  }
+
+  /* If we are configured to use ping IP address configuration and
+     hasn't been assigned an IP address yet, we accept all ICMP
+     packets. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    if(BUF->proto == UIP_PROTO_ICMP) {
+      UIP_LOG("ip: possible ping config packet received.");
+      goto icmp_input;
+    } else {
+      UIP_LOG("ip: packet dropped since no address assigned.");
+      goto drop;
+    }
+  }
+#endif /* UIP_PINGADDRCONF */
+
+  /* Check if the packet is destined for our IP address. */
+  if(BUF->destipaddr[0] != uip_hostaddr[0]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_LOG("ip: packet not for us.");
+    goto drop;
+  }
+  if(BUF->destipaddr[1] != uip_hostaddr[1]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_LOG("ip: packet not for us.");
+    goto drop;
+  }
+
+#if 0
+  // IP checksum is wrong through Netgear DSL router
+  if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header
+				    checksum. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.chkerr);
+    UIP_LOG("ip: bad checksum.");
+    goto drop;
+  }
+#endif
+
+  if(BUF->proto == UIP_PROTO_TCP)  /* Check for TCP packet. If so, jump
+                                     to the tcp_input label. */
+    goto tcp_input;
+
+#if UIP_UDP
+  if(BUF->proto == UIP_PROTO_UDP)
+    goto udp_input;
+#endif /* UIP_UDP */
+
+  if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from
+					here. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.protoerr);
+    UIP_LOG("ip: neither tcp nor icmp.");
+    goto drop;
+  }
+
+#if UIP_PINGADDRCONF
+ icmp_input:
+#endif
+  UIP_STAT(++uip_stat.icmp.recv);
+
+  /* ICMP echo (i.e., ping) processing. This is simple, we only change
+     the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+     checksum before we return the packet. */
+  if(ICMPBUF->type != ICMP_ECHO) {
+    UIP_STAT(++uip_stat.icmp.drop);
+    UIP_STAT(++uip_stat.icmp.typeerr);
+    UIP_LOG("icmp: not icmp echo.");
+    goto drop;
+  }
+
+  /* If we are configured to use ping IP address assignment, we use
+     the destination IP address of this ping packet and assign it to
+     ourself. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    uip_hostaddr[0] = BUF->destipaddr[0];
+    uip_hostaddr[1] = BUF->destipaddr[1];
+  }
+#endif /* UIP_PINGADDRCONF */
+
+  ICMPBUF->type = ICMP_ECHO_REPLY;
+
+  if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;
+  } else {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);
+  }
+
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  UIP_STAT(++uip_stat.icmp.sent);
+  goto send;
+
+  /* End of IPv4 input header processing code. */
+
+
+#if UIP_UDP
+  /* UDP input processing. */
+ udp_input:
+  /* UDP processing is really just a hack. We don't do anything to the
+     UDP/IP headers, but let the UDP application do all the hard
+     work. If the application sets uip_slen, it has a packet to
+     send. */
+#if UIP_UDP_CHECKSUMS
+  if(uip_udpchksum() != 0xffff) {
+    UIP_STAT(++uip_stat.udp.drop);
+    UIP_STAT(++uip_stat.udp.chkerr);
+    UIP_LOG("udp: bad checksum.");
+    goto drop;
+  }
+#endif /* UIP_UDP_CHECKSUMS */
+
+  /* Demultiplex this UDP packet between the UDP "connections". */
+  for(uip_udp_conn = &uip_udp_conns[0];
+      uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];
+      ++uip_udp_conn) {
+    if(uip_udp_conn->lport != 0 &&
+       UDPBUF->destport == uip_udp_conn->lport &&
+       (uip_udp_conn->rport == 0 ||
+        UDPBUF->srcport == uip_udp_conn->rport) &&
+       BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) {
+      goto udp_found;
+    }
+  }
+  goto drop;
+
+ udp_found:
+  uip_len = uip_len - 28;
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+  uip_flags = UIP_NEWDATA;
+  uip_slen = 0;
+  UIP_UDP_APPCALL();
+ udp_send:
+  if(uip_slen == 0) {
+    goto drop;
+  }
+  uip_len = uip_slen + 28;
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+
+  BUF->proto = UIP_PROTO_UDP;
+
+  UDPBUF->udplen = HTONS(uip_slen + 8);
+  UDPBUF->udpchksum = 0;
+#if UIP_UDP_CHECKSUMS
+  /* Calculate UDP checksum. */
+  UDPBUF->udpchksum = ~(uip_udpchksum());
+  if(UDPBUF->udpchksum == 0) {
+    UDPBUF->udpchksum = 0xffff;
+  }
+#endif /* UIP_UDP_CHECKSUMS */
+
+  BUF->srcport  = uip_udp_conn->lport;
+  BUF->destport = uip_udp_conn->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_udp_conn->ripaddr[0];
+  BUF->destipaddr[1] = uip_udp_conn->ripaddr[1];
+
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 40];
+  goto ip_send_nolen;
+#endif /* UIP_UDP */
+
+  /* TCP input processing. */
+ tcp_input:
+  UIP_STAT(++uip_stat.tcp.recv);
+
+  /* Start of TCP input header processing code. */
+
+#if 1  // FIXME
+  if(uip_tcpchksum() != 0xffff) {   /* Compute and check the TCP
+				       checksum. */
+    UIP_STAT(++uip_stat.tcp.drop);
+    UIP_STAT(++uip_stat.tcp.chkerr);
+    UIP_LOG("tcp: bad checksum.");
+    goto drop;
+  }
+#endif
+
+  /* Demultiplex this segment. */
+  /* First check any active connections. */
+  for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) {
+    if(uip_connr->tcpstateflags != CLOSED &&
+       BUF->destport == uip_connr->lport &&
+       BUF->srcport == uip_connr->rport &&
+       BUF->srcipaddr[0] == uip_connr->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_connr->ripaddr[1]) {
+      goto found;
+    }
+  }
+
+  /* If we didn't find and active connection that expected the packet,
+     either this packet is an old duplicate, or this is a SYN packet
+     destined for a connection in LISTEN. If the SYN flag isn't set,
+     it is an old packet and we send a RST. */
+  if((BUF->flags & TCP_CTL) != TCP_SYN)
+    goto reset;
+
+  tmp16 = BUF->destport;
+  /* Next, check listening connections. */
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(tmp16 == uip_listenports[c])
+      goto found_listen;
+  }
+
+  /* No matching connection found, so we send a RST packet. */
+  UIP_STAT(++uip_stat.tcp.synrst);
+ reset:
+
+  /* We do not send resets in response to resets. */
+  if(BUF->flags & TCP_RST)
+    goto drop;
+
+  UIP_STAT(++uip_stat.tcp.rst);
+
+  BUF->flags = TCP_RST | TCP_ACK;
+  uip_len = 40;
+  BUF->tcpoffset = 5 << 4;
+
+  /* Flip the seqno and ackno fields in the TCP header. */
+  c = BUF->seqno[3];
+  BUF->seqno[3] = BUF->ackno[3];
+  BUF->ackno[3] = c;
+
+  c = BUF->seqno[2];
+  BUF->seqno[2] = BUF->ackno[2];
+  BUF->ackno[2] = c;
+
+  c = BUF->seqno[1];
+  BUF->seqno[1] = BUF->ackno[1];
+  BUF->ackno[1] = c;
+
+  c = BUF->seqno[0];
+  BUF->seqno[0] = BUF->ackno[0];
+  BUF->ackno[0] = c;
+
+  /* We also have to increase the sequence number we are
+     acknowledging. If the least significant byte overflowed, we need
+     to propagate the carry to the other bytes as well. */
+  if(++BUF->ackno[3] == 0) {
+    if(++BUF->ackno[2] == 0) {
+      if(++BUF->ackno[1] == 0) {
+	++BUF->ackno[0];
+      }
+    }
+  }
+
+  /* Swap port numbers. */
+  tmp16 = BUF->srcport;
+  BUF->srcport = BUF->destport;
+  BUF->destport = tmp16;
+
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+
+  /* And send out the RST packet! */
+  goto tcp_send_noconn;
+
+  /* This label will be jumped to if we matched the incoming packet
+     with a connection in LISTEN. In that case, we should create a new
+     connection and send a SYNACK in return. */
+ found_listen:
+  /* First we check if there are any connections avaliable. Unused
+     connections are kept in the same table as used connections, but
+     unused ones have the tcpstate set to CLOSED. Also, connections in
+     TIME_WAIT are kept track of and we'll use the oldest one if no
+     CLOSED connections are found. Thanks to Eddie C. Dost for a very
+     nice algorithm for the TIME_WAIT search. */
+  uip_connr = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    if(uip_conns[c].tcpstateflags == CLOSED) {
+      uip_connr = &uip_conns[c];
+      break;
+    }
+    if(uip_conns[c].tcpstateflags == TIME_WAIT) {
+      if(uip_connr == 0 ||
+	 uip_conns[c].timer > uip_connr->timer) {
+	uip_connr = &uip_conns[c];
+      }
+    }
+  }
+
+  if(uip_connr == 0) {
+    /* All connections are used already, we drop packet and hope that
+       the remote end will retransmit the packet at a time when we
+       have more spare connections. */
+    UIP_STAT(++uip_stat.tcp.syndrop);
+    UIP_LOG("tcp: found no unused connections.");
+    goto drop;
+  }
+  uip_conn = uip_connr;
+
+  /* Fill in the necessary fields for the new connection. */
+  uip_connr->rto = uip_connr->timer = UIP_RTO;
+  uip_connr->sa = 0;
+  uip_connr->sv = 4;
+  uip_connr->nrtx = 0;
+  uip_connr->lport = BUF->destport;
+  uip_connr->rport = BUF->srcport;
+  uip_connr->ripaddr[0] = BUF->srcipaddr[0];
+  uip_connr->ripaddr[1] = BUF->srcipaddr[1];
+  uip_connr->tcpstateflags = SYN_RCVD;
+
+  uip_connr->snd_nxt[0] = iss[0];
+  uip_connr->snd_nxt[1] = iss[1];
+  uip_connr->snd_nxt[2] = iss[2];
+  uip_connr->snd_nxt[3] = iss[3];
+  uip_connr->len = 1;
+
+  /* rcv_nxt should be the seqno from the incoming packet + 1. */
+  uip_connr->rcv_nxt[3] = BUF->seqno[3];
+  uip_connr->rcv_nxt[2] = BUF->seqno[2];
+  uip_connr->rcv_nxt[1] = BUF->seqno[1];
+  uip_connr->rcv_nxt[0] = BUF->seqno[0];
+  uip_add_rcv_nxt(1);
+
+  /* Parse the TCP MSS option, if present. */
+  if((BUF->tcpoffset & 0xf0) > 0x50) {
+    for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+      opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+      if(opt == 0x00) {
+	/* End of options. */	
+	break;
+      } else if(opt == 0x01) {
+	++c;
+	/* NOP option. */
+      } else if(opt == 0x02 &&
+		uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	/* An MSS option with the right option length. */	
+	tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	  (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c];
+	uip_connr->initialmss = uip_connr->mss =
+	  tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+	
+	/* And we are done processing options. */
+	break;
+      } else {
+	/* All other options have a length field, so that we easily
+	   can skip past them. */
+	if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	  /* If the length field is zero, the options are malformed
+	     and we don't process them further. */
+	  break;
+	}
+	c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+      }
+    }
+  }
+
+  /* Our response will be a SYNACK. */
+#if UIP_ACTIVE_OPEN
+ tcp_send_synack:
+  BUF->flags = TCP_ACK;
+
+ tcp_send_syn:
+  BUF->flags |= TCP_SYN;
+#else /* UIP_ACTIVE_OPEN */
+ tcp_send_synack:
+  BUF->flags = TCP_SYN | TCP_ACK;
+#endif /* UIP_ACTIVE_OPEN */
+
+  /* We send out the TCP Maximum Segment Size option with our
+     SYNACK. */
+  BUF->optdata[0] = 2;
+  BUF->optdata[1] = 4;
+  BUF->optdata[2] = (UIP_TCP_MSS) / 256;
+  BUF->optdata[3] = (UIP_TCP_MSS) & 255;
+  uip_len = 44;
+  BUF->tcpoffset = 6 << 4;
+  goto tcp_send;
+
+  /* This label will be jumped to if we found an active connection. */
+ found:
+  uip_conn = uip_connr;
+  uip_flags = 0;
+
+  /* We do a very naive form of TCP reset processing; we just accept
+     any RST and kill our connection. We should in fact check if the
+     sequence number of this reset is wihtin our advertised window
+     before we accept the reset. */
+  if(BUF->flags & TCP_RST) {
+    uip_connr->tcpstateflags = CLOSED;
+    UIP_LOG("tcp: got reset, aborting connection.");
+    uip_flags = UIP_ABORT;
+    UIP_APPCALL();
+    goto drop;
+  }
+  /* Calculated the length of the data, if the application has sent
+     any data to us. */
+  c = (BUF->tcpoffset >> 4) << 2;
+  /* uip_len will contain the length of the actual TCP data. This is
+     calculated by subtracing the length of the TCP header (in
+     c) and the length of the IP header (20 bytes). */
+  uip_len = uip_len - c - 20;
+
+  /* First, check if the sequence number of the incoming packet is
+     what we're expecting next. If not, we send out an ACK with the
+     correct numbers in. */
+  if(uip_len > 0 &&
+     (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
+      BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+      BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+      BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
+    goto tcp_send_ack;
+  }
+
+  /* Next, check if the incoming segment acknowledges any outstanding
+     data. If so, we update the sequence number, reset the length of
+     the outstanding data, calculate RTT estimations, and reset the
+     retransmission timer. */
+  if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {
+    uip_add32(uip_connr->snd_nxt, uip_connr->len);
+    if(BUF->ackno[0] == uip_acc32[0] &&
+       BUF->ackno[1] == uip_acc32[1] &&
+       BUF->ackno[2] == uip_acc32[2] &&
+       BUF->ackno[3] == uip_acc32[3]) {
+      /* Update sequence number. */
+      uip_connr->snd_nxt[0] = uip_acc32[0];
+      uip_connr->snd_nxt[1] = uip_acc32[1];
+      uip_connr->snd_nxt[2] = uip_acc32[2];
+      uip_connr->snd_nxt[3] = uip_acc32[3];
+	
+
+      /* Do RTT estimation, unless we have done retransmissions. */
+      if(uip_connr->nrtx == 0) {
+	signed char m;
+	m = uip_connr->rto - uip_connr->timer;
+	/* This is taken directly from VJs original code in his paper */
+	m = m - (uip_connr->sa >> 3);
+	uip_connr->sa += m;
+	if(m < 0) {
+	  m = -m;
+	}
+	m = m - (uip_connr->sv >> 2);
+	uip_connr->sv += m;
+	uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
+
+      }
+      /* Set the acknowledged flag. */
+      uip_flags = UIP_ACKDATA;
+      /* Reset the retransmission timer. */
+      uip_connr->timer = uip_connr->rto;
+    }
+
+  }
+
+  /* Do different things depending on in what state the connection is. */
+  switch(uip_connr->tcpstateflags & TS_MASK) {
+    /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+	implemented, since we force the application to close when the
+	peer sends a FIN (hence the application goes directly from
+	ESTABLISHED to LAST_ACK). */
+  case SYN_RCVD:
+    /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+       we are waiting for an ACK that acknowledges the data we sent
+       out the last time. Therefore, we want to have the UIP_ACKDATA
+       flag set. If so, we enter the ESTABLISHED state. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = ESTABLISHED;
+      uip_flags = UIP_CONNECTED;
+      uip_connr->len = 0;
+      if(uip_len > 0) {
+        uip_flags |= UIP_NEWDATA;
+        uip_add_rcv_nxt(uip_len);
+      }
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto drop;
+#if UIP_ACTIVE_OPEN
+  case SYN_SENT:
+    /* In SYN_SENT, we wait for a SYNACK that is sent in response to
+       our SYN. The rcv_nxt is set to sequence number in the SYNACK
+       plus one, and we send an ACK. We move into the ESTABLISHED
+       state. */
+    if((uip_flags & UIP_ACKDATA) &&
+       BUF->flags == (TCP_SYN | TCP_ACK)) {
+
+      /* Parse the TCP MSS option, if present. */
+      if((BUF->tcpoffset & 0xf0) > 0x50) {
+	for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+	  opt = uip_buf[40 + UIP_LLH_LEN + c];
+	  if(opt == 0x00) {
+	    /* End of options. */	
+	    break;
+	  } else if(opt == 0x01) {
+	    ++c;
+	    /* NOP option. */
+	  } else if(opt == 0x02 &&
+		    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	    /* An MSS option with the right option length. */
+	    tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	      uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+	    uip_connr->initialmss =
+	      uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+
+	    /* And we are done processing options. */
+	    break;
+	  } else {
+	    /* All other options have a length field, so that we easily
+	       can skip past them. */
+	    if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	      /* If the length field is zero, the options are malformed
+		 and we don't process them further. */
+	      break;
+	    }
+	    c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+	  }
+	}
+      }
+      uip_connr->tcpstateflags = ESTABLISHED;
+      uip_connr->rcv_nxt[0] = BUF->seqno[0];
+      uip_connr->rcv_nxt[1] = BUF->seqno[1];
+      uip_connr->rcv_nxt[2] = BUF->seqno[2];
+      uip_connr->rcv_nxt[3] = BUF->seqno[3];
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+      uip_connr->len = 0;
+      uip_len = 0;
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto reset;
+#endif /* UIP_ACTIVE_OPEN */
+
+  case ESTABLISHED:
+    /* In the ESTABLISHED state, we call upon the application to feed
+    data into the uip_buf. If the UIP_ACKDATA flag is set, the
+    application should put new data into the buffer, otherwise we are
+    retransmitting an old segment, and the application should put that
+    data into the buffer.
+
+    If the incoming packet is a FIN, we should close the connection on
+    this side as well, and we send out a FIN and enter the LAST_ACK
+    state. We require that there is no outstanding data; otherwise the
+    sequence numbers will be screwed up. */
+
+    if(BUF->flags & TCP_FIN) {
+      if(uip_outstanding(uip_connr)) {
+	goto drop;
+      }
+      uip_add_rcv_nxt(1 + uip_len);
+      uip_flags = UIP_CLOSE;
+      if(uip_len > 0) {
+	uip_flags |= UIP_NEWDATA;
+      }
+      UIP_APPCALL();
+      uip_connr->len = 1;
+      uip_connr->tcpstateflags = LAST_ACK;
+      uip_connr->nrtx = 0;
+    tcp_send_finack:
+      BUF->flags = TCP_FIN | TCP_ACK;
+      goto tcp_send_nodata;
+    }
+
+    /* Check the URG flag. If this is set, the segment carries urgent
+       data that we must pass to the application. */
+    if(BUF->flags & TCP_URG) {
+#if UIP_URGDATA > 0
+      uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];
+      if(uip_urglen > uip_len) {
+	/* There is more urgent data in the next segment to come. */
+	uip_urglen = uip_len;
+      }
+      uip_add_rcv_nxt(uip_urglen);
+      uip_len -= uip_urglen;
+      uip_urgdata = uip_appdata;
+      uip_appdata += uip_urglen;
+    } else {
+      uip_urglen = 0;
+#endif /* UIP_URGDATA > 0 */
+      uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1];
+      uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];
+    }
+
+
+    /* If uip_len > 0 we have TCP data in the packet, and we flag this
+       by setting the UIP_NEWDATA flag and update the sequence number
+       we acknowledge. If the application has stopped the dataflow
+       using uip_stop(), we must not accept any data packets from the
+       remote host. */
+    if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
+      uip_flags |= UIP_NEWDATA;
+      uip_add_rcv_nxt(uip_len);
+    }
+
+    /* Check if the available buffer space advertised by the other end
+       is smaller than the initial MSS for this connection. If so, we
+       set the current MSS to the window size to ensure that the
+       application does not send more data than the other end can
+       handle.
+
+       If the remote host advertises a zero window, we set the MSS to
+       the initial MSS so that the application will send an entire MSS
+       of data. This data will not be acknowledged by the receiver,
+       and the application will retransmit it. This is called the
+       "persistent timer" and uses the retransmission mechanim.
+    */
+    tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1];
+    if(tmp16 > uip_connr->initialmss ||
+       tmp16 == 0) {
+      tmp16 = uip_connr->initialmss;
+    }
+    uip_connr->mss = tmp16;
+
+    /* If this packet constitutes an ACK for outstanding data (flagged
+       by the UIP_ACKDATA flag, we should call the application since it
+       might want to send more data. If the incoming packet had data
+       from the peer (as flagged by the UIP_NEWDATA flag), the
+       application must also be notified.
+
+       When the application is called, the global variable uip_len
+       contains the length of the incoming data. The application can
+       access the incoming data through the global pointer
+       uip_appdata, which usually points 40 bytes into the uip_buf
+       array.
+
+       If the application wishes to send any data, this data should be
+       put into the uip_appdata and the length of the data should be
+       put into uip_len. If the application don't have any data to
+       send, uip_len must be set to 0. */
+    if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {
+      uip_slen = 0;
+      UIP_APPCALL();
+
+    appsend:
+
+      if(uip_flags & UIP_ABORT) {
+	uip_slen = 0;
+	uip_connr->tcpstateflags = CLOSED;
+	BUF->flags = TCP_RST | TCP_ACK;
+	goto tcp_send_nodata;
+      }
+
+      if(uip_flags & UIP_CLOSE) {
+	uip_slen = 0;
+	uip_connr->len = 1;
+	uip_connr->tcpstateflags = FIN_WAIT_1;
+	uip_connr->nrtx = 0;
+	BUF->flags = TCP_FIN | TCP_ACK;
+	goto tcp_send_nodata;	
+      }
+
+      /* If uip_slen > 0, the application has data to be sent. */
+      if(uip_slen > 0) {
+
+	/* If the connection has acknowledged data, the contents of
+	   the ->len variable should be discarded. */
+	if((uip_flags & UIP_ACKDATA) != 0) {
+	  uip_connr->len = 0;
+	}
+
+	/* If the ->len variable is non-zero the connection has
+	   already data in transit and cannot send anymore right
+	   now. */
+	if(uip_connr->len == 0) {
+
+	  /* The application cannot send more than what is allowed by
+	     the mss (the minumum of the MSS and the available
+	     window). */
+	  if(uip_slen > uip_connr->mss) {
+	    uip_slen = uip_connr->mss;
+	  }
+
+	  /* Remember how much data we send out now so that we know
+	     when everything has been acknowledged. */
+	  uip_connr->len = uip_slen;
+	} else {
+
+	  /* If the application already had unacknowledged data, we
+	     make sure that the application does not send (i.e.,
+	     retransmit) out more than it previously sent out. */
+	  uip_slen = uip_connr->len;
+	}
+      } else {
+	uip_connr->len = 0;
+      }
+      uip_connr->nrtx = 0;
+    apprexmit:
+      uip_appdata = uip_sappdata;
+
+      /* If the application has data to be sent, or if the incoming
+         packet had new data in it, we must send out a packet. */
+      if(uip_slen > 0 && uip_connr->len > 0) {
+	/* Add the length of the IP and TCP headers. */
+	uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+	/* We always set the ACK flag in response packets. */
+	BUF->flags = TCP_ACK | TCP_PSH;
+	/* Send the packet. */
+	goto tcp_send_noopts;
+      }
+      /* If there is no data to send, just send out a pure ACK if
+	 there is newdata. */
+      if(uip_flags & UIP_NEWDATA) {
+	uip_len = UIP_TCPIP_HLEN;
+	BUF->flags = TCP_ACK;
+	goto tcp_send_noopts;
+      }
+    }
+    goto drop;
+  case LAST_ACK:
+    /* We can close this connection if the peer has acknowledged our
+       FIN. This is indicated by the UIP_ACKDATA flag. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = CLOSED;
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+    }
+    break;
+
+  case FIN_WAIT_1:
+    /* The application has closed the connection, but the remote host
+       hasn't closed its end yet. Thus we do nothing but wait for a
+       FIN from the other side. */
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      if(uip_flags & UIP_ACKDATA) {
+	uip_connr->tcpstateflags = TIME_WAIT;
+	uip_connr->timer = 0;
+	uip_connr->len = 0;
+      } else {
+	uip_connr->tcpstateflags = CLOSING;
+      }
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    } else if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = FIN_WAIT_2;
+      uip_connr->len = 0;
+      goto drop;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case FIN_WAIT_2:
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case TIME_WAIT:
+    goto tcp_send_ack;
+
+  case CLOSING:
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+    }
+  }
+  goto drop;
+
+
+  /* We jump here when we are ready to send the packet, and just want
+     to set the appropriate TCP sequence numbers in the TCP header. */
+ tcp_send_ack:
+  BUF->flags = TCP_ACK;
+ tcp_send_nodata:
+  uip_len = 40;
+ tcp_send_noopts:
+  BUF->tcpoffset = 5 << 4;
+ tcp_send:
+  /* We're done with the input processing. We are now ready to send a
+     reply. Our job is to fill in all the fields of the TCP and IP
+     headers before calculating the checksum and finally send the
+     packet. */
+  BUF->ackno[0] = uip_connr->rcv_nxt[0];
+  BUF->ackno[1] = uip_connr->rcv_nxt[1];
+  BUF->ackno[2] = uip_connr->rcv_nxt[2];
+  BUF->ackno[3] = uip_connr->rcv_nxt[3];
+
+  BUF->seqno[0] = uip_connr->snd_nxt[0];
+  BUF->seqno[1] = uip_connr->snd_nxt[1];
+  BUF->seqno[2] = uip_connr->snd_nxt[2];
+  BUF->seqno[3] = uip_connr->snd_nxt[3];
+
+  BUF->proto = UIP_PROTO_TCP;
+
+  BUF->srcport  = uip_connr->lport;
+  BUF->destport = uip_connr->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_connr->ripaddr[0];
+  BUF->destipaddr[1] = uip_connr->ripaddr[1];
+
+
+  if(uip_connr->tcpstateflags & UIP_STOPPED) {
+    /* If the connection has issued uip_stop(), we advertise a zero
+       window so that the remote host will stop sending data. */
+    BUF->wnd[0] = BUF->wnd[1] = 0;
+  } else {
+    BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);
+    BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff);
+  }
+
+ tcp_send_noconn:
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+
+  /* Calculate TCP checksum. */
+  BUF->tcpchksum = 0;
+  BUF->tcpchksum = ~(uip_tcpchksum());
+
+
+#if UIP_UDP
+ ip_send_nolen:
+#endif
+
+  BUF->vhl = 0x45;
+  BUF->tos = 0;
+  BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+  BUF->ttl  = UIP_TTL;
+  ++ipid;
+  BUF->ipid[0] = ipid >> 8;
+  BUF->ipid[1] = ipid & 0xff;
+
+  /* Calculate IP checksum. */
+  BUF->ipchksum = 0;
+  BUF->ipchksum = ~(uip_ipchksum());
+
+  UIP_STAT(++uip_stat.tcp.sent);
+ send:
+  UIP_STAT(++uip_stat.ip.sent);
+  /* Return and let the caller do the actual transmission. */
+  return;
+ drop:
+  uip_len = 0;
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+htons(u16_t val)
+{
+  return HTONS(val);
+}
+/*-----------------------------------------------------------------------------------*/
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip.h
new file mode 100644
index 000000000..0ff1b2a79
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip.h
@@ -0,0 +1,1060 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author Adam Dunkels 
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $
+ *
+ */
+
+#ifndef __UIP_H__
+#define __UIP_H__
+
+#include "uipopt.h"
+
+/*-----------------------------------------------------------------------------------*/
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses.
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte representation of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \
+                              uip_hostaddr[1] = addr[1]; } while(0)
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \
+                              addr[1] = uip_hostaddr[1]; } while(0)
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void uip_init(void);
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+  uip_len = devicedriver_poll();
+  if(uip_len > 0) {
+    uip_input();
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+  #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+  uip_len = ethernet_devicedrver_poll();
+  if(uip_len > 0) {
+    if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+      uip_arp_ipin();
+      uip_input();
+      if(uip_len > 0) {
+        uip_arp_out();
+	ethernet_devicedriver_send();
+      }
+    } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+      uip_arp_arpin();
+      if(uip_len > 0) {
+	ethernet_devicedriver_send();
+      }
+    }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input()        uip_process(UIP_DATA)
+
+/**
+ * Periodic processing for a connection identified by its number.
+ *
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The ususal way of calling the function is through a for() loop like
+ * this:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \
+                                uip_process(UIP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a connection identified by a pointer to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn(conn) do { uip_conn = conn; \
+                                     uip_process(UIP_TIMER); } while (0)
+
+#if UIP_UDP
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_prerioic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \
+                                uip_process(UIP_UDP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \
+                                         uip_process(UIP_UDP_TIMER); } while (0)
+
+
+#endif /* UIP_UDP */
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+    hwsend(&uip_buf[0], UIP_LLH_LEN);
+    hwsend(&uip_buf[UIP_LLH_LEN], 40);
+    hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN);
+ }
+ \endcode
+ */
+extern u8_t uip_buf[UIP_BUFSIZE+2]; /*_RB_ __attribute__ ((aligned (4)));*/
+
+/** @} */
+
+/*-----------------------------------------------------------------------------------*/
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+*/
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_listen(u16_t port);
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_unlisten(u16_t port);
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specied host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is avaliable only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a convertion using HTONS() or htons() is necessary.
+ *
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(ipaddr, 192,168,1,2);
+ uip_connect(ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param ripaddr A pointer to a 4-byte array representing the IP
+ * address of the remote hot.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.
+ *
+ */
+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port);
+
+
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding(conn) ((conn)->len)
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data.
+ *
+ * The amount of data that actually is sent out after a call to this
+ * funcion is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ *
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ *
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0)
+
+/**
+ * The length of any incoming data that is currently avaliable (if avaliable)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+#define uip_datalen()       uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()    uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close()         (uip_flags = UIP_CLOSE)
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occured that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort()         (uip_flags = UIP_ABORT)
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()          (uip_conn->tcpstateflags |= UIP_STOPPED)
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped(conn)   ((conn)->tcpstateflags & UIP_STOPPED)
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()         do { uip_flags |= UIP_NEWDATA; \
+                                   uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+                              } while(0)
+
+
+/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * avaliable through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()   (uip_flags & UIP_NEWDATA)
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data.
+ *
+ * \hideinitializer
+ */
+#define uip_acked()   (uip_flags & UIP_ACKDATA)
+
+/**
+ * Has the connection just been connected?
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() (uip_flags & UIP_CONNECTED)
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()    (uip_flags & UIP_CLOSE)
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()    (uip_flags & UIP_ABORT)
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()    (uip_flags & UIP_TIMEDOUT)
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()     (uip_flags & UIP_REXMIT)
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */
+#define uip_poll()       (uip_flags & UIP_POLL)
+
+/**
+ * Get the initial maxium segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()             (uip_conn->initialmss)
+
+/**
+ * Get the current maxium segment size that can be sent on the current
+ * connection.
+ *
+ * The current maxiumum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()             (uip_conn->mss)
+
+/**
+ * Set up a new UDP connection.
+ *
+ * \param ripaddr A pointer to a 4-byte structure representing the IP
+ * address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport);
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove(conn) (conn)->lport = 0
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send(len) uip_slen = (len)
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+
+/**
+ * Pack an IP address into a 4-byte array which is used by uIP to
+ * represent IP addresses.
+ *
+ * Example:
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ \endcode
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP addres.
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \
+                     (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \
+                     (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \
+                  } while(0)
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#   if BYTE_ORDER == BIG_ENDIAN
+#      define HTONS(n) (n)
+#   else /* BYTE_ORDER == BIG_ENDIAN */
+#      define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))
+#   endif /* BYTE_ORDER == BIG_ENDIAN */
+#endif /* HTONS */
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+u16_t htons(u16_t val);
+#endif /* htons */
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+extern volatile u8_t *uip_appdata;
+extern volatile u8_t *uip_sappdata;
+
+#if UIP_URGDATA > 0
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern volatile u8_t *uip_urgdata;
+#endif /* UIP_URGDATA > 0 */
+
+
+/* u[8|16]_t uip_len:
+ *
+ * When the application is called, uip_len contains the length of any
+ * new data that has been received from the remote host. The
+ * application should set this variable to the size of any data that
+ * the application wishes to send. When the network device driver
+ * output function is called, uip_len should contain the length of the
+ * outgoing packet.
+ */
+extern volatile u16_t uip_len, uip_slen;
+
+#if UIP_URGDATA > 0
+extern volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whos purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The size of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote host. */
+
+  u16_t lport;        /**< The local TCP port, in network byte order. */
+  u16_t rport;        /**< The local remote TCP port, in network byte
+			 order. */
+
+  u8_t rcv_nxt[4];    /**< The sequence number that we expect to
+			 receive next. */
+  u8_t snd_nxt[4];    /**< The sequence number that was last sent by
+                         us. */
+  u16_t len;          /**< Length of the data that was previously sent. */
+  u16_t mss;          /**< Current maximum segment size for the
+			 connection. */
+  u16_t initialmss;   /**< Initial maximum segment size for the
+			 connection. */
+  u8_t sa;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t sv;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t rto;           /**< Retransmission time-out. */
+  u8_t tcpstateflags; /**< TCP state and flags. */
+  u8_t timer;         /**< The retransmission timer. */
+  u8_t nrtx;          /**< The number of retransmissions for the last
+			 segment sent. */
+
+  /** The application state. */
+  u8_t appstate[UIP_APPSTATE_SIZE];
+};
+
+
+/* Pointer to the current connection. */
+extern struct uip_conn *uip_conn;
+/* The array containing all uIP connections. */
+extern struct uip_conn uip_conns[UIP_CONNS];
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern volatile u8_t uip_acc32[4];
+
+/** @} */
+
+
+#if UIP_UDP
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote peer. */
+  u16_t lport;        /**< The local port number in network byte order. */
+  u16_t rport;        /**< The remote port number in network byte order. */
+};
+
+extern struct uip_udp_conn *uip_udp_conn;
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats {
+  struct {
+    uip_stats_t drop;     /**< Number of dropped packets at the IP
+			     layer. */
+    uip_stats_t recv;     /**< Number of received packets at the IP
+			     layer. */
+    uip_stats_t sent;     /**< Number of sent packets at the IP
+			     layer. */
+    uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
+			     IP version or header length. */
+    uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+    uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+    uip_stats_t fragerr;  /**< Number of packets dropped since they
+			     were IP fragments. */
+    uip_stats_t chkerr;   /**< Number of packets dropped due to IP
+			     checksum errors. */
+    uip_stats_t protoerr; /**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+  } ip;                   /**< IP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped ICMP packets. */
+    uip_stats_t recv;     /**< Number of received ICMP packets. */
+    uip_stats_t sent;     /**< Number of sent ICMP packets. */
+    uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
+			     type. */
+  } icmp;                 /**< ICMP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped TCP segments. */
+    uip_stats_t recv;     /**< Number of recived TCP segments. */
+    uip_stats_t sent;     /**< Number of sent TCP segments. */
+    uip_stats_t chkerr;   /**< Number of TCP segments with a bad
+			     checksum. */
+    uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
+			     number. */
+    uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
+    uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
+    uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+    uip_stats_t synrst;   /**< Number of SYNs for closed ports,
+			     triggering a RST. */
+  } tcp;                  /**< TCP statistics. */
+};
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+extern struct uip_stats uip_stat;
+
+
+/*-----------------------------------------------------------------------------------*/
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+/*-----------------------------------------------------------------------------------*/
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * infomation.
+ */
+extern volatile u8_t uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA and
+   UIP_NEWDATA flags may both be set at the same time, whereas the
+   others are mutualy exclusive. Note that these flags should *NOT* be
+   accessed directly, but through the uIP functions/macros. */
+
+#define UIP_ACKDATA   1     /* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT    4     /* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL      8     /* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE     16    /* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT     32    /* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED 64    /* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT  128   /* The connection has been aborted due to
+			       too many retransmissions. */
+
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void uip_process(u8_t flag);
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. */
+
+#define UIP_DATA    1     /* Tells uIP that there is incoming data in
+                             the uip_buf buffer. The length of the
+                             data is stored in the global variable
+                             uip_len. */
+#define UIP_TIMER   2     /* Tells uIP that the periodic timer has
+                             fired. */
+#if UIP_UDP
+#define UIP_UDP_TIMER 3
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define CLOSED      0
+#define SYN_RCVD    1
+#define SYN_SENT    2
+#define ESTABLISHED 3
+#define FIN_WAIT_1  4
+#define FIN_WAIT_2  5
+#define CLOSING     6
+#define TIME_WAIT   7
+#define LAST_ACK    8
+#define TS_MASK     15
+
+#define UIP_STOPPED      16
+
+#define UIP_TCPIP_HLEN 40
+
+/* The TCP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} uip_tcpip_hdr;
+
+/* The ICMP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+  u16_t id, seqno;
+} uip_icmpip_hdr;
+
+
+/* The UDP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+
+  /* UDP header. */
+  u16_t srcport,
+    destport;
+  u16_t udplen;
+  u16_t udpchksum;
+} uip_udpip_hdr;
+
+#define UIP_PROTO_ICMP  1
+#define UIP_PROTO_TCP   6
+#define UIP_PROTO_UDP   17
+
+#if UIP_FIXEDADDR
+extern const u16_t uip_hostaddr[2];
+#else /* UIP_FIXEDADDR */
+extern u16_t uip_hostaddr[2];
+#endif /* UIP_FIXEDADDR */
+
+#endif /* __UIP_H__ */
+
+
+/** @} */
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c
new file mode 100644
index 000000000..9dad18cc5
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "uip_arch.h"
+
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define IP_PROTO_TCP    6
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_add32(u8_t *op32, u16_t op16)
+{
+
+  uip_acc32[3] = op32[3] + (op16 & 0xff);
+  uip_acc32[2] = op32[2] + (op16 >> 8);
+  uip_acc32[1] = op32[1];
+  uip_acc32[0] = op32[0];
+
+  if(uip_acc32[2] < (op16 >> 8)) {
+    ++uip_acc32[1];
+    if(uip_acc32[1] == 0) {
+      ++uip_acc32[0];
+    }
+  }
+
+
+  if(uip_acc32[3] < (op16 & 0xff)) {
+    ++uip_acc32[2];
+    if(uip_acc32[2] == 0) {
+      ++uip_acc32[1];
+      if(uip_acc32[1] == 0) {
+	++uip_acc32[0];
+      }
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_chksum(u16_t *sdata, u16_t len)
+{
+  u16_t acc;
+
+  for (acc = 0; len > 1; len -= 2) {
+    u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8);
+    if ((acc += u) < u) {
+      /* Overflow, so we add the carry to acc (i.e., increase by
+         one). */
+      ++acc;
+    }
+    ++sdata;
+  }
+
+  /* add up any odd byte */
+  if(len == 1) {
+    acc += htons(((u16_t)(*(u8_t *)sdata)) << 8);
+    if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) {
+      ++acc;
+    }
+  }
+
+  return acc;
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_ipchksum(void)
+{
+  return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20);
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_tcpchksum(void)
+{
+  u16_t hsum, sum;
+
+
+  /* Compute the checksum of the TCP header. */
+  hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20);
+
+  /* Compute the checksum of the data in the TCP packet and add it to
+     the TCP header checksum. */
+  sum = uip_chksum((u16_t *)uip_appdata,
+		   (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40)));
+
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+
+  if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) {
+    ++sum;
+  }
+  if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) {
+    ++sum;
+  }
+
+  hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20);
+
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+
+  return sum;
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h
new file mode 100644
index 000000000..b2d133f2e
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h
@@ -0,0 +1,130 @@
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c
new file mode 100644
index 000000000..db8d72d8c
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c
@@ -0,0 +1,429 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ *
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $
+ *
+ */
+
+
+#include "uip_arp.h"
+
+#include 
+
+struct arp_hdr {
+  struct uip_eth_hdr ethhdr;
+  u16_t hwtype;
+  u16_t protocol;
+  u8_t hwlen;
+  u8_t protolen;
+  u16_t opcode;
+  struct uip_eth_addr shwaddr;
+  u16_t sipaddr[2];
+  struct uip_eth_addr dhwaddr;
+  u16_t dipaddr[2];
+};
+
+struct ethip_hdr {
+  struct uip_eth_hdr ethhdr;
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+};
+
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#define ARP_HWTYPE_ETH 1
+
+struct arp_entry {
+  u16_t ipaddr[2];
+  struct uip_eth_addr ethaddr;
+  u8_t time;
+};
+
+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,
+				    UIP_ETHADDR1,
+				    UIP_ETHADDR2,
+				    UIP_ETHADDR3,
+				    UIP_ETHADDR4,
+				    UIP_ETHADDR5}};
+
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];
+static u16_t ipaddr[2];
+static u8_t i, c;
+
+static u8_t arptime;
+static u8_t tmpage;
+
+#define BUF   ((struct arp_hdr *)&uip_buf[0])
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the ARP module.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_init(void)
+{
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    memset(arp_table[i].ipaddr, 0, 4);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_timer(void)
+{
+  struct arp_entry *tabptr;
+
+  ++arptime;
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&
+       arptime - tabptr->time >= UIP_ARP_MAXAGE) {
+      memset(tabptr->ipaddr, 0, 4);
+    }
+  }
+
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
+  register struct arp_entry *tabptr;
+  /* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+
+    tabptr = &arp_table[i];
+    /* Only check those entries that are actually in use. */
+    if(tabptr->ipaddr[0] != 0 &&
+       tabptr->ipaddr[1] != 0) {
+
+      /* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+      if(ipaddr[0] == tabptr->ipaddr[0] &&
+	 ipaddr[1] == tabptr->ipaddr[1]) {
+	
+	/* An old entry found, update this and return. */
+	memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+	tabptr->time = arptime;
+
+	return;
+      }
+    }
+  }
+
+  /* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+  /* First, we try to find an unused entry in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(tabptr->ipaddr[0] == 0 &&
+       tabptr->ipaddr[1] == 0) {
+      break;
+    }
+  }
+
+  /* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+  if(i == UIP_ARPTAB_SIZE) {
+    tmpage = 0;
+    c = 0;
+    for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+      tabptr = &arp_table[i];
+      if(arptime - tabptr->time > tmpage) {
+	tmpage = arptime - tabptr->time;
+	c = i;
+      }
+    }
+    i = c;
+  }
+
+  /* Now, i is the ARP table entry which we will fill with the new
+     information. */
+  memcpy(tabptr->ipaddr, ipaddr, 4);
+  memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+  tabptr->time = arptime;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_ipin(void)
+{
+  uip_len -= sizeof(struct uip_eth_hdr);
+	
+  /* Only insert/update an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) !=
+     (uip_hostaddr[0] & uip_arp_netmask[0])) {
+    return;
+  }
+  if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) !=
+     (uip_hostaddr[1] & uip_arp_netmask[1])) {
+    return;
+  }
+  uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));
+
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+typedef struct arp_hdr aht;
+
+void
+uip_arp_arpin(void)
+{
+  int ul;
+
+  if(uip_len < sizeof(struct arp_hdr)) {
+    uip_len = 0;
+    return;
+  }
+
+  uip_len = 0;
+
+  switch(BUF->opcode) {
+  case HTONS(ARP_REQUEST):
+    /* ARP request. If it asked for our address, we send out a
+       reply. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+      /* The reply opcode is 2. */
+      BUF->opcode = HTONS(2);
+
+      memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);
+      memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);
+
+      BUF->dipaddr[0] = BUF->sipaddr[0];
+      BUF->dipaddr[1] = BUF->sipaddr[1];
+      BUF->sipaddr[0] = uip_hostaddr[0];
+      BUF->sipaddr[1] = uip_hostaddr[1];
+
+      ul = BUF->hwlen;
+      BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+      uip_len = sizeof(struct arp_hdr);
+    }
+    break;
+  case HTONS(ARP_REPLY):
+    /* ARP reply. We insert or update the ARP table if it was meant
+       for us. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+
+      uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
+    }
+    break;
+  }
+
+  ( void ) ul;
+
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_out(void)
+{
+  struct arp_entry *tabptr;
+  /* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP addres isn't on the
+     local network, we use the default router's IP address instead.
+
+     If not ARP table entry is found, we overwrite the original IP
+     packet with an ARP request for the IP address. */
+
+  /* Check if the destination address is on the local network. */
+  if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) !=
+     (uip_hostaddr[0] & uip_arp_netmask[0]) ||
+     (IPBUF->destipaddr[1] & uip_arp_netmask[1]) !=
+     (uip_hostaddr[1] & uip_arp_netmask[1])) {
+    /* Destination address was not on the local network, so we need to
+       use the default router's IP address instead of the destination
+       address when determining the MAC address. */
+    ipaddr[0] = uip_arp_draddr[0];
+    ipaddr[1] = uip_arp_draddr[1];
+  } else {
+    /* Else, we use the destination IP address. */
+    ipaddr[0] = IPBUF->destipaddr[0];
+    ipaddr[1] = IPBUF->destipaddr[1];
+  }
+
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(ipaddr[0] == tabptr->ipaddr[0] &&
+       ipaddr[1] == tabptr->ipaddr[1])
+      break;
+  }
+
+  if(i == UIP_ARPTAB_SIZE) {
+    /* The destination address was not in our ARP table, so we
+       overwrite the IP packet with an ARP request. */
+
+    memset(BUF->ethhdr.dest.addr, 0xff, 6);
+    memset(BUF->dhwaddr.addr, 0x00, 6);
+    memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+    memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+
+    BUF->dipaddr[0] = ipaddr[0];
+    BUF->dipaddr[1] = ipaddr[1];
+    BUF->sipaddr[0] = uip_hostaddr[0];
+    BUF->sipaddr[1] = uip_hostaddr[1];
+    BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */
+    BUF->hwtype = HTONS(ARP_HWTYPE_ETH);
+    BUF->protocol = HTONS(UIP_ETHTYPE_IP);
+    BUF->hwlen = 6;
+    BUF->protolen = 4;
+    BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+
+    uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+
+    uip_len = sizeof(struct arp_hdr);
+    return;
+  }
+
+  /* Build an ethernet header. */
+  memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);
+  memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+
+  IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);
+
+  uip_len += sizeof(struct uip_eth_hdr);
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h
new file mode 100644
index 000000000..fadad57bb
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h
@@ -0,0 +1,201 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp
+ * @{
+ */
+
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels 
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "uip.h"
+
+
+/**
+ * Representation of a 48-bit Ethernet address.
+ */
+struct uip_eth_addr {
+  u8_t addr[6];
+} /*_RB_ __attribute__ ((packed, aligned (1))) */;
+
+extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header.
+ */
+struct uip_eth_hdr {
+  struct uip_eth_addr dest;
+  struct uip_eth_addr src;
+  u16_t type;
+} /*_RB_ __attribute__ ((packed)) */;
+
+#define UIP_ETHTYPE_ARP 0x0806
+#define UIP_ETHTYPE_IP  0x0800
+#define UIP_ETHTYPE_IP6 0x86dd
+
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void uip_arp_init(void);
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+void uip_arp_ipin(void);
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void uip_arp_arpin(void);
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void uip_arp_out(void);
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void uip_arp_timer(void);
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \
+                                 uip_arp_draddr[1] = addr[1]; } while(0)
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \
+                                  uip_arp_netmask[1] = addr[1]; } while(0)
+
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \
+                                 addr[1] = uip_arp_draddr[1]; } while(0)
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \
+                                  addr[1] = uip_arp_netmask[1]; } while(0)
+
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \
+                              uip_ethaddr.addr[1] = eaddr.addr[1];\
+                              uip_ethaddr.addr[2] = eaddr.addr[2];\
+                              uip_ethaddr.addr[3] = eaddr.addr[3];\
+                              uip_ethaddr.addr[4] = eaddr.addr[4];\
+                              uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)
+
+/** @} */
+
+/**
+ * \internal Internal variables that are set using the macros
+ * uip_setdraddr and uip_setnetmask.
+ */
+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* __UIP_ARP_H__ */
+
+
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h b/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h
new file mode 100644
index 000000000..3701f6294
--- /dev/null
+++ b/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h
@@ -0,0 +1,560 @@
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * "uipopt.h". This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels 
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $
+ *
+ */
+
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttypedef uIP type definitions
+ * @{
+ */
+
+/**
+ * The 8-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * char" works for most compilers.
+ */
+typedef unsigned char u8_t;
+
+/**
+ * The 16-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * short" works for most compilers.
+ */
+typedef unsigned short u16_t;
+
+/**
+ * The statistics data type.
+ *
+ * This datatype determines how high the statistics counters are able
+ * to count.
+ */
+typedef unsigned short uip_stats_t;
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptstaticconf Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are appliciable only
+ * if uIP should be run over Ethernet.
+ *
+ * All of these should be changed to suit your project.
+*/
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDADDR    1
+
+/**
+ * Ping IP address asignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_PINGADDRCONF 0
+
+
+#define UIP_IPADDR0     172U  /**< The first octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR1     25U /**< The second octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR2     218U   /**< The third octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR3     204U  /**< The fourth octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_NETMASK0    255 /**< The first octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK1    255 /**< The second octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK2    0 /**< The third octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK3    0   /**< The fourth octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_DRIPADDR0   172 /**< The first octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR1   25 /**< The second octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR2   218   /**< The third octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR3   3   /**< The fourth octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR 0
+
+#define UIP_ETHADDR0    0x00  /**< The first octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR1    0xbd  /**< The second octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR2    0x3b  /**< The third octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR3    0x33  /**< The fourth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR4    0x06  /**< The fifth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR5    0x65  /**< The sixth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptip IP configuration options
+ * @{
+ *
+ */
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL         255
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additonal amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#define UIP_REASSEMBLY 0
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE 40
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptudp UDP configuration options
+ * @{
+ *
+ * \note The UDP support in uIP is still not entirely complete; there
+ * is no support for sending or receiving broadcast or multicast
+ * packets, but it works well enough to support a number of vital
+ * applications such as DNS queries, though
+ */
+
+/**
+ * Toggles wether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP           0
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CHECKSUMS 0
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CONNS    2
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_APPCALL  udp_appcall
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttcp TCP configuration options
+ * @{
+ */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#define UIP_ACTIVE_OPEN 0
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximatly 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_CONNS       25
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_LISTENPORTS 10
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+#define UIP_RECEIVE_WINDOW   32768
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+#define UIP_URGDATA      1
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO         3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX      8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX      3
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40.
+ */
+#define UIP_TCP_MSS     (UIP_BUFSIZE - UIP_LLH_LEN - 40)
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configiration option has no real implication, and it should be
+ * left untouched.
+ */
+#define UIP_TIME_WAIT_TIMEOUT 120
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptarp ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#define UIP_ARPTAB_SIZE 8
+
+/**
+ * The maxium age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE 120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptgeneral General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1500 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#define UIP_BUFSIZE     2048
+
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#define UIP_STATISTICS  1
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#define UIP_LOGGING 0
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void uip_log(char *msg);
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_LLH_LEN     14
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptcpu CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN  3412
+#endif /* LITTLE_ENDIAN */
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN     1234
+#endif /* BIGE_ENDIAN */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either BIG_ENDIAN (Motorola byte order) or
+ * LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+#ifndef BYTE_ORDER
+#define BYTE_ORDER     LITTLE_ENDIAN
+#endif /* BYTE_ORDER */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptapp Appication specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the size of the application
+ * structure with the UIP_APPSTATE_SIZE macro.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+void httpd_appcall(void);
+#define UIP_APPCALL     httpd_appcall
+
+struct httpd_state {
+  u8_t state;
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+ \endcode
+ */
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var #define UIP_APPSTATE_SIZE
+ *
+ * The size of the application state that is to be stored in the
+ * uip_conn structure.
+ */
+/** @} */
+
+/* Include the header file for the application program that should be
+   used. If you don't use the example web server, you should change
+   this. */
+#include "httpd.h"
+
+
+#endif /* __UIPOPT_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
new file mode 100644
index 000000000..41904f0be
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
@@ -0,0 +1,79 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+#define vPortYieldProcessor swi_handler
+
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 58982400 )	/* =14.7456MHz xtal multiplied by 4 using the PLL. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 128 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 10 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml b/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml
new file mode 100644
index 000000000..449adf2e4
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml
@@ -0,0 +1,29 @@
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h b/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h
new file mode 100644
index 000000000..3f1e3042d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h
@@ -0,0 +1,321 @@
+#ifndef lpc210x_h
+#define lpc210x_h
+/*******************************************************************************
+lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106
+
+           
+THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, 
+EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY 
+WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY 
+PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS 
+OF OTHERS.
+           
+This file may be freely used for commercial and non-commercial applications, 
+including being redistributed with any tools.
+
+If you find a problem with the file, please report it so that it can be fixed.
+
+Created by Sten Larsson (sten_larsson at yahoo com)
+
+Edited by Richard Barry.
+*******************************************************************************/
+
+#define REG8  (volatile unsigned char*)
+#define REG16 (volatile unsigned short*)
+#define REG32 (volatile unsigned int*)
+
+
+/*##############################################################################
+## MISC
+##############################################################################*/
+
+        /* Constants for data to put in IRQ/FIQ Exception Vectors */
+#define VECTDATA_IRQ  0xE51FFFF0  /* LDR PC,[PC,#-0xFF0] */
+#define VECTDATA_FIQ  /* __TODO */
+
+
+/*##############################################################################
+## VECTORED INTERRUPT CONTROLLER
+##############################################################################*/
+
+#define VICIRQStatus    (*(REG32 (0xFFFFF000)))
+#define VICFIQStatus    (*(REG32 (0xFFFFF004)))
+#define VICRawIntr      (*(REG32 (0xFFFFF008)))
+#define VICIntSelect    (*(REG32 (0xFFFFF00C)))
+#define VICIntEnable    (*(REG32 (0xFFFFF010)))
+#define VICIntEnClear   (*(REG32 (0xFFFFF014)))
+#define VICSoftInt      (*(REG32 (0xFFFFF018)))
+#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
+#define VICProtection   (*(REG32 (0xFFFFF020)))
+#define VICVectAddr     (*(REG32 (0xFFFFF030)))
+#define VICDefVectAddr  (*(REG32 (0xFFFFF034)))
+
+#define VICVectAddr0    (*(REG32 (0xFFFFF100)))
+#define VICVectAddr1    (*(REG32 (0xFFFFF104)))
+#define VICVectAddr2    (*(REG32 (0xFFFFF108)))
+#define VICVectAddr3    (*(REG32 (0xFFFFF10C)))
+#define VICVectAddr4    (*(REG32 (0xFFFFF110)))
+#define VICVectAddr5    (*(REG32 (0xFFFFF114)))
+#define VICVectAddr6    (*(REG32 (0xFFFFF118)))
+#define VICVectAddr7    (*(REG32 (0xFFFFF11C)))
+#define VICVectAddr8    (*(REG32 (0xFFFFF120)))
+#define VICVectAddr9    (*(REG32 (0xFFFFF124)))
+#define VICVectAddr10   (*(REG32 (0xFFFFF128)))
+#define VICVectAddr11   (*(REG32 (0xFFFFF12C)))
+#define VICVectAddr12   (*(REG32 (0xFFFFF130)))
+#define VICVectAddr13   (*(REG32 (0xFFFFF134)))
+#define VICVectAddr14   (*(REG32 (0xFFFFF138)))
+#define VICVectAddr15   (*(REG32 (0xFFFFF13C)))
+
+#define VICVectCntl0    (*(REG32 (0xFFFFF200)))
+#define VICVectCntl1    (*(REG32 (0xFFFFF204)))
+#define VICVectCntl2    (*(REG32 (0xFFFFF208)))
+#define VICVectCntl3    (*(REG32 (0xFFFFF20C)))
+#define VICVectCntl4    (*(REG32 (0xFFFFF210)))
+#define VICVectCntl5    (*(REG32 (0xFFFFF214)))
+#define VICVectCntl6    (*(REG32 (0xFFFFF218)))
+#define VICVectCntl7    (*(REG32 (0xFFFFF21C)))
+#define VICVectCntl8    (*(REG32 (0xFFFFF220)))
+#define VICVectCntl9    (*(REG32 (0xFFFFF224)))
+#define VICVectCntl10   (*(REG32 (0xFFFFF228)))
+#define VICVectCntl11   (*(REG32 (0xFFFFF22C)))
+#define VICVectCntl12   (*(REG32 (0xFFFFF230)))
+#define VICVectCntl13   (*(REG32 (0xFFFFF234)))
+#define VICVectCntl14   (*(REG32 (0xFFFFF238)))
+#define VICVectCntl15   (*(REG32 (0xFFFFF23C)))
+
+#define VICITCR         (*(REG32 (0xFFFFF300)))
+#define VICITIP1        (*(REG32 (0xFFFFF304)))
+#define VICITIP2        (*(REG32 (0xFFFFF308)))
+#define VICITOP1        (*(REG32 (0xFFFFF30C)))
+#define VICITOP2        (*(REG32 (0xFFFFF310)))
+#define VICPeriphID0    (*(REG32 (0xFFFFFFE0)))
+#define VICPeriphID1    (*(REG32 (0xFFFFFFE4)))
+#define VICPeriphID2    (*(REG32 (0xFFFFFFE8)))
+#define VICPeriphID3    (*(REG32 (0xFFFFFFEC)))
+
+#define VICIntEnClr     VICIntEnClear
+#define VICSoftIntClr   VICSoftIntClear
+
+
+/*##############################################################################
+## PCB - Pin Connect Block
+##############################################################################*/
+
+#define PCB_PINSEL0     (*(REG32 (0xE002C000)))
+#define PCB_PINSEL1     (*(REG32 (0xE002C004)))
+
+
+/*##############################################################################
+## GPIO - General Purpose I/O
+##############################################################################*/
+
+#define GPIO_IOPIN      (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
+#define GPIO_IOSET      (*(REG32 (0xE0028004)))
+#define GPIO_IODIR      (*(REG32 (0xE0028008)))
+#define GPIO_IOCLR      (*(REG32 (0xE002800C)))
+
+#define GPIO0_IOPIN     (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
+#define GPIO0_IOSET     (*(REG32 (0xE0028004)))
+#define GPIO0_IODIR     (*(REG32 (0xE0028008)))
+#define GPIO0_IOCLR     (*(REG32 (0xE002800C)))
+
+
+/*##############################################################################
+## UART0 / UART1
+##############################################################################*/
+
+/* ---- UART 0 --------------------------------------------- */
+#define UART0_RBR       (*(REG32 (0xE000C000)))
+#define UART0_THR       (*(REG32 (0xE000C000)))
+#define UART0_IER       (*(REG32 (0xE000C004)))
+#define UART0_IIR       (*(REG32 (0xE000C008)))
+#define UART0_FCR       (*(REG32 (0xE000C008)))
+#define UART0_LCR       (*(REG32 (0xE000C00C)))
+#define UART0_LSR       (*(REG32 (0xE000C014)))
+#define UART0_SCR       (*(REG32 (0xE000C01C)))
+#define UART0_DLL       (*(REG32 (0xE000C000)))
+#define UART0_DLM       (*(REG32 (0xE000C004)))
+
+/* ---- UART 1 --------------------------------------------- */
+#define UART1_RBR       (*(REG32 (0xE0010000)))
+#define UART1_THR       (*(REG32 (0xE0010000)))
+#define UART1_IER       (*(REG32 (0xE0010004)))
+#define UART1_IIR       (*(REG32 (0xE0010008)))
+#define UART1_FCR       (*(REG32 (0xE0010008)))
+#define UART1_LCR       (*(REG32 (0xE001000C)))
+#define UART1_LSR       (*(REG32 (0xE0010014)))
+#define UART1_SCR       (*(REG32 (0xE001001C)))
+#define UART1_DLL       (*(REG32 (0xE0010000)))
+#define UART1_DLM       (*(REG32 (0xE0010004)))
+#define UART1_MCR       (*(REG32 (0xE0010010)))
+#define UART1_MSR       (*(REG32 (0xE0010018)))
+
+
+/*##############################################################################
+## I2C
+##############################################################################*/
+
+#define I2C_I2CONSET    (*(REG32 (0xE001C000)))
+#define I2C_I2STAT      (*(REG32 (0xE001C004)))
+#define I2C_I2DAT       (*(REG32 (0xE001C008)))
+#define I2C_I2ADR       (*(REG32 (0xE001C00C)))
+#define I2C_I2SCLH      (*(REG32 (0xE001C010)))
+#define I2C_I2SCLL      (*(REG32 (0xE001C014)))
+#define I2C_I2CONCLR    (*(REG32 (0xE001C018)))
+
+
+/*##############################################################################
+## SPI - Serial Peripheral Interface
+##############################################################################*/
+
+#define SPI_SPCR        (*(REG32 (0xE0020000)))
+#define SPI_SPSR        (*(REG32 (0xE0020004)))
+#define SPI_SPDR        (*(REG32 (0xE0020008)))
+#define SPI_SPCCR       (*(REG32 (0xE002000C)))
+#define SPI_SPTCR       (*(REG32 (0xE0020010)))
+#define SPI_SPTSR       (*(REG32 (0xE0020014)))
+#define SPI_SPTOR       (*(REG32 (0xE0020018)))
+#define SPI_SPINT       (*(REG32 (0xE002001C)))
+
+
+/*##############################################################################
+## Timer 0 and Timer 1
+##############################################################################*/
+
+/* ---- Timer 0 -------------------------------------------- */
+#define T0_IR           (*(REG32 (0xE0004000)))
+#define T0_TCR          (*(REG32 (0xE0004004)))
+#define T0_TC           (*(REG32 (0xE0004008)))
+#define T0_PR           (*(REG32 (0xE000400C)))
+#define T0_PC           (*(REG32 (0xE0004010)))
+#define T0_MCR          (*(REG32 (0xE0004014)))
+#define T0_MR0          (*(REG32 (0xE0004018)))
+#define T0_MR1          (*(REG32 (0xE000401C)))
+#define T0_MR2          (*(REG32 (0xE0004020)))
+#define T0_MR3          (*(REG32 (0xE0004024)))
+#define T0_CCR          (*(REG32 (0xE0004028)))
+#define T0_CR0          (*(REG32 (0xE000402C)))
+#define T0_CR1          (*(REG32 (0xE0004030)))
+#define T0_CR2          (*(REG32 (0xE0004034)))
+#define T0_CR3          (*(REG32 (0xE0004038)))
+#define T0_EMR          (*(REG32 (0xE000403C)))
+
+/* ---- Timer 1 -------------------------------------------- */
+#define T1_IR           (*(REG32 (0xE0008000)))
+#define T1_TCR          (*(REG32 (0xE0008004)))
+#define T1_TC           (*(REG32 (0xE0008008)))
+#define T1_PR           (*(REG32 (0xE000800C)))
+#define T1_PC           (*(REG32 (0xE0008010)))
+#define T1_MCR          (*(REG32 (0xE0008014)))
+#define T1_MR0          (*(REG32 (0xE0008018)))
+#define T1_MR1          (*(REG32 (0xE000801C)))
+#define T1_MR2          (*(REG32 (0xE0008020)))
+#define T1_MR3          (*(REG32 (0xE0008024)))
+#define T1_CCR          (*(REG32 (0xE0008028)))
+#define T1_CR0          (*(REG32 (0xE000802C)))
+#define T1_CR1          (*(REG32 (0xE0008030)))
+#define T1_CR2          (*(REG32 (0xE0008034)))
+#define T1_CR3          (*(REG32 (0xE0008038)))
+#define T1_EMR          (*(REG32 (0xE000803C)))
+
+
+/*##############################################################################
+## PWM
+##############################################################################*/
+
+#define PWM_IR          (*(REG32 (0xE0014000)))
+#define PWM_TCR         (*(REG32 (0xE0014004)))
+#define PWM_TC          (*(REG32 (0xE0014008)))
+#define PWM_PR          (*(REG32 (0xE001400C)))
+#define PWM_PC          (*(REG32 (0xE0014010)))
+#define PWM_MCR         (*(REG32 (0xE0014014)))
+#define PWM_MR0         (*(REG32 (0xE0014018)))
+#define PWM_MR1         (*(REG32 (0xE001401C)))
+#define PWM_MR2         (*(REG32 (0xE0014020)))
+#define PWM_MR3         (*(REG32 (0xE0014024)))
+#define PWM_MR4         (*(REG32 (0xE0014040)))
+#define PWM_MR5         (*(REG32 (0xE0014044)))
+#define PWM_MR6         (*(REG32 (0xE0014048)))
+#define PWM_EMR         (*(REG32 (0xE001403C)))
+#define PWM_PCR         (*(REG32 (0xE001404C)))
+#define PWM_LER         (*(REG32 (0xE0014050)))
+#define PWM_CCR         (*(REG32 (0xE0014028)))
+#define PWM_CR0         (*(REG32 (0xE001402C)))
+#define PWM_CR1         (*(REG32 (0xE0014030)))
+#define PWM_CR2         (*(REG32 (0xE0014034)))
+#define PWM_CR3         (*(REG32 (0xE0014038)))
+
+/*##############################################################################
+## RTC
+##############################################################################*/
+
+/* ---- RTC: Miscellaneous Register Group ------------------ */
+#define RTC_ILR         (*(REG32 (0xE0024000)))
+#define RTC_CTC         (*(REG32 (0xE0024004)))
+#define RTC_CCR         (*(REG32 (0xE0024008)))  
+#define RTC_CIIR        (*(REG32 (0xE002400C)))
+#define RTC_AMR         (*(REG32 (0xE0024010)))
+#define RTC_CTIME0      (*(REG32 (0xE0024014)))
+#define RTC_CTIME1      (*(REG32 (0xE0024018)))
+#define RTC_CTIME2      (*(REG32 (0xE002401C)))
+
+/* ---- RTC: Timer Control Group --------------------------- */
+#define RTC_SEC         (*(REG32 (0xE0024020)))
+#define RTC_MIN         (*(REG32 (0xE0024024)))
+#define RTC_HOUR        (*(REG32 (0xE0024028)))
+#define RTC_DOM         (*(REG32 (0xE002402C)))
+#define RTC_DOW         (*(REG32 (0xE0024030)))
+#define RTC_DOY         (*(REG32 (0xE0024034)))
+#define RTC_MONTH       (*(REG32 (0xE0024038)))
+#define RTC_YEAR        (*(REG32 (0xE002403C)))
+
+/* ---- RTC: Alarm Control Group --------------------------- */
+#define RTC_ALSEC       (*(REG32 (0xE0024060)))
+#define RTC_ALMIN       (*(REG32 (0xE0024064)))
+#define RTC_ALHOUR      (*(REG32 (0xE0024068)))
+#define RTC_ALDOM       (*(REG32 (0xE002406C)))
+#define RTC_ALDOW       (*(REG32 (0xE0024070)))
+#define RTC_ALDOY       (*(REG32 (0xE0024074)))
+#define RTC_ALMON       (*(REG32 (0xE0024078)))
+#define RTC_ALYEAR      (*(REG32 (0xE002407C)))
+
+/* ---- RTC: Reference Clock Divider Group ----------------- */
+#define RTC_PREINT      (*(REG32 (0xE0024080)))
+#define RTC_PREFRAC     (*(REG32 (0xE0024084)))
+
+
+/*##############################################################################
+## WD - Watchdog
+##############################################################################*/
+
+#define WD_WDMOD        (*(REG32 (0xE0000000)))
+#define WD_WDTC         (*(REG32 (0xE0000004)))
+#define WD_WDFEED       (*(REG32 (0xE0000008)))
+#define WD_WDTV         (*(REG32 (0xE000000C)))
+
+
+/*##############################################################################
+## System Control Block
+##############################################################################*/
+
+#define SCB_EXTINT      (*(REG32 (0xE01FC140)))
+#define SCB_EXTWAKE     (*(REG32 (0xE01FC144)))
+#define SCB_MEMMAP      (*(REG32 (0xE01FC040)))
+#define SCB_PLLCON      (*(REG32 (0xE01FC080)))
+#define SCB_PLLCFG      (*(REG32 (0xE01FC084)))
+#define SCB_PLLSTAT     (*(REG32 (0xE01FC088)))
+#define SCB_PLLFEED     (*(REG32 (0xE01FC08C)))
+#define SCB_PCON        (*(REG32 (0xE01FC0C0)))
+#define SCB_PCONP       (*(REG32 (0xE01FC0C4)))
+#define SCB_VPBDIV      (*(REG32 (0xE01FC100)))
+
+/*##############################################################################
+## Memory Accelerator Module (MAM)
+##############################################################################*/
+
+#define MAM_TIM			(*(REG32 (0xE01FC004)))
+#define MAM_CR			(*(REG32 (0xE01FC000)))
+
+#endif /* lpc210x_h */
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/main.c b/Demo/uIP_Demo_Rowley_ARM7/main.c
new file mode 100644
index 000000000..9b416e960
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/main.c
@@ -0,0 +1,284 @@
+/*
+	FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the application tasks, then starts the scheduler.  
+ * 
+ * A task is created called "uIP".  This executes the uIP stack and small
+ * WEB server sample.  All the other tasks are from the set of standard
+ * demo tasks.  The WEB documentation provides more details of the standard
+ * demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.
+ * Each standard demo task maintains a unique count that is incremented each 
+ * time the task successfully completes its function.  Should any error occur 
+ * within such a task the count is permanently halted.  The check task inspects
+ * the count of each task to ensure it has changed since the last time the 
+ * check task executed.  If all the count variables have changed all the tasks 
+ * are still executing error free, and the check task toggles the yellow LED.  
+ * Should any task contain an error at any time the LED toggle rate will change 
+ * from 3 seconds to 500ms.
+ *
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "PollQ.h"
+#include "dynamic.h"
+#include "semtest.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup the PLL. */
+#define mainPLL_MUL_4		( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_DIV_1		( ( unsigned portCHAR ) 0x0000 )
+#define mainPLL_ENABLE		( ( unsigned portCHAR ) 0x0001 )
+#define mainPLL_CONNECT		( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_FEED_BYTE1	( ( unsigned portCHAR ) 0xaa )
+#define mainPLL_FEED_BYTE2	( ( unsigned portCHAR ) 0x55 )
+#define mainPLL_LOCK		( ( unsigned portLONG ) 0x0400 )
+
+/* Constants to setup the MAM. */
+#define mainMAM_TIM_3		( ( unsigned portCHAR ) 0x03 )
+#define mainMAM_MODE_FULL	( ( unsigned portCHAR ) 0x02 )
+
+/* Constants to setup the peripheral bus. */
+#define mainBUS_CLK_FULL	( ( unsigned portCHAR ) 0x01 )
+
+/* Priorities/stacks for the demo application tasks. */
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainUIP_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainUIP_TASK_STACK_SIZE		( 150 )
+
+/* The rate at which the on board LED will toggle when there is/is not an 
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+#define mainON_BOARD_LED_BIT		( ( unsigned portLONG ) 0x80 )
+#define mainYELLOW_LED				( 1 << 11 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * This is the uIP task which is defined within the uip.c file.  This has not
+ * been placed into a header file in order to minimise the changes to the uip
+ * code.
+ */
+extern void ( vuIP_TASK ) ( void *pvParameters );
+
+/*
+ * The Yellow LED is under the control of the Check task.  All the other LED's
+ * are under the control of the uIP task. 
+ */
+void prvToggleOnBoardLED( void );
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * The task that executes at the highest priority and calls 
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Olimex demo board.  This includes
+ * setup for the I/O, system clock, and access timings.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler. 
+ */
+int main( void )
+{
+	/* Configure the processor. */
+	prvSetupHardware();
+
+	/* Start the task that handles the TCP/IP functionality. */
+    xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );
+	
+	/* Start the demo/test application tasks.  These are created in addition 
+	to the TCP/IP task for demonstration and test purposes. */
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */	
+    xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Now all the tasks have been started - start the scheduler.
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+	vTaskStartScheduler();
+
+	/* Should never reach here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the on board LED flash rate will increase. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelay( xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without 
+		error.  */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		prvToggleOnBoardLED();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	#ifdef RUN_FROM_RAM
+		/* Remap the interrupt vectors to RAM if we are are running from RAM. */
+		SCB_MEMMAP = 2;
+	#endif
+
+	/* Setup the PLL to multiply the XTAL input by 4. */
+	SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
+
+	/* Activate the PLL by turning it on then feeding the correct sequence of
+	bytes. */
+	SCB_PLLCON = mainPLL_ENABLE;
+	SCB_PLLFEED = mainPLL_FEED_BYTE1;
+	SCB_PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Wait for the PLL to lock... */
+	while( !( SCB_PLLSTAT & mainPLL_LOCK ) );
+
+	/* ...before connecting it using the feed sequence again. */
+	SCB_PLLCON = mainPLL_CONNECT;
+	SCB_PLLFEED = mainPLL_FEED_BYTE1;
+	SCB_PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Setup and turn on the MAM.  Three cycle access is used due to the fast
+	PLL used.  It is possible faster overall performance could be obtained by
+	tuning the MAM and PLL settings. */
+	MAM_TIM = mainMAM_TIM_3;
+	MAM_CR = mainMAM_MODE_FULL;
+
+	/* Setup the peripheral bus to be the same as the PLL output. */
+	SCB_VPBDIV = mainBUS_CLK_FULL;
+}
+/*-----------------------------------------------------------*/
+
+void prvToggleOnBoardLED( void )
+{
+unsigned portLONG ulState;
+
+	ulState = GPIO0_IOPIN;
+	if( ulState & mainYELLOW_LED )
+	{
+		GPIO_IOCLR = mainYELLOW_LED;
+	}
+	else
+	{
+		GPIO_IOSET = mainYELLOW_LED;
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp
new file mode 100644
index 000000000..aff3c5c6d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp
@@ -0,0 +1,55 @@
+
+
+  
+    
+    
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+        
+      
+    
+    
+      
+      
+      
+      
+        
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+        
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+  
+  
+  
diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs
new file mode 100644
index 000000000..8d14df8d1
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs
@@ -0,0 +1,55 @@
+
+
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+  
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile b/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile
new file mode 100644
index 000000000..61d3a06aa
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile
@@ -0,0 +1,74 @@
+# Copyright (c) 2001, Adam Dunkels.
+# All rights reserved. 
+#
+# Redistribution and use in source and binary forms, with or without 
+# modification, are permitted provided that the following conditions 
+# are met: 
+# 1. Redistributions of source code must retain the above copyright 
+#    notice, this list of conditions and the following disclaimer. 
+# 2. Redistributions in binary form must reproduce the above copyright 
+#    notice, this list of conditions and the following disclaimer in the 
+#    documentation and/or other materials provided with the distribution. 
+# 3. All advertising materials mentioning features or use of this software
+#    must display the following acknowledgement:
+#      This product includes software developed by Adam Dunkels.
+# 4. The name of the author may not be used to endorse or promote
+#    products derived from this software without specific prior
+#    written permission.  
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+#
+# This file is part of the uIP TCP/IP stack.
+#
+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $
+#
+
+CC=gcc
+CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp  -I../apps/telnet -fpack-struct
+
+%.o:
+	$(CC) $(CFLAGS) -c $(<:.o=.c)
+
+
+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o 
+
+tapdev.o: tapdev.c uipopt.h
+main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \
+ tapdev.h
+uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h 
+uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h 
+
+uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h
+	$(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c
+
+
+cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h
+fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \
+ ../apps/httpd/fsdata.c
+fsdata.o: ../apps/httpd/fsdata.c
+httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \
+ ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \
+ ../apps/httpd/fsdata.h ../apps/httpd/cgi.h
+
+clean:
+	rm -f *.o *~ *core uip
+
+
+
+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c
new file mode 100644
index 000000000..06574a156
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c
@@ -0,0 +1,211 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server script language C functions file.
+ * \author Adam Dunkels 
+ *
+ * This file contains functions that are called by the web server
+ * scripts. The functions takes one argument, and the return value is
+ * interpreted as follows. A zero means that the function did not
+ * complete and should be invoked for the next packet as well. A
+ * non-zero value indicates that the function has completed and that
+ * the web server should move along to the next script line.
+ *
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "cgi.h"
+#include "httpd.h"
+#include "fs.h"
+
+#include 
+#include 
+
+static u8_t print_stats(u8_t next);
+static u8_t file_stats(u8_t next);
+static u8_t tcp_stats(u8_t next);
+
+cgifunction cgitab[] = {
+  print_stats,   /* CGI function "a" */
+  file_stats,    /* CGI function "b" */
+  tcp_stats      /* CGI function "c" */
+};
+
+static const char closed[] =   /*  "CLOSED",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, 
+ 0x44,  0};
+static const char syn_sent[] = /*  "SYN-SENT",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, 
+ 0x54,  0};
+static const char established[] = /*  "ESTABLISHED",*/
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, 
+ 0x45, 0x44, 0};
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 
+ 0x54, 0x2d, 0x31, 0};
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 
+ 0x54, 0x2d, 0x32, 0};
+static const char closing[] = /*  "CLOSING",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x49, 
+ 0x4e, 0x47, 0};
+static const char time_wait[] = /*  "TIME-WAIT,"*/
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, 
+ 0x49, 0x54, 0};
+static const char last_ack[] = /*  "LAST-ACK"*/
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, 
+ 0x4b, 0};
+
+static const char *states[] = {
+  closed,
+  syn_rcvd,
+  syn_sent,
+  established,
+  fin_wait_1,
+  fin_wait_2,
+  closing,
+  time_wait,
+  last_ack};
+  
+
+/*-----------------------------------------------------------------------------------*/
+/* print_stats:
+ *
+ * Prints out a part of the uIP statistics. The statistics data is
+ * written into the uip_appdata buffer. It overwrites any incoming
+ * packet.
+ */
+static u8_t
+print_stats(u8_t next)
+{
+#if UIP_STATISTICS
+  u16_t i, j;
+  u8_t *buf;
+  u16_t *databytes;
+  
+  if(next) {
+    /* If our last data has been acknowledged, we move on the next
+       chunk of statistics. */
+    hs->count = hs->count + 4;
+    if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {
+      /* We have printed out all statistics, so we return 1 to
+	 indicate that we are done. */
+      return 1;
+    }
+  }
+
+  /* Write part of the statistics into the uip_appdata buffer. */
+  databytes = (u16_t *)&uip_stat + hs->count;
+  buf       = (u8_t *)uip_appdata;
+
+  j = 4 + 1;
+  i = hs->count;
+  while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {
+    sprintf((char *)buf, "%5u\r\n", *databytes);
+    ++databytes;
+    buf += 6;
+    ++i;
+  }
+
+  /* Send the data. */
+  uip_send(uip_appdata, buf - uip_appdata);
+  
+  return 0;
+#else
+  return 1;
+#endif /* UIP_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+file_stats(u8_t next)
+{
+  /* We use sprintf() to print the number of file accesses to a
+     particular file (given as an argument to the function in the
+     script). We then use uip_send() to actually send the data. */
+  if(next) {
+    return 1;
+  }
+  uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4])));  
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+tcp_stats(u8_t next)
+{
+  struct uip_conn *conn;  
+
+  if(next) {
+    /* If the previously sent data has been acknowledged, we move
+       forward one connection. */
+    if(++hs->count == UIP_CONNS) {
+      /* If all connections has been printed out, we are done and
+	 return 1. */
+      return 1;
+    }
+  }
+  
+  conn = &uip_conns[hs->count];
+  if((conn->tcpstateflags & TS_MASK) == CLOSED) {
+    uip_send(uip_appdata, sprintf((char *)uip_appdata,
+				  "--%u%u%c %c\r\n",
+				  conn->nrtx,
+				  conn->timer,
+				  (uip_outstanding(conn))? '*':' ',
+    				  (uip_stopped(conn))? '!':' '));
+  } else {
+    uip_send(uip_appdata, sprintf((char *)uip_appdata,
+				  "%u.%u.%u.%u:%u%s%u%u%c %c\r\n",
+				  htons(conn->ripaddr[0]) >> 8,
+				  htons(conn->ripaddr[0]) & 0xff,
+				  htons(conn->ripaddr[1]) >> 8,
+				  htons(conn->ripaddr[1]) & 0xff,
+				  htons(conn->rport),
+				  states[conn->tcpstateflags & TS_MASK],
+				  conn->nrtx,
+				  conn->timer,
+				  (uip_outstanding(conn))? '*':' ',
+    				  (uip_stopped(conn))? '!':' '));
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h
new file mode 100644
index 000000000..d85389b52
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h
@@ -0,0 +1,57 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP script language header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+#ifndef __CGI_H__
+#define __CGI_H__
+
+typedef u8_t (* cgifunction)(u8_t next);
+
+/**
+ * A table containing pointers to C functions that can be called from
+ * a web server script.
+ */
+extern cgifunction cgitab[];
+
+#endif /* __CGI_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm b/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm
new file mode 100644
index 000000000..ef91f42a8
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm
@@ -0,0 +1,66 @@
+// Rowley C Compiler, runtime support.
+//
+// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited.
+//
+// This file may be distributed under the terms of the License Agreement
+// provided with this software.
+//
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+
+; Create sections
+        .data
+        .bss
+
+; Go to code section.
+        .code
+
+; Executed upon reset
+__reset proc
+
+; Turn off watchdog.  You can enable it in main() if required.
+        mov.w   #0x5a80, &0x120
+
+; Set up stack.
+        mov.w   #RAM_Start_Address+RAM_Size, sp
+
+; Copy from initialised data section to data section.
+        mov.w   #SFB(IDATA0), r15
+        mov.w   #data_init_begin, r14
+        mov.w   #data_init_end-data_init_begin, r13
+        call    #_memcpy
+
+; Zero the bss.  Ensure the stack is not allocated in the bss!
+        mov.w   #SFB(UDATA0), r15
+        mov.w   #0, r14
+        mov.w   #SFE(UDATA0)-SFB(UDATA0), r13
+        call    #_memset
+
+; Call user entry point void main(void).
+        call    #_main
+
+; If main() returns, kick off again.
+        jmp     __reset
+        endproc
+
+; Heap data structures; removed by the linker if the heap isn't used.
+        .break   
+        .data
+        align   WORD
+___heap_start__::
+        DW      0
+        DW      heap_size
+        DS      heap_size-4    
+
+; Reset vector
+        .vectors
+        .keep
+        org     0x1e
+        dw      __reset
+
+; Initialise the IDATA0 section by duplicating the contents into the
+; CONST section and copying them on startup.
+        .const
+data_init_begin:
+        .init  "IDATA0"
+data_init_end:
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c
new file mode 100644
index 000000000..3ae1b162f
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c
@@ -0,0 +1,522 @@
+// cs8900a.c: device driver for the CS8900a chip in 8-bit mode.
+
+#include 
+
+#include "cs8900a.h"
+#include "uip.h"
+#include "uip_arp.h"
+
+#define IOR                  (1<<12)          // CS8900's ISA-bus interface pins
+#define IOW                  (1<<13)
+
+// definitions for Crystal CS8900 ethernet-controller
+// based on linux-header by Russel Nelson
+
+#define PP_ChipID            0x0000          // offset 0h -> Corp-ID
+                     
+											 // offset 2h -> Model/Product Number
+#define LED_RED (1<<8)
+#define LED_GREEN (1<<10)
+#define LED_YELLOW (1<<11)
+
+#define PP_ISAIOB            0x0020          // IO base address
+#define PP_CS8900_ISAINT     0x0022          // ISA interrupt select
+#define PP_CS8900_ISADMA     0x0024          // ISA Rec DMA channel
+#define PP_ISASOF            0x0026          // ISA DMA offset
+#define PP_DmaFrameCnt       0x0028          // ISA DMA Frame count
+#define PP_DmaByteCnt        0x002A          // ISA DMA Byte count
+#define PP_CS8900_ISAMemB    0x002C          // Memory base
+#define PP_ISABootBase       0x0030          // Boot Prom base
+#define PP_ISABootMask       0x0034          // Boot Prom Mask
+
+// EEPROM data and command registers
+#define PP_EECMD             0x0040          // NVR Interface Command register
+#define PP_EEData            0x0042          // NVR Interface Data Register
+
+// Configuration and control registers
+#define PP_RxCFG             0x0102          // Rx Bus config
+#define PP_RxCTL             0x0104          // Receive Control Register
+#define PP_TxCFG             0x0106          // Transmit Config Register
+#define PP_TxCMD             0x0108          // Transmit Command Register
+#define PP_BufCFG            0x010A          // Bus configuration Register
+#define PP_LineCTL           0x0112          // Line Config Register
+#define PP_SelfCTL           0x0114          // Self Command Register
+#define PP_BusCTL            0x0116          // ISA bus control Register
+#define PP_TestCTL           0x0118          // Test Register
+
+// Status and Event Registers
+#define PP_ISQ               0x0120          // Interrupt Status
+#define PP_RxEvent           0x0124          // Rx Event Register
+#define PP_TxEvent           0x0128          // Tx Event Register
+#define PP_BufEvent          0x012C          // Bus Event Register
+#define PP_RxMiss            0x0130          // Receive Miss Count
+#define PP_TxCol             0x0132          // Transmit Collision Count
+#define PP_LineST            0x0134          // Line State Register
+#define PP_SelfST            0x0136          // Self State register
+#define PP_BusST             0x0138          // Bus Status
+#define PP_TDR               0x013C          // Time Domain Reflectometry
+
+// Initiate Transmit Registers
+#define PP_TxCommand         0x0144          // Tx Command
+#define PP_TxLength          0x0146          // Tx Length
+
+// Adress Filter Registers
+#define PP_LAF               0x0150          // Hash Table
+#define PP_IA                0x0158          // Physical Address Register
+
+// Frame Location
+#define PP_RxStatus          0x0400          // Receive start of frame
+#define PP_RxLength          0x0402          // Receive Length of frame
+#define PP_RxFrame           0x0404          // Receive frame pointer
+#define PP_TxFrame           0x0A00          // Transmit frame pointer
+
+// Primary I/O Base Address. If no I/O base is supplied by the user, then this
+// can be used as the default I/O base to access the PacketPage Area.
+#define DEFAULTIOBASE        0x0300
+
+// PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition - Read/write
+#define SKIP_1               0x0040
+#define RX_STREAM_ENBL       0x0080
+#define RX_OK_ENBL           0x0100
+#define RX_DMA_ONLY          0x0200
+#define AUTO_RX_DMA          0x0400
+#define BUFFER_CRC           0x0800
+#define RX_CRC_ERROR_ENBL    0x1000
+#define RX_RUNT_ENBL         0x2000
+#define RX_EXTRA_DATA_ENBL   0x4000
+
+// PP_RxCTL - Receive Control bit definition - Read/write
+#define RX_IA_HASH_ACCEPT    0x0040
+#define RX_PROM_ACCEPT       0x0080
+#define RX_OK_ACCEPT         0x0100
+#define RX_MULTCAST_ACCEPT   0x0200
+#define RX_IA_ACCEPT         0x0400
+#define RX_BROADCAST_ACCEPT  0x0800
+#define RX_BAD_CRC_ACCEPT    0x1000
+#define RX_RUNT_ACCEPT       0x2000
+#define RX_EXTRA_DATA_ACCEPT 0x4000
+
+// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write
+#define TX_LOST_CRS_ENBL     0x0040
+#define TX_SQE_ERROR_ENBL    0x0080
+#define TX_OK_ENBL           0x0100
+#define TX_LATE_COL_ENBL     0x0200
+#define TX_JBR_ENBL          0x0400
+#define TX_ANY_COL_ENBL      0x0800
+#define TX_16_COL_ENBL       0x8000
+
+// PP_TxCMD - Transmit Command bit definition - Read-only and
+// PP_TxCommand - Write-only
+#define TX_START_5_BYTES     0x0000
+#define TX_START_381_BYTES   0x0040
+#define TX_START_1021_BYTES  0x0080
+#define TX_START_ALL_BYTES   0x00C0
+#define TX_FORCE             0x0100
+#define TX_ONE_COL           0x0200
+#define TX_NO_CRC            0x1000
+#define TX_RUNT              0x2000
+
+// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write
+#define GENERATE_SW_INTERRUPT      0x0040
+#define RX_DMA_ENBL                0x0080
+#define READY_FOR_TX_ENBL          0x0100
+#define TX_UNDERRUN_ENBL           0x0200
+#define RX_MISS_ENBL               0x0400
+#define RX_128_BYTE_ENBL           0x0800
+#define TX_COL_COUNT_OVRFLOW_ENBL  0x1000
+#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
+#define RX_DEST_MATCH_ENBL         0x8000
+
+// PP_LineCTL - Line Control bit definition - Read/write
+#define SERIAL_RX_ON         0x0040
+#define SERIAL_TX_ON         0x0080
+#define AUI_ONLY             0x0100
+#define AUTO_AUI_10BASET     0x0200
+#define MODIFIED_BACKOFF     0x0800
+#define NO_AUTO_POLARITY     0x1000
+#define TWO_PART_DEFDIS      0x2000
+#define LOW_RX_SQUELCH       0x4000
+
+// PP_SelfCTL - Software Self Control bit definition - Read/write
+#define POWER_ON_RESET       0x0040
+#define SW_STOP              0x0100
+#define SLEEP_ON             0x0200
+#define AUTO_WAKEUP          0x0400
+#define HCB0_ENBL            0x1000
+#define HCB1_ENBL            0x2000
+#define HCB0                 0x4000
+#define HCB1                 0x8000
+
+// PP_BusCTL - ISA Bus Control bit definition - Read/write
+#define RESET_RX_DMA         0x0040
+#define MEMORY_ON            0x0400
+#define DMA_BURST_MODE       0x0800
+#define IO_CHANNEL_READY_ON  0x1000
+#define RX_DMA_SIZE_64K      0x2000
+#define ENABLE_IRQ           0x8000
+
+// PP_TestCTL - Test Control bit definition - Read/write
+#define LINK_OFF             0x0080
+#define ENDEC_LOOPBACK       0x0200
+#define AUI_LOOPBACK         0x0400
+#define BACKOFF_OFF          0x0800
+#define FDX_8900             0x4000
+
+// PP_RxEvent - Receive Event Bit definition - Read-only
+#define RX_IA_HASHED         0x0040
+#define RX_DRIBBLE           0x0080
+#define RX_OK                0x0100
+#define RX_HASHED            0x0200
+#define RX_IA                0x0400
+#define RX_BROADCAST         0x0800
+#define RX_CRC_ERROR         0x1000
+#define RX_RUNT              0x2000
+#define RX_EXTRA_DATA        0x4000
+#define HASH_INDEX_MASK      0xFC00          // Hash-Table Index Mask (6 Bit)
+
+// PP_TxEvent - Transmit Event Bit definition - Read-only
+#define TX_LOST_CRS          0x0040
+#define TX_SQE_ERROR         0x0080
+#define TX_OK                0x0100
+#define TX_LATE_COL          0x0200
+#define TX_JBR               0x0400
+#define TX_16_COL            0x8000
+#define TX_COL_COUNT_MASK    0x7800
+
+// PP_BufEvent - Buffer Event Bit definition - Read-only
+#define SW_INTERRUPT         0x0040
+#define RX_DMA               0x0080
+#define READY_FOR_TX         0x0100
+#define TX_UNDERRUN          0x0200
+#define RX_MISS              0x0400
+#define RX_128_BYTE          0x0800
+#define TX_COL_OVRFLW        0x1000
+#define RX_MISS_OVRFLW       0x2000
+#define RX_DEST_MATCH        0x8000
+
+// PP_LineST - Ethernet Line Status bit definition - Read-only
+#define LINK_OK              0x0080
+#define AUI_ON               0x0100
+#define TENBASET_ON          0x0200
+#define POLARITY_OK          0x1000
+#define CRS_OK               0x4000
+
+// PP_SelfST - Chip Software Status bit definition
+#define ACTIVE_33V           0x0040
+#define INIT_DONE            0x0080
+#define SI_BUSY              0x0100
+#define EEPROM_PRESENT       0x0200
+#define EEPROM_OK            0x0400
+#define EL_PRESENT           0x0800
+#define EE_SIZE_64           0x1000
+
+// PP_BusST - ISA Bus Status bit definition
+#define TX_BID_ERROR         0x0080
+#define READY_FOR_TX_NOW     0x0100
+
+// The following block defines the ISQ event types
+#define ISQ_RX_EVENT         0x0004
+#define ISQ_TX_EVENT         0x0008
+#define ISQ_BUFFER_EVENT     0x000C
+#define ISQ_RX_MISS_EVENT    0x0010
+#define ISQ_TX_COL_EVENT     0x0012
+
+#define ISQ_EVENT_MASK       0x003F          // ISQ mask to find out type of event
+
+// Ports for I/O-Mode
+#define RX_FRAME_PORT        0x0000
+#define TX_FRAME_PORT        0x0000
+#define TX_CMD_PORT          0x0004
+#define TX_LEN_PORT          0x0006
+#define ISQ_PORT             0x0008
+#define ADD_PORT             0x000A
+#define DATA_PORT            0x000C
+
+#define AUTOINCREMENT        0x8000          // Bit mask to set Bit-15 for autoincrement
+
+// EEProm Commands
+#define EEPROM_WRITE_EN      0x00F0
+#define EEPROM_WRITE_DIS     0x0000
+#define EEPROM_WRITE_CMD     0x0100
+#define EEPROM_READ_CMD      0x0200
+
+// Receive Header of each packet in receive area of memory for DMA-Mode
+#define RBUF_EVENT_LOW       0x0000          // Low byte of RxEvent
+#define RBUF_EVENT_HIGH      0x0001          // High byte of RxEvent
+#define RBUF_LEN_LOW         0x0002          // Length of received data - low byte
+#define RBUF_LEN_HI          0x0003          // Length of received data - high byte
+#define RBUF_HEAD_LEN        0x0004          // Length of this header
+
+// typedefs
+typedef struct {                             // struct to store CS8900's
+  unsigned int Addr;                         // init-sequence
+  unsigned int Data;
+} TInitSeq;
+
+unsigned short ticks;
+
+static void skip_frame(void);
+
+const TInitSeq InitSeq[] =
+{
+  PP_IA,       UIP_ETHADDR0 + (UIP_ETHADDR1 << 8),     // set our MAC as Individual Address
+  PP_IA + 2,   UIP_ETHADDR2 + (UIP_ETHADDR3 << 8),
+  PP_IA + 4,   UIP_ETHADDR4 + (UIP_ETHADDR5 << 8),
+  PP_LineCTL,  SERIAL_RX_ON | SERIAL_TX_ON,           // configure the Physical Interface
+  PP_RxCTL,    RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT
+};
+
+// Writes a word in little-endian byte order to a specified port-address
+void
+cs8900a_write(unsigned addr, unsigned int data)
+{
+  IODIR |= 0xff << 16;                           // Data port to output
+
+  IOCLR = 0xf << 4;                              // Put address on bus
+  IOSET = addr << 4;
+  
+  IOCLR = 0xff << 16;                            // Write low order byte to data bus
+  IOSET = data << 16;
+
+  IOCLR = IOW;                                   // Toggle IOW-signal
+  IOSET = IOW;
+
+  IOCLR = 0xf << 4;
+  IOSET = ((addr | 1) << 4);                     // And put next address on bus
+
+  IOCLR = 0xff << 16;                            // Write high order byte to data bus
+  IOSET = data >> 8 << 16;
+
+  IOCLR = IOW;                                   // Toggle IOW-signal
+  IOSET = IOW;
+}
+
+// Reads a word in little-endian byte order from a specified port-address
+unsigned
+cs8900a_read(unsigned addr)
+{
+  unsigned int value;
+
+  IODIR &= ~(0xff << 16);                        // Data port to input
+
+  IOCLR = 0xf << 4;                              // Put address on bus
+  IOSET = addr << 4;
+
+  IOCLR = IOR;                                   // IOR-signal low
+  value = (IOPIN >> 16) & 0xff;                  // get low order byte from data bus
+  IOSET = IOR;
+
+  IOSET = 1 << 4;                                // IOR high and put next address on bus
+
+  IOCLR = IOR;                                   // IOR-signal low
+  value |= ((IOPIN >> 8) & 0xff00);              // get high order byte from data bus
+  IOSET = IOR;                                   // IOR-signal low
+  
+  return value;
+}
+
+// Reads a word in little-endian byte order from a specified port-address
+unsigned
+cs8900a_read_addr_high_first(unsigned addr)
+{
+  unsigned int value;
+
+  IODIR &= ~(0xff << 16);                        // Data port to input
+
+  IOCLR = 0xf << 4;                              // Put address on bus
+  IOSET = (addr+1) << 4;
+
+  IOCLR = IOR;                                   // IOR-signal low
+  value = ((IOPIN >> 8) & 0xff00);               // get high order byte from data bus
+  IOSET = IOR;                                   // IOR-signal high
+
+  IOCLR = 1 << 4;                                // Put low address on bus
+
+  IOCLR = IOR;                                   // IOR-signal low
+  value |= (IOPIN >> 16) & 0xff;                 // get low order byte from data bus
+  IOSET = IOR;
+
+  return value;
+}
+
+void
+cs8900a_init(void)
+{
+  int i;
+
+  // Reset outputs, control lines high
+  IOSET = IOR | IOW;
+
+  // No LEDs on.
+  IOSET = LED_RED | LED_YELLOW | LED_GREEN;
+
+  // Port 3 as output (all pins but RS232)
+  IODIR = ~0U; // everything to output.
+
+  // Reset outputs
+  IOCLR = 0xff << 16;  // clear data outputs
+
+  // Reset the CS8900A
+  cs8900a_write(ADD_PORT, PP_SelfCTL);
+  cs8900a_write(DATA_PORT, POWER_ON_RESET);
+
+  // Wait until chip-reset is done
+  cs8900a_write(ADD_PORT, PP_SelfST);
+  while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0)
+    ;
+
+  // Configure the CS8900A
+  for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i)
+    {
+      cs8900a_write(ADD_PORT, InitSeq[i].Addr);
+      cs8900a_write(DATA_PORT, InitSeq[i].Data);
+    }
+}
+
+void
+cs8900a_send(void)
+{
+  unsigned u;
+
+  IOCLR = LED_RED;  // Light RED LED when frame starting
+
+  // Transmit command
+  cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES);
+  cs8900a_write(TX_LEN_PORT, uip_len);
+
+  // Maximum number of retries
+  u = 8;
+  for (;;)
+    {
+      // Check for avaliable buffer space
+      cs8900a_write(ADD_PORT, PP_BusST);
+      if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW)
+        break;
+      if (u -- == 0)
+        {
+          IOSET = LED_RED;  // Extinguish RED LED on end of frame
+          return;
+        }
+
+      // No space avaliable, skip a received frame and try again
+      skip_frame();
+    }
+
+  IODIR |= 0xff << 16;                           // Data port to output
+
+  // Send 40+14=54 bytes of header
+  for (u = 0; u < 54; u += 2)
+    {
+      IOCLR = 0xf << 4;                              // Put address on bus
+      IOSET = TX_FRAME_PORT << 4;
+
+      IOCLR = 0xff << 16;                            // Write low order byte to data bus
+      IOSET = uip_buf[u] << 16;                      // write low order byte to data bus
+
+      IOCLR = IOW;                                   // Toggle IOW-signal
+      IOSET = IOW;
+
+      IOCLR = 0xf << 4;                              // Put address on bus
+      IOSET = (TX_FRAME_PORT | 1) << 4;              // and put next address on bus
+
+      IOCLR = 0xff << 16;                            // Write low order byte to data bus
+      IOSET = uip_buf[u+1] << 16;                    // write low order byte to data bus
+
+      IOCLR = IOW;                                   // Toggle IOW-signal
+      IOSET = IOW;
+    }
+
+  if (uip_len <= 54)
+    {
+      IOSET = LED_RED;  // Extinguish RED LED on end of frame
+      return;
+    }
+
+  // Send remainder of packet, the application data
+  uip_len -= 54;
+  for (u = 0; u < uip_len; u += 2)
+    {
+
+      IOCLR = 0xf << 4;                          // Put address on bus
+      IOSET = TX_FRAME_PORT << 4;
+
+      IOCLR = 0xff << 16;                        // Write low order byte to data bus
+      IOSET = uip_appdata[u] << 16;              // write low order byte to data bus
+
+      IOCLR = IOW;                               // Toggle IOW-signal
+      IOSET = IOW;
+
+      IOCLR = 0xf << 4;                          // Put address on bus
+      IOSET = (TX_FRAME_PORT | 1) << 4;          // and put next address on bus
+
+      IOCLR = 0xff << 16;                        // Write low order byte to data bus
+      IOSET = uip_appdata[u+1] << 16;            // write low order byte to data bus
+
+      IOCLR = IOW;                               // Toggle IOW-signal
+      IOSET = IOW;
+    }
+
+  IOSET = LED_RED;  // Extinguish RED LED on end of frame
+}
+
+static void
+skip_frame(void)
+{
+  // No space avaliable, skip a received frame and try again
+  cs8900a_write(ADD_PORT, PP_RxCFG);
+  cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1);
+}
+
+u8_t
+cs8900a_poll(void)
+{
+  u16_t len, u;
+
+  // Check receiver event register to see if there are any valid frames avaliable
+  cs8900a_write(ADD_PORT, PP_RxEvent);
+  if ((cs8900a_read(DATA_PORT) & 0xd00) == 0)
+    return 0;
+
+  IOCLR = LED_GREEN;  // Light GREED LED when frame coming in.
+
+  // Read receiver status and discard it.
+  cs8900a_read_addr_high_first(RX_FRAME_PORT);
+
+  // Read frame length
+  len = cs8900a_read_addr_high_first(RX_FRAME_PORT);
+
+  // If the frame is too big to handle, throw it away
+  if (len > UIP_BUFSIZE)
+    {
+      skip_frame();
+      return 0;
+    }
+
+  // Data port to input
+  IODIR &= ~(0xff << 16);
+
+  IOCLR = 0xf << 4;                          // put address on bus
+  IOSET = RX_FRAME_PORT << 4; 
+
+  // Read bytes into uip_buf
+  u = 0;
+  while (u < len)
+    {
+      IOCLR = 1 << 4;                            // put address on bus
+
+      IOCLR = IOR;                               // IOR-signal low
+      uip_buf[u] = IOPIN >> 16;                // get high order byte from data bus
+      IOSET = IOR;                               // IOR-signal high
+
+      IOSET = 1 << 4;                            // put address on bus
+
+      IOCLR = IOR;                               // IOR-signal low
+      uip_buf[u+1] = IOPIN >> 16;                  // get high order byte from data bus
+      IOSET = IOR;                               // IOR-signal high
+      u += 2;
+    }
+
+  IOSET = LED_GREEN;  // Extinguish GREED LED when frame finished.
+  return len;
+}
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h
new file mode 100644
index 000000000..2d4b56fe0
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h
@@ -0,0 +1,10 @@
+#ifndef __CS8900A_H__
+#define __CS8900A_H__
+
+#include "uip_arch.h"
+
+void cs8900a_init(void);
+void cs8900a_send(void);
+u8_t cs8900a_poll(void);
+
+#endif /* __CS8900A_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c
new file mode 100644
index 000000000..7e15200b2
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c
@@ -0,0 +1,155 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server read-only file system code.
+ * \author Adam Dunkels 
+ *
+ * A simple read-only filesystem. 
+ */
+ 
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $
+ */
+
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+#include "fsdata.h"
+
+#define NULL (void *)0
+#include "fsdata.c"
+
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+static u16_t count[FS_NUMFILES];
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+fs_strcmp(const char *str1, const char *str2)
+{
+  u8_t i;
+  i = 0;
+ loop:
+
+  if(str2[i] == 0 ||
+     str1[i] == '\r' || 
+     str1[i] == '\n') {
+    return 0;
+  }
+
+  if(str1[i] != str2[i]) {
+    return 1;
+  }
+
+
+  ++i;
+  goto loop;
+}
+/*-----------------------------------------------------------------------------------*/
+int
+fs_open(const char *name, struct fs_file *file)
+{
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t i = 0;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+  struct fsdata_file_noconst *f;
+
+  for(f = (struct fsdata_file_noconst *)FS_ROOT;
+      f != NULL;
+      f = (struct fsdata_file_noconst *)f->next) {
+
+    if(fs_strcmp(name, f->name) == 0) {
+      file->data = f->data;
+      file->len = f->len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+      ++count[i];
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+      return 1;
+    }
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+    ++i;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+void
+fs_init(void)
+{
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t i;
+  for(i = 0; i < FS_NUMFILES; i++) {
+    count[i] = 0;
+  }
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1  
+u16_t fs_count
+(char *name)
+{
+  struct fsdata_file_noconst *f;
+  u16_t i;
+
+  i = 0;
+  for(f = (struct fsdata_file_noconst *)FS_ROOT;
+      f != NULL;
+      f = (struct fsdata_file_noconst *)f->next) {
+
+    if(fs_strcmp(name, f->name) == 0) {
+      return count[i];
+    }
+    ++i;
+  }
+  return 0;
+}
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h
new file mode 100644
index 000000000..65551ba41
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h
@@ -0,0 +1,80 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server read-only file system header file.
+ * \author Adam Dunkels 
+ */
+ 
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $
+ */
+#ifndef __FS_H__
+#define __FS_H__
+
+#include "uip.h"
+
+/**
+ * An open file in the read-only file system.
+ */
+struct fs_file {
+  char *data;  /**< The actual file data. */
+  int len;     /**< The length of the file data. */
+};
+
+/**
+ * Open a file in the read-only file system.
+ *
+ * \param name The name of the file.
+ *
+ * \param file The file pointer, which must be allocated by caller and
+ * will be filled in by the function.
+ */
+int fs_open(const char *name, struct fs_file *file);
+
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1  
+u16_t fs_count(char *name);
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+/**
+ * Initialize the read-only file system.
+ */
+void fs_init(void);
+
+#endif /* __FS_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html
new file mode 100644
index 000000000..8d6beec83
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html
@@ -0,0 +1 @@
+
404 - file not found

\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html
new file mode 100644
index 000000000..4c886897b
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html
@@ -0,0 +1,18 @@
+
+
+

+

+
Welcome

+

+These web pages are served by the small web server running on top of
+the uIP TCP/IP
+stack.
+

+

+Click on the links above to see some status information about the web
+server and the TCP/IP stack.
+

+

+

+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files
new file mode 100644
index 000000000..64e0b5005
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files
@@ -0,0 +1,28 @@
+# This script shows the access statistics for different files on the
+# web server.
+#
+# First, we include the HTML header.
+i /files_header.html
+# Print out the name of the file, and call the function that prints
+# the access statistics of that file.
+t /index.html
+c b /index.html
+t  /about.html
+c b /about.html
+t  /control.html
+c b /control.html
+t  /img/bg.png
+c b /img/bg.png
+t  /404.html
+c b /404.html
+t  /cgi/files
+c b /cgi/files
+t  /cgi/stats
+c b /cgi/stats
+t  /cgi/tcp
+c b /cgi/tcp
+t 
+# Include the HTML footer.
+i /files_footer.plain
+# End of script.
+.
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats
new file mode 100644
index 000000000..2c71c90dc
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats
@@ -0,0 +1,4 @@
+i /stats_header.html
+c a
+i /stats_footer.plain
+.
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp
new file mode 100644
index 000000000..14efd3700
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp
@@ -0,0 +1,4 @@
+i /tcp_header.html
+c c
+i /tcp_footer.plain
+.
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html
new file mode 100644
index 000000000..ce28dbe7d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html
@@ -0,0 +1,14 @@
+
+
+

+

+
uIP web server test pages

+[ About |
+Connections |
+Files |
+Statistics ]
+

+

+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain
new file mode 100644
index 000000000..0b6dceb4f
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain
@@ -0,0 +1,3 @@
+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html
new file mode 100644
index 000000000..25d86501e
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html
@@ -0,0 +1,4 @@
+
+
+

+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png
new file mode 100644
index 000000000..18533b369
Binary files /dev/null and b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png differ
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html
new file mode 100644
index 000000000..3429ef3af
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html
@@ -0,0 +1,14 @@
+
+uIP web server test page
+
+ 
+  
+  
+
+
+
+<body>
+Your browser must support frames
+</body>
+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain
new file mode 100644
index 000000000..0b6dceb4f
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain
@@ -0,0 +1,3 @@
+

+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html
new file mode 100644
index 000000000..4efaddf5b
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html
@@ -0,0 +1,30 @@
+
+
+

+
+

+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
	     
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
new file mode 100644
index 000000000..442c17a58
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
@@ -0,0 +1,5 @@
+
+

+

+
+
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html
new file mode 100644
index 000000000..1a5057167
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html
@@ -0,0 +1,6 @@
+
+
+

+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c
new file mode 100644
index 000000000..ff855e7dc
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c
@@ -0,0 +1,619 @@
+static const char data_cgi_files[] = {
+	/* /cgi/files */
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+	0x70, 0x74, 0x2e, 0xa, 0x2e, };
+
+static const char data_cgi_stats[] = {
+	/* /cgi/stats */
+	0x2f, 0x63, 0x67, 0x69, 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0,
+	0x69, 0x20, 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x5f, 0x68, 
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+	0x2e, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xa, 0x2e, 0xa, };
+
+static const char data_cgi_tcp[] = {
+	/* /cgi/tcp */
+	0x2f, 0x63, 0x67, 0x69, 0x2f, 0x74, 0x63, 0x70, 0,
+	0x69, 0x20, 0x2f, 0x74, 0x63, 0x70, 0x5f, 0x68, 0x65, 0x61, 
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+	0x69, 0x6e, 0xa, 0x2e, };
+
+static const char data_img_bg_png[] = {
+	/* /img/bg.png */
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+
+static const char data_about_html[] = {
+	/* /about.html */
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+
+static const char data_control_html[] = {
+	/* /control.html */
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+	0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x77, 0x69, 0x74, 
+	0x68, 0x6f, 0x75, 0x74, 0x20, 0x41, 0x43, 0x4b, 0x73, 0xa, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x52, 0x65, 0x73, 0x65, 0x74, 0x73, 0xa, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, 0x73, 
+	0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x9, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x4e, 0x6f, 0x20, 0x63, 0x6f, 
+	0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x61, 
+	0x76, 0x61, 0x6c, 0x69, 0x61, 0x62, 0x6c, 0x65, 0xa, 0x9, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 
+	0x63, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x61, 0x74, 0x74, 0x65, 
+	0x6d, 0x70, 0x74, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x63, 0x6c, 
+	0x6f, 0x73, 0x65, 0x64, 0x20, 0x70, 0x6f, 0x72, 0x74, 0x73, 
+	0xa, 0x3c, 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x9, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 
+	0x74, 0x64, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, };
+
+static const char data_tcp_footer_plain[] = {
+	/* /tcp_footer.plain */
+	0x2f, 0x74, 0x63, 0x70, 0x5f, 0x66, 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0,
+	0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 
+	0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x3e, 0xa, 
+	0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xa, 
+	0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 
+	0x68, 0x74, 0x6d, 0x6c, 0x3e, };
+
+static const char data_tcp_header_html[] = {
+	/* /tcp_header.html */
+	0x2f, 0x74, 0x63, 0x70, 0x5f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 
+	0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 
+	0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, 
+	0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 
+	0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, 
+	0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 
+	0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, 
+	0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 
+	0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 
+	0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x3c, 
+	0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 
+	0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, 
+	0x3e, 0xa, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 
+	0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, 
+	0x64, 0x74, 0x68, 0x3d, 0x22, 0x36, 0x30, 0x30, 0x22, 0x20, 
+	0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 0x22, 0x30, 0x22, 
+	0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 
+	0x52, 0x65, 0x6d, 0x6f, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 
+	0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x53, 0x74, 0x61, 0x74, 0x65, 
+	0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 
+	0x65, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, 
+	0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 
+	0x74, 0x68, 0x3e, 0x54, 0x69, 0x6d, 0x65, 0x72, 0x3c, 0x2f, 
+	0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x46, 0x6c, 0x61, 
+	0x67, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, 
+	0x72, 0x3e, 0xa, 0xa, };
+
+const struct fsdata_file file_cgi_files[] = {{NULL, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}};
+
+const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}};
+
+const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}};
+
+const struct fsdata_file file_img_bg_png[] = {{file_cgi_tcp, data_img_bg_png, data_img_bg_png + 12, sizeof(data_img_bg_png) - 12}};
+
+const struct fsdata_file file_about_html[] = {{file_img_bg_png, data_about_html, data_about_html + 12, sizeof(data_about_html) - 12}};
+
+const struct fsdata_file file_control_html[] = {{file_about_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}};
+
+const struct fsdata_file file_404_html[] = {{file_control_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};
+
+const struct fsdata_file file_files_footer_plain[] = {{file_404_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}};
+
+const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}};
+
+const struct fsdata_file file_index_html[] = {{file_files_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
+
+const struct fsdata_file file_stats_footer_plain[] = {{file_index_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}};
+
+const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}};
+
+const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}};
+
+const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}};
+
+#define FS_ROOT file_tcp_header_html
+
+#define FS_NUMFILES 14
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h
new file mode 100644
index 000000000..94086c4df
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $
+ */
+#ifndef __FSDATA_H__
+#define __FSDATA_H__
+
+#include "uipopt.h"
+
+struct fsdata_file {
+  const struct fsdata_file *next;
+  const char *name;
+  const char *data;
+  const int len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t count;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+};
+
+struct fsdata_file_noconst {
+  struct fsdata_file *next;
+  char *name;
+  char *data;
+  int len;
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1
+  u16_t count;
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+};
+
+#endif /* __FSDATA_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c
new file mode 100644
index 000000000..9d2c6e599
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c
@@ -0,0 +1,373 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \defgroup httpd Web server
+ * @{
+ *
+ * The uIP web server is a very simplistic implementation of an HTTP
+ * server. It can serve web pages and files from a read-only ROM
+ * filesystem, and provides a very small scripting language.
+ *
+ * The script language is very simple and works as follows. Each
+ * script line starts with a command character, either "i", "t", "c",
+ * "#" or ".".  The "i" command tells the script interpreter to
+ * "include" a file from the virtual file system and output it to the
+ * web browser. The "t" command should be followed by a line of text
+ * that is to be output to the browser. The "c" command is used to
+ * call one of the C functions from the httpd-cgi.c file. A line that
+ * starts with a "#" is ignored (i.e., the "#" denotes a comment), and
+ * the "." denotes the last script line.
+ *
+ * The script that produces the file statistics page looks somewhat
+ * like this:
+ *
+ \code
+i /header.html
+t 
File statistics

RemoteStateRetransmissionsTimerFlags

+t 
/index.html
+c a /index.html
+t 
 
/cgi/files
+c a /cgi/files
+t 
 
/cgi/tcp
+c a /cgi/tcp
+t 
 
/404.html
+c a /404.html
+t 

+i /footer.plain
+.
+ \endcode
+ *
+ */
+
+
+/**
+ * \file
+ * HTTP server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+#include "fsdata.h"
+#include "cgi.h"
+
+#define NULL (void *)0
+
+/* The HTTP server states: */
+#define HTTP_NOGET        0
+#define HTTP_FILE         1
+#define HTTP_TEXT         2
+#define HTTP_FUNC         3
+#define HTTP_END          4
+
+#ifdef DEBUG
+#include 
+#define PRINT(x) 
+#define PRINTLN(x)
+#else /* DEBUG */
+#define PRINT(x)
+#define PRINTLN(x)
+#endif /* DEBUG */
+
+struct httpd_state *hs;
+
+extern const struct fsdata_file file_index_html;
+extern const struct fsdata_file file_404_html;
+
+static void next_scriptline(void);
+static void next_scriptstate(void);
+
+#define ISO_G        0x47
+#define ISO_E        0x45
+#define ISO_T        0x54
+#define ISO_slash    0x2f    
+#define ISO_c        0x63
+#define ISO_g        0x67
+#define ISO_i        0x69
+#define ISO_space    0x20
+#define ISO_nl       0x0a
+#define ISO_cr       0x0d
+#define ISO_a        0x61
+#define ISO_t        0x74
+#define ISO_hash     0x23
+#define ISO_period   0x2e
+
+#define httpPORT	80
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the web server.
+ *
+ * Starts to listen for incoming connection requests on TCP port 80.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+httpd_init(void)
+{
+  fs_init();
+  
+  /* Listen to port 80. */
+  uip_listen(HTONS(httpPORT));
+}
+/*-----------------------------------------------------------------------------------*/
+void
+httpd_appcall(void)
+{
+  struct fs_file fsfile;  
+
+  u8_t i;
+
+  switch(uip_conn->lport) {
+    /* This is the web server: */
+  case HTONS(httpPORT):
+    /* Pick out the application state from the uip_conn structure. */
+    hs = (struct httpd_state *)(uip_conn->appstate);
+
+    /* We use the uip_ test functions to deduce why we were
+       called. If uip_connected() is non-zero, we were called
+       because a remote host has connected to us. If
+       uip_newdata() is non-zero, we were called because the
+       remote host has sent us new data, and if uip_acked() is
+       non-zero, the remote host has acknowledged the data we
+       previously sent to it. */
+    if(uip_connected()) {
+      /* Since we have just been connected with the remote host, we
+         reset the state for this connection. The ->count variable
+         contains the amount of data that is yet to be sent to the
+         remote host, and the ->state is set to HTTP_NOGET to signal
+         that we haven't received any HTTP GET request for this
+         connection yet. */
+
+      hs->state = HTTP_NOGET;
+      hs->count = 0;
+      return;
+
+    } else if(uip_poll()) {
+      /* If we are polled ten times, we abort the connection. This is
+         because we don't want connections lingering indefinately in
+         the system. */
+      if(hs->count++ >= 10) {
+	uip_abort();
+      }
+      return;
+    } else if(uip_newdata() && hs->state == HTTP_NOGET) {
+      /* This is the first data we receive, and it should contain a
+	 GET. */
+
+      /* Check for GET. */
+      if(uip_appdata[0] != ISO_G ||
+	 uip_appdata[1] != ISO_E ||
+	 uip_appdata[2] != ISO_T ||
+	 uip_appdata[3] != ISO_space) {
+	/* If it isn't a GET, we abort the connection. */
+	uip_abort();
+	return;
+      }
+	       
+      /* Find the file we are looking for. */
+      for(i = 4; i < 40; ++i) {
+	if(uip_appdata[i] == ISO_space ||
+	   uip_appdata[i] == ISO_cr ||
+	   uip_appdata[i] == ISO_nl) {
+	  uip_appdata[i] = 0;
+	  break;
+	}
+      }
+
+      PRINT("request for file ");
+      PRINTLN(&uip_appdata[4]);
+      
+      /* Check for a request for "/". */
+      if(uip_appdata[4] == ISO_slash &&
+	 uip_appdata[5] == 0) {
+	fs_open(file_index_html.name, &fsfile);    
+      } else {
+	if(!fs_open((const char *)&uip_appdata[4], &fsfile)) {
+	  PRINTLN("couldn't open file");
+	  fs_open(file_404_html.name, &fsfile);
+	}
+      } 
+
+
+      if(uip_appdata[4] == ISO_slash &&
+	 uip_appdata[5] == ISO_c &&
+	 uip_appdata[6] == ISO_g &&
+	 uip_appdata[7] == ISO_i &&
+	 uip_appdata[8] == ISO_slash) {
+	/* If the request is for a file that starts with "/cgi/", we
+           prepare for invoking a script. */	
+	hs->script = fsfile.data;
+	next_scriptstate();
+      } else {
+	hs->script = NULL;
+	/* The web server is now no longer in the HTTP_NOGET state, but
+	   in the HTTP_FILE state since is has now got the GET from
+	   the client and will start transmitting the file. */
+	hs->state = HTTP_FILE;
+
+	/* Point the file pointers in the connection state to point to
+	   the first byte of the file. */
+	hs->dataptr = fsfile.data;
+	hs->count = fsfile.len;	
+      }     
+    }
+
+    
+    if(hs->state != HTTP_FUNC) {
+      /* Check if the client (remote end) has acknowledged any data that
+	 we've previously sent. If so, we move the file pointer further
+	 into the file and send back more data. If we are out of data to
+	 send, we close the connection. */
+      if(uip_acked()) {
+	if(hs->count >= uip_conn->len) {
+	  hs->count -= uip_conn->len;
+	  hs->dataptr += uip_conn->len;
+	} else {
+	  hs->count = 0;
+	}
+	
+	if(hs->count == 0) {
+	  if(hs->script != NULL) {
+	    next_scriptline();
+	    next_scriptstate();
+	  } else {
+	    uip_close();
+	  }
+	}
+      }         
+    } else {
+      /* Call the CGI function. */
+      if(cgitab[hs->script[2] - ISO_a](uip_acked())) {
+	/* If the function returns non-zero, we jump to the next line
+           in the script. */
+	next_scriptline();
+	next_scriptstate();
+      }
+    }
+
+    if(hs->state != HTTP_FUNC && !uip_poll()) {
+      /* Send a piece of data, but not more than the MSS of the
+	 connection. */
+      uip_send(hs->dataptr, hs->count);
+    }
+
+    /* Finally, return to uIP. Our outgoing packet will soon be on its
+       way... */
+    return;
+
+  default:
+    /* Should never happen. */
+    uip_abort();
+    break;
+  }  
+}
+/*-----------------------------------------------------------------------------------*/
+/* next_scriptline():
+ *
+ * Reads the script until it finds a newline. */
+static void
+next_scriptline(void)
+{
+  /* Loop until we find a newline character. */
+  do {
+    ++(hs->script);
+  } while(hs->script[0] != ISO_nl);
+
+  /* Eat up the newline as well. */
+  ++(hs->script);
+}
+/*-----------------------------------------------------------------------------------*/
+/* next_sciptstate:
+ *
+ * Reads one line of script and decides what to do next.
+ */
+static void
+next_scriptstate(void)
+{
+  struct fs_file fsfile;
+  u8_t i;
+
+ again:
+  switch(hs->script[0]) {
+  case ISO_t:
+    /* Send a text string. */
+    hs->state = HTTP_TEXT;
+    hs->dataptr = &hs->script[2];
+
+    /* Calculate length of string. */
+    for(i = 0; hs->dataptr[i] != ISO_nl; ++i);
+    hs->count = i;    
+    break;
+  case ISO_c:
+    /* Call a function. */
+    hs->state = HTTP_FUNC;
+    hs->dataptr = NULL;
+    hs->count = 0;
+    cgitab[hs->script[2] - ISO_a](0);
+    break;
+  case ISO_i:   
+    /* Include a file. */
+    hs->state = HTTP_FILE;
+    if(!fs_open(&hs->script[2], &fsfile)) {
+      uip_abort();
+    }
+    hs->dataptr = fsfile.data;
+    hs->count = fsfile.len;
+    break;
+  case ISO_hash:
+    /* Comment line. */
+    next_scriptline();
+    goto again;
+    break;
+  case ISO_period:
+    /* End of script. */
+    hs->state = HTTP_END;
+    uip_close();
+    break;
+  default:
+    uip_abort();
+    break;
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h
new file mode 100644
index 000000000..34d6bb35f
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h
@@ -0,0 +1,77 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $
+ *
+ */
+
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+void httpd_init(void);
+void httpd_appcall(void);
+
+/* UIP_APPCALL: the name of the application function. This function
+   must return void and take no arguments (i.e., C type "void
+   appfunc(void)"). */
+#ifndef UIP_APPCALL
+#define UIP_APPCALL     httpd_appcall
+#endif
+
+struct httpd_state {
+  u8_t state; 
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+
+
+/* UIP_APPSTATE_SIZE: The size of the application-specific state
+   stored in the uip_conn structure. */
+#ifndef UIP_APPSTATE_SIZE
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+#endif
+
+#define FS_STATISTICS 1
+
+extern struct httpd_state *hs;
+
+#endif /* __HTTPD_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/main_led b/Demo/uIP_Demo_Rowley_ARM7/uip/main_led
new file mode 100644
index 000000000..8fe01ea6d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/main_led
@@ -0,0 +1,67 @@
+// Copyright (c) 2001-2004 Rowley Associates Limited.
+//
+// This file may be distributed under the terms of the License Agreement
+// provided with this software.
+//
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//                      Olimex LPC-P1  LED Example
+//
+// Description
+// -----------
+// This example demonstrates writing to the programmable peripheral interface.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include 
+
+#define LED_RED (1<<8)
+#define LED_GREEN (1<<10)
+#define LED_YELLOW (1<<11)
+
+#define LED1 LED_YELLOW
+
+static void
+ledInit()
+{
+  IODIR |= LED1;
+  IOSET = LED1;
+}
+
+static void
+ledOn(void)
+{
+  IOCLR = LED1;
+}
+
+static void
+ledOff(void)
+{
+  IOSET = LED1;
+}
+
+void
+delay(int d)
+{     
+  for(; d; --d);
+}
+ 
+int
+main(void)
+{
+  MAMCR = 2;
+  ledInit();
+  while (1)
+    {
+      ledOn();
+      delay(100000);
+      ledOff();
+      delay(100000);
+    }
+  return 0;
+}
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata b/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata
new file mode 100644
index 000000000..f5f75f174
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata
@@ -0,0 +1,93 @@
+#!/usr/bin/perl
+
+open(OUTPUT, "> fsdata.c");
+
+chdir("fs");
+open(FILES, "find . -type f |");
+
+while($file = ) {
+
+    # Do not include files in CVS directories nor backup files.
+    if($file =~ /(CVS|~)/) {
+    	next;
+    }
+    
+    chop($file);
+    
+    open(HEADER, "> /tmp/header") || die $!;
+    if($file =~ /404.html/) {
+      print(HEADER "HTTP/1.0 404 File not found\r\n");
+    } else {
+      print(HEADER "HTTP/1.0 200 OK\r\n");
+    }
+    print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n");
+    if($file =~ /\.html$/) {
+	print(HEADER "Content-type: text/html\r\n");
+    } elsif($file =~ /\.gif$/) {
+	print(HEADER "Content-type: image/gif\r\n");
+    } elsif($file =~ /\.png$/) {
+	print(HEADER "Content-type: image/png\r\n");
+    } elsif($file =~ /\.jpg$/) {
+	print(HEADER "Content-type: image/jpeg\r\n");
+    } else {
+	print(HEADER "Content-type: text/plain\r\n");
+    }
+    print(HEADER "\r\n");
+    close(HEADER);
+
+    unless($file =~ /\.plain$/ || $file =~ /cgi/) {
+	system("cat /tmp/header $file > /tmp/file");
+    } else {
+	system("cp $file /tmp/file");
+    }
+    
+    open(FILE, "/tmp/file");
+    unlink("/tmp/file");
+    unlink("/tmp/header");
+
+    $file =~ s/\.//;
+    $fvar = $file;
+    $fvar =~ s-/-_-g;
+    $fvar =~ s-\.-_-g;
+    print(OUTPUT "static const char data".$fvar."[] = {\n");
+    print(OUTPUT "\t/* $file */\n\t");
+    for($j = 0; $j < length($file); $j++) {
+	printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));
+    }
+    printf(OUTPUT "0,\n");
+    
+    
+    $i = 0;        
+    while(read(FILE, $data, 1)) {
+        if($i == 0) {
+            print(OUTPUT "\t");
+        }
+        printf(OUTPUT "%#02x, ", unpack("C", $data));
+        $i++;
+        if($i == 10) {
+            print(OUTPUT "\n");
+            $i = 0;
+        }
+    }
+    print(OUTPUT "};\n\n");
+    close(FILE);
+    push(@fvars, $fvar);
+    push(@files, $file);
+}
+
+for($i = 0; $i < @fvars; $i++) {
+    $file = $files[$i];
+    $fvar = $fvars[$i];
+
+    if($i == 0) {
+        $prevfile = "NULL";
+    } else {
+        $prevfile = "file" . $fvars[$i - 1];
+    }
+    print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");
+}
+
+print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n");
+print(OUTPUT "#define FS_NUMFILES $i");
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c
new file mode 100644
index 000000000..56e663446
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c
@@ -0,0 +1,152 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \file
+ * Memory block allocation routines.
+ * \author Adam Dunkels 
+ *
+ * The memory block allocation routines provide a simple yet powerful
+ * set of functions for managing a set of memory blocks of fixed
+ * size. A set of memory blocks is statically declared with the
+ * MEMB() macro. Memory blocks are allocated from the declared
+ * memory by the memb_alloc() function, and are deallocated with the
+ * memb_free() function.
+ *
+ * \note Because of namespace clashes only one MEMB() can be
+ * declared per C module, and the name scope of a MEMB() memory
+ * block is local to each C module.
+ *
+ * The following example shows how to declare and use a memory block
+ * called "cmem" which has 8 chunks of memory with each memory chunk
+ * being 20 bytes large.
+ *
+ \code
+ MEMB(cmem, 20, 8);
+
+ int main(int argc, char *argv[]) {
+    char *ptr;
+    
+    memb_init(&cmem);
+
+    ptr = memb_alloc(&cmem);
+
+    if(ptr != NULL) {
+       do_something(ptr);
+    } else {
+       printf("Could not allocate memory.\n");
+    }
+
+    if(memb_free(ptr) == 0) {
+       printf("Deallocation succeeded.\n");
+    }
+ }
+ \endcode
+ * 
+ */
+
+#include 
+
+#include "memb.h"
+
+/*------------------------------------------------------------------------------*/
+/**
+ * Initialize a memory block that was declared with MEMB().
+ *
+ * \param m A memory block previosly declared with MEMB().
+ */
+/*------------------------------------------------------------------------------*/
+void
+memb_init(struct memb_blocks *m)
+{
+  memset(m->mem, (m->size + 1) * m->num, 0);
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Allocate a memory block from a block of memory declared with MEMB().
+ *
+ * \param m A memory block previosly declared with MEMB().
+ */
+/*------------------------------------------------------------------------------*/
+char *
+memb_alloc(struct memb_blocks *m)
+{
+  int i;
+  char *ptr;
+
+  ptr = m->mem;
+  for(i = 0; i < m->num; ++i) {
+    if(*ptr == 0) {
+      /* If this block was unused, we increase the reference count to
+	 indicate that it now is used and return a pointer to the
+	 first byte following the reference counter. */
+      ++*ptr;
+      return ptr + 1;
+    }
+    ptr += m->size + 1;
+  }
+
+  /* No free block was found, so we return NULL to indicate failure to
+     allocate block. */
+  return NULL;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Deallocate a memory block from a memory block previously declared
+ * with MEMB().
+ *
+ * \param m m A memory block previosly declared with MEMB().
+ *
+ * \param ptr A pointer to the memory block that is to be deallocated.
+ *
+ * \return The new reference count for the memory block (should be 0
+ * if successfully deallocated) or -1 if the pointer "ptr" did not
+ * point to a legal memory block.
+ */
+/*------------------------------------------------------------------------------*/
+char
+memb_free(struct memb_blocks *m, char *ptr)
+{
+  int i;
+  char *ptr2;
+
+  /* Walk through the list of blocks and try to find the block to
+     which the pointer "ptr" points to. */
+  ptr2 = m->mem;
+  for(i = 0; i < m->num; ++i) {
+    
+    if(ptr2 == ptr - 1) {
+      /* We've found to block to which "ptr" points so we decrease the
+	 reference count and return the new value of it. */      
+      return --*ptr2;
+    }
+    ptr2 += m->size + 1;
+  }
+  return -1;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Increase the reference count for a memory chunk.
+ *
+ * \note No sanity checks are currently made.
+ *
+ * \param m m A memory block previosly declared with MEMB().
+ *
+ * \param ptr A pointer to the memory chunk for which the reference
+ * count should be increased.
+ *
+ * \return The new reference count.
+ */
+/*------------------------------------------------------------------------------*/
+char
+memb_ref(struct memb_blocks *m, char *ptr)
+{
+  return ++*(ptr - 1);
+}
+/*------------------------------------------------------------------------------*/
+
+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h
new file mode 100644
index 000000000..505846f4d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h
@@ -0,0 +1,43 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \file
+ * Memory block allocation routines.
+ * \author Adam Dunkels 
+ *
+ */
+
+#ifndef __MEMB_H__
+#define __MEMB_H__
+
+/**
+ * Declare a memory block.
+ *
+ * \param name The name of the memory block (later used with
+ * memb_init(), memb_alloc() and memb_free()).
+ *
+ * \param size The size of each memory chunk, in bytes.
+ *
+ * \param num The total number of memory chunks in the block.
+ *
+ */
+#define MEMB(name, size, num) \
+        static char memb_mem[(size + 1) * num]; \
+        static struct memb_blocks name = {size, num, memb_mem}
+
+struct memb_blocks {
+  unsigned short size;
+  unsigned short num;
+  char *mem;
+};
+
+void  memb_init(struct memb_blocks *m);
+char *memb_alloc(struct memb_blocks *m);
+char  memb_ref(struct memb_blocks *m, char *ptr);
+char  memb_free(struct memb_blocks *m, char *ptr);
+
+
+#endif /* __MEMB_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c
new file mode 100644
index 000000000..fc968c82e
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c
@@ -0,0 +1,202 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup slip Serial Line IP (SLIP) protocol
+ * @{
+ *
+ * The SLIP protocol is a very simple way to transmit IP packets over
+ * a serial line. It does not provide any framing or error control,
+ * and is therefore not very widely used today.
+ *
+ * This SLIP implementation requires two functions for accessing the
+ * serial device: slipdev_char_poll() and slipdev_char_put(). These
+ * must be implemented specifically for the system on which the SLIP
+ * protocol is to be run.
+ */
+
+/**
+ * \file
+ * SLIP protocol implementation
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $
+ *
+ */
+
+/*
+ * This is a generic implementation of the SLIP protocol over an RS232
+ * (serial) device. 
+ *
+ * Huge thanks to Ullrich von Bassewitz  of cc65 fame for
+ * and endless supply of bugfixes, insightsful comments and
+ * suggestions, and improvements to this code!
+ */
+
+#include "uip.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+static u8_t slip_buf[UIP_BUFSIZE];
+
+static u16_t len, tmplen;
+static u8_t lastc;
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Send the packet in the uip_buf and uip_appdata buffers using the
+ * SLIP protocol.
+ *
+ * The first 40 bytes of the packet (the IP and TCP headers) are read
+ * from the uip_buf buffer, and the following bytes (the application
+ * data) are read from the uip_appdata buffer.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+slipdev_send(void)
+{
+  u16_t i;
+  u8_t *ptr;
+  u8_t c;
+
+  slipdev_char_put(SLIP_END);
+
+  ptr = uip_buf;
+  for(i = 0; i < uip_len; ++i) {
+    if(i == 40) {
+      ptr = (u8_t *)uip_appdata;
+    }
+    c = *ptr++;
+    switch(c) {
+    case SLIP_END:
+      slipdev_char_put(SLIP_ESC);
+      slipdev_char_put(SLIP_ESC_END);
+      break;
+    case SLIP_ESC:
+      slipdev_char_put(SLIP_ESC);
+      slipdev_char_put(SLIP_ESC_ESC);
+      break;
+    default:
+      slipdev_char_put(c);
+      break;
+    }
+  }
+  slipdev_char_put(SLIP_END);
+}
+/*-----------------------------------------------------------------------------------*/
+/** 
+ * Poll the SLIP device for an available packet.
+ *
+ * This function will poll the SLIP device to see if a packet is
+ * available. It uses a buffer in which all avaliable bytes from the
+ * RS232 interface are read into. When a full packet has been read
+ * into the buffer, the packet is copied into the uip_buf buffer and
+ * the length of the packet is returned.
+ *
+ * \return The length of the packet placed in the uip_buf buffer, or
+ * zero if no packet is available.
+ */
+/*-----------------------------------------------------------------------------------*/
+u16_t
+slipdev_poll(void)
+{
+  u8_t c;
+  
+  while(slipdev_char_poll(c)) {
+    switch(c) {
+    case SLIP_ESC:
+      lastc = c;
+      break;
+      
+    case SLIP_END:
+      lastc = c;
+      /* End marker found, we copy our input buffer to the uip_buf
+	 buffer and return the size of the packet we copied. */
+      memcpy(uip_buf, slip_buf, len);
+      tmplen = len;
+      len = 0;
+      return tmplen;
+      
+    default:     
+      if(lastc == SLIP_ESC) {
+	lastc = c;
+	/* Previous read byte was an escape byte, so this byte will be
+	   interpreted differently from others. */
+	switch(c) {
+	case SLIP_ESC_END:
+	  c = SLIP_END;
+	  break;
+	case SLIP_ESC_ESC:
+	  c = SLIP_ESC;
+	  break;
+	}
+      } else {
+	lastc = c;
+      }
+      
+      slip_buf[len] = c;
+      ++len;
+      
+      if(len > UIP_BUFSIZE) {
+	len = 0;
+      }
+    
+      break;
+    }
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the SLIP module.
+ *
+ * This function does not initialize the underlying RS232 device, but
+ * only the SLIP part.
+ */ 
+/*-----------------------------------------------------------------------------------*/
+void
+slipdev_init(void)
+{
+  lastc = len = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h
new file mode 100644
index 000000000..3fbfe2d2d
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h
@@ -0,0 +1,88 @@
+/**
+ * \addtogroup slip
+ * @{
+ */
+
+/**
+ * \file
+ * SLIP header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $
+ *
+ */
+
+#ifndef __SLIPDEV_H__
+#define __SLIPDEV_H__
+
+#include "uip.h"
+
+/**
+ * Put a character on the serial device.
+ *
+ * This function is used by the SLIP implementation to put a character
+ * on the serial device. It must be implemented specifically for the
+ * system on which the SLIP implementation is to be run.
+ *
+ * \param c The character to be put on the serial device.
+ */
+void slipdev_char_put(u8_t c);
+
+/**
+ * Poll the serial device for a character.
+ *
+ * This function is used by the SLIP implementation to poll the serial
+ * device for a character. It must be implemented specifically for the
+ * system on which the SLIP implementation is to be run.
+ *
+ * The function should return immediately regardless if a character is
+ * available or not. If a character is available it should be placed
+ * at the memory location pointed to by the pointer supplied by the
+ * arguement c.
+ *
+ * \param c A pointer to a byte that is filled in by the function with
+ * the received character, if available.
+ *
+ * \retval 0 If no character is available.
+ * \retval Non-zero If a character is available.
+ */
+u8_t slipdev_char_poll(u8_t *c);
+
+void slipdev_init(void);
+void slipdev_send(void);
+u16_t slipdev_poll(void);
+
+#endif /* __SLIPDEV_H__ */
+
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c
new file mode 100644
index 000000000..0d23fc4d9
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ *
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ *
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef linux
+#include 
+#include 
+#include 
+#define DEVTAP "/dev/net/tun"
+#else  /* linux */
+#define DEVTAP "/dev/tap0"
+#endif /* linux */
+
+#include "uip.h"
+
+static int fd;
+
+static unsigned long lasttime;
+static struct timezone tz;
+
+/*-----------------------------------------------------------------------------------*/
+void
+tapdev_init(void)
+{
+  char buf[1024];
+  
+  fd = open(DEVTAP, O_RDWR);
+  if(fd == -1) {
+    perror("tapdev: tapdev_init: open");
+    exit(1);
+  }
+
+#ifdef linux
+  {
+    struct ifreq ifr;
+    memset(&ifr, 0, sizeof(ifr));
+    ifr.ifr_flags = IFF_TAP|IFF_NO_PI;
+    if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) {
+      perror(buf);
+      exit(1);
+    }
+  }
+#endif /* Linux */
+
+  snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d",
+	   UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3);
+  system(buf);
+
+  lasttime = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+unsigned int
+tapdev_read(void)
+{
+  fd_set fdset;
+  struct timeval tv, now;
+  int ret;
+  
+  if(lasttime >= 500000) {
+    lasttime = 0;
+    return 0;
+  }
+  
+  tv.tv_sec = 0;
+  tv.tv_usec = 500000 - lasttime;
+
+
+  FD_ZERO(&fdset);
+  FD_SET(fd, &fdset);
+
+  gettimeofday(&now, &tz);  
+  ret = select(fd + 1, &fdset, NULL, NULL, &tv);
+  if(ret == 0) {
+    lasttime = 0;    
+    return 0;
+  } 
+  ret = read(fd, uip_buf, UIP_BUFSIZE);  
+  if(ret == -1) {
+    perror("tap_dev: tapdev_read: read");
+  }
+  gettimeofday(&tv, &tz);
+  lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec);
+
+  return ret;
+}
+/*-----------------------------------------------------------------------------------*/
+void
+tapdev_send(void)
+{
+  int ret;
+  struct iovec iov[2];
+  
+#ifdef linux
+  {
+    char tmpbuf[UIP_BUFSIZE];
+    int i;
+
+    for(i = 0; i < 40 + UIP_LLH_LEN; i++) {
+      tmpbuf[i] = uip_buf[i];
+    }
+    
+    for(; i < uip_len; i++) {
+      tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN];
+    }
+    
+    ret = write(fd, tmpbuf, uip_len);
+  }  
+#else 
+
+  if(uip_len < 40 + UIP_LLH_LEN) {
+    ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN);
+  } else {
+    iov[0].iov_base = uip_buf;
+    iov[0].iov_len = 40 + UIP_LLH_LEN;
+    iov[1].iov_base = (char *)uip_appdata;
+    iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN);  
+    
+    ret = writev(fd, iov, 2);
+  }
+#endif
+  if(ret == -1) {
+    perror("tap_dev: tapdev_send: writev");
+    exit(1);
+  }
+}  
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h
new file mode 100644
index 000000000..66f1a4a71
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $
+ *
+ */
+
+#ifndef __TAPDEV_H__
+#define __TAPDEV_H__
+
+void tapdev_init(void);
+unsigned int tapdev_read(void);
+void tapdev_send(void);
+
+#endif /* __TAPDEV_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c
new file mode 100644
index 000000000..7dff714ca
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c
@@ -0,0 +1,181 @@
+/**
+ * \addtogroup telnetd
+ * @{
+ */
+
+/**
+ * \file
+ * An example telnet server shell
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the Contiki desktop OS.
+ *
+ * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "telnetd.h"
+#include 
+
+struct ptentry {
+  char c;
+  void (* pfunc)(struct telnetd_state *s, char *str);
+};
+
+/*-----------------------------------------------------------------------------------*/
+static void
+parse(struct telnetd_state *s, register char *str, struct ptentry *t)
+{
+  register struct ptentry *p;
+  char *sstr;
+
+  sstr = str;
+  
+  /* Loop over the parse table entries in t in order to find one that
+     matches the first character in str. */
+  for(p = t; p->c != 0; ++p) {
+    if(*str == p->c) {
+      /* Skip rest of the characters up to the first space. */
+      while(*str != ' ') {
+	++str;
+      }
+
+      /* Skip all spaces.*/
+      while(*str == ' ') {
+	++str;
+      }
+
+      /* Call parse table entry function and return. */
+      p->pfunc(s, str);
+      return;
+    }
+  }
+
+  /* Did not find matching entry in parse table. We just call the
+     default handler supplied by the caller and return. */
+  p->pfunc(s, str);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+exitt(struct telnetd_state *s, char *str)
+{
+  telnetd_close(s);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+inttostr(register char *str, unsigned int i)
+{
+  str[0] = '0' + i / 100;
+  if(str[0] == '0') {
+    str[0] = ' ';
+  }
+  str[1] = '0' + (i / 10) % 10;
+  if(str[1] == '0') {
+    str[1] = ' ';
+  }
+  str[2] = '0' + i % 10;
+  str[3] = ' ';
+  str[4] = 0;
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+stats(struct telnetd_state *s, char *strr)
+{
+  char str[10];
+
+  inttostr(str, uip_stat.ip.recv);
+  telnetd_output(s, "IP packets received ", str);
+  inttostr(str, uip_stat.ip.sent);
+  telnetd_output(s, "IP packets sent ", str);
+  inttostr(str, uip_stat.ip.drop);
+  telnetd_output(s, "IP packets dropped ", str);
+
+  inttostr(str, uip_stat.icmp.recv);
+  telnetd_output(s, "ICMP packets received ", str);
+  inttostr(str, uip_stat.icmp.sent);
+  telnetd_output(s, "ICMP packets sent ", str);
+  inttostr(str, uip_stat.icmp.drop);
+  telnetd_output(s, "ICMP packets dropped ", str);
+
+  inttostr(str, uip_stat.tcp.recv);
+  telnetd_output(s, "TCP packets received ", str);
+  inttostr(str, uip_stat.tcp.sent);
+  telnetd_output(s, "TCP packets sent ", str);
+  inttostr(str, uip_stat.tcp.drop);
+  telnetd_output(s, "TCP packets dropped ", str);
+  inttostr(str, uip_stat.tcp.rexmit);
+  telnetd_output(s, "TCP packets retransmitted ", str);
+  inttostr(str, uip_stat.tcp.synrst);
+  telnetd_output(s, "TCP connection attempts ", str);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+help(struct telnetd_state *s, char *str)
+{
+  telnetd_output(s, "Available commands:", "");
+  telnetd_output(s, "stats - show uIP statistics", "");
+  telnetd_output(s, "exit  - exit shell", "");  
+  telnetd_output(s, "?     - show this help", "");        
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+none(struct telnetd_state *s, char *str)
+{
+  if(strlen(str) > 0) {
+    telnetd_output(s, "Unknown command", "");
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static struct ptentry configparsetab[] =
+  {{'s', stats},
+   {'e', exitt},
+   {'?', help},
+
+   /* Default action */
+   {0, none}};
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_connected(struct telnetd_state *s)
+{
+  telnetd_output(s, "uIP command shell", "");
+  telnetd_output(s, "Type '?' for help", "");  
+  telnetd_prompt(s, "uIP-0.9> "); 
+}
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_input(struct telnetd_state *s, char *cmd)
+{
+  parse(s, cmd, configparsetab);
+  telnetd_prompt(s, "uIP-0.9> "); 
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c
new file mode 100644
index 000000000..dba522271
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c
@@ -0,0 +1,392 @@
+/**
+ * \addtogroup exampleapps
+ * @{
+ */
+
+/**
+ * \defgroup telnetd Telnet server
+ * @{
+ *
+ * The uIP telnet server provides a command based interface to uIP. It
+ * allows using the "telnet" application to access uIP, and implements
+ * the required telnet option negotiation.
+ *
+ * The code is structured in a way which makes it possible to add
+ * commands without having to rewrite the main telnet code. The main
+ * telnet code calls two callback functions, telnetd_connected() and
+ * telnetd_input(), when a telnet connection has been established and
+ * when a line of text arrives on a telnet connection. These two
+ * functions can be implemented in a way which suits the particular
+ * application or environment in which the uIP system is intended to
+ * be run.
+ *
+ * The uIP distribution contains an example telnet shell
+ * implementation that provides a basic set of commands.
+ */
+
+/**
+ * \file
+ * Implementation of the Telnet server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "memb.h"
+#include "telnetd.h"
+#include 
+
+#define ISO_nl       0x0a
+#define ISO_cr       0x0d
+
+MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES);
+
+static u8_t i;
+
+#define STATE_NORMAL 0
+#define STATE_IAC    1
+#define STATE_WILL   2
+#define STATE_WONT   3
+#define STATE_DO     4  
+#define STATE_DONT   5
+#define STATE_CLOSE  6
+
+#define TELNET_IAC   255
+#define TELNET_WILL  251
+#define TELNET_WONT  252
+#define TELNET_DO    253
+#define TELNET_DONT  254
+/*-----------------------------------------------------------------------------------*/
+static char *
+alloc_line(void)
+{  
+  return memb_alloc(&linemem);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+dealloc_line(char *line)
+{
+  memb_free(&linemem, line);
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+sendline(struct telnetd_state *s, char *line)
+{
+  static unsigned int i;
+  for(i = 0; i < TELNETD_NUMLINES; ++i) {
+    if(s->lines[i] == NULL) {
+      s->lines[i] = line;
+      break;
+    }
+  }
+  if(i == TELNETD_NUMLINES) {
+    dealloc_line(line);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Close a telnet session.
+ *
+ * This function can be called from a telnet command in order to close
+ * the connection.
+ *
+ * \param s The connection which is to be closed.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_close(struct telnetd_state *s)
+{
+  s->state = STATE_CLOSE;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Print a prompt on a telnet connection.
+ *
+ * This function can be called by the telnet command shell in order to
+ * print out a command prompt.
+ *
+ * \param s A telnet connection.
+ *
+ * \param str The command prompt.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_prompt(struct telnetd_state *s, char *str)
+{
+  char *line;
+  line = alloc_line();
+  if(line != NULL) {
+    strncpy(line, str, TELNETD_LINELEN);
+    sendline(s, line);
+  }         
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Print out a string on a telnet connection.
+ *
+ * This function can be called from a telnet command parser in order
+ * to print out a string of text on the connection. The two strings
+ * given as arguments to the function will be concatenated, a carrige
+ * return and a new line character will be added, and the line is
+ * sent.
+ *
+ * \param s The telnet connection.
+ *
+ * \param str1 The first string.
+ *
+ * \param str2 The second string.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_output(struct telnetd_state *s, char *str1, char *str2)
+{
+  static unsigned len;
+  char *line;
+  
+  line = alloc_line();
+  if(line != NULL) {
+    len = strlen(str1);
+    strncpy(line, str1, TELNETD_LINELEN);
+    if(len < TELNETD_LINELEN) {
+      strncpy(line + len, str2, TELNETD_LINELEN - len);
+    }
+    len = strlen(line);
+    if(len < TELNETD_LINELEN - 2) {
+      line[len] = ISO_cr;
+      line[len+1] = ISO_nl;
+      line[len+2] = 0;
+    }
+    sendline(s, line);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the telnet server.
+ *
+ * This function will perform the necessary initializations and start
+ * listening on TCP port 23.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_init(void)
+{
+  memb_init(&linemem);
+  uip_listen(HTONS(23));
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+acked(struct telnetd_state *s)     
+{
+  dealloc_line(s->lines[0]);
+  for(i = 1; i < TELNETD_NUMLINES; ++i) {
+    s->lines[i - 1] = s->lines[i];
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+senddata(struct telnetd_state *s)    
+{
+  if(s->lines[0] != NULL) {
+    uip_send(s->lines[0], strlen(s->lines[0]));
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+getchar(struct telnetd_state *s, u8_t c)
+{
+  if(c == ISO_cr) {
+    return;
+  }
+  
+  s->buf[(int)s->bufptr] = c;  
+  if(s->buf[(int)s->bufptr] == ISO_nl ||
+     s->bufptr == sizeof(s->buf) - 1) {    
+    if(s->bufptr > 0) {
+      s->buf[(int)s->bufptr] = 0;
+    }
+    telnetd_input(s, s->buf);
+    s->bufptr = 0;
+  } else {
+    ++s->bufptr;
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+sendopt(struct telnetd_state *s, u8_t option, u8_t value)
+{
+  char *line;
+  line = alloc_line();
+  if(line != NULL) {
+    line[0] = TELNET_IAC;
+    line[1] = option;
+    line[2] = value;
+    line[3] = 0;
+    sendline(s, line);
+  }       
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+newdata(struct telnetd_state *s)
+{
+  u16_t len;
+  u8_t c;
+    
+  
+  len = uip_datalen();
+  
+  while(len > 0 && s->bufptr < sizeof(s->buf)) {
+    c = *uip_appdata;
+    ++uip_appdata;
+    --len;
+    switch(s->state) {
+    case STATE_IAC:
+      if(c == TELNET_IAC) {
+	getchar(s, c);
+	s->state = STATE_NORMAL;
+      } else {
+	switch(c) {
+	case TELNET_WILL:
+	  s->state = STATE_WILL;
+	  break;
+	case TELNET_WONT:
+	  s->state = STATE_WONT;
+	  break;
+	case TELNET_DO:
+	  s->state = STATE_DO;
+	  break;
+	case TELNET_DONT:
+	  s->state = STATE_DONT;
+	  break;
+	default:
+	  s->state = STATE_NORMAL;
+	  break;
+	}
+      }
+      break;
+    case STATE_WILL:
+      /* Reply with a DONT */
+      sendopt(s, TELNET_DONT, c);
+      s->state = STATE_NORMAL;
+      break;
+      
+    case STATE_WONT:
+      /* Reply with a DONT */
+      sendopt(s, TELNET_DONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_DO:
+      /* Reply with a WONT */
+      sendopt(s, TELNET_WONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_DONT:
+      /* Reply with a WONT */
+      sendopt(s, TELNET_WONT, c);
+      s->state = STATE_NORMAL;
+      break;
+    case STATE_NORMAL:
+      if(c == TELNET_IAC) {
+	s->state = STATE_IAC;
+      } else {
+	getchar(s, c);
+      }      
+      break;
+    } 
+
+    
+  }  
+  
+}
+/*-----------------------------------------------------------------------------------*/
+void
+telnetd_app(void)
+{
+  struct telnetd_state *s;
+
+  s = (struct telnetd_state *)uip_conn->appstate;
+  
+  if(uip_connected()) {
+
+    for(i = 0; i < TELNETD_NUMLINES; ++i) {
+      s->lines[i] = NULL;
+    }
+    s->bufptr = 0;
+    s->state = STATE_NORMAL;
+
+    telnetd_connected(s);
+    senddata(s);
+    return;
+  }
+
+  if(s->state == STATE_CLOSE) {
+    s->state = STATE_NORMAL;
+    uip_close();
+    return;
+  }
+  
+  if(uip_closed()) {
+    telnetd_output(s, "Connection closed", "");
+  }
+
+  
+  if(uip_aborted()) {
+    telnetd_output(s, "Connection reset", "");
+  }
+  
+  if(uip_timedout()) {
+    telnetd_output(s, "Connection timed out", "");
+  }
+  
+  if(uip_acked()) {
+    acked(s);
+  }
+  
+  if(uip_newdata()) {
+    newdata(s);
+  }
+  
+  if(uip_rexmit() ||
+     uip_newdata() ||
+     uip_acked()) {
+    senddata(s);
+  } else if(uip_poll()) {    
+    senddata(s);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h
new file mode 100644
index 000000000..254e44ff1
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h
@@ -0,0 +1,114 @@
+/**
+ * \addtogroup telnetd
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the telnet server.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2002, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+#ifndef __TELNETD_H__
+#define __TELNETD_H__
+
+#include "uip.h"
+
+/**
+ * The maximum length of a telnet line.
+ *
+ * \hideinitializer
+ */
+#define TELNETD_LINELEN 36
+
+/**
+ * The number of output lines being buffered for all telnet
+ * connections.
+ *
+ * \hideinitializer
+ */
+#define TELNETD_NUMLINES 2
+
+/**
+ * A telnet connection structure.
+ */
+struct telnetd_state {
+  char *lines[TELNETD_NUMLINES];
+  char buf[TELNETD_LINELEN];
+  char bufptr;
+  u8_t state;
+};
+
+
+/**
+ * Callback function that is called when a telnet connection has been
+ * established.
+ *
+ * \param s The telnet connection. 
+ */
+void telnetd_connected(struct telnetd_state *s);
+
+/**
+ * Callback function that is called when a line of text has arrived on
+ * a telnet connection.
+ *
+ * \param s The telnet connection.
+ *
+ * \param cmd The line of text.
+ */
+void telnetd_input(struct telnetd_state *s, char *cmd);
+
+
+void telnetd_close(struct telnetd_state *s);
+void telnetd_output(struct telnetd_state *s, char *s1, char *s2);
+void telnetd_prompt(struct telnetd_state *s, char *str);
+
+void telnetd_app(void);
+
+#ifndef UIP_APPCALL
+#define UIP_APPCALL     telnetd_app
+#endif
+
+#ifndef UIP_APPSTATE_SIZE
+#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state))
+#endif
+
+void telnetd_init(void);
+
+
+#endif /* __TELNET_H__ */
+
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c
new file mode 100644
index 000000000..85d2f469e
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $
+ *
+ */
+
+
+#include    /* For system(). */
+#include     /* For printf(). */
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef HTONS
+
+#include "cs8900a.h"
+#include "uip.h"
+#include "uip_arp.h"
+#include "tapdev.h"
+#include "httpd.h"
+
+static const struct uip_eth_addr ethaddr = {{0x00,0x00,0xe2,0x58,0xb6,0x6b}};
+
+#define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+#define uipSHORT_DELAY		( ( portTickType ) 2 / portTICK_RATE_MS )
+
+#ifndef NULL
+#define NULL (void *)0
+#endif /* NULL */
+
+static volatile portTickType start, current;
+
+#define RT_CLOCK_SECOND ( configTICK_RATE_HZ / 2 )
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * \internal
+ * A real-time clock.
+ *
+ * This example main() function uses polling of a real-time clock in
+ * order to know when the periodic processing should be
+ * performed. This is implemented using this function - rt_ticks(). In
+ * this example unix implementation, it simply calls the unix function
+ * gettimeofday() which returns the current wall clock time.
+ *
+ * For a micro-controller, a simple way to implement this function is
+ * by having a counter that is incremented by a timer interrupt and
+ * read by this function.
+ * 
+ * The macro RT_CLOCK_SECOND should be defined as the approximate
+ * number of ticks that are elapsed during one second. 
+ */
+#define rt_ticks xTaskGetTickCount
+
+/*-----------------------------------------------------------------------------------*/
+void vuIP_TASK( void *pvParameters )
+{
+u8_t i, arptimer;
+u16_t addr[2];
+int z = 3;
+
+	/* Initialize the uIP TCP/IP stack. */
+	uip_init();
+	uip_arp_init();
+
+	/* Initialize the device driver. */ 
+	cs8900a_init();
+
+	/* Initialize the HTTP server. */
+	httpd_init();
+
+	start = rt_ticks();
+	arptimer = 0;
+  
+	while(1) 
+	{
+		/* Let the network device driver read an entire IP packet
+		into the uip_buf. If it returns > 0, there is a packet in the
+		uip_buf buffer. */
+		uip_len = cs8900a_poll();
+
+		if(uip_len > 0) 
+		{
+			/* A packet is present in the packet buffer. We call the
+			appropriate ARP functions depending on what kind of packet we
+			have received. If the packet is an IP packet, we should call
+			uip_input() as well. */
+			if(BUF->type == htons(UIP_ETHTYPE_IP)) 
+			{
+				uip_arp_ipin();
+				uip_input();
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */
+				if(uip_len > 0) 
+				{
+					uip_arp_out();
+					cs8900a_send();
+				}
+			} 
+			else if(BUF->type == htons(UIP_ETHTYPE_ARP)) 
+			{
+				uip_arp_arpin();
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */	
+				if(uip_len > 0) 
+				{	
+					cs8900a_send();
+				}
+			}
+		} 
+		else 
+		{
+			/* The poll function returned 0, so no packet was
+			received. Instead we check if there is time that we do the
+			periodic processing. */
+			current = rt_ticks();
+
+			if((u16_t)(current - start) >= (u16_t)RT_CLOCK_SECOND / 2) 
+			{
+				start = current;
+
+				for(i = 0; i < UIP_CONNS; i++) 
+				{
+					uip_periodic(i);
+
+					/* If the above function invocation resulted in data that
+					should be sent out on the network, the global variable
+					uip_len is set to a value > 0. */
+					
+					if(uip_len > 0) 
+					{
+						uip_arp_out();
+						cs8900a_send();
+					}
+				}
+
+				#if UIP_UDP
+					for(i = 0; i < UIP_UDP_CONNS; i++) 
+					{
+						uip_udp_periodic(i);
+
+						/* If the above function invocation resulted in data that
+						should be sent out on the network, the global variable
+						uip_len is set to a value > 0. */
+
+						if(uip_len > 0) 
+						{
+							uip_arp_out();
+							tapdev_send();
+						}
+					}
+				#endif /* UIP_UDP */
+
+				/* Call the ARP timer function every 10 seconds. */
+				if(++arptimer == 20) 
+				{	
+					uip_arp_timer();
+					arptimer = 0;
+				}
+			}
+			else
+			{
+				vTaskDelay( uipSHORT_DELAY );
+		}   }
+	}
+}
+/*-----------------------------------------------------------------------------------*/
+
+
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c
new file mode 100644
index 000000000..3ef7e8d6c
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c
@@ -0,0 +1,1509 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $
+ *
+ */
+
+/*
+This is a small implementation of the IP and TCP protocols (as well as
+some basic ICMP stuff). The implementation couples the IP, TCP and the
+application layers very tightly. To keep the size of the compiled code
+down, this code also features heavy usage of the goto statement.
+
+The principle is that we have a small buffer, called the uip_buf, in
+which the device driver puts an incoming packet. The TCP/IP stack
+parses the headers in the packet, and calls upon the application. If
+the remote host has sent data to the application, this data is present
+in the uip_buf and the application read the data from there. It is up
+to the application to put this data into a byte stream if needed. The
+application will not be fed with data that is out of sequence.
+
+If the application whishes to send data to the peer, it should put its
+data into the uip_buf, 40 bytes from the start of the buffer. The
+TCP/IP stack will calculate the checksums, and fill in the necessary
+header fields and finally send the packet back to the peer.
+*/
+
+#include "uip.h"
+#include "uipopt.h"
+#include "uip_arch.h"
+
+/*-----------------------------------------------------------------------------------*/
+/* Variable definitions. */
+
+
+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+const u16_t uip_hostaddr[2] =
+  {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),
+   HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};
+const u16_t uip_arp_draddr[2] =
+  {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),
+   HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};
+const u16_t uip_arp_netmask[2] =
+  {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),
+   HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};
+#else
+u16_t uip_hostaddr[2];       
+u16_t uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* UIP_FIXEDADDR */
+
+u8_t uip_buf[UIP_BUFSIZE+2];   /* The packet buffer that contains
+				incoming packets. */
+volatile u8_t *uip_appdata;  /* The uip_appdata pointer points to
+				application data. */
+volatile u8_t *uip_sappdata;  /* The uip_appdata pointer points to the
+				 application data which is to be sent. */
+#if UIP_URGDATA > 0
+volatile u8_t *uip_urgdata;  /* The uip_urgdata pointer points to
+				urgent data (out-of-band data), if
+				present. */
+volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+volatile u16_t uip_len, uip_slen;
+                             /* The uip_len is either 8 or 16 bits,
+				depending on the maximum packet
+				size. */
+
+volatile u8_t uip_flags;     /* The uip_flags variable is used for
+				communication between the TCP/IP stack
+				and the application program. */
+struct uip_conn *uip_conn;   /* uip_conn always points to the current
+				connection. */
+
+struct uip_conn uip_conns[UIP_CONNS];
+                             /* The uip_conns array holds all TCP
+				connections. */
+u16_t uip_listenports[UIP_LISTENPORTS];
+                             /* The uip_listenports list all currently
+				listning ports. */
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_conn;
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+
+static u16_t ipid;           /* Ths ipid variable is an increasing
+				number that is used for the IP ID
+				field. */
+
+static u8_t iss[4];          /* The iss variable is used for the TCP
+				initial sequence number. */
+
+#if UIP_ACTIVE_OPEN
+static u16_t lastport;       /* Keeps track of the last port used for
+				a new connection. */
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+volatile u8_t uip_acc32[4];
+static u8_t c, opt;
+static u16_t tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN 0x01
+#define TCP_SYN 0x02
+#define TCP_RST 0x04
+#define TCP_PSH 0x08
+#define TCP_ACK 0x10
+#define TCP_URG 0x20
+#define TCP_CTL 0x3f
+
+#define ICMP_ECHO_REPLY 0
+#define ICMP_ECHO       8     
+
+/* Macros. */
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0])
+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+#if UIP_STATISTICS == 1
+struct uip_stats uip_stat;
+#define UIP_STAT(s) s
+#else
+#define UIP_STAT(s)
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+#include 
+void uip_log(char *msg);
+#define UIP_LOG(m) uip_log(m)
+#else
+#define UIP_LOG(m)
+#endif /* UIP_LOGGING == 1 */
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_init(void)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    uip_listenports[c] = 0;
+  }
+  for(c = 0; c < UIP_CONNS; ++c) {
+    uip_conns[c].tcpstateflags = CLOSED;
+  }
+#if UIP_ACTIVE_OPEN
+  lastport = 1024;
+#endif /* UIP_ACTIVE_OPEN */
+
+#if UIP_UDP
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    uip_udp_conns[c].lport = 0;
+  }
+#endif /* UIP_UDP */
+  
+
+  /* IPv4 initialization. */
+#if UIP_FIXEDADDR == 0
+  uip_hostaddr[0] = uip_hostaddr[1] = 0;
+#endif /* UIP_FIXEDADDR */
+
+}
+/*-----------------------------------------------------------------------------------*/
+#if UIP_ACTIVE_OPEN
+struct uip_conn *
+uip_connect(u16_t *ripaddr, u16_t rport)
+{
+  register struct uip_conn *conn, *cconn;
+  
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  /* Check if this port is already in use, and if so try to find
+     another one. */
+  for(c = 0; c < UIP_CONNS; ++c) {
+    conn = &uip_conns[c];
+    if(conn->tcpstateflags != CLOSED &&
+       conn->lport == htons(lastport)) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    cconn = &uip_conns[c]; 
+    if(cconn->tcpstateflags == CLOSED) {
+      conn = cconn;
+      break;
+    }
+    if(cconn->tcpstateflags == TIME_WAIT) {
+      if(conn == 0 ||
+	 cconn->timer > uip_conn->timer) {
+	conn = cconn;
+      }
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+  
+  conn->tcpstateflags = SYN_SENT;
+
+  conn->snd_nxt[0] = iss[0];
+  conn->snd_nxt[1] = iss[1];
+  conn->snd_nxt[2] = iss[2];
+  conn->snd_nxt[3] = iss[3];
+
+  conn->initialmss = conn->mss = UIP_TCP_MSS;
+  
+  conn->len = 1;   /* TCP length of the SYN is one. */
+  conn->nrtx = 0;
+  conn->timer = 1; /* Send the SYN next time around. */
+  conn->rto = UIP_RTO;
+  conn->sa = 0;
+  conn->sv = 16;
+  conn->lport = htons(lastport);
+  conn->rport = rport;
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+  
+  return conn;
+}
+#endif /* UIP_ACTIVE_OPEN */
+/*-----------------------------------------------------------------------------------*/
+#if UIP_UDP
+struct uip_udp_conn *
+uip_udp_new(u16_t *ripaddr, u16_t rport)
+{
+  register struct uip_udp_conn *conn;
+  
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+  
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == lastport) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == 0) {
+      conn = &uip_udp_conns[c]; 
+      break;
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+  
+  conn->lport = HTONS(lastport);
+  conn->rport = HTONS(rport);
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+  
+  return conn;
+}
+#endif /* UIP_UDP */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_unlisten(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == port) {
+      uip_listenports[c] = 0;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_listen(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == 0) {
+      uip_listenports[c] = port;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/* XXX: IP fragment reassembly: not well-tested. */
+
+#if UIP_REASSEMBLY
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,
+				    0x0f, 0x07, 0x03, 0x01};
+static u16_t uip_reasslen;
+static u8_t uip_reassflags;
+#define UIP_REASS_FLAG_LASTFRAG 0x01
+static u8_t uip_reasstmr;
+
+#define IP_HLEN 20
+#define IP_MF   0x20
+
+static u8_t
+uip_reass(void)
+{
+  u16_t offset, len;
+  u16_t i;
+
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if(uip_reasstmr == 0) {
+    memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN);
+    uip_reasstmr = UIP_REASS_MAXAGE;
+    uip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0);
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&
+     BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&
+     BUF->destipaddr[0] == FBUF->destipaddr[0] &&
+     BUF->destipaddr[1] == FBUF->destipaddr[1] &&
+     BUF->ipid[0] == FBUF->ipid[0] &&
+     BUF->ipid[1] == FBUF->ipid[1]) {
+
+    len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;
+    offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if(offset > UIP_REASS_BUFSIZE ||
+       offset + len > UIP_REASS_BUFSIZE) {
+      uip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    memcpy(&uip_reassbuf[IP_HLEN + offset],
+	   (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
+	   len);
+      
+    /* Update the bitmap. */
+    if(offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      /* If the two endpoints are in the same byte, we only update
+	 that byte. */
+	     
+      uip_reassbitmap[offset / (8 * 8)] |=
+	     bitmap_bits[(offset / 8 ) & 7] &
+	     ~bitmap_bits[((offset + len) / 8 ) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+	 bytes in the endpoints and fill the stuff inbetween with
+	 0xff. */
+      uip_reassbitmap[offset / (8 * 8)] |=
+	bitmap_bits[(offset / 8 ) & 7];
+      for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+	uip_reassbitmap[i] = 0xff;
+      }      
+      uip_reassbitmap[(offset + len) / (8 * 8)] |=
+	~bitmap_bits[((offset + len) / 8 ) & 7];
+    }
+    
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if((BUF->ipoffset[0] & IP_MF) == 0) {
+      uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+      uip_reasslen = offset + len;
+    }
+    
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+	 the bitmap. */
+      for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {
+	if(uip_reassbitmap[i] != 0xff) {
+	  goto nullreturn;
+	}
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+	 right amount of bits. */
+      if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=
+	 (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
+	goto nullreturn;
+      }
+
+      /* If we have come this far, we have a full packet in the
+	 buffer, so we allocate a pbuf and copy the packet into it. We
+	 also reset the timer. */
+      uip_reasstmr = 0;
+      memcpy(BUF, FBUF, uip_reasslen);
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+	 from now on. */
+      BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+      BUF->len[0] = uip_reasslen >> 8;
+      BUF->len[1] = uip_reasslen & 0xff;
+      BUF->ipchksum = 0;
+      BUF->ipchksum = ~(uip_ipchksum());
+
+      return uip_reasslen;
+    }
+  }
+
+ nullreturn:
+  return 0;
+}
+#endif /* UIP_REASSEMBL */
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_add_rcv_nxt(u16_t n)
+{
+  uip_add32(uip_conn->rcv_nxt, n);
+  uip_conn->rcv_nxt[0] = uip_acc32[0];
+  uip_conn->rcv_nxt[1] = uip_acc32[1];
+  uip_conn->rcv_nxt[2] = uip_acc32[2];
+  uip_conn->rcv_nxt[3] = uip_acc32[3];
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_process(u8_t flag)
+{
+  register struct uip_conn *uip_connr = uip_conn;
+  
+  uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+
+  
+  /* Check if we were invoked because of the perodic timer fireing. */
+  if(flag == UIP_TIMER) {
+#if UIP_REASSEMBLY
+    if(uip_reasstmr != 0) {
+      --uip_reasstmr;
+    }
+#endif /* UIP_REASSEMBLY */
+    /* Increase the initial sequence number. */
+    if(++iss[3] == 0) {
+      if(++iss[2] == 0) {
+	if(++iss[1] == 0) {
+	  ++iss[0];
+	}
+      }
+    }    
+    uip_len = 0;
+    if(uip_connr->tcpstateflags == TIME_WAIT ||
+       uip_connr->tcpstateflags == FIN_WAIT_2) {
+      ++(uip_connr->timer);
+      if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {
+	uip_connr->tcpstateflags = CLOSED;
+      }
+    } else if(uip_connr->tcpstateflags != CLOSED) {
+      /* If the connection has outstanding data, we increase the
+	 connection's timer and see if it has reached the RTO value
+	 in which case we retransmit. */
+      if(uip_outstanding(uip_connr)) {
+	if(uip_connr->timer-- == 0) {
+	  if(uip_connr->nrtx == UIP_MAXRTX ||
+	     ((uip_connr->tcpstateflags == SYN_SENT ||
+	       uip_connr->tcpstateflags == SYN_RCVD) &&
+	      uip_connr->nrtx == UIP_MAXSYNRTX)) {
+	    uip_connr->tcpstateflags = CLOSED;
+
+	    /* We call UIP_APPCALL() with uip_flags set to
+	       UIP_TIMEDOUT to inform the application that the
+	       connection has timed out. */
+	    uip_flags = UIP_TIMEDOUT;
+	    UIP_APPCALL();
+
+	    /* We also send a reset packet to the remote host. */
+	    BUF->flags = TCP_RST | TCP_ACK;
+	    goto tcp_send_nodata;
+	  }
+
+	  /* Exponential backoff. */
+	  uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
+					 4:
+					 uip_connr->nrtx);
+	  ++(uip_connr->nrtx);
+	  
+	  /* Ok, so we need to retransmit. We do this differently
+	     depending on which state we are in. In ESTABLISHED, we
+	     call upon the application so that it may prepare the
+	     data for the retransmit. In SYN_RCVD, we resend the
+	     SYNACK that we sent earlier and in LAST_ACK we have to
+	     retransmit our FINACK. */
+	  UIP_STAT(++uip_stat.tcp.rexmit);
+	  switch(uip_connr->tcpstateflags & TS_MASK) {
+	  case SYN_RCVD:
+	    /* In the SYN_RCVD state, we should retransmit our
+               SYNACK. */
+	    goto tcp_send_synack;
+	    
+#if UIP_ACTIVE_OPEN
+	  case SYN_SENT:
+	    /* In the SYN_SENT state, we retransmit out SYN. */
+	    BUF->flags = 0;
+	    goto tcp_send_syn;
+#endif /* UIP_ACTIVE_OPEN */
+	    
+	  case ESTABLISHED:
+	    /* In the ESTABLISHED state, we call upon the application
+               to do the actual retransmit after which we jump into
+               the code for sending out the packet (the apprexmit
+               label). */
+	    uip_len = 0;
+	    uip_slen = 0;
+	    uip_flags = UIP_REXMIT;
+	    UIP_APPCALL();
+	    goto apprexmit;
+	    
+	  case FIN_WAIT_1:
+	  case CLOSING:
+	  case LAST_ACK:
+	    /* In all these states we should retransmit a FINACK. */
+	    goto tcp_send_finack;
+	    
+	  }
+	}
+      } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) {
+	/* If there was no need for a retransmission, we poll the
+           application for new data. */
+	uip_len = 0;
+	uip_slen = 0;
+	uip_flags = UIP_POLL;
+	UIP_APPCALL();
+	goto appsend;
+      }
+    }
+    goto drop;
+  }
+#if UIP_UDP 
+  if(flag == UIP_UDP_TIMER) {
+    if(uip_udp_conn->lport != 0) {
+      uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+      uip_len = uip_slen = 0;
+      uip_flags = UIP_POLL;
+      UIP_UDP_APPCALL();
+      goto udp_send;
+    } else {
+      goto drop;
+    }
+  }
+#endif
+
+  /* This is where the input processing starts. */
+  UIP_STAT(++uip_stat.ip.recv);
+
+
+  /* Start of IPv4 input header processing code. */
+  
+  /* Check validity of the IP header. */  
+  if(BUF->vhl != 0x45)  { /* IP version and header length. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.vhlerr);
+    UIP_LOG("ip: invalid version or header length.");
+    goto drop;
+  }
+  
+  /* Check the size of the packet. If the size reported to us in
+     uip_len doesn't match the size reported in the IP header, there
+     has been a transmission error and we drop the packet. */
+  
+  if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */
+    uip_len = (uip_len & 0xff) | (BUF->len[0] << 8);
+  }
+  if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */
+    uip_len = (uip_len & 0xff00) | BUF->len[1];
+  }
+
+  /* Check the fragment flag. */
+  if((BUF->ipoffset[0] & 0x3f) != 0 ||
+     BUF->ipoffset[1] != 0) { 
+#if UIP_REASSEMBLY
+    uip_len = uip_reass();
+    if(uip_len == 0) {
+      goto drop;
+    }
+#else
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.fragerr);
+    UIP_LOG("ip: fragment dropped.");    
+    goto drop;
+#endif /* UIP_REASSEMBLY */
+  }
+
+  /* If we are configured to use ping IP address configuration and
+     hasn't been assigned an IP address yet, we accept all ICMP
+     packets. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    if(BUF->proto == UIP_PROTO_ICMP) {
+      UIP_LOG("ip: possible ping config packet received.");
+      goto icmp_input;
+    } else {
+      UIP_LOG("ip: packet dropped since no address assigned.");
+      goto drop;
+    }
+  }
+#endif /* UIP_PINGADDRCONF */
+  
+  /* Check if the packet is destined for our IP address. */  
+  if(BUF->destipaddr[0] != uip_hostaddr[0]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_LOG("ip: packet not for us.");        
+    goto drop;
+  }
+  if(BUF->destipaddr[1] != uip_hostaddr[1]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_LOG("ip: packet not for us.");        
+    goto drop;
+  }
+
+#if 0
+  // IP checksum is wrong through Netgear DSL router
+  if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header
+				    checksum. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.chkerr);
+    UIP_LOG("ip: bad checksum.");    
+    goto drop;
+  }
+#endif
+
+  if(BUF->proto == UIP_PROTO_TCP)  /* Check for TCP packet. If so, jump
+                                     to the tcp_input label. */
+    goto tcp_input;
+
+#if UIP_UDP
+  if(BUF->proto == UIP_PROTO_UDP)
+    goto udp_input;
+#endif /* UIP_UDP */
+
+  if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from
+					here. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.protoerr);
+    UIP_LOG("ip: neither tcp nor icmp.");        
+    goto drop;
+  }
+  
+ icmp_input:
+  UIP_STAT(++uip_stat.icmp.recv);
+  
+  /* ICMP echo (i.e., ping) processing. This is simple, we only change
+     the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+     checksum before we return the packet. */
+  if(ICMPBUF->type != ICMP_ECHO) {
+    UIP_STAT(++uip_stat.icmp.drop);
+    UIP_STAT(++uip_stat.icmp.typeerr);
+    UIP_LOG("icmp: not icmp echo.");
+    goto drop;
+  }
+
+  /* If we are configured to use ping IP address assignment, we use
+     the destination IP address of this ping packet and assign it to
+     ourself. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    uip_hostaddr[0] = BUF->destipaddr[0];
+    uip_hostaddr[1] = BUF->destipaddr[1];
+  }
+#endif /* UIP_PINGADDRCONF */  
+  
+  ICMPBUF->type = ICMP_ECHO_REPLY;
+  
+  if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;
+  } else {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);
+  }
+  
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  UIP_STAT(++uip_stat.icmp.sent);
+  goto send;
+
+  /* End of IPv4 input header processing code. */
+  
+
+#if UIP_UDP
+  /* UDP input processing. */
+ udp_input:
+  /* UDP processing is really just a hack. We don't do anything to the
+     UDP/IP headers, but let the UDP application do all the hard
+     work. If the application sets uip_slen, it has a packet to
+     send. */
+#if UIP_UDP_CHECKSUMS
+  if(uip_udpchksum() != 0xffff) { 
+    UIP_STAT(++uip_stat.udp.drop);
+    UIP_STAT(++uip_stat.udp.chkerr);
+    UIP_LOG("udp: bad checksum.");    
+    goto drop;
+  }  
+#endif /* UIP_UDP_CHECKSUMS */
+
+  /* Demultiplex this UDP packet between the UDP "connections". */
+  for(uip_udp_conn = &uip_udp_conns[0];
+      uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];
+      ++uip_udp_conn) {
+    if(uip_udp_conn->lport != 0 &&
+       UDPBUF->destport == uip_udp_conn->lport &&
+       (uip_udp_conn->rport == 0 ||
+        UDPBUF->srcport == uip_udp_conn->rport) &&
+       BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) {
+      goto udp_found; 
+    }
+  }
+  goto drop;
+  
+ udp_found:
+  uip_len = uip_len - 28;
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+  uip_flags = UIP_NEWDATA;
+  uip_slen = 0;
+  UIP_UDP_APPCALL();
+ udp_send:
+  if(uip_slen == 0) {
+    goto drop;      
+  }
+  uip_len = uip_slen + 28;
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+  
+  BUF->proto = UIP_PROTO_UDP;
+
+  UDPBUF->udplen = HTONS(uip_slen + 8);
+  UDPBUF->udpchksum = 0;
+#if UIP_UDP_CHECKSUMS 
+  /* Calculate UDP checksum. */
+  UDPBUF->udpchksum = ~(uip_udpchksum());
+  if(UDPBUF->udpchksum == 0) {
+    UDPBUF->udpchksum = 0xffff;
+  }
+#endif /* UIP_UDP_CHECKSUMS */
+
+  BUF->srcport  = uip_udp_conn->lport;
+  BUF->destport = uip_udp_conn->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_udp_conn->ripaddr[0];
+  BUF->destipaddr[1] = uip_udp_conn->ripaddr[1];
+ 
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 40];
+  goto ip_send_nolen;
+#endif /* UIP_UDP */
+  
+  /* TCP input processing. */  
+ tcp_input:
+  UIP_STAT(++uip_stat.tcp.recv);
+
+  /* Start of TCP input header processing code. */
+  
+#if 1  // FIXME
+  if(uip_tcpchksum() != 0xffff) {   /* Compute and check the TCP
+				       checksum. */
+    UIP_STAT(++uip_stat.tcp.drop);
+    UIP_STAT(++uip_stat.tcp.chkerr);
+    UIP_LOG("tcp: bad checksum.");    
+    goto drop;
+  }
+#endif
+  
+  /* Demultiplex this segment. */
+  /* First check any active connections. */
+  for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) {
+    if(uip_connr->tcpstateflags != CLOSED &&
+       BUF->destport == uip_connr->lport &&
+       BUF->srcport == uip_connr->rport &&
+       BUF->srcipaddr[0] == uip_connr->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_connr->ripaddr[1]) {
+      goto found;    
+    }
+  }
+
+  /* If we didn't find and active connection that expected the packet,
+     either this packet is an old duplicate, or this is a SYN packet
+     destined for a connection in LISTEN. If the SYN flag isn't set,
+     it is an old packet and we send a RST. */
+  if((BUF->flags & TCP_CTL) != TCP_SYN)
+    goto reset;
+  
+  tmp16 = BUF->destport;
+  /* Next, check listening connections. */  
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(tmp16 == uip_listenports[c])
+      goto found_listen;
+  }
+  
+  /* No matching connection found, so we send a RST packet. */
+  UIP_STAT(++uip_stat.tcp.synrst);
+ reset:
+
+  /* We do not send resets in response to resets. */
+  if(BUF->flags & TCP_RST) 
+    goto drop;
+
+  UIP_STAT(++uip_stat.tcp.rst);
+  
+  BUF->flags = TCP_RST | TCP_ACK;
+  uip_len = 40;
+  BUF->tcpoffset = 5 << 4;
+
+  /* Flip the seqno and ackno fields in the TCP header. */
+  c = BUF->seqno[3];
+  BUF->seqno[3] = BUF->ackno[3];  
+  BUF->ackno[3] = c;
+  
+  c = BUF->seqno[2];
+  BUF->seqno[2] = BUF->ackno[2];  
+  BUF->ackno[2] = c;
+  
+  c = BUF->seqno[1];
+  BUF->seqno[1] = BUF->ackno[1];
+  BUF->ackno[1] = c;
+  
+  c = BUF->seqno[0];
+  BUF->seqno[0] = BUF->ackno[0];  
+  BUF->ackno[0] = c;
+
+  /* We also have to increase the sequence number we are
+     acknowledging. If the least significant byte overflowed, we need
+     to propagate the carry to the other bytes as well. */
+  if(++BUF->ackno[3] == 0) {
+    if(++BUF->ackno[2] == 0) {
+      if(++BUF->ackno[1] == 0) {
+	++BUF->ackno[0];
+      }
+    }
+  }
+ 
+  /* Swap port numbers. */
+  tmp16 = BUF->srcport;
+  BUF->srcport = BUF->destport;
+  BUF->destport = tmp16;
+  
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  
+  /* And send out the RST packet! */
+  goto tcp_send_noconn;
+
+  /* This label will be jumped to if we matched the incoming packet
+     with a connection in LISTEN. In that case, we should create a new
+     connection and send a SYNACK in return. */
+ found_listen:
+  /* First we check if there are any connections avaliable. Unused
+     connections are kept in the same table as used connections, but
+     unused ones have the tcpstate set to CLOSED. Also, connections in
+     TIME_WAIT are kept track of and we'll use the oldest one if no
+     CLOSED connections are found. Thanks to Eddie C. Dost for a very
+     nice algorithm for the TIME_WAIT search. */
+  uip_connr = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    if(uip_conns[c].tcpstateflags == CLOSED) {
+      uip_connr = &uip_conns[c];
+      break;
+    }
+    if(uip_conns[c].tcpstateflags == TIME_WAIT) {
+      if(uip_connr == 0 ||
+	 uip_conns[c].timer > uip_connr->timer) {
+	uip_connr = &uip_conns[c];
+      }
+    }
+  }
+
+  if(uip_connr == 0) {
+    /* All connections are used already, we drop packet and hope that
+       the remote end will retransmit the packet at a time when we
+       have more spare connections. */
+    UIP_STAT(++uip_stat.tcp.syndrop);
+    UIP_LOG("tcp: found no unused connections.");
+    goto drop;
+  }
+  uip_conn = uip_connr;
+  
+  /* Fill in the necessary fields for the new connection. */
+  uip_connr->rto = uip_connr->timer = UIP_RTO;
+  uip_connr->sa = 0;
+  uip_connr->sv = 4;  
+  uip_connr->nrtx = 0;
+  uip_connr->lport = BUF->destport;
+  uip_connr->rport = BUF->srcport;
+  uip_connr->ripaddr[0] = BUF->srcipaddr[0];
+  uip_connr->ripaddr[1] = BUF->srcipaddr[1];
+  uip_connr->tcpstateflags = SYN_RCVD;
+
+  uip_connr->snd_nxt[0] = iss[0];
+  uip_connr->snd_nxt[1] = iss[1];
+  uip_connr->snd_nxt[2] = iss[2];
+  uip_connr->snd_nxt[3] = iss[3];
+  uip_connr->len = 1;
+
+  /* rcv_nxt should be the seqno from the incoming packet + 1. */
+  uip_connr->rcv_nxt[3] = BUF->seqno[3];
+  uip_connr->rcv_nxt[2] = BUF->seqno[2];
+  uip_connr->rcv_nxt[1] = BUF->seqno[1];
+  uip_connr->rcv_nxt[0] = BUF->seqno[0];
+  uip_add_rcv_nxt(1);
+
+  /* Parse the TCP MSS option, if present. */
+  if((BUF->tcpoffset & 0xf0) > 0x50) {
+    for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+      opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+      if(opt == 0x00) {
+	/* End of options. */	
+	break;
+      } else if(opt == 0x01) {
+	++c;
+	/* NOP option. */
+      } else if(opt == 0x02 &&
+		uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	/* An MSS option with the right option length. */	
+	tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	  (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c];
+	uip_connr->initialmss = uip_connr->mss =
+	  tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+	
+	/* And we are done processing options. */
+	break;
+      } else {
+	/* All other options have a length field, so that we easily
+	   can skip past them. */
+	if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	  /* If the length field is zero, the options are malformed
+	     and we don't process them further. */
+	  break;
+	}
+	c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+      }      
+    }
+  }
+  
+  /* Our response will be a SYNACK. */
+#if UIP_ACTIVE_OPEN
+ tcp_send_synack:
+  BUF->flags = TCP_ACK;    
+  
+ tcp_send_syn:
+  BUF->flags |= TCP_SYN;    
+#else /* UIP_ACTIVE_OPEN */
+ tcp_send_synack:
+  BUF->flags = TCP_SYN | TCP_ACK;    
+#endif /* UIP_ACTIVE_OPEN */
+  
+  /* We send out the TCP Maximum Segment Size option with our
+     SYNACK. */
+  BUF->optdata[0] = 2;
+  BUF->optdata[1] = 4;
+  BUF->optdata[2] = (UIP_TCP_MSS) / 256;
+  BUF->optdata[3] = (UIP_TCP_MSS) & 255;
+  uip_len = 44;
+  BUF->tcpoffset = 6 << 4;
+  goto tcp_send;
+
+  /* This label will be jumped to if we found an active connection. */
+ found:
+  uip_conn = uip_connr;
+  uip_flags = 0;
+
+  /* We do a very naive form of TCP reset processing; we just accept
+     any RST and kill our connection. We should in fact check if the
+     sequence number of this reset is wihtin our advertised window
+     before we accept the reset. */
+  if(BUF->flags & TCP_RST) {
+    uip_connr->tcpstateflags = CLOSED;
+    UIP_LOG("tcp: got reset, aborting connection.");
+    uip_flags = UIP_ABORT;
+    UIP_APPCALL();
+    goto drop;
+  }      
+  /* Calculated the length of the data, if the application has sent
+     any data to us. */
+  c = (BUF->tcpoffset >> 4) << 2;
+  /* uip_len will contain the length of the actual TCP data. This is
+     calculated by subtracing the length of the TCP header (in
+     c) and the length of the IP header (20 bytes). */
+  uip_len = uip_len - c - 20;
+
+  /* First, check if the sequence number of the incoming packet is
+     what we're expecting next. If not, we send out an ACK with the
+     correct numbers in. */
+  if(uip_len > 0 &&
+     (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
+      BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+      BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+      BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
+    goto tcp_send_ack;
+  }
+
+  /* Next, check if the incoming segment acknowledges any outstanding
+     data. If so, we update the sequence number, reset the length of
+     the outstanding data, calculate RTT estimations, and reset the
+     retransmission timer. */
+  if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {
+    uip_add32(uip_connr->snd_nxt, uip_connr->len);
+    if(BUF->ackno[0] == uip_acc32[0] &&
+       BUF->ackno[1] == uip_acc32[1] &&
+       BUF->ackno[2] == uip_acc32[2] &&
+       BUF->ackno[3] == uip_acc32[3]) {
+      /* Update sequence number. */
+      uip_connr->snd_nxt[0] = uip_acc32[0];
+      uip_connr->snd_nxt[1] = uip_acc32[1];
+      uip_connr->snd_nxt[2] = uip_acc32[2];
+      uip_connr->snd_nxt[3] = uip_acc32[3];
+	
+
+      /* Do RTT estimation, unless we have done retransmissions. */
+      if(uip_connr->nrtx == 0) {
+	signed char m;
+	m = uip_connr->rto - uip_connr->timer;
+	/* This is taken directly from VJs original code in his paper */
+	m = m - (uip_connr->sa >> 3);
+	uip_connr->sa += m;
+	if(m < 0) {
+	  m = -m;
+	}
+	m = m - (uip_connr->sv >> 2);
+	uip_connr->sv += m;
+	uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
+
+      }
+      /* Set the acknowledged flag. */
+      uip_flags = UIP_ACKDATA;
+      /* Reset the retransmission timer. */
+      uip_connr->timer = uip_connr->rto;
+    }
+    
+  }
+
+  /* Do different things depending on in what state the connection is. */
+  switch(uip_connr->tcpstateflags & TS_MASK) {
+    /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+	implemented, since we force the application to close when the
+	peer sends a FIN (hence the application goes directly from
+	ESTABLISHED to LAST_ACK). */
+  case SYN_RCVD:
+    /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+       we are waiting for an ACK that acknowledges the data we sent
+       out the last time. Therefore, we want to have the UIP_ACKDATA
+       flag set. If so, we enter the ESTABLISHED state. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = ESTABLISHED;
+      uip_flags = UIP_CONNECTED;
+      uip_connr->len = 0;
+      if(uip_len > 0) {
+        uip_flags |= UIP_NEWDATA;
+        uip_add_rcv_nxt(uip_len);
+      }
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto drop;
+#if UIP_ACTIVE_OPEN
+  case SYN_SENT:
+    /* In SYN_SENT, we wait for a SYNACK that is sent in response to
+       our SYN. The rcv_nxt is set to sequence number in the SYNACK
+       plus one, and we send an ACK. We move into the ESTABLISHED
+       state. */
+    if((uip_flags & UIP_ACKDATA) &&
+       BUF->flags == (TCP_SYN | TCP_ACK)) {
+
+      /* Parse the TCP MSS option, if present. */
+      if((BUF->tcpoffset & 0xf0) > 0x50) {
+	for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+	  opt = uip_buf[40 + UIP_LLH_LEN + c];
+	  if(opt == 0x00) {
+	    /* End of options. */	
+	    break;
+	  } else if(opt == 0x01) {
+	    ++c;
+	    /* NOP option. */
+	  } else if(opt == 0x02 &&
+		    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	    /* An MSS option with the right option length. */
+	    tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	      uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+	    uip_connr->initialmss =
+	      uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+
+	    /* And we are done processing options. */
+	    break;
+	  } else {
+	    /* All other options have a length field, so that we easily
+	       can skip past them. */
+	    if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	      /* If the length field is zero, the options are malformed
+		 and we don't process them further. */
+	      break;
+	    }
+	    c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+	  }      
+	}
+      }
+      uip_connr->tcpstateflags = ESTABLISHED;      
+      uip_connr->rcv_nxt[0] = BUF->seqno[0];
+      uip_connr->rcv_nxt[1] = BUF->seqno[1];
+      uip_connr->rcv_nxt[2] = BUF->seqno[2];
+      uip_connr->rcv_nxt[3] = BUF->seqno[3];
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+      uip_connr->len = 0;
+      uip_len = 0;
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto reset;
+#endif /* UIP_ACTIVE_OPEN */
+    
+  case ESTABLISHED:
+    /* In the ESTABLISHED state, we call upon the application to feed
+    data into the uip_buf. If the UIP_ACKDATA flag is set, the
+    application should put new data into the buffer, otherwise we are
+    retransmitting an old segment, and the application should put that
+    data into the buffer.
+
+    If the incoming packet is a FIN, we should close the connection on
+    this side as well, and we send out a FIN and enter the LAST_ACK
+    state. We require that there is no outstanding data; otherwise the
+    sequence numbers will be screwed up. */
+
+    if(BUF->flags & TCP_FIN) {
+      if(uip_outstanding(uip_connr)) {
+	goto drop;
+      }
+      uip_add_rcv_nxt(1 + uip_len);      
+      uip_flags = UIP_CLOSE;
+      if(uip_len > 0) {
+	uip_flags |= UIP_NEWDATA;
+      }
+      UIP_APPCALL();
+      uip_connr->len = 1;
+      uip_connr->tcpstateflags = LAST_ACK;
+      uip_connr->nrtx = 0;
+    tcp_send_finack:
+      BUF->flags = TCP_FIN | TCP_ACK;      
+      goto tcp_send_nodata;
+    }
+
+    /* Check the URG flag. If this is set, the segment carries urgent
+       data that we must pass to the application. */
+    if(BUF->flags & TCP_URG) {
+#if UIP_URGDATA > 0
+      uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];
+      if(uip_urglen > uip_len) {
+	/* There is more urgent data in the next segment to come. */
+	uip_urglen = uip_len;
+      }
+      uip_add_rcv_nxt(uip_urglen);
+      uip_len -= uip_urglen;
+      uip_urgdata = uip_appdata;
+      uip_appdata += uip_urglen;
+    } else {
+      uip_urglen = 0;
+#endif /* UIP_URGDATA > 0 */
+      uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1];
+      uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];
+    }
+    
+    
+    /* If uip_len > 0 we have TCP data in the packet, and we flag this
+       by setting the UIP_NEWDATA flag and update the sequence number
+       we acknowledge. If the application has stopped the dataflow
+       using uip_stop(), we must not accept any data packets from the
+       remote host. */
+    if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
+      uip_flags |= UIP_NEWDATA;
+      uip_add_rcv_nxt(uip_len);
+    }
+
+    /* Check if the available buffer space advertised by the other end
+       is smaller than the initial MSS for this connection. If so, we
+       set the current MSS to the window size to ensure that the
+       application does not send more data than the other end can
+       handle.
+
+       If the remote host advertises a zero window, we set the MSS to
+       the initial MSS so that the application will send an entire MSS
+       of data. This data will not be acknowledged by the receiver,
+       and the application will retransmit it. This is called the
+       "persistent timer" and uses the retransmission mechanim.
+    */
+    tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1];
+    if(tmp16 > uip_connr->initialmss ||
+       tmp16 == 0) {
+      tmp16 = uip_connr->initialmss;
+    }
+    uip_connr->mss = tmp16;
+
+    /* If this packet constitutes an ACK for outstanding data (flagged
+       by the UIP_ACKDATA flag, we should call the application since it
+       might want to send more data. If the incoming packet had data
+       from the peer (as flagged by the UIP_NEWDATA flag), the
+       application must also be notified.
+
+       When the application is called, the global variable uip_len
+       contains the length of the incoming data. The application can
+       access the incoming data through the global pointer
+       uip_appdata, which usually points 40 bytes into the uip_buf
+       array.
+
+       If the application wishes to send any data, this data should be
+       put into the uip_appdata and the length of the data should be
+       put into uip_len. If the application don't have any data to
+       send, uip_len must be set to 0. */
+    if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {
+      uip_slen = 0;
+      UIP_APPCALL();
+
+    appsend:
+      
+      if(uip_flags & UIP_ABORT) {
+	uip_slen = 0;
+	uip_connr->tcpstateflags = CLOSED;
+	BUF->flags = TCP_RST | TCP_ACK;
+	goto tcp_send_nodata;
+      }
+
+      if(uip_flags & UIP_CLOSE) {
+	uip_slen = 0;
+	uip_connr->len = 1;
+	uip_connr->tcpstateflags = FIN_WAIT_1;
+	uip_connr->nrtx = 0;
+	BUF->flags = TCP_FIN | TCP_ACK;
+	goto tcp_send_nodata;	
+      }
+
+      /* If uip_slen > 0, the application has data to be sent. */
+      if(uip_slen > 0) {
+
+	/* If the connection has acknowledged data, the contents of
+	   the ->len variable should be discarded. */ 
+	if((uip_flags & UIP_ACKDATA) != 0) {
+	  uip_connr->len = 0;
+	}
+
+	/* If the ->len variable is non-zero the connection has
+	   already data in transit and cannot send anymore right
+	   now. */
+	if(uip_connr->len == 0) {
+
+	  /* The application cannot send more than what is allowed by
+	     the mss (the minumum of the MSS and the available
+	     window). */
+	  if(uip_slen > uip_connr->mss) {
+	    uip_slen = uip_connr->mss;
+	  }
+
+	  /* Remember how much data we send out now so that we know
+	     when everything has been acknowledged. */
+	  uip_connr->len = uip_slen;
+	} else {
+
+	  /* If the application already had unacknowledged data, we
+	     make sure that the application does not send (i.e.,
+	     retransmit) out more than it previously sent out. */
+	  uip_slen = uip_connr->len;
+	}
+      } else {
+	uip_connr->len = 0;
+      }
+      uip_connr->nrtx = 0;
+    apprexmit:
+      uip_appdata = uip_sappdata;
+      
+      /* If the application has data to be sent, or if the incoming
+         packet had new data in it, we must send out a packet. */
+      if(uip_slen > 0 && uip_connr->len > 0) {
+	/* Add the length of the IP and TCP headers. */
+	uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+	/* We always set the ACK flag in response packets. */
+	BUF->flags = TCP_ACK | TCP_PSH;
+	/* Send the packet. */
+	goto tcp_send_noopts;
+      }
+      /* If there is no data to send, just send out a pure ACK if
+	 there is newdata. */
+      if(uip_flags & UIP_NEWDATA) {
+	uip_len = UIP_TCPIP_HLEN;
+	BUF->flags = TCP_ACK;
+	goto tcp_send_noopts;
+      }
+    }
+    goto drop;
+  case LAST_ACK:
+    /* We can close this connection if the peer has acknowledged our
+       FIN. This is indicated by the UIP_ACKDATA flag. */     
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = CLOSED;
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+    }
+    break;
+    
+  case FIN_WAIT_1:
+    /* The application has closed the connection, but the remote host
+       hasn't closed its end yet. Thus we do nothing but wait for a
+       FIN from the other side. */
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      if(uip_flags & UIP_ACKDATA) {
+	uip_connr->tcpstateflags = TIME_WAIT;
+	uip_connr->timer = 0;
+	uip_connr->len = 0;
+      } else {
+	uip_connr->tcpstateflags = CLOSING;
+      }
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    } else if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = FIN_WAIT_2;
+      uip_connr->len = 0;
+      goto drop;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+      
+  case FIN_WAIT_2:
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case TIME_WAIT:
+    goto tcp_send_ack;
+    
+  case CLOSING:
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+    }
+  }  
+  goto drop;
+  
+
+  /* We jump here when we are ready to send the packet, and just want
+     to set the appropriate TCP sequence numbers in the TCP header. */
+ tcp_send_ack:
+  BUF->flags = TCP_ACK;
+ tcp_send_nodata:
+  uip_len = 40;
+ tcp_send_noopts:
+  BUF->tcpoffset = 5 << 4;
+ tcp_send:
+  /* We're done with the input processing. We are now ready to send a
+     reply. Our job is to fill in all the fields of the TCP and IP
+     headers before calculating the checksum and finally send the
+     packet. */
+  BUF->ackno[0] = uip_connr->rcv_nxt[0];
+  BUF->ackno[1] = uip_connr->rcv_nxt[1];
+  BUF->ackno[2] = uip_connr->rcv_nxt[2];
+  BUF->ackno[3] = uip_connr->rcv_nxt[3];
+  
+  BUF->seqno[0] = uip_connr->snd_nxt[0];
+  BUF->seqno[1] = uip_connr->snd_nxt[1];
+  BUF->seqno[2] = uip_connr->snd_nxt[2];
+  BUF->seqno[3] = uip_connr->snd_nxt[3];
+
+  BUF->proto = UIP_PROTO_TCP;
+  
+  BUF->srcport  = uip_connr->lport;
+  BUF->destport = uip_connr->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_connr->ripaddr[0];
+  BUF->destipaddr[1] = uip_connr->ripaddr[1];
+ 
+
+  if(uip_connr->tcpstateflags & UIP_STOPPED) {
+    /* If the connection has issued uip_stop(), we advertise a zero
+       window so that the remote host will stop sending data. */
+    BUF->wnd[0] = BUF->wnd[1] = 0;
+  } else {
+    BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);
+    BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); 
+  }
+
+ tcp_send_noconn:
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+
+  /* Calculate TCP checksum. */
+  BUF->tcpchksum = 0;
+  BUF->tcpchksum = ~(uip_tcpchksum());
+  
+ ip_send_nolen:
+
+  BUF->vhl = 0x45;
+  BUF->tos = 0;
+  BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+  BUF->ttl  = UIP_TTL;
+  ++ipid;
+  BUF->ipid[0] = ipid >> 8;
+  BUF->ipid[1] = ipid & 0xff;
+  
+  /* Calculate IP checksum. */
+  BUF->ipchksum = 0;
+  BUF->ipchksum = ~(uip_ipchksum());
+
+  UIP_STAT(++uip_stat.tcp.sent);
+ send:
+  UIP_STAT(++uip_stat.ip.sent);
+  /* Return and let the caller do the actual transmission. */
+  return;
+ drop:
+  uip_len = 0;
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+htons(u16_t val)
+{
+  return HTONS(val);
+}
+/*-----------------------------------------------------------------------------------*/
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h
new file mode 100644
index 000000000..f6367a261
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h
@@ -0,0 +1,1060 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author Adam Dunkels 
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $
+ *
+ */
+
+#ifndef __UIP_H__
+#define __UIP_H__
+
+#include "uipopt.h"
+
+/*-----------------------------------------------------------------------------------*/
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses. 
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte representation of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \
+                              uip_hostaddr[1] = addr[1]; } while(0)
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \
+                              addr[1] = uip_hostaddr[1]; } while(0)
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void uip_init(void);
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+  uip_len = devicedriver_poll();
+  if(uip_len > 0) {
+    uip_input();
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+  #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+  uip_len = ethernet_devicedrver_poll();
+  if(uip_len > 0) {
+    if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+      uip_arp_ipin();
+      uip_input();
+      if(uip_len > 0) {
+        uip_arp_out();
+	ethernet_devicedriver_send();
+      }
+    } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+      uip_arp_arpin();
+      if(uip_len > 0) {
+	ethernet_devicedriver_send();
+      }
+    }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input()        uip_process(UIP_DATA)
+
+/**
+ * Periodic processing for a connection identified by its number.
+ * 
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The ususal way of calling the function is through a for() loop like
+ * this:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode 
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \
+                                uip_process(UIP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a connection identified by a pointer to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn(conn) do { uip_conn = conn; \
+                                     uip_process(UIP_TIMER); } while (0)
+
+#if UIP_UDP
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_prerioic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }   
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }   
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \
+                                uip_process(UIP_UDP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \
+                                         uip_process(UIP_UDP_TIMER); } while (0)
+
+
+#endif /* UIP_UDP */
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+    hwsend(&uip_buf[0], UIP_LLH_LEN);
+    hwsend(&uip_buf[UIP_LLH_LEN], 40);
+    hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN);
+ }
+ \endcode
+ */
+extern u8_t uip_buf[UIP_BUFSIZE+2] __attribute__ ((aligned (4)));
+
+/** @} */
+
+/*-----------------------------------------------------------------------------------*/
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+*/
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80)); 
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_listen(u16_t port);
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80)); 
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_unlisten(u16_t port);
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specied host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is avaliable only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a convertion using HTONS() or htons() is necessary.
+ *
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(ipaddr, 192,168,1,2);
+ uip_connect(ipaddr, HTONS(80)); 
+ \endcode
+ * 
+ * \param ripaddr A pointer to a 4-byte array representing the IP
+ * address of the remote hot.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.   
+ *
+ */
+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port);
+
+
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding(conn) ((conn)->len)
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data. 
+ *
+ * The amount of data that actually is sent out after a call to this
+ * funcion is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ * 
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ * 
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0)   
+
+/**
+ * The length of any incoming data that is currently avaliable (if avaliable)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+#define uip_datalen()       uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()    uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close()         (uip_flags = UIP_CLOSE)
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occured that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort()         (uip_flags = UIP_ABORT)
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()          (uip_conn->tcpstateflags |= UIP_STOPPED)
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped(conn)   ((conn)->tcpstateflags & UIP_STOPPED)
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()         do { uip_flags |= UIP_NEWDATA; \
+                                   uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+                              } while(0)
+
+
+/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * avaliable through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()   (uip_flags & UIP_NEWDATA)
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data. 
+ *
+ * \hideinitializer
+ */
+#define uip_acked()   (uip_flags & UIP_ACKDATA)
+
+/**
+ * Has the connection just been connected?  
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() (uip_flags & UIP_CONNECTED)
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()    (uip_flags & UIP_CLOSE)
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()    (uip_flags & UIP_ABORT)
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()    (uip_flags & UIP_TIMEDOUT)
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()     (uip_flags & UIP_REXMIT)
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */ 
+#define uip_poll()       (uip_flags & UIP_POLL)
+
+/**
+ * Get the initial maxium segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()             (uip_conn->initialmss)
+
+/**
+ * Get the current maxium segment size that can be sent on the current
+ * connection.
+ *
+ * The current maxiumum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()             (uip_conn->mss)
+
+/**
+ * Set up a new UDP connection.
+ *
+ * \param ripaddr A pointer to a 4-byte structure representing the IP
+ * address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport);
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove(conn) (conn)->lport = 0
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send(len) uip_slen = (len)
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+ 
+/**
+ * Pack an IP address into a 4-byte array which is used by uIP to
+ * represent IP addresses.
+ *
+ * Example:
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(&ipaddr, 192,168,1,2); 
+ \endcode
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP addres.
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address. 
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \
+                     (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \
+                     (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \
+                  } while(0)
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#   if BYTE_ORDER == BIG_ENDIAN
+#      define HTONS(n) (n)
+#   else /* BYTE_ORDER == BIG_ENDIAN */
+#      define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))
+#   endif /* BYTE_ORDER == BIG_ENDIAN */
+#endif /* HTONS */
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+u16_t htons(u16_t val);
+#endif /* htons */
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+extern volatile u8_t *uip_appdata;
+extern volatile u8_t *uip_sappdata; 
+
+#if UIP_URGDATA > 0 
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern volatile u8_t *uip_urgdata; 
+#endif /* UIP_URGDATA > 0 */
+
+
+/* u[8|16]_t uip_len:
+ *
+ * When the application is called, uip_len contains the length of any
+ * new data that has been received from the remote host. The
+ * application should set this variable to the size of any data that
+ * the application wishes to send. When the network device driver
+ * output function is called, uip_len should contain the length of the
+ * outgoing packet.
+ */
+extern volatile u16_t uip_len, uip_slen;
+
+#if UIP_URGDATA > 0 
+extern volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whos purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The size of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote host. */
+  
+  u16_t lport;        /**< The local TCP port, in network byte order. */
+  u16_t rport;        /**< The local remote TCP port, in network byte
+			 order. */  
+  
+  u8_t rcv_nxt[4];    /**< The sequence number that we expect to
+			 receive next. */
+  u8_t snd_nxt[4];    /**< The sequence number that was last sent by
+                         us. */
+  u16_t len;          /**< Length of the data that was previously sent. */
+  u16_t mss;          /**< Current maximum segment size for the
+			 connection. */
+  u16_t initialmss;   /**< Initial maximum segment size for the
+			 connection. */  
+  u8_t sa;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t sv;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t rto;           /**< Retransmission time-out. */
+  u8_t tcpstateflags; /**< TCP state and flags. */
+  u8_t timer;         /**< The retransmission timer. */
+  u8_t nrtx;          /**< The number of retransmissions for the last
+			 segment sent. */
+
+  /** The application state. */
+  u8_t appstate[UIP_APPSTATE_SIZE];  
+};
+
+
+/* Pointer to the current connection. */
+extern struct uip_conn *uip_conn;
+/* The array containing all uIP connections. */
+extern struct uip_conn uip_conns[UIP_CONNS];
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern volatile u8_t uip_acc32[4];
+
+/** @} */
+
+
+#if UIP_UDP
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote peer. */
+  u16_t lport;        /**< The local port number in network byte order. */
+  u16_t rport;        /**< The remote port number in network byte order. */
+};
+
+extern struct uip_udp_conn *uip_udp_conn;
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats {
+  struct {
+    uip_stats_t drop;     /**< Number of dropped packets at the IP
+			     layer. */
+    uip_stats_t recv;     /**< Number of received packets at the IP
+			     layer. */
+    uip_stats_t sent;     /**< Number of sent packets at the IP
+			     layer. */
+    uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
+			     IP version or header length. */
+    uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+    uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+    uip_stats_t fragerr;  /**< Number of packets dropped since they
+			     were IP fragments. */
+    uip_stats_t chkerr;   /**< Number of packets dropped due to IP
+			     checksum errors. */
+    uip_stats_t protoerr; /**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+  } ip;                   /**< IP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped ICMP packets. */
+    uip_stats_t recv;     /**< Number of received ICMP packets. */
+    uip_stats_t sent;     /**< Number of sent ICMP packets. */
+    uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
+			     type. */
+  } icmp;                 /**< ICMP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped TCP segments. */
+    uip_stats_t recv;     /**< Number of recived TCP segments. */
+    uip_stats_t sent;     /**< Number of sent TCP segments. */
+    uip_stats_t chkerr;   /**< Number of TCP segments with a bad
+			     checksum. */
+    uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
+			     number. */
+    uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
+    uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
+    uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+    uip_stats_t synrst;   /**< Number of SYNs for closed ports,
+			     triggering a RST. */
+  } tcp;                  /**< TCP statistics. */
+};
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+extern struct uip_stats uip_stat;
+
+
+/*-----------------------------------------------------------------------------------*/
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+/*-----------------------------------------------------------------------------------*/
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * infomation.
+ */
+extern volatile u8_t uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA and
+   UIP_NEWDATA flags may both be set at the same time, whereas the
+   others are mutualy exclusive. Note that these flags should *NOT* be
+   accessed directly, but through the uIP functions/macros. */
+
+#define UIP_ACKDATA   1     /* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT    4     /* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL      8     /* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE     16    /* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT     32    /* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED 64    /* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT  128   /* The connection has been aborted due to
+			       too many retransmissions. */
+
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void uip_process(u8_t flag);
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. */
+
+#define UIP_DATA    1     /* Tells uIP that there is incoming data in
+                             the uip_buf buffer. The length of the
+                             data is stored in the global variable
+                             uip_len. */
+#define UIP_TIMER   2     /* Tells uIP that the periodic timer has
+                             fired. */
+#if UIP_UDP
+#define UIP_UDP_TIMER 3
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define CLOSED      0
+#define SYN_RCVD    1
+#define SYN_SENT    2
+#define ESTABLISHED 3
+#define FIN_WAIT_1  4
+#define FIN_WAIT_2  5
+#define CLOSING     6
+#define TIME_WAIT   7
+#define LAST_ACK    8
+#define TS_MASK     15
+  
+#define UIP_STOPPED      16
+
+#define UIP_TCPIP_HLEN 40
+
+/* The TCP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],  
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];     
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} uip_tcpip_hdr;
+
+/* The ICMP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+  u16_t id, seqno;  
+} uip_icmpip_hdr;
+
+
+/* The UDP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  
+  /* UDP header. */
+  u16_t srcport,
+    destport;
+  u16_t udplen;
+  u16_t udpchksum;
+} uip_udpip_hdr;
+
+#define UIP_PROTO_ICMP  1
+#define UIP_PROTO_TCP   6
+#define UIP_PROTO_UDP   17
+
+#if UIP_FIXEDADDR
+extern const u16_t uip_hostaddr[2];
+#else /* UIP_FIXEDADDR */
+extern u16_t uip_hostaddr[2];
+#endif /* UIP_FIXEDADDR */
+
+#endif /* __UIP_H__ */
+
+
+/** @} */
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c
new file mode 100644
index 000000000..4cd08c3c7
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "uip_arch.h"
+#include <__cross_studio_io.h>
+
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define IP_PROTO_TCP    6
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_add32(u8_t *op32, u16_t op16)
+{
+  
+  uip_acc32[3] = op32[3] + (op16 & 0xff);
+  uip_acc32[2] = op32[2] + (op16 >> 8);
+  uip_acc32[1] = op32[1];
+  uip_acc32[0] = op32[0];
+  
+  if(uip_acc32[2] < (op16 >> 8)) {
+    ++uip_acc32[1];    
+    if(uip_acc32[1] == 0) {
+      ++uip_acc32[0];
+    }
+  }
+  
+  
+  if(uip_acc32[3] < (op16 & 0xff)) {
+    ++uip_acc32[2];  
+    if(uip_acc32[2] == 0) {
+      ++uip_acc32[1];    
+      if(uip_acc32[1] == 0) {
+	++uip_acc32[0];
+      }
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_chksum(u16_t *sdata, u16_t len)
+{
+  u16_t acc;
+  
+  for (acc = 0; len > 1; len -= 2) {
+    u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8);
+    if ((acc += u) < u) {
+      /* Overflow, so we add the carry to acc (i.e., increase by
+         one). */
+      ++acc;
+    }
+    ++sdata;
+  }
+
+  /* add up any odd byte */
+  if(len == 1) {
+    acc += htons(((u16_t)(*(u8_t *)sdata)) << 8);
+    if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) {
+      ++acc;
+    }
+  }
+
+  return acc;
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_ipchksum(void)
+{
+  return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20);
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_tcpchksum(void)
+{
+  u16_t hsum, sum;
+
+  
+  /* Compute the checksum of the TCP header. */
+  hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20);
+
+  /* Compute the checksum of the data in the TCP packet and add it to
+     the TCP header checksum. */
+  sum = uip_chksum((u16_t *)uip_appdata,
+		   (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40)));
+
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+  
+  if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) {
+    ++sum;
+  }
+  if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) {
+    ++sum;
+  }
+
+  hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20);
+  
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+
+  return sum;
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h
new file mode 100644
index 000000000..b2d133f2e
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h
@@ -0,0 +1,130 @@
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c
new file mode 100644
index 000000000..f2804df95
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c
@@ -0,0 +1,427 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ * 
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+ 
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $
+ *
+ */
+
+
+#include "uip_arp.h"
+
+#include 
+
+struct arp_hdr {
+  struct uip_eth_hdr ethhdr;
+  u16_t hwtype;
+  u16_t protocol;
+  u8_t hwlen;
+  u8_t protolen;
+  u16_t opcode;
+  struct uip_eth_addr shwaddr;
+  u16_t sipaddr[2];
+  struct uip_eth_addr dhwaddr;
+  u16_t dipaddr[2]; 
+};
+
+struct ethip_hdr {
+  struct uip_eth_hdr ethhdr;
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+};
+
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#define ARP_HWTYPE_ETH 1
+
+struct arp_entry {
+  u16_t ipaddr[2];
+  struct uip_eth_addr ethaddr;
+  u8_t time;
+};
+
+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,
+				    UIP_ETHADDR1,
+				    UIP_ETHADDR2,
+				    UIP_ETHADDR3,
+				    UIP_ETHADDR4,
+				    UIP_ETHADDR5}};
+
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];
+static u16_t ipaddr[2];
+static u8_t i, c;
+
+static u8_t arptime;
+static u8_t tmpage;
+
+#define BUF   ((struct arp_hdr *)&uip_buf[0])
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the ARP module.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_init(void)
+{
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    memset(arp_table[i].ipaddr, 0, 4);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_timer(void)
+{
+  struct arp_entry *tabptr;
+  
+  ++arptime;
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&
+       arptime - tabptr->time >= UIP_ARP_MAXAGE) {
+      memset(tabptr->ipaddr, 0, 4);
+    }
+  }
+
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
+  register struct arp_entry *tabptr;
+  /* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+
+    tabptr = &arp_table[i];
+    /* Only check those entries that are actually in use. */
+    if(tabptr->ipaddr[0] != 0 &&
+       tabptr->ipaddr[1] != 0) {
+
+      /* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+      if(ipaddr[0] == tabptr->ipaddr[0] &&
+	 ipaddr[1] == tabptr->ipaddr[1]) {
+	 
+	/* An old entry found, update this and return. */
+	memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+	tabptr->time = arptime;
+
+	return;
+      }
+    }
+  }
+
+  /* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+  /* First, we try to find an unused entry in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(tabptr->ipaddr[0] == 0 &&
+       tabptr->ipaddr[1] == 0) {
+      break;
+    }
+  }
+
+  /* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+  if(i == UIP_ARPTAB_SIZE) {
+    tmpage = 0;
+    c = 0;
+    for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+      tabptr = &arp_table[i];
+      if(arptime - tabptr->time > tmpage) {
+	tmpage = arptime - tabptr->time;
+	c = i;
+      }
+    }
+    i = c;
+  }
+
+  /* Now, i is the ARP table entry which we will fill with the new
+     information. */
+  memcpy(tabptr->ipaddr, ipaddr, 4);
+  memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+  tabptr->time = arptime;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_ipin(void)
+{
+  uip_len -= sizeof(struct uip_eth_hdr);
+	
+  /* Only insert/update an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) !=
+     (uip_hostaddr[0] & uip_arp_netmask[0])) {
+    return;
+  }
+  if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) !=
+     (uip_hostaddr[1] & uip_arp_netmask[1])) {
+    return;
+  }
+  uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));
+  
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+typedef struct arp_hdr aht;
+
+void
+uip_arp_arpin(void)
+{
+  int ul;
+
+  if(uip_len < sizeof(struct arp_hdr)) {
+    uip_len = 0;
+    return;
+  }
+
+  uip_len = 0;
+  
+  switch(BUF->opcode) {
+  case HTONS(ARP_REQUEST):
+    /* ARP request. If it asked for our address, we send out a
+       reply. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+      /* The reply opcode is 2. */
+      BUF->opcode = HTONS(2);
+
+      memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);
+      memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);
+      
+      BUF->dipaddr[0] = BUF->sipaddr[0];
+      BUF->dipaddr[1] = BUF->sipaddr[1];
+      BUF->sipaddr[0] = uip_hostaddr[0];
+      BUF->sipaddr[1] = uip_hostaddr[1];
+
+      ul = BUF->hwlen;
+      BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);      
+      uip_len = sizeof(struct arp_hdr);
+    }      
+    break;
+  case HTONS(ARP_REPLY):
+    /* ARP reply. We insert or update the ARP table if it was meant
+       for us. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+
+      uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
+    }
+    break;
+  }
+
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_out(void)
+{
+  struct arp_entry *tabptr;
+  /* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP addres isn't on the
+     local network, we use the default router's IP address instead.
+
+     If not ARP table entry is found, we overwrite the original IP
+     packet with an ARP request for the IP address. */
+
+  /* Check if the destination address is on the local network. */
+  if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) !=
+     (uip_hostaddr[0] & uip_arp_netmask[0]) ||
+     (IPBUF->destipaddr[1] & uip_arp_netmask[1]) !=
+     (uip_hostaddr[1] & uip_arp_netmask[1])) {
+    /* Destination address was not on the local network, so we need to
+       use the default router's IP address instead of the destination
+       address when determining the MAC address. */
+    ipaddr[0] = uip_arp_draddr[0];
+    ipaddr[1] = uip_arp_draddr[1];
+  } else {
+    /* Else, we use the destination IP address. */
+    ipaddr[0] = IPBUF->destipaddr[0];
+    ipaddr[1] = IPBUF->destipaddr[1];
+  }
+      
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(ipaddr[0] == tabptr->ipaddr[0] &&
+       ipaddr[1] == tabptr->ipaddr[1])
+      break;
+  }
+
+  if(i == UIP_ARPTAB_SIZE) {
+    /* The destination address was not in our ARP table, so we
+       overwrite the IP packet with an ARP request. */
+
+    memset(BUF->ethhdr.dest.addr, 0xff, 6);
+    memset(BUF->dhwaddr.addr, 0x00, 6);
+    memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+    memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+    
+    BUF->dipaddr[0] = ipaddr[0];
+    BUF->dipaddr[1] = ipaddr[1];
+    BUF->sipaddr[0] = uip_hostaddr[0];
+    BUF->sipaddr[1] = uip_hostaddr[1];
+    BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */
+    BUF->hwtype = HTONS(ARP_HWTYPE_ETH);
+    BUF->protocol = HTONS(UIP_ETHTYPE_IP);
+    BUF->hwlen = 6;
+    BUF->protolen = 4;
+    BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+
+    uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+    
+    uip_len = sizeof(struct arp_hdr);
+    return;
+  }
+
+  /* Build an ethernet header. */
+  memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);
+  memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+  
+  IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);
+
+  uip_len += sizeof(struct uip_eth_hdr);
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h
new file mode 100644
index 000000000..bf9049888
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h
@@ -0,0 +1,201 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp 
+ * @{
+ */
+ 
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels 
+ */
+  
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "uip.h"
+
+
+/**
+ * Representation of a 48-bit Ethernet address.
+ */
+struct uip_eth_addr {
+  u8_t addr[6];
+} __attribute__ ((packed, aligned (1)));
+
+extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header. 
+ */
+struct uip_eth_hdr {
+  struct uip_eth_addr dest;
+  struct uip_eth_addr src;
+  u16_t type;
+} __attribute__ ((packed));
+
+#define UIP_ETHTYPE_ARP 0x0806
+#define UIP_ETHTYPE_IP  0x0800
+#define UIP_ETHTYPE_IP6 0x86dd 
+
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void uip_arp_init(void);
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+void uip_arp_ipin(void);
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void uip_arp_arpin(void);
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void uip_arp_out(void);
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void uip_arp_timer(void);
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \
+                                 uip_arp_draddr[1] = addr[1]; } while(0)
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \
+                                  uip_arp_netmask[1] = addr[1]; } while(0)
+
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \
+                                 addr[1] = uip_arp_draddr[1]; } while(0)
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \
+                                  addr[1] = uip_arp_netmask[1]; } while(0)
+
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \
+                              uip_ethaddr.addr[1] = eaddr.addr[1];\
+                              uip_ethaddr.addr[2] = eaddr.addr[2];\
+                              uip_ethaddr.addr[3] = eaddr.addr[3];\
+                              uip_ethaddr.addr[4] = eaddr.addr[4];\
+                              uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)
+
+/** @} */
+
+/**
+ * \internal Internal variables that are set using the macros
+ * uip_setdraddr and uip_setnetmask.
+ */
+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* __UIP_ARP_H__ */
+
+
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h
new file mode 100644
index 000000000..9d274d534
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h
@@ -0,0 +1,602 @@
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * "uipopt.h". This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels 
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $
+ *
+ */
+
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttypedef uIP type definitions
+ * @{
+ */
+
+/**
+ * The 8-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * char" works for most compilers.
+ */
+typedef unsigned char u8_t;
+
+/**
+ * The 16-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * short" works for most compilers.
+ */
+typedef unsigned short u16_t;
+
+/**
+ * The statistics data type.
+ *
+ * This datatype determines how high the statistics counters are able
+ * to count.
+ */
+typedef unsigned short uip_stats_t;
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptstaticconf Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are appliciable only
+ * if uIP should be run over Ethernet.
+ *
+ * All of these should be changed to suit your project.
+*/
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDADDR    1
+
+/**
+ * Ping IP address asignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_PINGADDRCONF 0
+
+#if 0
+#define UIP_IPADDR0     172U /**< The first octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR1     25U /**< The second octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR2     218U   /**< The third octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR3     202U  /**< The fourth octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_NETMASK0    255 /**< The first octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK1    255 /**< The second octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK2    255 /**< The third octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK3    0   /**< The fourth octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+
+#define UIP_DRIPADDR0   192 /**< The first octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR1   168 /**< The second octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR2   0   /**< The third octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR3   1   /**< The fourth octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#else
+
+#define UIP_IPADDR0     172U  /**< The first octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR1     25U /**< The second octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR2     218U   /**< The third octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR3     202U  /**< The fourth octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_NETMASK0    255 /**< The first octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK1    255 /**< The second octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK2    255 /**< The third octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK3    0   /**< The fourth octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_DRIPADDR0   172 /**< The first octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR1   25 /**< The second octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR2   218   /**< The third octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR3   3   /**< The fourth octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#endif
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR 0
+
+#define UIP_ETHADDR0    0x00  /**< The first octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR1    0xbd  /**< The second octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR2    0x3b  /**< The third octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR3    0x33  /**< The fourth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR4    0x05  /**< The fifth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR5    0x71  /**< The sixth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptip IP configuration options
+ * @{
+ *
+ */
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL         255
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additonal amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#define UIP_REASSEMBLY 0
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE 40
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptudp UDP configuration options
+ * @{
+ *
+ * \note The UDP support in uIP is still not entirely complete; there
+ * is no support for sending or receiving broadcast or multicast
+ * packets, but it works well enough to support a number of vital
+ * applications such as DNS queries, though
+ */
+
+/**
+ * Toggles wether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP           0
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CHECKSUMS 0
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CONNS    2
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_APPCALL  udp_appcall
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttcp TCP configuration options
+ * @{
+ */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#define UIP_ACTIVE_OPEN 1
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximatly 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_CONNS       20
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_LISTENPORTS 10
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+#define UIP_RECEIVE_WINDOW   32768
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+#define UIP_URGDATA      1
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO         3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX      8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX      3
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40.
+ */
+#define UIP_TCP_MSS     (UIP_BUFSIZE - UIP_LLH_LEN - 40)
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configiration option has no real implication, and it should be
+ * left untouched.
+ */ 
+#define UIP_TIME_WAIT_TIMEOUT 120
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptarp ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#define UIP_ARPTAB_SIZE 8
+
+/**
+ * The maxium age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE 120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptgeneral General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1500 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#define UIP_BUFSIZE     2048
+
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#define UIP_STATISTICS  1
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#define UIP_LOGGING 0
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void uip_log(char *msg);
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_LLH_LEN     14
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptcpu CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN  3412
+#endif /* LITTLE_ENDIAN */
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN     1234
+#endif /* BIGE_ENDIAN */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either BIG_ENDIAN (Motorola byte order) or
+ * LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+#ifndef BYTE_ORDER
+#define BYTE_ORDER     LITTLE_ENDIAN
+#endif /* BYTE_ORDER */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptapp Appication specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the size of the application
+ * structure with the UIP_APPSTATE_SIZE macro.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+void httpd_appcall(void);
+#define UIP_APPCALL     httpd_appcall
+
+struct httpd_state {
+  u8_t state; 
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+ \endcode
+ */
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var #define UIP_APPSTATE_SIZE
+ *
+ * The size of the application state that is to be stored in the
+ * uip_conn structure.
+ */
+/** @} */
+
+/* Include the header file for the application program that should be
+   used. If you don't use the example web server, you should change
+   this. */
+#include "httpd.h"
+
+
+#endif /* __UIPOPT_H__ */
diff --git a/License/license.txt b/License/license.txt
new file mode 100644
index 000000000..d846b800b
--- /dev/null
+++ b/License/license.txt
@@ -0,0 +1,395 @@
+The FreeRTOS source code is licensed by the modified GNU General Public 
+License (GPL) text provided below.  The FreeRTOS download also includes 
+demo application source code, some of which is provided by third parties 
+AND IS LICENSED SEPARATELY FROM FREERTOS.  
+
+For the avoidance of any doubt refer to the comment included at the top
+of each source and header file for license and copyright information.
+
+This is a list of files for which Richard Barry is not the copyright owner
+and are NOT COVERED BY THE GPL.
+
+
+1) Various header files provided by silicon manufacturers and tool vendors
+   that define processor specific memory addresses and utility macros.
+   Permission has been granted by the various copyright holders for these
+   files to be included in the FreeRTOS download.  Users must ensure license
+   conditions are adhered to for any use other than compilation of the 
+   FreeRTOS demo application.
+
+2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels.
+   Users must ensure the open source license conditions stated at the top 
+   of each uIP source file is understood and adhered to.
+
+3) The lwIP TCP/IP stack the copyright of which is held by the Swedish 
+   Institute of Computer Science.  Users must ensure the open source license 
+   conditions stated at the top  of each lwIP source file is understood and 
+   adhered to.
+
+4) All files contained within the FreeRTOS\Demo\CORTEX_LM3S102_GCC\hw_include
+   directory.  The copyright of these files is owned by Luminary Micro.
+   Permission has been granted by Luminary Micro for these files to be 
+   included in the FreeRTOS download.  Users must ensure the license 
+   conditions stated at the top of the human readable files are understood 
+   and adhered at all times for all files in that directory.
+
+
+Errors and omissions should be reported to Richard Barry, contact details for
+whom can be obtained from http://www.FreeRTOS.org.
+
+
+
+
+
+The GPL license text follows.
+
+An exception to this license exists that can be applied should you 
+wish to use FreeRTOS in a work that includes commercial or 
+proprietary code without being obliged to provide source code for the 
+proprietary components.  See the licensing section of 
+http://www.FreeRTOS.org for full details.
+--------------------------------------------------------------------
+
+
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
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+
+  Finally, any free program is threatened constantly by software
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+
+  The precise terms and conditions for copying, distribution and
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+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
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+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    
+    Copyright (C)   
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  , 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
+
diff --git a/Source/croutine.c b/Source/croutine.c
new file mode 100644
index 000000000..c758a8e4d
--- /dev/null
+++ b/Source/croutine.c
@@ -0,0 +1,342 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static xList xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static xList xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static xList * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static xList * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static xList xPendingReadyList;											/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+corCRCB * pxCurrentCoRoutine = NULL;
+static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0;
+static portTickType xCoRoutineTickCount = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue 
+ * for the priority.  It is inserted at the end of the list.  
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}	
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static inline void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to 
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time - 
+ * meaning once one co-routine has been found whose timer has not expired 
+ * we need not look any further down the list.
+ */
+static inline void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex )
+{
+portBASE_TYPE xReturn;
+corCRCB *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the xListItem.  
+		This is so we can get back to the containing CRCB from a generic item 
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+	
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );
+		
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{		
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+	
+	return xReturn;	
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList )
+{
+portTickType xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static inline void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access 
+	the	ready lists itself. */
+	while( !listLIST_IS_EMPTY( &xPendingReadyList ) )
+	{
+		corCRCB *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{	
+			pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) );			
+			vListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		vListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );	
+	}
+}
+/*-----------------------------------------------------------*/
+
+static inline void prvCheckDelayedList( void )
+{
+static portTickType xLastTickCount, xPassedTicks;
+corCRCB *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			xList * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL )
+		{	
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )				
+			{			
+				/* Timeout not yet expired. */																			
+				break;																				
+			}																						
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical 
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following 
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				vListRemove( &( pxCRCB->xGenericListItem ) );											
+
+				/* Is the co-routine waiting on an event also? */												
+				if( pxCRCB->xEventListItem.pvContainer )													
+				{															
+					vListRemove( &( pxCRCB->xEventListItem ) );											
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );													
+		}																									
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+unsigned portBASE_TYPE uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( xList * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( xList * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( xList * ) &xPendingReadyList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the 
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList )
+{
+corCRCB *pxUnblockedCRCB;
+portBASE_TYPE xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list. */
+	pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	vListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h
new file mode 100644
index 000000000..1036a4001
--- /dev/null
+++ b/Source/include/FreeRTOS.h
@@ -0,0 +1,111 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+
+/* 
+ * Include the generic headers required for the FreeRTOS port being used. 
+ */
+#include 
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+
+
+
+
+
+
+/*
+ * Check all the required application specific macros have been defined. 
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configUSE_PREEMPTION
+	#error Missing definition:  configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+	#error Missing definition:  configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+	#error Missing definition:  configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+	#error  Missing definition:  configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+	#error Missing definition:  INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+	#error Missing definition:  INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelete		
+	#error Missing definition:  INCLUDE_vTaskDelete		 should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskCleanUpResources
+	#error Missing definition:  INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskSuspend	
+	#error Missing definition:  INCLUDE_vTaskSuspend	 should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+	#error Missing definition:  INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+	#error Missing definition:  INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+	#error Missing definition:  configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#endif
diff --git a/Source/include/croutine.h b/Source/include/croutine.h
new file mode 100644
index 000000000..88b47383f
--- /dev/null
+++ b/Source/include/croutine.h
@@ -0,0 +1,713 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#include "list.h"
+
+/* Used to hide the implementation of the co-routine control block.  The 
+control block structure however has to be included in the header due to 
+the macro implementation of the co-routine functionality. */
+typedef void * xCoRoutineHandle;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 		pxCoRoutineFunction;
+	xListItem				xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	xListItem				xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	unsigned portBASE_TYPE 	uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	unsigned portBASE_TYPE 	uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	unsigned portSHORT 		uxState;			/*< Used internally by the co-routine implementation. */
+} corCRCB; /* Co-routine control block.  Note must be identical in size down to uxPriority with tskTCB. */
+
+/**
+ * croutine. h
+ *
+ portBASE_TYPE xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 unsigned portBASE_TYPE uxPriority,
+                                 unsigned portBASE_TYPE uxIndex
+                               );

+ *
+ * Create a new co-routine and add it to the list of co-routines that are 
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine 
+ * functions require special syntax - see the co-routine section of the WEB 
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which 
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how long to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ unsigned char ucParameterToPass;
+ xTaskHandle xHandle;
+		
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }  
+ }
+   

+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex );
+
+
+/**
+ * croutine. h
+ *
+ void vCoRoutineSchedule( void );

+ *
+ * Run a co-routine.
+ * 
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one 
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then 
+ * vCoRoutineSchedule should be called from the idle task (in an idle task 
+ * hook).
+ *
+ * Example usage:
+   
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to 
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ 

+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * 
+ crSTART( xCoRoutineHandle xHandle );

+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portLONG ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * 
+ crEND();

+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portLONG ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation 
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *
+ crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );

+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay 
+ * for.  The actual amount of time this equates to is defined by 
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_RATE_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( xTicksToDelay > 0 )																\
+	{																					\
+		vCoRoutineAddToDelayedList( xTicksToDelay, NULL );								\
+	}																					\
+	crSET_STATE0( xHandle );
+
+/**
+ * 
+ crQUEUE_SEND( 
+                  xCoRoutineHandle xHandle, 
+                  xQueueHandle pxQueue, 
+                  void *pvItemToQueue, 
+                  portTickType xTicksToWait, 
+                  portBASE_TYPE *pxResult 
+             )

+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine 
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.  
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas  
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on 
+ * passing data between tasks and co-routines and between ISR's and 
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.  
+ * The handle is obtained as the return value when the queue is created using 
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block 
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined 
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant 
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an 
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portBASE_TYPE xNumberToPost = 0;
+ static portBASE_TYPE xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+ 
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }

+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait );					\
+	if( *pxResult == errQUEUE_BLOCKED )													\
+	{																					\
+		crSET_STATE0( xHandle );														\
+		*pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 );							\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( xHandle );														\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_RECEIVE( 
+                     xCoRoutineHandle xHandle, 
+                     xQueueHandle pxQueue, 
+                     void *pvBuffer, 
+                     portTickType xTicksToWait, 
+                     portBASE_TYPE *pxResult 
+                 )

+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine 
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.  
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas  
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on 
+ * passing data between tasks and co-routines and between ISR's and 
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.  
+ * The handle is obtained as the return value when the queue is created using 
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block 
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined 
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant 
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ 
+ // A co-routine receives the number of an LED to flash from a queue.  It 
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portBASE_TYPE xResult;
+ static unsigned portBASE_TYPE uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }

+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait );						\
+	if( *pxResult == errQUEUE_BLOCKED ) 												\
+	{																					\
+		crSET_STATE0( xHandle );														\
+		*pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 );							\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( xHandle );														\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_SEND_FROM_ISR( 
+                            xQueueHandle pxQueue, 
+                            void *pvItemToQueue, 
+                            portBASE_TYPE xCoRoutinePreviouslyWoken
+                       )

+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the 
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() 
+ * functions used by tasks.  
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and 
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on 
+ * passing data between tasks and co-routines and between ISR's and 
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ * 
+ * @param pvItemToQueue A pointer to the item that is to be placed on the 
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.  
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is 
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ portCHAR cRxedChar;
+ portBASE_TYPE xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+    
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ portCHAR cRxedChar;
+ portBASE_TYPE xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+        
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE 
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }

+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )
+
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_SEND_FROM_ISR( 
+                            xQueueHandle pxQueue, 
+                            void *pvBuffer, 
+                            portBASE_TYPE * pxCoRoutineWoken
+                       )

+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the 
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() 
+ * functions used by tasks.  
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and 
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data 
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on 
+ * passing data between tasks and co-routines and between ISR's and 
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ * 
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a 
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise 
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ 
+ // A co-routine that posts a character to a queue then blocks for a fixed 
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static portCHAR cCharToTx = 'a';
+ portBASE_TYPE xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+    
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period. 
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ portCHAR cCharToTx;
+ portBASE_TYPE xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }

+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the 
+ * prototype appears here.  The function should not be used by application 
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the 
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList );
+
+
+#endif /* CO_ROUTINE_H */
diff --git a/Source/include/list.h b/Source/include/list.h
new file mode 100644
index 000000000..3f3aa7b3c
--- /dev/null
+++ b/Source/include/list.h
@@ -0,0 +1,270 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * xLists can only store pointers to xListItems.  Each xListItem contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST_ITEM
+{
+	portTickType xItemValue;				/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	volatile struct xLIST_ITEM * pxNext;	/*< Pointer to the next xListItem in the list. */
+	volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */
+	void * pvOwner;							/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	void * pvContainer;						/*< Pointer to the list in which this list item is placed (if any). */
+};
+typedef struct xLIST_ITEM xListItem;		/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	portTickType xItemValue;
+	volatile struct xLIST_ITEM *pxNext;
+	volatile struct xLIST_ITEM *pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM xMiniListItem;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	volatile unsigned portBASE_TYPE uxNumberOfItems;
+	volatile xListItem * pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */
+	volatile xMiniListItem xListEnd;		/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+} xList;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( pxListItem )->pvOwner = ( void * ) pxOwner
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )		( pxListItem )->xItemValue = xValue
+
+/*
+ * Access macro the retrieve the value of the list item.  The value can
+ * represent anything - for example a the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )				( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )				( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )		( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entries pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )									\
+	/* Increment the index to the next item and return the item, ensuring */			\
+	/* we don't return the marker used at the end of the list.  */						\
+	( pxList )->pxIndex = ( pxList )->pxIndex->pxNext;									\
+	if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) )				\
+	{																					\
+		( pxList )->pxIndex = ( pxList )->pxIndex->pxNext;								\
+	}																					\
+	pxTCB = ( pxList )->pxIndex->pvOwner
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE is the list item is in the list, otherwise pdFALSE.
+ * pointer against
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( xList *pxList );
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( xListItem *pxItem );
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item to that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( xList *pxList, xListItem *pxNewListItem );
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pvIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pvIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pvIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem );
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param vListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * \page vListRemove vListRemove
+ * \ingroup LinkedList
+ */
+void vListRemove( xListItem *pxItemToRemove );
+
+
+
+#endif
+
diff --git a/Source/include/portable.h b/Source/include/portable.h
new file mode 100644
index 000000000..74450cc8d
--- /dev/null
+++ b/Source/include/portable.h
@@ -0,0 +1,172 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http:www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http:www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Include the macro file relevant to the port being used. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "..\..\source\portable\MPLAB\PIC18F\portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef KEIL_ARM7
+	#include "..\..\Source\portable\Keil\ARM7\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif	
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize );
+void vPortFree( void *pv );
+void vPortInitialiseBlocks( void );
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+portBASE_TYPE xPortStartScheduler( void );
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void );
+
+
+#endif /* PORTABLE_H */
+
diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h
new file mode 100644
index 000000000..354f96e54
--- /dev/null
+++ b/Source/include/projdefs.h
@@ -0,0 +1,54 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/* Defines to prototype to which task functions must conform. */
+typedef void (*pdTASK_CODE)( void * );
+
+#define pdTRUE		( 1 )
+#define pdFALSE		( 0 )
+
+#define pdPASS		( 1 )
+#define pdFAIL		( 0 )
+
+/* Error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errNO_TASK_TO_RUN						( -2 )
+#define errQUEUE_FULL							( -3 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+#endif
+
+
diff --git a/Source/include/queue.h b/Source/include/queue.h
new file mode 100644
index 000000000..5a7b96779
--- /dev/null
+++ b/Source/include/queue.h
@@ -0,0 +1,471 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+typedef void * xQueueHandle;
+
+/**
+ * queue. h
+ * 
+ xQueueHandle xQueueCreate( 
+                              unsigned portBASE_TYPE uxQueueLength, 
+                              unsigned portBASE_TYPE uxItemSize 
+                          );
+ * 

+ *
+ * Creates a new queue instance.  This allocates the storage required by the
+ * new queue and returns a handle for the queue.
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.  
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly 
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ * 
+ * Example usage:
+   
+ struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+    if( xQueue1 == 0 )
+    {
+        // Queue was not created and must not be used.
+    }
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue2 == 0 )
+    {
+        // Queue was not created and must not be used.
+    }
+
+    // ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );
+
+/**
+ * queue. h
+ * 
+ portBASE_TYPE xQueueSend( 
+                             xQueueHandle xQueue, 
+                             const void * pvItemToQueue, 
+                             portTickType xTicksToWait 
+                         );
+ * 

+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ * 
+ * @param pvItemToQueue A pointer to the item that is to be placed on the 
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0.  The
+ * time is defined in tick periods so the constant portTICK_RATE_MS 
+ * should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ unsigned portLONG ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+    // ...
+
+    if( xQueue1 != 0 )
+    {
+        // Send an unsigned long.  Wait for 10 ticks for space to become 
+        // available if necessary.
+        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
+        {
+            // Failed to post the message, even after 10 ticks.
+        }
+    }
+
+    if( xQueue2 != 0 )
+    {
+        // Send a pointer to a struct AMessage object.  Don't block if the
+        // queue is already full.
+        pxMessage = & xMessage;
+        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
+    }
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait );
+
+/**
+ * queue. h
+ * 
+ portBASE_TYPE xQueueReceive( 
+                                xQueueHandle xQueue, 
+                                void *pvBuffer, 
+                                portTickType xTicksToWait 
+                            );

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of 
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param pxQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ * 
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.    The time is defined in tick periods so the constant 
+ * portTICK_RATE_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ xQueueHandle xQueue;
+ 
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Send a pointer to a struct AMessage object.  Don't block if the
+    // queue is already full.
+    pxMessage = & xMessage;
+    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+    if( xQueue != 0 )
+    {
+        // Receive a message on the created queue.  Block for 10 ticks if a
+        // message is not immediately available.
+        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
+        {
+            // pcRxedMessage now points to the struct AMessage variable posted
+            // by vATask.
+        }
+    }
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait );
+
+/**
+ * queue. h
+ * 
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ * 
+ * @return The number of messages available in the queue.
+ *
+ * \page uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
+
+/**
+ * queue. h
+ * 
void vQueueDelete( xQueueHandle xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ * 
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \page vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( xQueueHandle xQueue );
+
+/**
+ * queue. h
+ * 
+ portBASE_TYPE xQueueSendFromISR( 
+                                    xQueueHandle pxQueue, 
+                                    const void *pvItemToQueue, 
+                                    portBASE_TYPE xTaskPreviouslyWoken 
+                                );
+ 

+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ * 
+ * @param pvItemToQueue A pointer to the item that is to be placed on the 
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param cTaskPreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.  See the file serial .c in the
+ * PC port for a good example of this mechanism.
+ *
+ * @return pdTRUE if a task was woken by posting onto the queue.  This is 
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ portCHAR cIn;
+ portBASE_TYPE xTaskWokenByPost;
+
+    // We have not woken a task at the start of the ISR.
+    cTaskWokenByPost = pdFALSE;
+
+    // Loop until the buffer is empty.
+    do
+    {
+        // Obtain a byte from the buffer.
+        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
+
+        // Post the byte.  The first time round the loop cTaskWokenByPost
+        // will be pdFALSE.  If the queue send causes a task to wake we do
+        // not want the task to run until we have finished the ISR, so
+        // xQueueSendFromISR does not cause a context switch.  Also we 
+        // don't want subsequent posts to wake any other tasks, so we store
+        // the return value back into cTaskWokenByPost so xQueueSendFromISR
+        // knows not to wake any task the next iteration of the loop.
+        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
+
+    } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+    // Now the buffer is empty we can switch context if necessary.
+    if( cTaskWokenByPost )
+    {
+        taskYIELD ();
+    }
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken );
+
+/**
+ * queue. h
+ * 
+ portBASE_TYPE xQueueReceiveFromISR( 
+                                       xQueueHandle pxQueue, 
+                                       void *pvBuffer, 
+                                       portBASE_TYPE *pxTaskWoken 
+                                   ); 
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param pxQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ * 
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ 
+ xQueueHandle xQueue;
+ 
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ portCHAR cValueToPost;
+ const portTickType xBlockTime = ( portTickType )0xff;
+
+    // Create a queue capable of containing 10 characters.
+    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Post some characters that will be used within an ISR.  If the queue
+    // is full then this task will block for xBlockTime ticks.
+    cValueToPost = 'a';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+    cValueToPost = 'b';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+
+    // ... keep posting characters ... this task may block when the queue
+    // becomes full.
+
+    cValueToPost = 'c';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+ }
+
+ // ISR that outputs all the characters received on the queue. 
+ void vISR_Routine( void )
+ {
+ portBASE_TYPE xTaskWokenByReceive = pdFALSE;
+ portCHAR cRxedChar;
+
+    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+    {
+        // A character was received.  Output the character now.
+        vOutputCharacter( cRxedChar );
+
+        // If removing the character from the queue woke the task that was 
+        // posting onto the queue cTaskWokenByReceive will have been set to
+        // pdTRUE.  No matter how many times this loop iterates only one
+        // task will be woken.
+    }
+
+    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
+    {
+        taskYIELD ();
+    }
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
+
+
+/* 
+ * The functions defined above are for passing data to and from tasks.  The 
+ * functions below are the equivalents for passing data to and from 
+ * co-rtoutines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );
+
+#endif
+
diff --git a/Source/include/semphr.h b/Source/include/semphr.h
new file mode 100644
index 000000000..e8aa5a4ff
--- /dev/null
+++ b/Source/include/semphr.h
@@ -0,0 +1,289 @@
+/*
+	FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#include "queue.h"
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+typedef xQueueHandle xSemaphoreHandle;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( unsigned portCHAR ) 1 )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( unsigned portCHAR ) 0 )
+#define semGIVE_BLOCK_TIME					( ( portTickType ) 0 )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )

+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type xSemaphoreHandle.
+ *
+ * Example usage:
+ 
+ xSemaphoreHandle xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.  
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#define vSemaphoreCreateBinary( xSemaphore )		{																							\
+														xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH );	\
+														if( xSemaphore != NULL )																\
+														{																						\
+															xSemaphoreGive( xSemaphore );														\
+														}																						\
+													}
+
+/**
+ * semphr. h
+ * xSemaphoreTake( 
+ *                   xSemaphoreHandle xSemaphore, 
+ *                   portTickType xBlockTime 
+ *               )
+ * + * Macro to obtain a semaphore. The semaphore must of been created using + * vSemaphoreCreateBinary (). + * + * @param xSemaphore A handle to the semaphore being obtained. This is the + * handle returned by vSemaphoreCreateBinary (); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_RATE_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + 
+ xSemaphoreHandle xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.	
+        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the 
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) + +/** + * semphr. h + * 
xSemaphoreGive( xSemaphoreHandle xSemaphore )
+ * + * Macro to release a semaphore. The semaphore must of been created using + * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). + * + * This must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned by vSemaphoreCreateBinary (); + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + 
+ xSemaphoreHandle xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+
+ * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) + +/** + * semphr. h + * 
+ xSemaphoreGiveFromISR( 
+                          xSemaphoreHandle xSemaphore, 
+                          portSHORT sTaskPreviouslyWoken 
+                      )
+ * + * Macro to release a semaphore. The semaphore must of been created using + * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned by vSemaphoreCreateBinary (); + * + * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls + * to xSemaphoreGiveFromISR () from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of using xSemaphoreGiveFromISR (). + * + * @return pdTRUE if a task was woken by releasing the semaphore. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ #define LONG_TIME 0xffff
+ #define TICKS_TO_WAIT	10
+ xSemaphoreHandle xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks or a timer.  The semaphore 
+        // was created before this task was started
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute 
+            // again.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static unsigned portCHAR ucLocalTickCount = 0;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGive( xSemaphore );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+ }
+
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) + + +#endif + diff --git a/Source/include/task.h b/Source/include/task.h new file mode 100644 index 000000000..a47b0c6db --- /dev/null +++ b/Source/include/task.h @@ -0,0 +1,906 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef TASK_H +#define TASK_H + +#include "portable.h" +#include "list.h" + +/*----------------------------------------------------------- + * MACROS AND DEFINITIONS + *----------------------------------------------------------*/ + +#define tskKERNEL_VERSION_NUMBER "V3.2.4" + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an xTaskHandle variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \page xTaskHandle xTaskHandle + * \ingroup Tasks + */ +typedef void * xTaskHandle; + +/* + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \page taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \page taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \page taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + + +/*----------------------------------------------------------- + * TASK CREATION API + *----------------------------------------------------------*/ + +/** + * task. h + *
+ portBASE_TYPE xTaskCreate(
+                              pdTASK_CODE pvTaskCode,
+                              const portCHAR * const pcName,
+                              unsigned portSHORT usStackDepth,
+                              void *pvParameters,
+                              unsigned portBASE_TYPE uxPriority,
+                              xTaskHandle *pvCreatedTask
+                          );
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. + * + * @param pvCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file errors. h + * + * Example usage: + 
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+     }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ unsigned char ucParameterToPass;
+ xTaskHandle xHandle;
+		
+     // Create the task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+		
+     // Use the handle to delete the task.
+     vTaskDelete( xHandle );
+ }
+
+ * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); + +/** + * task. h + * 
void vTaskDelete( xTaskHandle pxTask );
+ * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernels management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param pxTask The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + 
+ void vOtherFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create the task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // Use the handle to delete the task.
+     vTaskDelete( xHandle );
+ }
+
+ * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( xTaskHandle pxTask ); + + +/*----------------------------------------------------------- + * TASK CONTROL API + *----------------------------------------------------------*/ + +/** + * task. h + * 
void vTaskDelay( portTickType xTicksToDelay );
+ * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_RATE_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + 
+ // Wait 10 ticks before performing an action.
+ // NOTE:
+ // This is for demonstration only and would be better achieved
+ // using vTaskDelayUntil ().
+ void vTaskFunction( void * pvParameters )
+ {
+ portTickType xDelay, xNextTime;
+
+     // Calc the time at which we want to perform the action
+     // next.
+     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
+
+     for( ;; )
+     {
+         xDelay = xNextTime - xTaskGetTickCount ();
+         xNextTime += ( portTickType ) 10;
+
+         // Guard against overflow
+         if( xDelay <= ( portTickType ) 10 )
+         {
+             vTaskDelay( xDelay );
+         }
+
+         // Perform action here.
+     }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( portTickType xTicksToDelay ); + +/** + * task. h + * 
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
+ * + * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by cyclical + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The constant portTICK_RATE_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within vTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * Example usage: + 
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ portTickType xLastWakeTime;
+ const portTickType xFrequency = 10;
+
+     // Initialise the xLastWakeTime variable with the current time.
+     xLastWakeTime = xTaskGetTickCount ();
+     for( ;; )
+     {
+         // Wait for the next cycle.
+         vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+         // Perform action here.
+     }
+ }
+
+ * \defgroup vTaskDelayUntil vTaskDelayUntil + * \ingroup TaskCtrl + */ +void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); + +/** + * task. h + * 
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
+ * + * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param pxTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of pxTask. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to obtain the priority of the created task.
+     // It was created with tskIDLE_PRIORITY, but may have changed
+     // it itself.
+     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+     {
+         // The task has changed it's priority.
+     }
+
+     // ...
+
+     // Is our priority higher than the created task?
+     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+     {
+         // Our priority (obtained using NULL handle) is higher.
+     }
+ }
+
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); + +/** + * task. h + * 
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
+ * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param pxTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+     // ...
+
+     // Use the handle to raise the priority of the created task.
+     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+     // ...
+
+     // Use a NULL handle to raise our priority to the same value.
+     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+
+ * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); + +/** + * task. h + * 
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to suspend the created task.
+     vTaskSuspend( xHandle );
+
+     // ...
+		
+     // The created task will not run during this period, unless
+     // another task calls vTaskResume( xHandle ).
+		
+     //...
+		
+
+     // Suspend ourselves.
+     vTaskSuspend( NULL );
+
+     // We cannot get here unless another task calls vTaskResume
+     // with our handle as the parameter.
+ }
+
+ * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( xTaskHandle pxTaskToSuspend ); + +/** + * task. h + * 
void vTaskResume( xTaskHandle pxTaskToResume );
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one of more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param pxTaskToResume Handle to the task being readied. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to suspend the created task.
+     vTaskSuspend( xHandle );
+
+     // ...
+	
+     // The created task will not run during this period, unless
+     // another task calls vTaskResume( xHandle ).
+		
+     //...
+		
+
+     // Resume the suspended task ourselves.
+     vTaskResume( xHandle );
+
+     // The created task will once again get microcontroller processing
+     // time in accordance with it priority within the system.
+ }
+
+ * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( xTaskHandle pxTaskToResume ); + +/*----------------------------------------------------------- + * SCHEDULER CONTROL + *----------------------------------------------------------*/ + +/** + * task. h + * 
void vTaskStartScheduler( void );
+ * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. This function + * does not return until an executing task calls vTaskEndScheduler (). + * + * At least one task should be created via a call to xTaskCreate () + * before calling vTaskStartScheduler (). The idle task is created + * automatically when the first application task is created. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + 
+ void vAFunction( void )
+ {
+     // Create at least one task before starting the kernel.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+     // Start the real time kernel with preemption.
+     vTaskStartScheduler ();
+
+     // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+
+ * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ); + +/** + * task. h + * 
void vTaskEndScheduler( void );
+ * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + 
+ void vTaskCode( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // At some point we want to end the real time kernel processing
+         // so call ...
+         vTaskEndScheduler ();
+     }
+ }
+
+ void vAFunction( void )
+ {
+     // Create at least one task before starting the kernel.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+     // Start the real time kernel with preemption.
+     vTaskStartScheduler ();
+
+     // Will only get here when the vTaskCode () task has called
+     // vTaskEndScheduler ().  When we get here we are back to single task
+     // execution.
+ }
+
+ * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ); + +/** + * task. h + * 
void vTaskSuspendAll( void );
+ * + * Suspends all real time kernel activity while keeping interrupts (including the + * kernel tick) enabled. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * Example usage: + 
+ void vTask1( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // ...
+
+         // At some point the task wants to perform a long operation during
+         // which it does not want to get swapped out.  It cannot use
+         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+         // operation may cause interrupts to be missed - including the
+         // ticks.
+
+         // Prevent the real time kernel swapping out the task.
+         vTaskSuspendAll ();
+
+         // Perform the operation here.  There is no need to use critical
+         // sections as we have all the microcontroller processing time.
+         // During this time interrupts will still operate and the kernel
+         // tick count will be maintained.
+
+         // ...
+
+         // The operation is complete.  Restart the kernel.
+         xTaskResumeAll ();
+     }
+ }
+
+ * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ); + +/** + * task. h + * 
portCHAR xTaskResumeAll( void );
+ * + * Resumes real time kernel activity following a call to vTaskSuspendAll (). + * After a call to vTaskSuspendAll () the kernel will take control of which + * task is executing at any time. + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + 
+ void vTask1( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // ...
+
+         // At some point the task wants to perform a long operation during
+         // which it does not want to get swapped out.  It cannot use
+         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+         // operation may cause interrupts to be missed - including the
+         // ticks.
+
+         // Prevent the real time kernel swapping out the task.
+         vTaskSuspendAll ();
+
+         // Perform the operation here.  There is no need to use critical
+         // sections as we have all the microcontroller processing time.
+         // During this time interrupts will still operate and the real
+         // time kernel tick count will be maintained.
+
+         // ...
+
+         // The operation is complete.  Restart the kernel.  We want to force
+         // a context switch - but there is no point if resuming the scheduler
+         // caused a context switch already.
+         if( !xTaskResumeAll () )
+         {
+              taskYIELD ();
+         }
+     }
+ }
+
+ * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +signed portBASE_TYPE xTaskResumeAll( void ); + + +/*----------------------------------------------------------- + * TASK UTILITIES + *----------------------------------------------------------*/ + +/** + * task. h + * 
volatile portTickType xTaskGetTickCount( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \page xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +portTickType xTaskGetTickCount( void ); + +/** + * task. h + * 
unsigned portSHORT uxTaskGetNumberOfTasks( void );
+ * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); + +/** + * task. h + * 
void vTaskList( portCHAR *pcWriteBuffer );
+ * + * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend + * must all be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * NOTE: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ascii form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \page vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( signed portCHAR *pcWriteBuffer ); + +/** + * task. h + * 
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
+ * + * Starts a real time kernel activity trace. The trace logs the identity of + * which task is running when. + * + * The trace file is stored in binary format. A separate DOS utility called + * convtrce.exe is used to convert this into a tab delimited text file which + * can be viewed and plotted in a spread sheet. + * + * @param pcBuffer The buffer into which the trace will be written. + * + * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue + * until either the buffer in full, or ulTaskEndTrace () is called. + * + * \page vTaskStartTrace vTaskStartTrace + * \ingroup TaskUtils + */ +void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); + +/** + * task. h + * 
unsigned portLONG ulTaskEndTrace( void );
+ * + * Stops a kernel activity trace. See vTaskStartTrace (). + * + * @return The number of bytes that have been written into the trace buffer. + * + * \page usTaskEndTrace usTaskEndTrace + * \ingroup TaskUtils + */ +unsigned portLONG ulTaskEndTrace( void ); + + +/*----------------------------------------------------------- + * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES + *----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. + */ +inline void vTaskIncrementTick( void ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks,the constant + * portTICK_RATE_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList () will be called if either an event occurs to + * unblock a task, or the block timeout period expires. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 + * for this function to be available. + * See the configuration section for more information. + * + * Empties the ready and delayed queues of task control blocks, freeing the + * memory allocated for the task control block and task stacks as it goes. + */ +void vTaskCleanUpResources( void ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +inline void vTaskSwitchContext( void ); + +/* + * Return the handle of the calling task. + */ +xTaskHandle xTaskGetCurrentTaskHandle( void ); + + +#endif /* TASK_H */ + + + diff --git a/Source/list.c b/Source/list.c new file mode 100644 index 000000000..e72689901 --- /dev/null +++ b/Source/list.c @@ -0,0 +1,200 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.0 + + + Removed the volatile modifier from the function parameters. This was + only ever included to prevent compiler warnings. Now warnings are + removed by casting parameters where the calls are made. + + + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been + removed from the c file and added as macros to the h file. + + + uxNumberOfItems has been added to the list structure. This removes the + need for a pointer comparison when checking if a list is empty, and so + is slightly faster. + + + Removed the NULL check in vListRemove(). This makes the call faster but + necessitates any application code utilising the list implementation to + ensure NULL pointers are not passed. + +Changes from V2.0.0 + + + Double linked the lists to allow faster removal item removal. + +Changes from V2.6.1 + + + Make use of the new portBASE_TYPE definition where ever appropriate. + +Changes from V3.0.0 + + + API changes as described on the FreeRTOS.org WEB site. + +Changes from V3.2.4 + + + Removed the pxHead member of the xList structure. This always pointed + to the same place so has been removed to free a few bytes of RAM. + + + Introduced the xMiniListItem structure that does not include the + xListItem members that are not required by the xListEnd member of a list. + Again this was done to reduce RAM usage. + + + Changed the volatile definitions of some structure members to clean up + the code where the list structures are used. +*/ + +#include +#include "FreeRTOS.h" +#include "list.h" + +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( xList *pxList ) +{ + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); + pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); + + pxList->uxNumberOfItems = 0; +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( xListItem *pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pvContainer = NULL; +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) +{ +volatile xListItem * pxIndex; + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by + the pxIndex member. */ + pxIndex = pxList->pxIndex; + + pxNewListItem->pxNext = pxIndex->pxNext; + pxNewListItem->pxPrevious = pxList->pxIndex; + pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; + pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; + pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( xList *pxList, xListItem *pxNewListItem ) +{ +volatile xListItem *pxIterator; +portTickType xValueOfInsertion; + + /* Insert the new list item into the list, sorted in ulListItem order. */ + xValueOfInsertion = pxNewListItem->xItemValue; + + /* If the list already contains a list item with the same item value then + the new list item should be placed after it. This ensures that TCB's which + are stored in ready lists (all of which have the same ulListItem value) + get an equal share of the CPU. However, if the xItemValue is the same as + the back marker the iteration loop below will not end. This means we need + to guard against this by checking the value first and modifying the + algorithm slightly if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue < xValueOfInsertion; pxIterator = pxIterator->pxNext ) + { + /* There is nothing to do here, we are just iterating to the + wanted insertion position. */ + } + } + else + { + for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) + { + /* There is nothing to do here, we are just iterating to the + wanted insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListRemove( xListItem *pxItemToRemove ) +{ +xList * pxList; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* The list item knows which list it is in. Obtain the list from the list + item. */ + pxList = ( xList * ) pxItemToRemove->pvContainer; + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + + pxItemToRemove->pvContainer = NULL; + ( pxList->uxNumberOfItems )--; +} +/*-----------------------------------------------------------*/ + diff --git a/Source/portable/BCC/16BitDOS/Flsh186/port.c b/Source/portable/BCC/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..98613af79 --- /dev/null +++ b/Source/portable/BCC/16BitDOS/Flsh186/port.c @@ -0,0 +1,253 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portBASE_TYPE xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual +context switches. This is then used to restore the original routine during +prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const unsigned portSHORT usTimerDisable = 0x0000; +unsigned portSHORT usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usMaxCountRegister = 0xff5a; +const unsigned portSHORT usTimerPriorityRegister = 0xff32; +const unsigned portSHORT usTimerEnable = 0xC000; +const unsigned portSHORT usRetrigger = 0x0001; +const unsigned portSHORT usTimerHighPriority = 0x0000; +unsigned portSHORT usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const unsigned portLONG ulClockFrequency = ( unsigned portLONG ) 0x7f31a0UL; + +unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h new file mode 100644 index 000000000..a76cb4820 --- /dev/null +++ b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -0,0 +1,98 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/BCC/16BitDOS/PC/port.c b/Source/portable/BCC/16BitDOS/PC/port.c new file mode 100644 index 000000000..11ee3e1db --- /dev/null +++ b/Source/portable/BCC/16BitDOS/PC/port.c @@ -0,0 +1,279 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static portSHORT sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portBASE_TYPE xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + /* The ISR used depends on whether the preemptive or cooperative + scheduler is being used. */ + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + /* This won't set the frequency quite the same as it was, + but using an integer value removes the need for any floating + point in the scheduler code. */ + prvSetTickFrequency( ( unsigned portLONG ) portDOS_TICK_RATE ); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180UL; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; +unsigned portLONG ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); +} + + +/*lint +e950 */ + diff --git a/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/Source/portable/BCC/16BitDOS/PC/prtmacro.h new file mode 100644 index 000000000..8947bc1ab --- /dev/null +++ b/Source/portable/BCC/16BitDOS/PC/prtmacro.h @@ -0,0 +1,97 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT long +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/BCC/16BitDOS/common/portasm.h b/Source/portable/BCC/16BitDOS/common/portasm.h new file mode 100644 index 000000000..bcf36f2c0 --- /dev/null +++ b/Source/portable/BCC/16BitDOS/common/portasm.h @@ -0,0 +1,87 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + __asm { mov ax, seg pxCurrentTCB } \ + __asm { mov ds, ax } \ + __asm { les bx, dword ptr pxCurrentTCB } \ + __asm { mov ss, es:[ bx + 2 ] } \ + __asm { mov sp, es:[ bx ] } \ + __asm { pop bx } \ + __asm { pop di } \ + __asm { pop si } \ + __asm { pop ds } \ + __asm { pop es } \ + __asm { pop dx } \ + __asm { pop cx } \ + __asm { pop bx } \ + __asm { pop ax } \ + __asm { iret } + + diff --git a/Source/portable/BCC/16BitDOS/common/portcomn.c b/Source/portable/BCC/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..856dfea50 --- /dev/null +++ b/Source/portable/BCC/16BitDOS/common/portcomn.c @@ -0,0 +1,125 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.6.1 + + + Move usPortCheckFreeStackSpace() to tasks.c. +*/ + + +#include +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + diff --git a/Source/portable/CodeWarrior/HCS12/port.c b/Source/portable/CodeWarrior/HCS12/port.c new file mode 100644 index 000000000..fd77e9423 --- /dev/null +++ b/Source/portable/CodeWarrior/HCS12/port.c @@ -0,0 +1,243 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* Interrupt service routines have to be in non-banked memory - as does the +scheduler startup function. */ +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Manual context switch function. This is the SWI ISR. */ + void interrupt vPortYield( void ); + + /* Tick context switch function. This is the timer ISR. */ + void interrupt vPortTickInterrupt( void ); + + /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not + start the scheduler directly because the header file containing the + xPortStartScheduler() prototype is part of the common kernel code, and + therefore cannot use the CODE_SEG pragma. */ + static portBASE_TYPE xBankedStartScheduler( void ); + +#pragma CODE_SEG DEFAULT + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile unsigned portBASE_TYPE uxCriticalNesting = 0xff; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This can be uncommented to provide useful stack markers when debugging. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x33; + pxTopOfStack--; + */ + + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 ); + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 ); + pxTopOfStack--; + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xff; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xee; + pxTopOfStack--; + + /* X register */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xdd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; + pxTopOfStack--; + + /* A register contains parameter high byte. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 ); + pxTopOfStack--; + + /* B register contains parameter low byte. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 ); + pxTopOfStack--; + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; + pxTopOfStack--; + + #ifdef BANKED_MODEL + /* The page of the task. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ( int ) pxCode ); + pxTopOfStack--; + #endif + + /* Finally the critical nesting depth is initialised with 0 (not within + a critical section). */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + TickTimer_SetFreqHz( configTICK_RATE_HZ ); + TickTimer_Enable(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xBankedStartScheduler() - + which does use the CODE_SEG pragma. */ + + return xBankedStartScheduler(); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +static portBASE_TYPE xBankedStartScheduler( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of an interrupt to start the scheduler off. */ + __asm( "rti" ); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are both interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void interrupt vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void interrupt vPortTickInterrupt( void ) +{ + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + vTaskIncrementTick(); + + /* ... then see if the new tick value has necessitated a + context switch. */ + vTaskSwitchContext(); + + TFLG1 = 1; + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + vTaskIncrementTick(); + TFLG1 = 1; + } + #endif +} + +#pragma CODE_SEG DEFAULT + + diff --git a/Source/portable/CodeWarrior/HCS12/portmacro.h b/Source/portable/CodeWarrior/HCS12/portmacro.h new file mode 100644 index 000000000..9b7cf0793 --- /dev/null +++ b/Source/portable/CodeWarrior/HCS12/portmacro.h @@ -0,0 +1,205 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +#define portNOP() __asm( "nop" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + __asm( "pula" ); \ + __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \ + __asm( "psha" ); \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#endif + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/ARM7_AT91FR40008/port.c b/Source/portable/GCC/ARM7_AT91FR40008/port.c new file mode 100644 index 000000000..b36a036a6 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91FR40008/port.c @@ -0,0 +1,239 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel AT91R40008 + * port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" +#include "tc.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) +#define portTICK_PRIORITY_6 ( 6 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the tick timer to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +volatile unsigned portLONG ulDummy; + + /* Enable clock to the tick timer... */ + AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; + + /* Stop the tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; + + /* Start with tick timer interrupts disabled... */ + portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; + + /* Clear any pending tick timer interrupts... */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Store interrupt handler function address in tick timer vector register... + The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick; + } + #else // else use cooperative scheduler + { + extern void ( vNonPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick; + } + #endif + + /* Tick timer interrupt level-sensitive, priority 6... */ + AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; + + /* Enable the tick timer interrupt... + + First at timer level */ + portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; + + /* Then at the AIC level. */ + AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); + + /* Calculate timer compare value to achieve the desired tick rate... */ + if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) + { + /* The tick rate is fast enough for us to use the faster timer input + clock (main clock / 2). */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); + } + else + { + /* We must use a slower timer input clock (main clock / 8) because the + tick rate is too slow for the faster input clock. */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); + } + + /* Start tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; +} +/*-----------------------------------------------------------*/ + diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c new file mode 100644 index 000000000..a024b74db --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -0,0 +1,236 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + static volatile unsigned portLONG ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + vTaskIncrementTick(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + } + +#else /* else preemption is turned on */ + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* WARNING - Do not use local (stack) variables here. Use globals + if you must! */ + static volatile unsigned portLONG ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h new file mode 100644 index 000000000..8ae8658cc --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -0,0 +1,269 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm volatile ( "SWI" ); +#define portNOP() asm volatile ( "NOP" ); + +/* + * These define the timer to use for generating the tick interrupt. + * They are put in this file so they can be shared between "port.c" + * and "portisr.c". + */ +#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 +#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 +#define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + *----------------------------------------------------------*/ + +#define portENTER_SWITCHING_ISR() \ + /* Save the context of the interrupted task. */ \ + portSAVE_CONTEXT(); \ + \ + /* We don't know the stack requirements for the ISR, so the frame */\ + /* pointer will be set to the top of the task stack, and the stack*/\ + /* pointer left where it is. The IRQ stack will get used for any */\ + /* functions calls made by this ISR. */ \ + asm volatile ( "SUB R11, LR, #4" ); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + portRESTORE_CONTEXT(); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h new file mode 100644 index 000000000..a14279e0b --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -0,0 +1,2731 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ +{ \ + unsigned int mask ; \ + \ + mask = 0x1 << irq_id; \ + /* Disable the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_IDCR = mask ; \ + /* Save the interrupt handler routine pointer and the interrupt priority */ \ + AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ + /* Store the Source Mode Register */ \ + AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ + /* Clear the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_ICCR = mask ; \ +} + + +#endif diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h new file mode 100644 index 000000000..8ea721e28 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -0,0 +1,4698 @@ +// - ---------------------------------------------------------------------------- +// - ATMEL Microcontroller Software Support - ROUSSET - +// - ---------------------------------------------------------------------------- +// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// - ---------------------------------------------------------------------------- +// - File Name : AT91SAM7X256.h +// - Object : AT91SAM7X256 definitions +// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// - +// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// - ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + + + +// - Hardware register definition + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR System Peripherals +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// - ***************************************************************************** +// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#if 0 /*_RB_*/ +AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level +AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level +AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level +AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type +AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive +AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered +AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered +AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered +// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status +AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status +// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode +AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask +#endif +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// - ***************************************************************************** +// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable +// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Debug Unit +// - ***************************************************************************** +// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver +AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter +AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable +AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable +AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable +AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable +AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits +// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type +AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity +AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity +AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) +AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) +AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity +AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode +AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode +AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt +AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt +AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt +AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt +AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt +AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt +AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt +AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt +AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt +AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt +// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Clock Generator Controler +// - ***************************************************************************** +// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time +// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready +// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter +AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier +AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks +AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Power Management Controler +// - ***************************************************************************** +// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock +AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock +AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output +// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected +AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock +AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 +// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask +AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask +AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask +// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Reset Controller Interface +// - ***************************************************************************** +// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset +AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset +AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset +AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password +// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status +AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. +AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. +AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. +AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. +AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level +AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. +// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable +AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable +AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// - ***************************************************************************** +// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart +// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value +// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value +// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status +AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// - ***************************************************************************** +// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value +AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable +// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status +// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value +AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter +// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// - ***************************************************************************** +// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart +AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password +// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable +AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt +// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow +AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// - ***************************************************************************** +// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Memory Controller Interface +// - ***************************************************************************** +// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit +// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status +AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status +AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte +AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word +AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word +AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read +AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write +AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch +AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source +AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source +AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source +// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready +AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error +AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error +AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming +AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State +AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations +AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations +AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations +AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations +AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number +// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command +AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. +AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. +AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. +AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. +AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. +AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number +AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key +// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status +AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Serial Parallel Interface +// - ***************************************************************************** +// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable +AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable +AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset +AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer +// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode +AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select +AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode +AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection +AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection +AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection +AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects +// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data +AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data +AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full +AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty +AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error +AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status +AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer +AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt +AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status +// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity +AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase +AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer +AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer +AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer +AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK +AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Usart +// - ***************************************************************************** +// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break +AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break +AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out +AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address +AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations +AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge +AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out +AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable +AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable +AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable +AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable +// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode +AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal +AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 +AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem +AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 +AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 +AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA +AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking +AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock +AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 +AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) +AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) +AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits +AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits +AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits +AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits +AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select +AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits +AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit +AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits +AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order +AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length +AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select +AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode +AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge +AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK +AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions +AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter +// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break +AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out +AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached +AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge +AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag +AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag +AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag +AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag +// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input +AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input +AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input +AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// - ***************************************************************************** +// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable +AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable +AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable +AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable +AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset +// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection +AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock +AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal +AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin +AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection +AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output +AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion +AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection +AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start +AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input +AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input +AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input +AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input +AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input +AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input +AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 +AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay +AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection +// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length +AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode +AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First +AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame +AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length +AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection +AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection +// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value +AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable +// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready +AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty +AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission +AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty +AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready +AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun +AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception +AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full +AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync +AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync +AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable +AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable +// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Two-wire Interface +// - ***************************************************************************** +// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition +AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition +AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled +AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled +AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset +// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size +AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address +AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address +AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address +AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address +AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction +AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address +// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider +AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider +AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider +// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed +AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY +AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY +AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error +AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error +AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged +// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR PWMC Channel Interface +// - ***************************************************************************** +// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) +AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment +AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity +AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period +// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle +// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period +// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter +// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// - ***************************************************************************** +// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. +AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A +AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) +AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. +AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B +AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) +// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 +AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 +AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 +AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 +// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR USB Device Interface +// - ***************************************************************************** +// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats +AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error +AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK +// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable +AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured +AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume +AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host +AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable +// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value +AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable +// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt +AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt +AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt +AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt +AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt +AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt +AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt +AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt +AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt +// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt +// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 +AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 +AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 +AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 +AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 +AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 +// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR +AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 +AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) +AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) +AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready +AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction +AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type +AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control +AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT +AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT +AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT +AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN +AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN +AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN +AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle +AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable +AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO +// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) +AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// - ***************************************************************************** +// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command +AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command +AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command +// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection +AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK +AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK +AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK +AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK +AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK +AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 +AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 +AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 +AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert +AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection +AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal +AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock +AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock +AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock +AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare +AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading +AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare +AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading +AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection +AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection +AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection +AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input +AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output +AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output +AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output +AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection +AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable +AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection +AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare +AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare +AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable +AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) +AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA +AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none +AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set +AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear +AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle +AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection +AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None +AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA +AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA +AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none +AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set +AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear +AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle +AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection +AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None +AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA +AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA +AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none +AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set +AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear +AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle +AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA +AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none +AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set +AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear +AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle +AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB +AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none +AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set +AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear +AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle +AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB +AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none +AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set +AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear +AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle +AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB +AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none +AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set +AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear +AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle +AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB +AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none +AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set +AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear +AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle +// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow +AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun +AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare +AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare +AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare +AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading +AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading +AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger +AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling +AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror +AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror +// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Interface +// - ***************************************************************************** +// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command +// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection +AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 +AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 +AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 +AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 +AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection +AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 +AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 +AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 +AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 +AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection +AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 +AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 +AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 +AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// - ***************************************************************************** +// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark +AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority +AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type +AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) +// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode +AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode +AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version +// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value +AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code +AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request +AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort +AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready +AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored +// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox +AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network Interface +// - ***************************************************************************** +// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable +AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode +AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode +AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame +AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame +AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode +AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze +AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat +// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag +AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag +AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag +AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag +AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag +AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag +AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag +AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag +AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag +AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag +AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag +AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag +AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag +AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag +AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag +AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag +AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag +AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag +AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag +AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag +AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag +AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag +AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag +AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag +AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error +AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error +AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error +AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error +AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error +// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy +AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy +AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy +// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment +AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment +AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment +AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment +AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler +AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode +// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field +// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter +AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter +// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field +// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// - ***************************************************************************** +// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. +AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. +AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. +AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. +AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. +AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. +AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. +AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. +AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. +AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. +AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. +AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame +AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame +// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. +AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. +AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. +AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. +AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. +AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable +AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. +AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. +AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. +AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) +AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 +AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 +AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 +AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 +AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) +AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) +AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer +AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable +AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS +AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) +AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS +// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go +AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame +AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) +// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) +AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) +AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) +AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) +AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) +AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) +AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) +AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) +// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) +AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) +AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) +AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) +AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) +// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII +// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address +AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable +AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable +AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable +// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// - ***************************************************************************** +// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset +AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion +// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable +AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. +AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection +AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 +AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 +AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 +AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 +AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 +AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 +AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger +AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. +AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution +AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution +AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode +AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection +AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time +AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time +// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 +AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 +AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 +AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 +AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 +AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 +AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 +AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 +// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion +AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion +AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion +AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion +AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion +AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion +AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion +AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion +AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error +AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error +AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error +AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error +AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error +AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error +AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error +AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error +AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready +AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun +AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer +AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt +// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted +// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data +// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// - ***************************************************************************** +// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- +AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing +AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset +AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading +// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode +AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay +AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode +AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). +AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode +AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. +AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. +AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. +AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. +AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. +AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode +AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size +AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. +AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. +AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. +AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. +AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. +AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key +AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type +AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. +AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. +AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. +AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. +AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. +// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY +AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End +AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End +AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full +AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty +AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection +// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status +AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. +AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. +AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. +AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. +AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. +AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// - ***************************************************************************** +// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing +AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset +// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode +AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode +AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode +AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode +AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). +AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode +AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. +AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. +AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. +AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. +AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode +AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size +AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. +AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. +AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. +AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. +// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY +AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End +AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End +AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full +AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty +AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection +// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status +AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. +AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. +AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. +AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. + +// - ***************************************************************************** +// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// - ***************************************************************************** +// - ========== Register definition for SYS peripheral ========== +// - ========== Register definition for AIC peripheral ========== +AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register +AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register +AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register +AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) +AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register +AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register +AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register +AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register +AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register +AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register +AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register +AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register +AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register +AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register +AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register +AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register +AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register +AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register +// - ========== Register definition for PDC_DBGU peripheral ========== +AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register +AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register +AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register +AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register +AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register +AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register +AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register +AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register +AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register +AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register +// - ========== Register definition for DBGU peripheral ========== +AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register +AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register +AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register +AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register +AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register +AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register +AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register +AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register +AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register +AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register +AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register +AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register +// - ========== Register definition for PIOA peripheral ========== +AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr +AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register +AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register +AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register +AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register +AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register +AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register +AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register +AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register +AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register +AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register +AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register +AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register +AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register +AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register +AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register +AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register +AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register +AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register +AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register +AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register +AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register +AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register +AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register +AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register +AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register +AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register +AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register +AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register +// - ========== Register definition for PIOB peripheral ========== +AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register +AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register +AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register +AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register +AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register +AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register +AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register +AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register +AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register +AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register +AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register +AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register +AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register +AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register +AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register +AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register +AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr +AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register +AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register +AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register +AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register +AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register +AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register +AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register +AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register +AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register +AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register +AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register +AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register +// - ========== Register definition for CKGR peripheral ========== +AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register +AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register +AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register +// - ========== Register definition for PMC peripheral ========== +AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register +AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register +AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register +AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register +AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register +AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register +AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register +AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register +AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register +AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register +AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register +AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register +AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register +AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register +AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register +// - ========== Register definition for RSTC peripheral ========== +AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register +AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register +AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register +// - ========== Register definition for RTTC peripheral ========== +AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register +AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register +AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register +AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register +// - ========== Register definition for PITC peripheral ========== +AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register +AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register +AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register +AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register +// - ========== Register definition for WDTC peripheral ========== +AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register +AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register +AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register +// - ========== Register definition for VREG peripheral ========== +AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register +// - ========== Register definition for MC peripheral ========== +AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register +AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register +AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register +AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register +AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register +AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register +// - ========== Register definition for PDC_SPI1 peripheral ========== +AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register +AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register +AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register +AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register +AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register +AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register +AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register +AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register +AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register +AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register +// - ========== Register definition for SPI1 peripheral ========== +AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register +AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register +AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register +AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register +AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register +AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register +AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register +AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register +AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register +// - ========== Register definition for PDC_SPI0 peripheral ========== +AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register +AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register +AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register +AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register +AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register +AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register +AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register +AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register +AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register +AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register +// - ========== Register definition for SPI0 peripheral ========== +AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register +AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register +AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register +AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register +AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register +AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register +AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register +AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register +AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register +// - ========== Register definition for PDC_US1 peripheral ========== +AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register +AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register +AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register +AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register +AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register +AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register +AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register +AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register +AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register +AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register +// - ========== Register definition for US1 peripheral ========== +AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register +AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register +AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register +AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register +AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register +AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register +AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register +AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register +AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register +AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register +AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register +AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register +AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register +AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register +// - ========== Register definition for PDC_US0 peripheral ========== +AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register +AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register +AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register +AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register +AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register +AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register +AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register +AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register +AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register +AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register +// - ========== Register definition for US0 peripheral ========== +AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register +AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register +AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register +AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register +AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register +AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register +AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register +AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register +AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register +AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register +AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register +AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register +AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register +AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register +// - ========== Register definition for PDC_SSC peripheral ========== +AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register +AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register +AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register +AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register +AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register +AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register +AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register +AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register +AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register +AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register +// - ========== Register definition for SSC peripheral ========== +AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register +AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register +AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register +AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register +AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register +AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister +AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register +AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register +AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register +AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register +AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register +AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register +AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register +AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register +// - ========== Register definition for TWI peripheral ========== +AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register +AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register +AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register +AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register +AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register +AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register +AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register +AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register +AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register +AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register +// - ========== Register definition for PWMC_CH3 peripheral ========== +AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register +AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved +AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register +AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register +AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register +AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register +// - ========== Register definition for PWMC_CH2 peripheral ========== +AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved +AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register +AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register +AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register +AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register +AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register +// - ========== Register definition for PWMC_CH1 peripheral ========== +AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved +AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register +AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register +AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register +AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register +AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register +// - ========== Register definition for PWMC_CH0 peripheral ========== +AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved +AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register +AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register +AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register +AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register +AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register +// - ========== Register definition for PWMC peripheral ========== +AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register +AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register +AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register +AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register +AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register +AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register +AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register +AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register +AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register +// - ========== Register definition for UDP peripheral ========== +AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register +AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register +AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register +AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register +AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register +AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register +AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register +AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register +AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register +AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register +AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register +AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register +// - ========== Register definition for TC0 peripheral ========== +AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register +AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C +AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B +AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register +AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register +AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A +AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register +AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value +AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register +// - ========== Register definition for TC1 peripheral ========== +AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B +AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register +AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register +AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register +AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register +AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A +AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C +AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register +AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value +// - ========== Register definition for TC2 peripheral ========== +AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register +AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value +AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A +AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B +AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register +AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register +AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C +AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register +AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register +// - ========== Register definition for TCB peripheral ========== +AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register +AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register +// - ========== Register definition for CAN_MB0 peripheral ========== +AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register +AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register +AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register +AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register +AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register +AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register +AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register +AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register +// - ========== Register definition for CAN_MB1 peripheral ========== +AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register +AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register +AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register +AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register +AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register +AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register +AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register +AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register +// - ========== Register definition for CAN_MB2 peripheral ========== +AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register +AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register +AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register +AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register +AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register +AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register +AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register +AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register +// - ========== Register definition for CAN_MB3 peripheral ========== +AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register +AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register +AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register +AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register +AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register +AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register +AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register +AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register +// - ========== Register definition for CAN_MB4 peripheral ========== +AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register +AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register +AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register +AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register +AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register +AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register +AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register +AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB5 peripheral ========== +AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register +AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register +AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register +AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register +AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register +AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register +AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register +AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB6 peripheral ========== +AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register +AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register +AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register +AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register +AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register +AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register +AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register +AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register +// - ========== Register definition for CAN_MB7 peripheral ========== +AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register +AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register +AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register +AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register +AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register +AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register +AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register +AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register +// - ========== Register definition for CAN peripheral ========== +AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register +AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register +AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register +AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register +AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register +AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register +AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register +AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register +AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register +AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register +AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register +AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register +// - ========== Register definition for EMAC peripheral ========== +AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register +AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes +AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes +AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register +AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register +AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register +AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register +AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register +AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register +AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register +AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes +AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register +AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes +AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register +AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register +AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register +AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register +AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register +AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] +AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer +AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register +AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register +AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes +AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register +AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register +AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register +AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer +AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register +AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register +AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] +AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register +AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register +AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register +AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register +AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register +AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register +AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register +AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register +AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register +AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register +AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register +AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes +AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register +AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register +AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes +AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register +AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes +AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register +AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register +// - ========== Register definition for PDC_ADC peripheral ========== +AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register +AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register +AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register +AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register +AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register +AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register +AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register +AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register +AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register +AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register +// - ========== Register definition for ADC peripheral ========== +AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 +AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 +AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 +AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 +AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register +AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register +AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 +AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 +AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register +AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register +AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register +AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 +AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 +AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register +AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register +AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register +AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register +AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register +// - ========== Register definition for PDC_AES peripheral ========== +AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register +AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register +AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register +AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register +AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register +AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register +AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register +AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register +AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register +AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register +// - ========== Register definition for AES peripheral ========== +AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register +AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register +AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register +AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register +AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register +AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register +AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register +AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register +AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register +AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register +AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register +// - ========== Register definition for PDC_TDES peripheral ========== +AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register +AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register +AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register +AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register +AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register +AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register +AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register +AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register +AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register +AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register +// - ========== Register definition for TDES peripheral ========== +AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register +AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register +AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register +AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register +AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register +AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register +AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register +AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register +AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register +AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register +AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register +AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register +AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register + +// - ***************************************************************************** +// - PIO DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 +AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data +AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 +AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data +AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 +AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data +AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 +AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock +AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 +AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 +AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 +AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 +AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 +AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 +AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input +AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 +AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave +AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 +AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave +AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 +AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock +AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 +AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive +AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 +AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock +AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 +AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit +AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 +AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync +AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 +AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 +AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock +AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock +AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 +AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data +AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave +AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 +AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data +AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave +AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 +AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock +AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 +AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync +AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 +AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data +AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 +AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 +AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data +AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 +AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input +AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 +AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send +AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 +AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 +AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 +AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send +AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 +AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data +AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 +AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data +AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 +AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock +AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 +AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send +AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 +AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send +AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 +AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock +AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 +AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable +AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 +AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 +AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 +AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 +AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 +AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error +AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input +AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 +AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 +AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 +AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 +AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 +AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid +AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 +AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected +AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 +AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock +AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 +AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec +AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger +AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 +AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 +AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input +AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 +AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 +AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 +AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 +AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 +AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 +AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 +AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 +AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 +AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A +AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect +AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 +AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B +AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready +AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 +AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A +AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready +AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 +AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B +AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator +AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 +AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A +AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 +AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 +AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B +AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 +AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 +AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 +AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 +AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 +AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 +AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 +AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 +AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 +AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 +AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 +AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 +AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 +AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 +AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 +AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error +AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 +AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock +AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 +AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output + +// - ***************************************************************************** +// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) +AT91C_ID_SYS EQU ( 1) ;- System Peripheral +AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A +AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B +AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 +AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 +AT91C_ID_US0 EQU ( 6) ;- USART 0 +AT91C_ID_US1 EQU ( 7) ;- USART 1 +AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller +AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface +AT91C_ID_PWMC EQU (10) ;- PWM Controller +AT91C_ID_UDP EQU (11) ;- USB Device Port +AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 +AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 +AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 +AT91C_ID_CAN EQU (15) ;- Control Area Network Controller +AT91C_ID_EMAC EQU (16) ;- Ethernet MAC +AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter +AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit +AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard +AT91C_ID_20_Reserved EQU (20) ;- Reserved +AT91C_ID_21_Reserved EQU (21) ;- Reserved +AT91C_ID_22_Reserved EQU (22) ;- Reserved +AT91C_ID_23_Reserved EQU (23) ;- Reserved +AT91C_ID_24_Reserved EQU (24) ;- Reserved +AT91C_ID_25_Reserved EQU (25) ;- Reserved +AT91C_ID_26_Reserved EQU (26) ;- Reserved +AT91C_ID_27_Reserved EQU (27) ;- Reserved +AT91C_ID_28_Reserved EQU (28) ;- Reserved +AT91C_ID_29_Reserved EQU (29) ;- Reserved +AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) +AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) + +// - ***************************************************************************** +// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address +AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address +AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address +AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address +AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address +AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address +AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address +AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address +AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address +AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address +AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address +AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address +AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address +AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address +AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address +AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address +AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address +AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address +AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address +AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address +AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address +AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address +AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address +AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address +AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address +AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address +AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address +AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address +AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address +AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address +AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address +AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address +AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address +AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address +AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address +AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address +AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address +AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address +AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address +AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address +AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address +AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address +AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address +AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address +AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address +AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address +AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address +AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address +AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address +AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address +AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address + +// - ***************************************************************************** +// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address +AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) +AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address +AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) + + + +#endif /* AT91SAM7X256_H */ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c new file mode 100644 index 000000000..9cbd823c6 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c @@ -0,0 +1,51 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + + +#include "AT91SAM7X256.h" + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- + diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h new file mode 100644 index 000000000..e66b4e1e1 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/Source/portable/GCC/ARM7_AT91SAM7S/port.c new file mode 100644 index 000000000..697470ad6 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/port.c @@ -0,0 +1,222 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + ulCriticalNesting is now saved as part of the task context, as is + therefore added to the initial task stack during pxPortInitialiseStack. +*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Processor constants. */ +#include "AT91SAM7X256.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + extern void ( vNonPreemptiveTick ) ( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); + + #else + + extern void ( vPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c new file mode 100644 index 000000000..ba81cd90a --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -0,0 +1,231 @@ +/* + FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "AT91SAM7X256.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + unsigned portLONG ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may wake a task. */ + vTaskIncrementTick(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;; + + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); +void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + +void vPortDisableInterruptsFromThumb( void ) +{ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + +void vPortEnableInterruptsFromThumb( void ) +{ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h new file mode 100644 index 000000000..07c98cec9 --- /dev/null +++ b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -0,0 +1,265 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + *----------------------------------------------------------*/ + + +#define portENTER_SWITCHING_ISR() \ + /* Save the context of the interrupted task. */ \ + portSAVE_CONTEXT(); \ + \ + /* We don't know the stack requirements for the ISR, so the frame */\ + /* pointer will be set to the top of the task stack, and the stack*/\ + /* pointer left where it is. The IRQ stack will get used for any */\ + /* functions calls made by this ISR. */ \ + asm volatile ( "SUB R11, LR, #4" ); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + portRESTORE_CONTEXT(); + +#define portYIELD() asm volatile ( "SWI" ); +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/ARM7_LPC2000/port.c b/Source/portable/GCC/ARM7_LPC2000/port.c new file mode 100644 index 000000000..42c7835c6 --- /dev/null +++ b/Source/portable/GCC/ARM7_LPC2000/port.c @@ -0,0 +1,245 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + ulCriticalNesting is now saved as part of the task context, as is + therefore added to the initial task stack during pxPortInitialiseStack. + + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0_PR + instead of T0_PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0_PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0_MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + VICVectAddr0 = ( portLONG ) vPreemptiveTick; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + VICVectAddr0 = ( portLONG ) vNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0_TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/GCC/ARM7_LPC2000/portISR.c b/Source/portable/GCC/ARM7_LPC2000/portISR.c new file mode 100644 index 000000000..9f73f6463 --- /dev/null +++ b/Source/portable/GCC/ARM7_LPC2000/portISR.c @@ -0,0 +1,235 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + The critical section management functions have been changed. These no + longer modify the stack and are safe to use at all optimisation levels. + The functions are now also the same for both ARM and THUMB modes. + + Changes from V2.6.0 + + + Removed the 'static' from the definition of vNonPreemptiveTick() to + allow the demo to link when using the cooperative scheduler. + + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + vTaskIncrementTick(); + T0_IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0_IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/Source/portable/GCC/ARM7_LPC2000/portmacro.h new file mode 100644 index 000000000..674876fa1 --- /dev/null +++ b/Source/portable/GCC/ARM7_LPC2000/portmacro.h @@ -0,0 +1,264 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + *----------------------------------------------------------*/ + + +#define portENTER_SWITCHING_ISR() \ + /* Save the context of the interrupted task. */ \ + portSAVE_CONTEXT(); \ + \ + /* We don't know the stack requirements for the ISR, so the frame */\ + /* pointer will be set to the top of the task stack, and the stack*/\ + /* pointer left where it is. The IRQ stack will get used for any */\ + /* functions calls made by this ISR. */ \ + asm volatile ( "SUB R11, LR, #4" ); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + portRESTORE_CONTEXT(); + +#define portYIELD() asm volatile ( "SWI" ); +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c new file mode 100644 index 000000000..08b6ac2c8 --- /dev/null +++ b/Source/portable/GCC/ARM_CM3/port.c @@ -0,0 +1,299 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes between V4.0.0 and V4.0.1 + + + Reduced the code used to setup the initial stack frame. + + The kernel no longer has to install or handle the fault interrupt. +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) +#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) +#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portNVIC_PENDSV_PRI 0x00ff0000 +#define portNVIC_SVCALL_PRI 0xff000000 +#define portNVIC_SYSTICK_PRI 0xff000000 + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__ (( naked )); +void xPortSysTickHandler( void ) __attribute__ (( naked )); + +/* + * Set the MSP/PSP to a known value. + */ +void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked )); +void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0xfffffffd; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void prvSetPSP( unsigned long ulValue ) +{ + asm volatile( "msr psp, r0" ); + asm volatile( "bx lr" ); +} +/*-----------------------------------------------------------*/ + +void prvSetMSP( unsigned long ulValue ) +{ + asm volatile( "msr msp, r0" ); + asm volatile( "bx lr" ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + prvSetPSP( 0 ); + prvSetMSP( *((unsigned portLONG *) 0 ) ); + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* Enable interrupts */ + portENABLE_INTERRUPTS(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the CM3 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* This function is also called in response to a Yield(), so we want + the yield to occur immediately. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* Start first task if the stack has not yet been setup. */ + __asm volatile + ( + " mrs r0, psp \n" + " cbz r0, no_save \n" + " \n" /* Save the context into the TCB. */ + " sub r0, #0x20 \n" + " stm r0, {r4-r11} \n" + " nop \n" + " sub r0, #0x04 \n" + " ldr r1, uxCriticalNestingConst \n" + " ldr r1, [r1] \n" + " stm r0, {r1} \n" + " ldr r1, pxCurrentTCBConst \n" + " ldr r1, [r1] \n" + " str r0, [r1] \n" + " \n" + "no_save:\n" + " ldr r0, vTaskSwitchContextConst \n" /* Find the task to execute. */ + " push {r14} \n" + " cpsid i \n" + " blx r0 \n" + " cpsie i \n" + " pop {r14} \n" + " \n" /* Restore the context. */ + " ldr r1, pxCurrentTCBConst \n" + " ldr r1, [r1] \n" + " ldr r0, [r1] \n" + " ldm r0, {r1, r4-r11} \n" + " nop \n" + " ldr r2, uxCriticalNestingConst \n" + " str r1, [r2] \n" + " add r0, #0x24 \n" + " msr psp, r0 \n" + " orr r14, #0xd \n" + " \n" /* Exit with interrupts in the state required by the task. */ + " cbnz r1, sv_disable_interrupts \n" + " bx r14 \n" + " \n" + "sv_disable_interrupts: \n" + " cpsid i \n" + " bx r14 \n" + " \n" + " .align 2 \n" + "vTaskSwitchContextConst: .word vTaskSwitchContext \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "uxCriticalNestingConst: .word uxCriticalNesting \n" + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + extern void vTaskIncrementTick( void ); + extern void vPortYieldFromISR( void ); + + /* Call the scheduler tick function. */ + __asm volatile + ( + " ldr r0, vTaskIncrementTickConst \n" + " push {r14} \n" + " cpsid i \n" + " blx r0 \n" + " cpsie i \n" + " pop {r14}" + ); + + /* If using preemption, also force a context switch. */ + #if configUSE_PREEMPTION == 1 + __asm volatile + ( + " push {r14} \n" + " ldr r0, vPortYieldFromISRConst2 \n" + " blx r0 \n" + " pop {r14}" + ); + #endif + + /* Exit with interrupts in the correct state. */ + __asm volatile + ( + " ldr r2, uxCriticalNestingConst2 \n" + " ldr r2, [r2] \n" + " cbnz r2, tick_disable_interrupts \n" + " bx r14" + ); + + __asm volatile + ( + "tick_disable_interrupts: \n" + " cpsid i \n" + " bx r14 \n" + " \n" + " .align 2 \n" + "vPortYieldFromISRConst2: .word vPortYieldFromISR\n" + "vTaskIncrementTickConst: .word vTaskIncrementTick\n" + "uxCriticalNestingConst2: .word uxCriticalNesting" + ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} + + diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h new file mode 100644 index 000000000..6cae66f7d --- /dev/null +++ b/Source/portable/GCC/ARM_CM3/portmacro.h @@ -0,0 +1,101 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYieldFromISR( void ); + +#define portYIELD() vPortYieldFromISR() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortEnableInterrupts( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __asm volatile( "cpsid i" ) +#define portENABLE_INTERRUPTS() __asm volatile( "cpsie i" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline +#define portNOP() + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/ATMega323/port.c b/Source/portable/GCC/ATMega323/port.c new file mode 100644 index 000000000..aa59e9fc3 --- /dev/null +++ b/Source/portable/GCC/ATMega323/port.c @@ -0,0 +1,432 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + +Changes from V2.6.0 + + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) +#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero as the compiler expects it to be thus, however some + * of the math routines make use of R1. + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ + +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, 0x3d \n\t" \ + "st x+, r0 \n\t" \ + "in r0, 0x3e \n\t" \ + "st x+, r0 \n\t" \ + ); + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ + +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" \ + ); + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portSHORT usAddress; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Simulate how the stack would look after a call to vPortYield() generated by + the compiler. */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The start of the task code will be popped off the stack last, so place + it on first. */ + usAddress = ( unsigned portSHORT ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( unsigned portSHORT ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x28; /* R28 Y */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x29; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ + pxTopOfStack--; + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* In this port we ignore the parameter and use the configUSE_PREEMPTION + definition instead. */ + + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + vTaskIncrementTick(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; +unsigned portCHAR ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( unsigned portLONG ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + ucLowByte = TIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + TIMSK = ucLowByte; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) ); + void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm volatile ( "reti" ); + } +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) ); + void SIG_OUTPUT_COMPARE1A( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/Source/portable/GCC/ATMega323/portmacro.h b/Source/portable/GCC/ATMega323/portmacro.h new file mode 100644 index 000000000..b59405eed --- /dev/null +++ b/Source/portable/GCC/ATMega323/portmacro.h @@ -0,0 +1,100 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ + asm volatile ( "cli" :: ); \ + asm volatile ( "push __tmp_reg__" :: ) + +#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ + asm volatile ( "out __SREG__, __tmp_reg__" :: ) + +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/H8S2329/port.c b/Source/portable/GCC/H8S2329/port.c new file mode 100644 index 000000000..cac359753 --- /dev/null +++ b/Source/portable/GCC/H8S2329/port.c @@ -0,0 +1,306 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the H8S port. + *----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* When the task starts interrupts should be enabled. */ +#define portINITIAL_CCR ( ( portSTACK_TYPE ) 0x00 ) + +/* Hardware specific constants used to generate the RTOS tick from the TPU. */ +#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( unsigned portCHAR ) 0x20 ) +#define portCLOCK_DIV_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_DIV ( ( unsigned portLONG ) 64 ) +#define portTGRA_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x01 ) +#define portTIMER_CHANNEL ( ( unsigned portCHAR ) 0x02 ) +#define portMSTP13 ( ( unsigned portSHORT ) 0x2000 ) + +/* + * Setup TPU channel one for the RTOS tick at the requested frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The ISR used by portYIELD(). This is installed as a trap handler. + */ +void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulValue; + + /* This requires an even address. */ + ulValue = ( unsigned portLONG ) pxTopOfStack; + if( ulValue & 1UL ) + { + pxTopOfStack = pxTopOfStack - 1; + } + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + pxTopOfStack--; + *pxTopOfStack = 0xaa; + pxTopOfStack--; + *pxTopOfStack = 0xbb; + pxTopOfStack--; + *pxTopOfStack = 0xcc; + pxTopOfStack--; + *pxTopOfStack = 0xdd; + + /* The initial stack mimics an interrupt stack. First there is the program + counter (24 bits). */ + ulValue = ( unsigned portLONG ) pxCode; + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + + /* Followed by the CCR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_CCR; + + /* Next all the general purpose registers - with the parameters being passed + in ER0. The parameter order must match that used by the compiler when the + "saveall" function attribute is used. */ + + /* ER6 */ + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + + /* ER0 */ + ulValue = ( unsigned portLONG ) pvParameters; + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + + /* ER1 */ + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + + /* ER2 */ + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + + /* ER3 */ + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + + /* ER4 */ + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + + /* ER5 */ + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void * pxCurrentTCB; + + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. This + mirrors the function epilogue code generated by the compiler when the + "saveall" function attribute is used. */ + asm volatile ( + "MOV.L @_pxCurrentTCB, ER6 \n\t" + "MOV.L @ER6, ER7 \n\t" + "LDM.L @SP+, (ER4-ER5) \n\t" + "LDM.L @SP+, (ER0-ER3) \n\t" + "MOV.L @ER7+, ER6 \n\t" + "RTE \n\t" + ); + + ( void ) pxCurrentTCB; + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the h8 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is a trap handler. The "saveall" function + * attribute is used so the context is saved by the compiler prologue. All + * we have to do is save the stack pointer. + */ +void vPortYield( void ) +{ + portSAVE_STACK_POINTER(); + vTaskSwitchContext(); + portRESTORE_STACK_POINTER(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler installed for the RTOS tick depends on whether the + * preemptive or cooperative scheduler is being used. + */ +#if( configUSE_PREEMPTION == 1 ) + + /* + * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). + * The function prologue saves the context so all we have to do is save + * the stack pointer. + */ + void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + void vTickISR( void ) + { + portSAVE_STACK_POINTER(); + + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + + portRESTORE_STACK_POINTER(); + } + +#else + + /* + * The cooperative scheduler is being used so all we have to do is + * periodically increment the tick. This can just be a normal ISR and + * the "saveall" attribute is not required. + */ + void vTickISR( void ) __attribute__ ( ( interrupt_handler ) ); + void vTickISR( void ) + { + vTaskIncrementTick(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; + + /* Turn the module on. */ + MSTPCR &= ~portMSTP13; + + /* Configure timer 1. */ + TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64; + + /* Configure the compare match value for a tick of configTICK_RATE_HZ. */ + TGR1A = ulCompareMatch; + + /* Start the timer and enable the interrupt - we can do this here as + interrupts are globally disabled when this function is called. */ + TIER1 |= portTGRA_INTERRUPT_ENABLE; + TSTR |= portTIMER_CHANNEL; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/GCC/H8S2329/portmacro.h b/Source/portable/GCC/H8S2329/portmacro.h new file mode 100644 index 000000000..f672a5eaf --- /dev/null +++ b/Source/portable/GCC/H8S2329/portmacro.h @@ -0,0 +1,131 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() asm volatile( "TRAPA #0" ) +#define portNOP() asm volatile( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" ); +#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" ); + +/* Push the CCR then disable interrupts. */ +#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \ + portDISABLE_INTERRUPTS(); + +/* Pop the CCR to set the interrupt masking back to its previous state. */ +#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" ); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Context switch macros. These macros are very simple as the context +is saved simply by selecting the saveall attribute of the context switch +interrupt service routines. These macros save and restore the stack +pointer to the TCB. */ + +#define portSAVE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L ER7, @ER5 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + + +#define portRESTORE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L @ER5, ER7 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Macros to allow a context switch from within an application ISR. */ + +#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { + +#define portEXIT_SWITCHING_ISR( x ) \ + if( x ) \ + { \ + extern void vTaskSwitchContext( void ); \ + vTaskSwitchContext(); \ + } \ + } portRESTORE_STACK_POINTER(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/MSP430F449/port.c b/Source/portable/GCC/MSP430F449/port.c new file mode 100644 index 000000000..897e2a6ad --- /dev/null +++ b/Source/portable/GCC/MSP430F449/port.c @@ -0,0 +1,327 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V2.5.2 + + + usCriticalNesting now has a volatile qualifier. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on +the stack before disabling interrupts. Exiting the critical section is then +simply a case of popping the flags from the stack. As mspgcc does not use +a frame pointer this cannot be done as modifying the stack will clobber all +the stack variables. Instead each task maintains a count of the critical +section nesting depth. Each time a critical section is entered the count is +incremented. Each time a critical section is left the count is decremented - +with interrupts only being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This simply pushes all the + * general purpose msp430 registers onto the stack, followed by the + * usCriticalNesting value used by the task. Finally the resultant stack + * pointer value is saved into the task control block so it can be retrieved + * the next time the task executes. + */ +#define portSAVE_CONTEXT() \ + asm volatile ( "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "mov.w usCriticalNesting, r14 \n\t" \ + "push r14 \n\t" \ + "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w r1, @r12 \n\t" \ + ); + +/* + * Macro to restore a task context from the task stack. This is effectively + * the reverse of portSAVE_CONTEXT(). First the stack pointer value is + * loaded from the task control block. Next the value for usCriticalNesting + * used by the task is retrieved from the stack - followed by the value of all + * the general purpose msp430 registers. + */ +#define portRESTORE_CONTEXT() \ + asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w @r12, r1 \n\t" \ + "pop r15 \n\t" \ + "mov.w r15, usCriticalNesting \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "reti \n\t" \ + ); +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* The code generated by the mspgcc compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + * + * The first thing we do is save the registers so we can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + /* We want the stack of the task being saved to look exactly as if the task + was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the + msp430 places the status register onto the stack. As this is a function + call and not an ISR we have to do this manually. */ + asm volatile ( "push r2" ); + _DINT(); + + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/Source/portable/GCC/MSP430F449/portmacro.h b/Source/portable/GCC/MSP430F449/portmacro.h new file mode 100644 index 000000000..5724d902a --- /dev/null +++ b/Source/portable/GCC/MSP430F449/portmacro.h @@ -0,0 +1,120 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ) +#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/GCC/MicroBlaze/port.c b/Source/portable/GCC/MicroBlaze/port.c new file mode 100644 index 000000000..66ed460ad --- /dev/null +++ b/Source/portable/GCC/MicroBlaze/port.c @@ -0,0 +1,337 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MicroBlaze port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +/* Tasks are started with interrupts enabled. */ +#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 ) + +/* Tasks are started with a critical section nesting of 0 - however prior +to the scheduler being commenced we don't want the critical nesting level +to reach zero, so it is initialised to a high value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* Our hardware setup only uses one counter. */ +#define portCOUNTER_0 0 + +/* The stack used by the ISR is filled with a known value to assist in +debugging. */ +#define portISR_STACK_FILL_VALUE 0x55555555 + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task +maintains it's own count, so this variable is saved as part of the task +context. */ +volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* To limit the amount of stack required by each task, this port uses a +separate stack for interrupts. */ +unsigned portLONG *pulISRStack; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +extern void *_SDA2_BASE_, *_SDA_BASE_; +const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_; +const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + This is essential for the Microblaze port and these lines must + not be omitted. The parameter value will overwrite the + 0x22222222 value during the function prologue. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333; + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + is initialised to zero as tasks are started with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */ + pxTopOfStack--; + + /* The MSR is stacked between R30 and R31. */ + *pxTopOfStack = portINITIAL_MSR_STATE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */ + pxTopOfStack--; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void ( __FreeRTOS_interrupt_Handler )( void ); +extern void ( vStartFirstTask )( void ); + + + /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ + asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ + "sw r6, r1, r0 \n\t" \ + "lhu r7, r1, r0 \n\t" \ + "shi r7, r0, 0x12 \n\t" \ + "shi r6, r0, 0x16 " ); + + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Allocate the stack to be used by the interrupt handler. */ + pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); + + /* Restore the context of the first task that is going to run. */ + if( pulISRStack != NULL ) + { + /* Fill the ISR stack with a known value to facilitate debugging. */ + memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); + pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); + + /* Kick off the first task. */ + vStartFirstTask(); + } + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ +extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + not interrupted by the tick ISR. It is not a problem to do this as + each task maintains it's own interrupt status. */ + portENTER_CRITICAL(); + /* Jump directly to the yield function to ensure there is no + compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +XTmrCtr xTimer; +const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; +unsigned portBASE_TYPE uxMask; + + /* The OPB timer1 is used to generate the tick. Use the provided library + functions to enable the timer and set the tick frequency. */ + XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK ); + + /* Set the timer interrupt enable bit while maintaining the other bit + states. */ + uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); + + XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler placed in the interrupt vector when the scheduler is + * started. The task context has already been saved when this is called. + * This handler determines the interrupt source and calls the relevant + * peripheral handler. + */ +void vTaskISRHandler( void ) +{ +static unsigned portLONG ulPending; + + /* Which interrupts are pending? */ + ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); + + if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) + { + static XIntc_VectorTableEntry *pxTablePtr; + static XIntc_Config *pxConfig; + static unsigned portLONG ulInterruptMask; + + ulInterruptMask = ( unsigned portLONG ) 1 << ulPending; + + /* Get the configuration data using the device ID */ + pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ]; + + pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); + if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) + { + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + } + else + { + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. + */ +void vTickISR( void *pvBaseAddress ) +{ +unsigned portLONG ulCSR; + + /* Increment the RTOS tick - this might cause a task to unblock. */ + vTaskIncrementTick(); + + /* Clear the timer interrupt */ + ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); + + /* If we are using the preemptive scheduler then we also need to determine + if this tick should cause a context switch. */ + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/Source/portable/GCC/MicroBlaze/portasm.s b/Source/portable/GCC/MicroBlaze/portasm.s new file mode 100644 index 000000000..b818daa9e --- /dev/null +++ b/Source/portable/GCC/MicroBlaze/portasm.s @@ -0,0 +1,171 @@ + .extern pxCurrentTCB + .extern vTaskISRHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + + .global __FreeRTOS_interrupt_handler + .global VPortYieldASM + .global vStartFirstTask + + +.macro portSAVE_CONTEXT + /* Make room for the context on the stack. */ + addik r1, r1, -132 + /* Save r31 so it can then be used. */ + swi r31, r1, 4 + /* Copy the msr into r31 - this is stacked later. */ + mfs r31, rmsr + /* Stack general registers. */ + swi r30, r1, 12 + swi r29, r1, 16 + swi r28, r1, 20 + swi r27, r1, 24 + swi r26, r1, 28 + swi r25, r1, 32 + swi r24, r1, 36 + swi r23, r1, 40 + swi r22, r1, 44 + swi r21, r1, 48 + swi r20, r1, 52 + swi r19, r1, 56 + swi r18, r1, 60 + swi r17, r1, 64 + swi r16, r1, 68 + swi r15, r1, 72 + swi r13, r1, 80 + swi r12, r1, 84 + swi r11, r1, 88 + swi r10, r1, 92 + swi r9, r1, 96 + swi r8, r1, 100 + swi r7, r1, 104 + swi r6, r1, 108 + swi r5, r1, 112 + swi r4, r1, 116 + swi r3, r1, 120 + swi r2, r1, 124 + /* Stack the critical section nesting value. */ + lwi r3, r0, uxCriticalNesting + swi r3, r1, 128 + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + /* Load the top of stack value from the TCB. */ + lwi r3, r0, pxCurrentTCB + lw r1, r0, r3 + /* Restore the general registers. */ + lwi r31, r1, 4 + lwi r30, r1, 12 + lwi r29, r1, 16 + lwi r28, r1, 20 + lwi r27, r1, 24 + lwi r26, r1, 28 + lwi r25, r1, 32 + lwi r24, r1, 36 + lwi r23, r1, 40 + lwi r22, r1, 44 + lwi r21, r1, 48 + lwi r20, r1, 52 + lwi r19, r1, 56 + lwi r18, r1, 60 + lwi r17, r1, 64 + lwi r16, r1, 68 + lwi r15, r1, 72 + lwi r14, r1, 76 + lwi r13, r1, 80 + lwi r12, r1, 84 + lwi r11, r1, 88 + lwi r10, r1, 92 + lwi r9, r1, 96 + lwi r8, r1, 100 + lwi r7, r1, 104 + lwi r6, r1, 108 + lwi r5, r1, 112 + lwi r4, r1, 116 + lwi r2, r1, 124 + + /* Load the critical nesting value. */ + lwi r3, r1, 128 + swi r3, r0, uxCriticalNesting + + /* Obtain the MSR value from the stack. */ + lwi r3, r1, 8 + + /* Are interrupts enabled in the MSR? If so return using an return from + interrupt instruction to ensure interrupts are enabled only once the task + is running again. */ + andi r3, r3, 2 + beqid r3, 36 + or r0, r0, r0 + + /* Reload the rmsr from the stack, clear the enable interrupt bit in the + value before saving back to rmsr register, then return enabling interrupts + as we return. */ + lwi r3, r1, 8 + andi r3, r3, ~2 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtid r14, 0 + or r0, r0, r0 + + /* Reload the rmsr from the stack, place it in the rmsr register, and + return without enabling interrupts. */ + lwi r3, r1, 8 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtsd r14, 0 + or r0, r0, r0 + + .endm + + .text + .align 2 + + +__FreeRTOS_interrupt_handler: + portSAVE_CONTEXT + /* Entered via an interrupt so interrupts must be enabled in msr. */ + ori r31, r31, 2 + /* Stack msr. */ + swi r31, r1, 8 + /* Stack the return address. As we entered via an interrupt we do + not need to modify the return address prior to stacking. */ + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskISRHandler + or r0, r0, r0 + portRESTORE_CONTEXT + + +VPortYieldASM: + portSAVE_CONTEXT + /* Stack msr. */ + swi r31, r1, 8 + /* Modify the return address so we return to the instruction after the + exception. */ + addi r14, r14, 8 + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskSwitchContext + or r0, r0, r0 + portRESTORE_CONTEXT + +vStartFirstTask: + portRESTORE_CONTEXT + + + + + + diff --git a/Source/portable/GCC/MicroBlaze/portmacro.h b/Source/portable/GCC/MicroBlaze/portmacro.h new file mode 100644 index 000000000..c6b27dc5f --- /dev/null +++ b/Source/portable/GCC/MicroBlaze/portmacro.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() { \ + extern unsigned portBASE_TYPE uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() { \ + extern unsigned portBASE_TYPE uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +void vTaskSwitchContext(); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/IAR/ATMega323/port.c b/Source/portable/IAR/ATMega323/port.c new file mode 100644 index 000000000..88b2af8b3 --- /dev/null +++ b/Source/portable/IAR/ATMega323/port.c @@ -0,0 +1,320 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR/IAR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) +#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* The number of bytes used on the hardware stack by the task start address. */ +#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portSHORT usAddress; +portSTACK_TYPE *pxTopOfHardwareStack; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Remember where the top of the hardware stack is - this is required + below. */ + pxTopOfHardwareStack = pxTopOfStack; + + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + + + /* The IAR compiler requires two stacks per task. First there is the + hardware call stack which uses the AVR stack pointer. Second there is the + software stack (local variables, parameter passing, etc.) which uses the + AVR Y register. + + This function places both stacks within the memory block passed in as the + first parameter. The hardware stack is placed at the bottom of the memory + block. A gap is then left for the hardware stack to grow. Next the software + stack is placed. The amount of space between the software and hardware + stacks is defined by configCALL_STACK_SIZE. + + + + The first part of the stack is the hardware stack. Place the start + address of the task on the hardware stack. */ + usAddress = ( unsigned portSHORT ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + + /* Leave enough space for the hardware stack before starting the software + stack. The '- 2' is because we have already used two spaces for the + address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( unsigned portSHORT ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + + + + /* Now the remaining registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( unsigned portSHORT ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + gets saved into the task control block. */ + + *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + + /* Should not get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; +unsigned portCHAR ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( unsigned portLONG ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + __task void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm( "reti" ); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ + __interrupt void SIG_OUTPUT_COMPARE1A( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/Source/portable/IAR/ATMega323/portmacro.h b/Source/portable/IAR/ATMega323/portmacro.h new file mode 100644 index 000000000..e92979b9c --- /dev/null +++ b/Source/portable/IAR/ATMega323/portmacro.h @@ -0,0 +1,110 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE portCHAR + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() asm( "in r15, 3fh" ); \ + asm( "cli" ); \ + asm( "st -y, r15" ) + +#define portEXIT_CRITICAL() asm( "ld r15, y+" ); \ + asm( "out 3fh, r15" ) + +#define portDISABLE_INTERRUPTS() asm( "cli" ); +#define portENABLE_INTERRUPTS() asm( "sti" ); +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +#ifdef IAR_MEGA_AVR + #define outb( PORT, VALUE ) PORT = VALUE +#endif +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/Source/portable/IAR/ATMega323/portmacro.s90 b/Source/portable/IAR/ATMega323/portmacro.s90 new file mode 100644 index 000000000..3c3f95dd4 --- /dev/null +++ b/Source/portable/IAR/ATMega323/portmacro.s90 @@ -0,0 +1,240 @@ +; FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + +#include + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN SIG_OUTPUT_COMPARE1A +EXTERN SIG_UART_RECV +EXTERN SIG_UART_DATA + + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN vTaskIncrementTick + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortStart + + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + + ORG TIMER1_COMPA_vect ; Vector address + jmp SIG_OUTPUT_COMPARE1A ; ISR + + ORG USART_RXC_vect ; Vector address + jmp SIG_UART_RECV ; ISR + + ORG USART_UDRE_vect ; Vector address + jmp SIG_UART_DATA ; ISR + + + RSEG CODE + + + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield() and vPortYieldFromTick() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskIncrementTick ; Call the timer tick function. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + + END + diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h new file mode 100644 index 000000000..8f9ddb43a --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -0,0 +1,1914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYSC { + AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register + AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register + AT91_REG SYSC_AIC_IVR; // IRQ Vector Register + AT91_REG SYSC_AIC_FVR; // FIQ Vector Register + AT91_REG SYSC_AIC_ISR; // Interrupt Status Register + AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register + AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register + AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register + AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register + AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register + AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register + AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register + AT91_REG SYSC_AIC_SPU; // Spurious Vector Register + AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register + AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register + AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG SYSC_DBGU_CR; // Control Register + AT91_REG SYSC_DBGU_MR; // Mode Register + AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register + AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register + AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register + AT91_REG SYSC_DBGU_CSR; // Channel Status Register + AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register + AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register + AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register + AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register + AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register + AT91_REG SYSC_DBGU_RCR; // Receive Counter Register + AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register + AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register + AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register + AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register + AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register + AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register + AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG SYSC_PIOA_PER; // PIO Enable Register + AT91_REG SYSC_PIOA_PDR; // PIO Disable Register + AT91_REG SYSC_PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG SYSC_PIOA_OER; // Output Enable Register + AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr + AT91_REG SYSC_PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register + AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register + AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG SYSC_PIOA_SODR; // Set Output Data Register + AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register + AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register + AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register + AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register + AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register + AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register + AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register + AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register + AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register + AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register + AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register + AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG SYSC_PIOA_ASR; // Select A Register + AT91_REG SYSC_PIOA_BSR; // Select B Register + AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register + AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register + AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG SYSC_PMC_SCER; // System Clock Enable Register + AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register + AT91_REG SYSC_PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register + AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG SYSC_PMC_MOR; // Main Oscillator Register + AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG SYSC_PMC_PLLR; // PLL Register + AT91_REG SYSC_PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register + AT91_REG SYSC_PMC_IER; // Interrupt Enable Register + AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register + AT91_REG SYSC_PMC_SR; // Status Register + AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved17[36]; // + AT91_REG SYSC_RSTC_RCR; // Reset Control Register + AT91_REG SYSC_RSTC_RSR; // Reset Status Register + AT91_REG SYSC_RSTC_RMR; // Reset Mode Register + AT91_REG Reserved18[5]; // + AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register + AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register + AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register + AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register + AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register + AT91_REG SYSC_PITC_PISR; // Period Interval Status Register + AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register + AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register + AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register + AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register + AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved19[5]; // + AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register +} AT91S_SYSC, *AT91PS_SYSC; + +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG US_XXR; // XON_XOFF Register + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved1[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) + +#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h new file mode 100644 index 000000000..7d2657a20 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -0,0 +1,1812 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +// *** Register offset in AT91S_SYSC structure *** +#define SYSC_AIC_SMR ( 0) // Source Mode Register +#define SYSC_AIC_SVR (128) // Source Vector Register +#define SYSC_AIC_IVR (256) // IRQ Vector Register +#define SYSC_AIC_FVR (260) // FIQ Vector Register +#define SYSC_AIC_ISR (264) // Interrupt Status Register +#define SYSC_AIC_IPR (268) // Interrupt Pending Register +#define SYSC_AIC_IMR (272) // Interrupt Mask Register +#define SYSC_AIC_CISR (276) // Core Interrupt Status Register +#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register +#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register +#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register +#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register +#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register +#define SYSC_AIC_SPU (308) // Spurious Vector Register +#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) +#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register +#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register +#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register +#define SYSC_DBGU_CR (512) // Control Register +#define SYSC_DBGU_MR (516) // Mode Register +#define SYSC_DBGU_IER (520) // Interrupt Enable Register +#define SYSC_DBGU_IDR (524) // Interrupt Disable Register +#define SYSC_DBGU_IMR (528) // Interrupt Mask Register +#define SYSC_DBGU_CSR (532) // Channel Status Register +#define SYSC_DBGU_RHR (536) // Receiver Holding Register +#define SYSC_DBGU_THR (540) // Transmitter Holding Register +#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register +#define SYSC_DBGU_C1R (576) // Chip ID1 Register +#define SYSC_DBGU_C2R (580) // Chip ID2 Register +#define SYSC_DBGU_FNTR (584) // Force NTRST Register +#define SYSC_DBGU_RPR (768) // Receive Pointer Register +#define SYSC_DBGU_RCR (772) // Receive Counter Register +#define SYSC_DBGU_TPR (776) // Transmit Pointer Register +#define SYSC_DBGU_TCR (780) // Transmit Counter Register +#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register +#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register +#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register +#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register +#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register +#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register +#define SYSC_PIOA_PER (1024) // PIO Enable Register +#define SYSC_PIOA_PDR (1028) // PIO Disable Register +#define SYSC_PIOA_PSR (1032) // PIO Status Register +#define SYSC_PIOA_OER (1040) // Output Enable Register +#define SYSC_PIOA_ODR (1044) // Output Disable Registerr +#define SYSC_PIOA_OSR (1048) // Output Status Register +#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register +#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register +#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register +#define SYSC_PIOA_SODR (1072) // Set Output Data Register +#define SYSC_PIOA_CODR (1076) // Clear Output Data Register +#define SYSC_PIOA_ODSR (1080) // Output Data Status Register +#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register +#define SYSC_PIOA_IER (1088) // Interrupt Enable Register +#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register +#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register +#define SYSC_PIOA_ISR (1100) // Interrupt Status Register +#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register +#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register +#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register +#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register +#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register +#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register +#define SYSC_PIOA_ASR (1136) // Select A Register +#define SYSC_PIOA_BSR (1140) // Select B Register +#define SYSC_PIOA_ABSR (1144) // AB Select Status Register +#define SYSC_PIOA_OWER (1184) // Output Write Enable Register +#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register +#define SYSC_PIOA_OWSR (1192) // Output Write Status Register +#define SYSC_PMC_SCER (3072) // System Clock Enable Register +#define SYSC_PMC_SCDR (3076) // System Clock Disable Register +#define SYSC_PMC_SCSR (3080) // System Clock Status Register +#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register +#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register +#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register +#define SYSC_PMC_MOR (3104) // Main Oscillator Register +#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register +#define SYSC_PMC_PLLR (3116) // PLL Register +#define SYSC_PMC_MCKR (3120) // Master Clock Register +#define SYSC_PMC_PCKR (3136) // Programmable Clock Register +#define SYSC_PMC_IER (3168) // Interrupt Enable Register +#define SYSC_PMC_IDR (3172) // Interrupt Disable Register +#define SYSC_PMC_SR (3176) // Status Register +#define SYSC_PMC_IMR (3180) // Interrupt Mask Register +#define SYSC_RSTC_RCR (3328) // Reset Control Register +#define SYSC_RSTC_RSR (3332) // Reset Status Register +#define SYSC_RSTC_RMR (3336) // Reset Mode Register +#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register +#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register +#define SYSC_RTTC_RTVR (3368) // Real-time Value Register +#define SYSC_RTTC_RTSR (3372) // Real-time Status Register +#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register +#define SYSC_PITC_PISR (3380) // Period Interval Status Register +#define SYSC_PITC_PIVR (3384) // Period Interval Value Register +#define SYSC_PITC_PIIR (3388) // Period Interval Image Register +#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register +#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register +#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register +#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_C1R (64) // Chip ID1 Register +#define DBGU_C2R (68) // Chip ID2 Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pad Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_RC0R (56) // Receive Compare 0 Register +#define SSC_RC1R (60) // Receive Compare 1 Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_XXR (72) // XON_XOFF Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_SMR ( 8) // Slave Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel 0 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) + + diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h new file mode 100644 index 000000000..ae4f35f81 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) + +#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h new file mode 100644 index 000000000..96b680a5e --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) + + diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h new file mode 100644 index 000000000..6b73f8a93 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h new file mode 100644 index 000000000..5b8dfe811 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) + + diff --git a/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h new file mode 100644 index 000000000..9d012c4d7 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -0,0 +1,3265 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7S64.h +//* Object : AT91SAM7S64 inlined functions +//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +//* +//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// +//*---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7S64_H +#define lib_AT91SAM7S64_H + +/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA10_DTXD ) | + ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA14_PWM3 ) | + ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PA25_PWM2 ) | + ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PA24_PWM1 ) | + ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PA23_PWM0 ) | + ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA17_TD ) | + ((unsigned int) AT91C_PA15_TF ) | + ((unsigned int) AT91C_PA19_RK ) | + ((unsigned int) AT91C_PA18_RD ) | + ((unsigned int) AT91C_PA20_RF ) | + ((unsigned int) AT91C_PA16_TK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_NPCS0 ) | + ((unsigned int) AT91C_PA13_MOSI ) | + ((unsigned int) AT91C_PA31_NPCS1 ) | + ((unsigned int) AT91C_PA12_MISO ) | + ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A + ((unsigned int) AT91C_PA9_NPCS1 ) | + ((unsigned int) AT91C_PA30_NPCS2 ) | + ((unsigned int) AT91C_PA10_NPCS2 ) | + ((unsigned int) AT91C_PA22_NPCS3 ) | + ((unsigned int) AT91C_PA3_NPCS3 ) | + ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA26_TIOA2 ) | + ((unsigned int) AT91C_PA27_TIOB2 ) | + ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TIOA1 ) | + ((unsigned int) AT91C_PA16_TIOB1 ) | + ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA0_TIOA0 ) | + ((unsigned int) AT91C_PA1_TIOB0 ) | + ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA17_PCK1 ) | + ((unsigned int) AT91C_PA21_PCK1 ) | + ((unsigned int) AT91C_PA31_PCK2 ) | + ((unsigned int) AT91C_PA18_PCK2 ) | + ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA3_TWD ) | + ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA21_RXD1 ) | + ((unsigned int) AT91C_PA27_DTR1 ) | + ((unsigned int) AT91C_PA26_DCD1 ) | + ((unsigned int) AT91C_PA22_TXD1 ) | + ((unsigned int) AT91C_PA24_RTS1 ) | + ((unsigned int) AT91C_PA23_SCK1 ) | + ((unsigned int) AT91C_PA28_DSR1 ) | + ((unsigned int) AT91C_PA29_RI1 ) | + ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA5_RXD0 ) | + ((unsigned int) AT91C_PA6_TXD0 ) | + ((unsigned int) AT91C_PA7_RTS0 ) | + ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A + ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A + ((unsigned int) AT91C_PA20_IRQ0 ) | + ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B +} + +#endif // lib_AT91SAM7S64_H diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h new file mode 100644 index 000000000..805a2bce9 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X128.h +//* Object : AT91SAM7X128 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X128_H +#define lib_AT91SAM7X128_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X128_H diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h new file mode 100644 index 000000000..02ee9008d --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/Source/portable/IAR/AtmelSAM7S64/port.c b/Source/portable/IAR/AtmelSAM7S64/port.c new file mode 100644 index 000000000..0fbd8de9c --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/port.c @@ -0,0 +1,253 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + unsigned portLONG ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* Currently the IAR port requires the preemptive tick function to be + defined in an asm file. */ + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); + + #else + + extern void ( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/Source/portable/IAR/AtmelSAM7S64/portasm.s79 new file mode 100644 index 000000000..691b95be4 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -0,0 +1,59 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vTaskIncrementTick + + PUBLIC vPortYieldProcessor + PUBLIC vPortPreemptiveTick + PUBLIC vPortStartFirstTask + +#include "AT91SAM7S64_inc.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTick: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vTaskIncrementTick ; Increment the tick count - this may wake a task. + mov lr, pc + BX R0 + LDR R0, =vTaskSwitchContext ; Select the next task to execute. + mov lr, pc + BX R0 + + LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt + LDR R0, [R14, #PITC_PIVR ] + + LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC + STR R14, [R14, #AIC_EOICR] + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/Source/portable/IAR/AtmelSAM7S64/portmacro.h new file mode 100644 index 000000000..daf2b7238 --- /dev/null +++ b/Source/portable/IAR/AtmelSAM7S64/portmacro.h @@ -0,0 +1,109 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/Source/portable/IAR/LPC2000/ISR_Support.h b/Source/portable/IAR/LPC2000/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/Source/portable/IAR/LPC2000/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/Source/portable/IAR/LPC2000/port.c b/Source/portable/IAR/LPC2000/port.c new file mode 100644 index 000000000..3c274b5e7 --- /dev/null +++ b/Source/portable/IAR/LPC2000/port.c @@ -0,0 +1,313 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Philips ARM7 port. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* This function is called from an asm wrapper, so does not require the __irq + keyword. */ + void vPortPreemptiveTick( void ); + void vPortPreemptiveTick( void ) + { + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPortPreemptiveTickEntry )( void ); + + VICVectAddr0 = ( unsigned portLONG ) vPortPreemptiveTickEntry; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + + VICVectAddr0 = ( portLONG ) vPortNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Source/portable/IAR/LPC2000/portasm.s79 b/Source/portable/IAR/LPC2000/portasm.s79 new file mode 100644 index 000000000..d679660f2 --- /dev/null +++ b/Source/portable/IAR/LPC2000/portasm.s79 @@ -0,0 +1,50 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vTaskIncrementTick + EXTERN vPortPreemptiveTick + + PUBLIC vPortPreemptiveTickEntry + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickEntry: +#if configUSE_PREEMPTION == 1 + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. +#endif + + END + diff --git a/Source/portable/IAR/LPC2000/portmacro.h b/Source/portable/IAR/LPC2000/portmacro.h new file mode 100644 index 000000000..daf2b7238 --- /dev/null +++ b/Source/portable/IAR/LPC2000/portmacro.h @@ -0,0 +1,109 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/Source/portable/IAR/STR71x/ISR_Support.h b/Source/portable/IAR/STR71x/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/Source/portable/IAR/STR71x/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/Source/portable/IAR/STR71x/port.c b/Source/portable/IAR/STR71x/port.c new file mode 100644 index 000000000..894ae688b --- /dev/null +++ b/Source/portable/IAR/STR71x/port.c @@ -0,0 +1,250 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR71x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "wdg.h" +#include "eic.h" + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +__arm __irq void vPortNonPreemptiveTick( void ); +void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +__arm __irq void vPortNonPreemptiveTick( void ) +{ + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set the watchdog up to generate a periodic tick. */ + WDG_ECITConfig( DISABLE ); + WDG_CntOnOffConfig( DISABLE ); + WDG_PeriodValueConfig( configTICK_RATE_HZ ); + + /* Setup the tick interrupt in the EIC. */ + EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); + EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + WDG_ECITConfig( ENABLE ); + + /* Start the timer - interrupts are actually disabled at this point so + it is safe to do this here. */ + WDG_CntOnOffConfig( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Source/portable/IAR/STR71x/portasm.s79 b/Source/portable/IAR/STR71x/portasm.s79 new file mode 100644 index 000000000..d9f0fc347 --- /dev/null +++ b/Source/portable/IAR/STR71x/portasm.s79 @@ -0,0 +1,49 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + PUBLIC vPortPreemptiveTickISR + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get used if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. + MOV lr, pc + BX R0 + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/Source/portable/IAR/STR71x/portmacro.h b/Source/portable/IAR/STR71x/portmacro.h new file mode 100644 index 000000000..dbafdfeb0 --- /dev/null +++ b/Source/portable/IAR/STR71x/portmacro.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* EIC utilities. */ +#define portEIC_CICR_ADDR *( ( unsigned portLONG * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( unsigned portLONG * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR + +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/Source/portable/Keil/ARM7/port.c b/Source/portable/Keil/ARM7/port.c new file mode 100644 index 000000000..8229533f4 --- /dev/null +++ b/Source/portable/Keil/ARM7/port.c @@ -0,0 +1,242 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port + * using the Keil compiler. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + Remember where the top of the (simulated) stack is before we place + anything on it. */ + pxOriginalTOS = pxTopOfStack; + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef KEIL_THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* The code generated by the Keil compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Start the first task. This is done from portISR.c as ARM mode must be + used. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. If this is required - stop the tick ISR then + return back to main. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + #ifdef KEIL_THUMB_INTERWORK + extern void ( vPreemptiveTick )( void ) __arm __task; + #else + extern void ( vPreemptiveTick )( void ) __task; + #endif + + VICVectAddr0 = ( unsigned portLONG ) vPreemptiveTick; + } + #else + { + extern void ( vNonPreemptiveTick )( void ) __irq; + + VICVectAddr0 = ( portLONG ) vNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/Keil/ARM7/portISR.c b/Source/portable/Keil/ARM7/portISR.c new file mode 100644 index 000000000..d8140df1e --- /dev/null +++ b/Source/portable/Keil/ARM7/portISR.c @@ -0,0 +1,244 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* This file must always be compiled to ARM mode as it contains ISR +definitions. */ +#pragma ARM + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/*-----------------------------------------------------------*/ + +/* The code generated by the Keil compiler does not maintain separate +stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +use the stack as per other ports. Instead a variable is used to keep +track of the critical section nesting. This variable has to be stored +as part of the task context and must be initialised to a non zero value. */ + +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Interrupt service routine for the SWI interrupt. The vector table is + * configured within startup.s. + * + * vPortYieldProcessor() is used to manually force a context switch. The + * SWI interrupt is generated by a call to taskYIELD() or portYIELD(). + */ +void vPortYieldProcessor( void ) __task +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + __asm{ ADD LR, LR, #4 }; + + /* Perform the context switch. */ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* + * The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ + void vNonPreemptiveTick( void ); + void vNonPreemptiveTick( void ) __irq + { + /* Increment the tick count - this may make a delaying task ready + to run - but a context switch is not performed. */ + vTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* + * The preemptive scheduler ISR is defined as "naked" as the full context + * is saved on entry as part of the context switch. + */ + void vPreemptiveTick( void ); + void vPreemptiveTick( void ) __task + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may make a delayed task ready to + run. */ + vTaskIncrementTick(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the highest priority task that is ready to + run. */ + portRESTORE_CONTEXT(); + } +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here + * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined + * then the utilities are defined as macros in portmacro.h - as per other + * ports. + */ +#ifdef KEIL_THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __task; + void vPortEnableInterruptsFromThumb( void ) __task; + + void vPortDisableInterruptsFromThumb( void ) __task + { + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + __asm{ BX R14 }; /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) __task + { + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + __asm{ BX R14 }; /* Return back to thumb. */ + } + +#endif /* KEIL_THUMB_INTERWORK */ + + + +/* The code generated by the Keil compiler does not maintain separate +stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +use the stack as per other ports. Instead a variable is used to keep +track of the critical section nesting. This necessitates the use of a +function in place of the macro. */ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + } + } +} + + + + + + + + + + diff --git a/Source/portable/Keil/ARM7/portmacro.h b/Source/portable/Keil/ARM7/portmacro.h new file mode 100644 index 000000000..dc0b1b796 --- /dev/null +++ b/Source/portable/Keil/ARM7/portmacro.h @@ -0,0 +1,224 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile unsigned portLONG ulCriticalNesting; \ +extern volatile void * volatile pxCurrentTCB; \ + \ + __asm{ LDR R1, =pxCurrentTCB };/* Set the LR to the task stack. The location was ... */ \ + __asm{ LDR R0, [R1] }; /* ... stored in pxCurrentTCB. */ \ + __asm{ LDR LR, [R0] }; \ + \ + __asm{ LDR R0, =ulCriticalNesting }; /* The critical nesting depth is the first item on ... */ \ + __asm{ LDMFD LR!, {R1 } } /* ... the stack. Load it into the ulCriticalNesting var. */ \ + __asm{ STR R1, [R0] } \ + \ + __asm{ LDMFD LR!, {R0} }; /* Get the SPSR from the stack. */ \ + __asm{ MSR SPSR_CXSF, R0 }; \ + \ + __asm{ LDMFD LR, {R0-R14}^ }; /* Restore all system mode registers for the task. */ \ + __asm{ NOP }; \ + \ + __asm{ LDR LR, [LR, #+60] }; /* Restore the return address. */ \ + \ + /* And return - correcting the offset in the LR to obtain ... */ \ + __asm{ SUBS PC, LR, #4 }; /* ... the correct address. */ \ +} +/*----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile unsigned portLONG ulCriticalNesting; \ +extern volatile void * volatile pxCurrentTCB; \ + \ + __asm{ STMDB SP!, {R0} }; /* Store R0 first as we need to use it. */ \ + \ + __asm{ STMDB SP,{SP}^ }; /* Set R0 to point to the task stack pointer. */ \ + __asm{ NOP }; \ + __asm{ SUB SP, SP, #4 }; \ + __asm{ LDMIA SP!,{R0} }; \ + \ + __asm{ STMDB R0!, {LR} }; /* Push the return address onto the stack. */ \ + __asm{ MOV LR, R0 }; /* Now we have saved LR we can use it instead of R0. */ \ + __asm{ LDMIA SP!, {R0} }; /* Pop R0 so we can save it onto the system mode stack. */ \ + \ + __asm{ STMDB LR,{R0-LR}^ }; /* Push all the system mode registers onto the task stack. */ \ + __asm{ NOP }; \ + __asm{ SUB LR, LR, #60 }; \ + \ + __asm{ MRS R0, SPSR }; /* Push the SPSR onto the task stack. */ \ + __asm{ STMDB LR!, {R0} }; \ + \ + __asm{ LDR R0, =ulCriticalNesting }; \ + __asm{ LDR R0, [R0] }; \ + __asm{ STMDB LR!, {R0} }; \ + \ + __asm{ LDR R0, =pxCurrentTCB };/* Store the new top of stack for the task. */ \ + __asm{ LDR R1, [R0] }; \ + __asm{ STR LR, [R1] }; \ +} + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from an ISR. + *----------------------------------------------------------*/ + +#define portENTER_SWITCHING_ISR() \ + portSAVE_CONTEXT(); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + portRESTORE_CONTEXT(); + + +/* Yield the processor - force a context switch. */ +#define portYIELD() __asm{ SWI 0 }; +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + +/*----------------------------------------------------------- + * Interrupt control macros. + * + * The interrupt management utilities can only be called from ARM mode. When + * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + *----------------------------------------------------------*/ + +#ifdef KEIL_THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __task; + extern void vPortEnableInterruptsFromThumb( void ) __task; + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + /*-----------------------------------------------------------*/ + + #define portDISABLE_INTERRUPTS() \ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ \ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ + __asm{ LDMIA SP!, {R0} } /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ \ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ + __asm{ LDMIA SP!, {R0} } /* Pop R0. */ + +#endif /* KEIL_THUMB_INTERWORK */ + +/*----------------------------------------------------------- + * Critical section control + * + * The code generated by the Keil compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This necessitates the use of a + * function in place of the macro. + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define register +#define portNOP() __asm{ NOP } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __task +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/MPLAB/PIC18F/port.c b/Source/portable/MPLAB/PIC18F/port.c new file mode 100644 index 000000000..9e9c53179 --- /dev/null +++ b/Source/portable/MPLAB/PIC18F/port.c @@ -0,0 +1,626 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes between V1.2.4 and V1.2.5 + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes from V1.2.5 + + + Set the interrupt vector address to 0x08. Previously it was at the + incorrect address for compatibility mode of 0x18. + +Changes from V2.1.1 + + + PCLATU and PCLATH are now saved as part of the context. This allows + function pointers to be used within tasks. Thanks to Javier Espeche + for the enhancement. + +Changes from V2.3.1 + + + TABLAT is now saved as part of the task context. + +Changes from V3.2.0 + + + TBLPTRU is now initialised to zero as the MPLAB compiler expects this + value and does not write to the register. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPLAB library include file. */ +#include "timers.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC port. + *----------------------------------------------------------*/ + +/* Hardware setup for tick. */ +#define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 ) + +/* Initial interrupt enable state for newly created tasks. This value is +copied into INTCON when a task switches in for the first time. */ +#define portINITAL_INTERRUPT_STATE 0xc0 + +/* Just the bit within INTCON for the global interrupt flag. */ +#define portGLOBAL_INTERRUPT_FLAG 0x80 + +/* Constant used for context switch macro when we require the interrupt +enable state to be unchanged when the interrupted task is switched back in. */ +#define portINTERRUPTS_UNCHANGED 0x00 + +/* Some memory areas get saved as part of the task context. These memory +area's get used by the compiler for temporary storage, especially when +performing mathematical operations, or when using 32bit data types. This +constant defines the size of memory area which must be saved. */ +#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* IO port constants. */ +#define portBIT_SET ( ( unsigned portCHAR ) 1 ) +#define portBIT_CLEAR ( ( unsigned portCHAR ) 0 ) + +/* + * The serial port ISR's are defined in serial.c, but are called from portable + * as they use the same vector as the tick ISR. + */ +void vSerialTxISR( void ); +void vSerialRxISR( void ); + +/* + * Perform hardware setup to enable ticks. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * ISR to maintain the tick, and perform tick context switches if the + * preemptive scheduler is being used. + */ +static void prvTickISR( void ); + +/* + * ISR placed on the low priority vector. This calls the appropriate ISR for + * the actual interrupt. + */ +static void prvLowInterrupt( void ); + +/* + * Macro that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save the INTCON + * register with the enable bits forced to be set - and ucForcedInterruptFlags + * must contain these bit settings. This means the interrupts will again be + * enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to save the INTCON so it is restored with its current state, + * and ucForcedInterruptFlags must be 0. This allows a yield from within + * a critical section. + * + * The compiler uses some locations at the bottom of the memory for temporary + * storage during math and other computations. This is especially true if + * 32bit data types are utilised (as they are by the scheduler). The .tmpdata + * and MATH_DATA sections have to be stored in there entirety as part of a task + * context. This macro stores from data address 0x00 to + * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo + * applications but you should check the map file for your project to ensure + * this is sufficient for your needs. It is not clear whether this size is + * fixed for all compilations or has the potential to be program specific. + */ +#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \ +{ \ + _asm \ + /* Save the status and WREG registers first, as these will get modified \ + by the operations below. */ \ + MOVFF WREG, PREINC1 \ + MOVFF STATUS, PREINC1 \ + /* Save the INTCON register with the appropriate bits forced if \ + necessary - as described above. */ \ + MOVFF INTCON, WREG \ + IORLW ucForcedInterruptFlags \ + MOVFF WREG, PREINC1 \ + _endasm \ + \ + portDISABLE_INTERRUPTS(); \ + \ + _asm \ + /* Store the necessary registers to the stack. */ \ + MOVFF BSR, PREINC1 \ + MOVFF FSR2L, PREINC1 \ + MOVFF FSR2H, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + MOVFF TABLAT, PREINC1 \ + MOVFF TBLPTRU, PREINC1 \ + MOVFF TBLPTRH, PREINC1 \ + MOVFF TBLPTRL, PREINC1 \ + MOVFF PRODH, PREINC1 \ + MOVFF PRODL, PREINC1 \ + MOVFF PCLATU, PREINC1 \ + MOVFF PCLATH, PREINC1 \ + /* Store the .tempdata and MATH_DATA areas as described above. */ \ + CLRF FSR0L, 0 \ + CLRF FSR0H, 0 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF INDF0, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + /* Store the hardware stack pointer in a temp register before we \ + modify it. */ \ + MOVFF STKPTR, FSR0L \ + _endasm \ + \ + /* Store each address from the hardware stack. */ \ + while( STKPTR > ( unsigned portCHAR ) 0 ) \ + { \ + _asm \ + MOVFF TOSL, PREINC1 \ + MOVFF TOSH, PREINC1 \ + MOVFF TOSU, PREINC1 \ + POP \ + _endasm \ + } \ + \ + _asm \ + /* Store the number of addresses on the hardware stack (from the \ + temporary register). */ \ + MOVFF FSR0L, PREINC1 \ + MOVF PREINC1, 1, 0 \ + _endasm \ + \ + /* Save the new top of the software stack in the TCB. */ \ + _asm \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + MOVFF FSR1L, POSTINC0 \ + MOVFF FSR1H, POSTINC0 \ + _endasm \ +} +/*-----------------------------------------------------------*/ + +/* + * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more + * details. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + \ + /* De-reference FSR0 to set the address it holds into FSR1. \ + (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ + MOVFF POSTINC0, FSR1L \ + MOVFF POSTINC0, FSR1H \ + \ + /* How many return addresses are there on the hardware stack? Discard \ + the first byte as we are pointing to the next free space. */ \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR0L \ + _endasm \ + \ + /* Fill the hardware stack from our software stack. */ \ + STKPTR = 0; \ + \ + while( STKPTR < FSR0L ) \ + { \ + _asm \ + PUSH \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSU, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSH, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSL, 0 \ + _endasm \ + } \ + \ + _asm \ + /* Restore the .tmpdata and MATH_DATA memory. */ \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, INDF0 \ + /* Restore the other registers forming the tasks context. */ \ + MOVFF POSTDEC1, PCLATH \ + MOVFF POSTDEC1, PCLATU \ + MOVFF POSTDEC1, PRODL \ + MOVFF POSTDEC1, PRODH \ + MOVFF POSTDEC1, TBLPTRL \ + MOVFF POSTDEC1, TBLPTRH \ + MOVFF POSTDEC1, TBLPTRU \ + MOVFF POSTDEC1, TABLAT \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR2H \ + MOVFF POSTDEC1, FSR2L \ + MOVFF POSTDEC1, BSR \ + /* The next byte is the INTCON register. Read this into WREG as some \ + manipulation is required. */ \ + MOVFF POSTDEC1, WREG \ + _endasm \ + \ + /* From the INTCON register, only the interrupt enable bits form part \ + of the tasks context. It is perfectly legitimate for another task to \ + have modified any other bits. We therefore only restore the top two bits. \ + */ \ + if( WREG & portGLOBAL_INTERRUPT_FLAG ) \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return enabling interrupts. */ \ + RETFIE 0 \ + _endasm \ + } \ + else \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return without effecting interrupts. The context may have \ + been saved from a critical region. */ \ + RETURN 0 \ + _endasm \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulAddress; +unsigned portCHAR ucBlock; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + + + /* Simulate how the stack would look after a call to vPortYield() generated + by the compiler. + + First store the function parameters. This is where the task will expect to + find them when it starts running. */ + ulAddress = ( unsigned portLONG ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + ulAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + /* Next we just leave a space. When a context is saved the stack pointer + is incremented before it is used so as not to corrupt whatever the stack + pointer is actually pointing to. This is especially necessary during + function epilogue code generated by the compiler. */ + *pxTopOfStack = 0x44; + pxTopOfStack++; + + /* Next are all the registers that form part of the task context. */ + + *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */ + pxTopOfStack++; + + /* INTCON is saved with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */ + pxTopOfStack++; + + /* Next the .tmpdata and MATH_DATA sections. */ + for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ ) + { + *pxTopOfStack = ( portSTACK_TYPE ) ucBlock; + *pxTopOfStack++; + } + + /* Store the top of the global data section. */ + *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */ + pxTopOfStack++; + + /* The only function return address so far is the address of the + task. */ + ulAddress = ( unsigned portLONG ) pxCode; + + /* TOS low. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS high. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS even higher. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + /* Store the number of return addresses on the hardware stack - so far only + the address of the task entry point. */ + *pxTopOfStack = ( portSTACK_TYPE ) 1; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* In this port we ignore the parameter and use the configUSE_PREEMPTION + definition instead. */ + + /* Setup a timer for the tick ISR is using the preemptive scheduler. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here. Use the function name to stop compiler warnings. */ + ( void ) prvLowInterrupt; + ( void ) prvTickISR; + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* This can get called with interrupts either enabled or disabled. We + will save the INTCON register with the interrupt enable bits unmodified. */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Start executing the task we have just switched to. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Vector for ISR. Nothing here must alter any registers! + */ +#pragma code high_vector=0x08 +static void prvLowInterrupt( void ) +{ + /* Was the interrupt the tick? */ + if( PIR1bits.CCP1IF ) + { + _asm + goto prvTickISR + _endasm + } + + /* Was the interrupt a byte being received? */ + if( PIR1bits.RCIF ) + { + _asm + goto vSerialRxISR + _endasm + } + + /* Was the interrupt the Tx register becoming empty? */ + if( PIR1bits.TXIF ) + { + if( PIE1bits.TXIE ) + { + _asm + goto vSerialTxISR + _endasm + } + } +} +#pragma code + +/*-----------------------------------------------------------*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + save the context with interrupts enabled. */ + portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG ); + PIR1bits.CCP1IF = 0; + + /* Maintain the tick count. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + #endif + + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ ); +unsigned portLONG ulCompareValue; +unsigned portCHAR ucByte; + + /* Interrupts are disabled when this function is called. + + Setup CCP1 to provide the tick interrupt using a compare match on timer + 1. + + Clear the time count then setup timer. */ + TMR1H = ( unsigned portCHAR ) 0x00; + TMR1L = ( unsigned portCHAR ) 0x00; + + /* Set the compare match value. */ + ulCompareValue = ulConstCompareValue; + CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); + ulCompareValue >>= ( unsigned portLONG ) 8; + CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); + + CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */ + CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */ + PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */ + + /* We are only going to use the global interrupt bit, so set the peripheral + bit to true. */ + INTCONbits.GIEL = portBIT_SET; + + /* Provided library function for setting up the timer that will produce the + tick. */ + OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 ); +} + diff --git a/Source/portable/MPLAB/PIC18F/portmacro.h b/Source/portable/MPLAB/PIC18F/portmacro.h new file mode 100644 index 000000000..0cda0a3aa --- /dev/null +++ b/Source/portable/MPLAB/PIC18F/portmacro.h @@ -0,0 +1,110 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned char +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portGLOBAL_INT_ENABLE_BIT 0x80 +#define portSTACK_GROWTH 1 +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0; +#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1; + +/* Push the INTCON register onto the stack, then disable interrupts. */ +#define portENTER_CRITICAL() POSTINC1 = INTCON; \ + INTCONbits.GIEH = 0; + +/* Retrieve the INTCON register from the stack, and enable interrupts +if they were saved as being enabled. Don't modify any other bits +within the INTCON register as these may have lagitimately have been +modified within the critical region. */ +#define portEXIT_CRITICAL() _asm \ + MOVF POSTDEC1, 1, 0 \ + _endasm \ + if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \ + { \ + portENABLE_INTERRUPTS(); \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline + +#define portNOP() _asm \ + NOP \ + _endasm + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/MPLAB/PIC18F/stdio.h b/Source/portable/MPLAB/PIC18F/stdio.h new file mode 100644 index 000000000..e69de29bb diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c new file mode 100644 index 000000000..4d05bd5c0 --- /dev/null +++ b/Source/portable/MemMang/heap_1.c @@ -0,0 +1,132 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + +Changes between V2.5.1 and V2.5.1 + + + The memory pool has been defined within a struct to ensure correct memory + alignment on 32bit systems. + +Changes between V2.6.1 and V3.0.0 + + + An overflow check has been added to ensure the next free byte variable + does not wrap around. +*/ + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Setup the correct byte alignment mask for the defined byte alignment. */ +#if portBYTE_ALIGNMENT == 4 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) +#endif + +#ifndef heapBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +static struct xRTOS_HEAP +{ + unsigned portLONG ulDummy; + unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +static size_t xNextFreeByte = ( size_t ) 0; +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn = NULL; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + #if portBYTE_ALIGNMENT != 1 + if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); + } + #endif + + vTaskSuspendAll(); + { + /* Check there is enough room left for the allocation. */ + if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + block. */ + pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); + xNextFreeByte += xWantedSize; + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c + for alternative implementations, and the memory management pages of + http://www.FreeRTOS.org for more information. */ + ( void ) pv; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} + + diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c new file mode 100644 index 000000000..ed935df84 --- /dev/null +++ b/Source/portable/MemMang/heap_2.c @@ -0,0 +1,236 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that permits + * allocated blocks to be freed, but does not combine adjacent free blocks + * into a single larger block. + * + * See heap_1.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include + +#include "FreeRTOS.h" +#include "task.h" + +/* Setup the correct byte alignment mask for the defined byte alignment. */ +#if portBYTE_ALIGNMENT == 4 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) +#endif + +#ifndef heapBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +static struct xRTOS_HEAP +{ + unsigned portLONG ulDummy; + unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +/* Define the linked list structure. This is used to link free blocks in order +of their size. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} xBlockLink; + + +static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) + +/* Create a couple of list links to mark the start and end of the list. */ +static xBlockLink xStart, xEnd; + +/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ + +/* + * Insert a block into the list of free blocks - which is ordered by size of + * the block. Small blocks at the start of the list and large blocks at the end + * of the list. + */ +#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ +{ \ +xBlockLink *pxIterator; \ +size_t xBlockSize; \ + \ + xBlockSize = pxBlockToInsert->xBlockSize; \ + \ + /* Iterate through the list until a block is found that has a larger size */ \ + /* than the block we are inserting. */ \ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ + { \ + /* There is nothing to do here - just iterate to the correct position. */ \ + } \ + \ + /* Update the list to include the block being inserted in the correct */ \ + /* position. */ \ + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ + pxIterator->pxNextFreeBlock = pxBlockToInsert; \ +} +/*-----------------------------------------------------------*/ + +#define prvHeapInit() \ +{ \ +xBlockLink *pxFirstFreeBlock; \ + \ + /* xStart is used to hold a pointer to the first item in the list of free */ \ + /* blocks. The void cast is used to prevent compiler warnings. */ \ + xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ + xStart.xBlockSize = ( size_t ) 0; \ + \ + /* xEnd is used to mark the end of the list of free blocks. */ \ + xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ + xEnd.pxNextFreeBlock = NULL; \ + \ + /* To start with there is a single free block that is sized to take up the \ + entire heap space. */ \ + pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ + pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ + pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ +} +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; +void *pvReturn = NULL; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } + + /* The wanted size is increased so it can contain a xBlockLink + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += heapSTRUCT_SIZE; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); + } + } + + if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) + { + /* Blocks are stored in byte order - traverse the list from the start + (smallest) block until one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If we found the end marker then a block of adequate size was not found. */ + if( pxBlock != &xEnd ) + { + /* Return the memory space - jumping over the xBlockLink structure + at its start. */ + pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); + + /* This block is being returned for use so must be taken our of the + list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new block + following the number of bytes requested. The void cast is + used to prevent byte alignment warnings from the compiler. */ + pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the single + block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + } + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ +unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; +xBlockLink *pxLink; + + if( pv ) + { + /* The memory being freed will have an xBlockLink structure immediately + before it. */ + puc -= heapSTRUCT_SIZE; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c new file mode 100644 index 000000000..b2ec40f0e --- /dev/null +++ b/Source/portable/MemMang/heap_3.c @@ -0,0 +1,79 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_2.c and heap_1.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } +} + + + diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c new file mode 100644 index 000000000..226c148e3 --- /dev/null +++ b/Source/portable/RVDS/ARM_CM3/port.c @@ -0,0 +1,297 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes between V4.0.0 and V4.0.1 + + + Reduced the code used to setup the initial stack frame. + + The kernel no longer has to install or handle the fault interrupt. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) +#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) +#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) +#define portNVIC_HARD_FAULT_STATUS 0xe000ed2c +#define portNVIC_FORCED_FAULT_BIT 0x40000000 +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portNVIC_PENDSV_PRI 0x00ff0000 +#define portNVIC_SVCALL_PRI 0xff000000 +#define portNVIC_SYSTICK_PRI 0xff000000 + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; + +/* Constant hardware definitions to assist asm code. */ +const unsigned long ulHardFaultStatus = portNVIC_HARD_FAULT_STATUS; +const unsigned long ulNVICIntCtrl = ( unsigned long ) 0xe000ed04; +const unsigned long ulForceFaultBit = portNVIC_FORCED_FAULT_BIT; +const unsigned long ulPendSVBit = portNVIC_PENDSVSET; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Set the MSP/PSP to a known value. + */ +void prvSetMSP( unsigned long ulValue ); +void prvSetPSP( unsigned long ulValue ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0xfffffffd; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +__asm void prvSetPSP( unsigned long ulValue ) +{ + msr psp, r0 + bx lr; +} +/*-----------------------------------------------------------*/ + +__asm void prvSetMSP( unsigned long ulValue ) +{ + msr msp, r0 + bx lr; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + *(portNVIC_SYSPRI1) |= portNVIC_SVCALL_PRI; + + /* Start the first task. */ + prvSetPSP( 0 ); + prvSetMSP( *((unsigned portLONG *) 0 ) ); + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* Enable interrupts */ + portENABLE_INTERRUPTS(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the CM3 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +__asm void vPortDisableInterrupts( void ) +{ + cpsid i; + bx lr; +} +/*-----------------------------------------------------------*/ + +__asm void vPortEnableInterrupts( void ) +{ + cpsie i; + bx lr; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + vPortDisableInterrupts(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + vPortEnableInterrupts(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + + /* Start first task if the stack has not yet been setup. */ + mrs r0, psp + cbz r0, no_save + + /* Save the context into the TCB. */ + sub r0, #0x20 + stm r0, {r4-r11} + sub r0, #0x04 + ldr r1, =uxCriticalNesting + ldr r1, [r1] + stm r0, {r1} + ldr r1, =pxCurrentTCB + ldr r1, [r1] + str r0, [r1] + +no_save; + + /* Find the task to execute. */ + ldr r0, =vTaskSwitchContext + push {r14} + cpsid i + blx r0 + cpsie i + pop {r14} + + /* Restore the context. */ + ldr r1, =pxCurrentTCB + ldr r1, [r1]; + ldr r0, [r1]; + ldm r0, {r1, r4-r11} + ldr r2, =uxCriticalNesting + str r1, [r2] + ldr r2, [r2] + add r0, #0x24 + msr psp, r0 + orr r14, #0xd + + /* Exit with interrupts in the state required by the task. */ + cbnz r2, sv_disable_interrupts + + bx r14 + +sv_disable_interrupts; + cpsid i + bx r14 +} +/*-----------------------------------------------------------*/ + +__asm void xPortSysTickHandler( void ) +{ + extern vTaskIncrementTick + + /* Call the scheduler tick function. */ + ldr r0, =vTaskIncrementTick + push {r14} + cpsid i + blx r0 + cpsie i + pop {r14} + + /* If using preemption, also force a context switch. */ + #if configUSE_PREEMPTION == 1 + extern vPortYieldFromISR + push {r14} + ldr r0, =vPortYieldFromISR + blx r0 + pop {r14} + #endif + + /* Exit with interrupts in the correct state. */ + ldr r2, =uxCriticalNesting + ldr r2, [r2] + cbnz r2, tick_disable_interrupts + + bx r14 + +tick_disable_interrupts; + cpsid i + bx r14 +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} + + diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h new file mode 100644 index 000000000..e1867234e --- /dev/null +++ b/Source/portable/RVDS/ARM_CM3/portmacro.h @@ -0,0 +1,102 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +extern void vPortYieldFromISR( void ); + +#define portYIELD() vPortYieldFromISR() +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortDisableInterrupts( void ); +extern void vPortEnableInterrupts( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortDisableInterrupts() +#define portENABLE_INTERRUPTS() vPortEnableInterrupts() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline +#define portNOP() + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/Rowley/ARM7/readme.txt b/Source/portable/Rowley/ARM7/readme.txt new file mode 100644 index 000000000..8d3e87f57 --- /dev/null +++ b/Source/portable/Rowley/ARM7/readme.txt @@ -0,0 +1 @@ +The Rowley ARM7 demo uses the GCC ARM7 port files. \ No newline at end of file diff --git a/Source/portable/Rowley/MSP430F449/Port1/port.c b/Source/portable/Rowley/MSP430F449/Port1/port.c new file mode 100644 index 000000000..651fffa5e --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port1/port.c @@ -0,0 +1,177 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/Rowley/MSP430F449/Port1/portext.asm b/Source/portable/Rowley/MSP430F449/Port1/portext.asm new file mode 100644 index 000000000..4bf0aeb06 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port1/portext.asm @@ -0,0 +1,116 @@ +#include "FreeRTOSConfig.h" + +portSAVE_CONTEXT macro + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + reti + endm +/*-----------------------------------------------------------*/ + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_vTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + call #_vTaskSwitchContext + #endif + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/Source/portable/Rowley/MSP430F449/Port1/portmacro.h b/Source/portable/Rowley/MSP430F449/Port1/portmacro.h new file mode 100644 index 000000000..f13fa9b81 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port1/portmacro.h @@ -0,0 +1,134 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_RB_PORT + +#define portNOP() + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/Rowley/MSP430F449/Port2/port.c b/Source/portable/Rowley/MSP430F449/Port2/port.c new file mode 100644 index 000000000..7627415ef --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port2/port.c @@ -0,0 +1,221 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + * Milos Prokic + * + * File adopted from the MSP430 GCC port + * Interrupt handling, xPortStartScheduler, vPortYield, portSAVE_CONTEXT(), portRESTORE_CONTEXT() +/* Standard includes. */ + +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +unsigned portCHAR ucReschedule; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void ISROsTick( void ) + { + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void ISROsTick( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/Source/portable/Rowley/MSP430F449/Port2/portext.asm b/Source/portable/Rowley/MSP430F449/Port2/portext.asm new file mode 100644 index 000000000..0eb8b6bf3 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port2/portext.asm @@ -0,0 +1,147 @@ +#include + +/* + * Milos Prokic + */ + +/********************************************************** +All Interrupts should follow the naming convention : ISR"name" and declared +as a normal function in C. + +One must not forget to allocate interrupts below (see the line "MSPINT OsTick" +below for an example). + +By default the ISR will not cause the context switch, but if called in +conjunction with portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR(wakeup), where +wakeup = TRUE upon exit the ISR will force the context switch via the +ucReschedule global variable. +**********************************************************/ +MSPINT macro name +_##name:: + call #_portSAVE_CONTEXT + call #_ISR##name + br #_portSWITCH_EXIT + endm + + +/********************************************************** +API code +**********************************************************/ + + .CODE +_vPortYield:: + /* Mimic an INT call by pushing SR. */ + push SR + /* no INTs !! */ + dint + /* Save the context of the current task. */ + call #_portSAVE_CONTEXT + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + /* Restore the context of the new task. */ + br #_portSWITCH_EXIT + +_xPortStartScheduler:: + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + jmp _portRESTORE_CONTEXT + +_portSAVE_CONTEXT:: + /* Function to save the context. When this function is called the + return address will appear on the stack. This does not need to be + saved so is overwritten by R4 - hence R4 is not saved initially. + + Save the general purpose registers. */ + push R5 + push R6 + push R7 + push R8 + push R9 + push R10 + push R11 + push R12 + push R13 + push R14 + push R15 + + /* Now R10 has been saved we can use it to hold the return address, + which is about to be overwritten. */ + mov 22(R1),R10 + + /* Store R4 where the return address was on the stack. */ + mov R4,22(R1) + + /* Save the critical nesting depth. */ + mov.w &_usCriticalNesting, R14 + push R14 + + /* Finally save the new top of stack. */ + mov.w &_pxCurrentTCB, R12 + mov.w R1, @R12 + + /* No rescheduling by default. */ + mov.b #0,&_ucReschedule + + /* Return using the saved return address. */ + br R10 + + +_portSWITCH_EXIT:: + /* Check ucReschedule to see if a context switch is required. */ + tst.b &_ucReschedule + jz _portRESTORE_CONTEXT + call #_vTaskSwitchContext +_portRESTORE_CONTEXT:: + /* Restore the context in the opposite order to the save. */ + mov.w &_pxCurrentTCB, R12 + mov.w @R12, R1 + pop R15 + mov.w R15, &_usCriticalNesting + pop R15 + pop R14 + pop R13 + pop R12 + pop R11 + pop R10 + pop R9 + pop R8 + pop R7 + pop R6 + pop R5 + pop R4 + reti + + +/********************************************************** +Allocate Interrupts using the MSPINT macro (defined at the top of this file. +ex: MSPINT "name" +**********************************************************/ + + MSPINT OsTick + MSPINT Com1Rx + MSPINT Com1Tx + + +/********************************************************* +Interrupt Vectors +Timer_A0 +ex: PORT1 would look like: +ORG PORT1_VECTOR +DW _"name" +**********************************************************/ + .VECTORS + .KEEP + + ORG TIMERA0_VECTOR + DW _OsTick + + ORG UART1RX_VECTOR + DW _Com1Rx + + ORG UART1TX_VECTOR + DW _Com1Tx + + END diff --git a/Source/portable/Rowley/MSP430F449/Port2/portmacro.h b/Source/portable/Rowley/MSP430F449/Port2/portmacro.h new file mode 100644 index 000000000..f3bee44f7 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/Port2/portmacro.h @@ -0,0 +1,144 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); + +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +#define portENTER_SWITCHING_ISR() +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + { \ + extern unsigned portCHAR ucReschedule; \ + if( SwitchRequired ) \ + { \ + ucReschedule = 1; \ + } \ + } + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline +#define portNOP() + + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_MP_PORT + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/Rowley/MSP430F449/port.c b/Source/portable/Rowley/MSP430F449/port.c new file mode 100644 index 000000000..651fffa5e --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/port.c @@ -0,0 +1,177 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/Source/portable/Rowley/MSP430F449/portext.asm b/Source/portable/Rowley/MSP430F449/portext.asm new file mode 100644 index 000000000..4bf0aeb06 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/portext.asm @@ -0,0 +1,116 @@ +#include "FreeRTOSConfig.h" + +portSAVE_CONTEXT macro + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + reti + endm +/*-----------------------------------------------------------*/ + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_vTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + call #_vTaskSwitchContext + #endif + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/Source/portable/Rowley/MSP430F449/portmacro.h b/Source/portable/Rowley/MSP430F449/portmacro.h new file mode 100644 index 000000000..7b02fcd8e --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/portmacro.h @@ -0,0 +1,133 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_RB_PORT + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/Rowley/MSP430F449/readme.txt b/Source/portable/Rowley/MSP430F449/readme.txt new file mode 100644 index 000000000..f438b3642 --- /dev/null +++ b/Source/portable/Rowley/MSP430F449/readme.txt @@ -0,0 +1,5 @@ +To use Port1, copy the three files from the Port1 directory into this directory. + +To use Port2, copy the three files from the Port2 directory into this directory. + +Ensure to perform a complete rebuild. \ No newline at end of file diff --git a/Source/portable/SDCC/Cygnal/port.c b/Source/portable/SDCC/Cygnal/port.c new file mode 100644 index 000000000..d830617f2 --- /dev/null +++ b/Source/portable/SDCC/Cygnal/port.c @@ -0,0 +1,427 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Cygnal port. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup timer 2 to produce the RTOS tick. */ +#define portCLOCK_DIVISOR ( ( unsigned portLONG ) 12 ) +#define portMAX_TIMER_VALUE ( ( unsigned portLONG ) 0xffff ) +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x04 ) +#define portTIMER_2_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* The value used in the IE register when a task first starts. */ +#define portGLOBAL_INTERRUPT_BIT ( ( portSTACK_TYPE ) 0x80 ) + +/* The value used in the PSW register when a task first starts. */ +#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00 ) + +/* Macro to clear the timer 2 interrupt flag. */ +#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80; + +/* Used during a context switch to store the size of the stack being copied +to or from XRAM. */ +data static unsigned portCHAR ucStackBytes; + +/* Used during a context switch to point to the next byte in XRAM from/to which +a RAM byte is to be copied. */ +xdata static portSTACK_TYPE * data pxXRAMStack; + +/* Used during a context switch to point to the next byte in RAM from/to which +an XRAM byte is to be copied. */ +data static portSTACK_TYPE * data pxRAMStack; + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* + * Setup the hardware to generate an interrupt off timer 2 at the required + * frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +/* + * Macro that copies the current stack from internal RAM to XRAM. This is + * required as the 8051 only contains enough internal RAM for a single stack, + * but we have a stack for every task. + */ +#define portCOPY_STACK_TO_XRAM() \ +{ \ + /* pxCurrentTCB points to a TCB which itself points to the location into \ + which the first stack byte should be copied. Set pxXRAMStack to point \ + to the location into which the first stack byte is to be copied. */ \ + pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ + \ + /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \ + pxRAMStack = ( data portSTACK_TYPE * data ) configSTACK_START; \ + \ + /* Calculate the size of the stack we are about to copy from the current \ + stack pointer value. */ \ + ucStackBytes = SP - ( configSTACK_START - 1 ); \ + \ + /* Before starting to copy the stack, store the calculated stack size so \ + the stack can be restored when the task is resumed. */ \ + *pxXRAMStack = ucStackBytes; \ + \ + /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ + have already stored the stack size into XRAM. */ \ + while( ucStackBytes ) \ + { \ + pxXRAMStack++; \ + *pxXRAMStack = *pxRAMStack; \ + pxRAMStack++; \ + ucStackBytes--; \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that copies the stack of the task being resumed from XRAM into + * internal RAM. + */ +#define portCOPY_XRAM_TO_STACK() \ +{ \ + /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \ + copy the data back out of XRAM and into the stack. */ \ + pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ + pxRAMStack = ( data portSTACK_TYPE * data ) ( configSTACK_START - 1 ); \ + \ + /* The first value stored in XRAM was the size of the stack - i.e. the \ + number of bytes we need to copy back. */ \ + ucStackBytes = pxXRAMStack[ 0 ]; \ + \ + /* Copy the required number of bytes back into the stack. */ \ + do \ + { \ + pxXRAMStack++; \ + pxRAMStack++; \ + *pxRAMStack = *pxXRAMStack; \ + ucStackBytes--; \ + } while( ucStackBytes ); \ + \ + /* Restore the stack pointer ready to use the restored stack. */ \ + SP = ( unsigned portCHAR ) pxRAMStack; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro to push the current execution context onto the stack, before the stack + * is moved to XRAM. + */ +#define portSAVE_CONTEXT() \ +{ \ + _asm \ + /* Push ACC first, as when restoring the context it must be restored \ + last (it is used to set the IE register). */ \ + push ACC \ + /* Store the IE register then disable interrupts. */ \ + push IE \ + clr _EA \ + push DPL \ + push DPH \ + push b \ + push ar2 \ + push ar3 \ + push ar4 \ + push ar5 \ + push ar6 \ + push ar7 \ + push ar0 \ + push ar1 \ + push PSW \ + _endasm; \ + PSW = 0; \ + _asm \ + push _bp \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that restores the execution context from the stack. The execution + * context was saved into the stack before the stack was copied into XRAM. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + pop _bp \ + pop PSW \ + pop ar1 \ + pop ar0 \ + pop ar7 \ + pop ar6 \ + pop ar5 \ + pop ar4 \ + pop ar3 \ + pop ar2 \ + pop b \ + pop DPH \ + pop DPL \ + /* The next byte of the stack is the IE register. Only the global \ + enable bit forms part of the task context. Pop off the IE then set \ + the global enable bit to match that of the stored IE register. */ \ + pop ACC \ + JB ACC.7,0098$ \ + CLR IE.7 \ + LJMP 0099$ \ + 0098$: \ + SETB IE.7 \ + 0099$: \ + /* Finally pop off the ACC, which was the first register saved. */ \ + pop ACC \ + reti \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulAddress; +portSTACK_TYPE *pxStartOfStack; + + /* Leave space to write the size of the stack as the first byte. */ + pxStartOfStack = pxTopOfStack; + pxTopOfStack++; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be uncommented if required. + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + */ + + /* Simulate how the stack would look after a call to the scheduler tick + ISR. + + The return address that would have been pushed by the MCU. */ + ulAddress = ( unsigned portLONG ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress ); + pxTopOfStack++; + + /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */ + *pxTopOfStack = 0xaa; /* acc */ + pxTopOfStack++; + + /* We want tasks to start with interrupts enabled. */ + *pxTopOfStack = portGLOBAL_INTERRUPT_BIT; + pxTopOfStack++; + + /* The function parameters will be passed in the DPTR and B register as + a three byte generic pointer is used. */ + ulAddress = ( unsigned portLONG ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPL */ + ulAddress >>= 8; + *pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPH */ + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* b */ + pxTopOfStack++; + + /* The remaining registers are straight forward. */ + *pxTopOfStack = 0x02; /* R2 */ + pxTopOfStack++; + *pxTopOfStack = 0x03; /* R3 */ + pxTopOfStack++; + *pxTopOfStack = 0x04; /* R4 */ + pxTopOfStack++; + *pxTopOfStack = 0x05; /* R5 */ + pxTopOfStack++; + *pxTopOfStack = 0x06; /* R6 */ + pxTopOfStack++; + *pxTopOfStack = 0x07; /* R7 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* R0 */ + pxTopOfStack++; + *pxTopOfStack = 0x01; /* R1 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* PSW */ + pxTopOfStack++; + *pxTopOfStack = 0xbb; /* BP */ + + /* Dont increment the stack size here as we don't want to include + the stack size byte as part of the stack size count. + + Finally we place the stack size at the beginning. */ + *pxStartOfStack = ( portSTACK_TYPE ) ( pxTopOfStack - pxStartOfStack ); + + /* Unlike most ports, we return the start of the stack as this is where the + size of the stack is stored. */ + return pxStartOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup timer 2 to generate the RTOS tick. */ + prvSetupTimerInterrupt(); + + /* Make sure we start with the expected SFR page. This line should not + really be required. */ + SFRPAGE = 0; + + /* Copy the stack for the first task to execute from XRAM into the stack, + restore the task context from the new stack, then start running the task. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + + /* Should never get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented for this port. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) _naked +{ + /* Save the execution context onto the stack, then copy the entire stack + to XRAM. This is necessary as the internal RAM is only large enough to + hold one stack, and we want one per task. + + PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH + IS REQUIRED. */ + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + /* Call the standard scheduler context switch function. */ + vTaskSwitchContext(); + + /* Copy the stack of the task about to execute from XRAM into RAM and + restore it's context ready to run on exiting. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + void vTimer2ISR( void ) interrupt 5 _naked + { + /* Preemptive context switch function triggered by the timer 2 ISR. + This does the same as vPortYield() (see above) with the addition + of incrementing the RTOS tick count. */ + + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + vTaskIncrementTick(); + vTaskSwitchContext(); + + portCLEAR_INTERRUPT_FLAG(); + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + } +#else + void vTimer2ISR( void ) interrupt 5 + { + /* When using the cooperative scheduler the timer 2 ISR is only + required to increment the RTOS tick count. */ + + vTaskIncrementTick(); + portCLEAR_INTERRUPT_FLAG(); + } +#endif +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + +/* Constants calculated to give the required timer capture values. */ +const unsigned portLONG ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR; +const unsigned portLONG ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ; +const unsigned portLONG ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime; +const unsigned portCHAR ucLowCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue & ( unsigned portLONG ) 0xff ); +const unsigned portCHAR ucHighCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue >> ( unsigned portLONG ) 8 ); + + /* NOTE: This uses a timer only present on 8052 architecture. */ + + /* Remember the current SFR page so we can restore it at the end of the + function. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + /* TMR2CF can be left in its default state. */ + TMR2CF = ( unsigned portCHAR ) 0; + + /* Setup the overflow reload value. */ + RCAP2L = ucLowCaptureByte; + RCAP2H = ucHighCaptureByte; + + /* The initial load is performed manually. */ + TMR2L = ucLowCaptureByte; + TMR2H = ucHighCaptureByte; + + /* Enable the timer 2 interrupts. */ + IE |= portTIMER_2_INTERRUPT_ENABLE; + + /* Interrupts are disabled when this is called so the timer can be started + here. */ + TMR2CN = portENABLE_TIMER; + + /* Restore the original SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} + + + + diff --git a/Source/portable/SDCC/Cygnal/portmacro.h b/Source/portable/SDCC/Cygnal/portmacro.h new file mode 100644 index 000000000..998cdbb34 --- /dev/null +++ b/Source/portable/SDCC/Cygnal/portmacro.h @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if configUSE_PREEMPTION == 0 + void vTimer2ISR( void ) interrupt 5; +#else + void vTimer2ISR( void ) interrupt 5 _naked; +#endif + +void vSerialISR( void ) interrupt 4; + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE float +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() _asm \ + push ACC \ + push IE \ + _endasm; \ + EA = 0; + +#define portEXIT_CRITICAL() _asm \ + pop ACC \ + _endasm; \ + ACC &= 0x80; \ + IE |= ACC; \ + _asm \ + pop ACC \ + _endasm; + +#define portDISABLE_INTERRUPTS() EA = 0; +#define portENABLE_INTERRUPTS() EA = 1; +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( 1 ) +#define portTICK_RATE_MS ( ( unsigned portLONG ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ) _naked; +#define portYIELD() vPortYield(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define portNOP() _asm \ + nop \ + _endasm; + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c new file mode 100644 index 000000000..514801da4 --- /dev/null +++ b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -0,0 +1,143 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode is pulled inline and portTICKisr() is therefore + deleted from this file. + + + Prescaler logic for Timer1 added to allow for a wider + range of TickRates. + +Changes from V3.0.1 +*/ + +#include +#include + +/* IO port constants. */ +#define portBIT_SET (1) +#define portBIT_CLEAR (0) + +/* + * Hardware setup for the tick. + * We use a compare match on timer1. Depending on MPU-frequency + * and requested tickrate, a prescaled value with a matching + * prescaler are determined. + */ +#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ) + +#if portTIMER_COMPARE_BASE < 0x10000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x20000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#elif portTIMER_COMPARE_BASE < 0x40000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x80000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#else + #error "TickRate out of range" +#endif + +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +void portSetupTick( void ) +{ + /* + * Interrupts are disabled when this function is called. + */ + + /* + * Setup CCP1 + * Provide the tick interrupt using a compare match on timer1. + */ + + /* + * Set the compare match value. + */ + CCPR1H = ( unsigned portCHAR ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff ); + CCPR1L = ( unsigned portCHAR ) ( portTIMER_COMPARE_VALUE & 0xff ); + + /* + * Set Compare Special Event Trigger Mode + */ + bCCP1M3 = portBIT_SET; + bCCP1M2 = portBIT_CLEAR; + bCCP1M1 = portBIT_SET; + bCCP1M0 = portBIT_SET; + + /* + * Enable CCP1 interrupt + */ + bCCP1IE = portBIT_SET; + + /* + * We are only going to use the global interrupt bit, so disable + * interruptpriorities and enable peripheral interrupts. + */ + bIPEN = portBIT_CLEAR; + bPEIE = portBIT_SET; + + /* + * Set up timer1 + * It will produce the system tick. + */ + + /* + * Clear the time count + */ + TMR1H = ( unsigned portCHAR ) 0x00; + TMR1L = ( unsigned portCHAR ) 0x00; + + /* + * Setup the timer + */ + bRD16 = portBIT_SET; // 16-bit + bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler + bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler + bT1OSCEN = portBIT_SET; // Oscillator enable + bT1SYNC = portBIT_SET; // No external clock sync + bTMR1CS = portBIT_CLEAR; // Internal clock + + bTMR1ON = portBIT_SET; // Start timer1 +} diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c new file mode 100644 index 000000000..db32fdbaf --- /dev/null +++ b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -0,0 +1,86 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ + +#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C +#define _FREERTOS_DRIVERS_TICK_ISRTICK_C + +{ + /* + * Was the interrupt the SystemClock? + */ + if( bCCP1IF && bCCP1IE ) + { + /* + * Reset the interrupt flag + */ + bCCP1IF = 0; + + /* + * Maintain the tick count. + */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* + * Ask for a switch to the highest priority task + * that is ready to run. + */ + uxSwitchRequested = pdTRUE; + } + #endif + } +} + +#pragma wizcpp uselib "$__PATHNAME__/Tick.c" + +#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */ diff --git a/Source/portable/WizC/PIC18/Install.bat b/Source/portable/WizC/PIC18/Install.bat new file mode 100644 index 000000000..af00cd352 --- /dev/null +++ b/Source/portable/WizC/PIC18/Install.bat @@ -0,0 +1,164 @@ +@echo off +cls + +SET PACKAGENAME=the FreeRTOS port for fedC and wizC + +echo. +echo Hello, I'm the installationscript for %PACKAGENAME%. +echo. + +:CHECKFEDC + set FED=C:\Program Files\FED\PIC_C + echo. + echo I'm checking your system for fedC + if not exist "%FED%" goto NOFEDC + echo YES, I found a fedC-installation! + goto FOUNDFED +:NOFEDC + echo I could not find a fedC-installation. + + +:CHECKWIZC + set FED=C:\Program Files\FED\PIXIE + echo. + echo I'm checking your system for wizC + if not exist "%FED%" goto NOWIZC + echo YES, I found a wizC-installation! + goto FOUNDFED +:noWIZC + echo I could not find a wizC-installation. + + +:ERROR + echo. + echo. + echo I could not find a FED C-compiler installation on your system. + echo. + echo Perhaps I got confused because you installed fedC or wizC in a non-default directory. + echo If this is the case, please change the path at the top of this install-script. + echo After that rerun the script and I will be happy to try again. + echo. + goto ENDIT + + +:FOUNDFED + echo. + echo. + + set FEDLIBS=%FED%\Libs + set FEDLIBSUSER=%FEDLIBS%\LibsUser + + if exist "%FEDLIBS%" goto INSTALL + echo The FED installationdirectory "%FED%" + echo contains no Libs subdirectory. This is weird! + echo. + echo Installation is aborted, sorry... + goto ENDIT + + +:INSTALL + echo I am about to install %PACKAGENAME% + echo into directory %FEDLIBSUSER% + echo. + echo Press 'enter' to let me do my thing + echo Press 'ctrl-c' to stop me + pause >nul + echo. + echo Installing... + + +:RESET_READONLY + echo. + echo Removing ReadOnly attributes + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + +:CREATE_DIRECTORIES + echo. + echo Creating directories (if necessary)... + if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%" + if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules" + echo Done + + + echo. + echo Copying Files... +:COPY_MODULES + echo Modules... + copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + +:COPY_DRIVERS + echo Drivers... + copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + +:COPY_HEADERS + echo Headers... + copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul + + + echo Done + + +:SET_READONLY + echo. + echo Setting files to ReadOnly + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + + +:FINISHED + echo. + echo The installation of %PACKAGENAME% is completed. + echo. + echo Please review the installation instructions as additional libraries and + echo fedC/wizC configuration settings are needed for FreeRTOS to function correctly. + + goto ENDIT + + +:ENDIT + echo. + echo. + echo Press 'enter' to close this window + pause >nul \ No newline at end of file diff --git a/Source/portable/WizC/PIC18/addFreeRTOS.h b/Source/portable/WizC/PIC18/addFreeRTOS.h new file mode 100644 index 000000000..7ef370bdd --- /dev/null +++ b/Source/portable/WizC/PIC18/addFreeRTOS.h @@ -0,0 +1,54 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * The installation script will automatically prepend this file to the default FreeRTOS.h. + */ + +#ifndef WIZC_FREERTOS_H +#define WIZC_FREERTOS_H + +#pragma noheap +#pragma wizcpp expandnl on +#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/tasks.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/queue.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/list.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/port.c" + +#endif /* WIZC_FREERTOS_H */ diff --git a/Source/portable/WizC/PIC18/port.c b/Source/portable/WizC/PIC18/port.c new file mode 100644 index 000000000..1010a406a --- /dev/null +++ b/Source/portable/WizC/PIC18/port.c @@ -0,0 +1,313 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.2.1 + + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12. + +Changes from V3.2.0 + + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves + an error on devices with more than 64kB ROM. + +Changes from V3.0.0 + + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being + handled before the scheduler is started. + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include +#include + +#include + +/*--------------------------------------------------------------------------- + * Implementation of functions defined in portable.h for the WizC PIC18 port. + *---------------------------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to + * know any details of its type. + */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* + * Define minimal-stack constants + * ----- + * FSR's: + * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L, + * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL, + * (PCLATU), PCLATH + * sfr's within parenthesis only on devices > 64kB + * ----- + * Call/Return stack: + * 2 bytes per entry on devices <= 64kB + * 3 bytes per entry on devices > 64kB + * ----- + * Other bytes: + * 2 bytes: FunctionParameter for initial taskcode + * 1 byte : Number of entries on call/return stack + * 1 byte : ucCriticalNesting + * 16 bytes: Free space on stack + */ +#if _ROMSIZE > 0x8000 + #define portSTACK_FSR_BYTES ( 15 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 ) +#else + #define portSTACK_FSR_BYTES ( 13 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 ) +#endif + +#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 ) +#define portSTACK_OTHER_BYTES ( 20 ) + +unsigned portSHORT usCalcMinStackSize = 0; + +/*-----------------------------------------------------------*/ + +/* + * We initialise ucCriticalNesting to the middle value an + * unsigned char can contain. This way portENTER_CRITICAL() + * and portEXIT_CRITICAL() can be called without interrupts + * being enabled before the scheduler starts. + */ +register unsigned portCHAR ucCriticalNesting = 0x7F; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a new task. + * See portSAVE_CONTEXT macro for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portCHAR ucScratch; + /* + * Get the size of the RAMarea in page 0 used by the compiler + * We do this here already to avoid W-register conflicts. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movwf PRODL,ACCESS ; PRODL is used as temp register + _Pragma("asmend") + ucScratch = PRODL; + + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. + */ +// *pxTopOfStack-- = 0x11; +// *pxTopOfStack-- = 0x22; +// *pxTopOfStack-- = 0x33; + + /* + * Simulate how the stack would look after a call to vPortYield() + * generated by the compiler. + */ + + /* + * First store the function parameters. This is where the task expects + * to find them when it starts running. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) ( (( unsigned portSHORT ) pvParameters >> 8) & 0x00ff ); + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pvParameters & 0x00ff ); + + /* + * Next are all the registers that form part of the task context. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x11; /* STATUS. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x22; /* WREG. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x33; /* BSR. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x44; /* PRODH. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x55; /* PRODL. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x66; /* FSR0H. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x77; /* FSR0L. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x88; /* FSR1H. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x99; /* FSR1L. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xAA; /* TABLAT. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xCC; /* TBLPTRH. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDD; /* TBLPTRL. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xEE; /* PCLATU. */ +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF; /* PCLATH. */ + + /* + * Next the compiler's scratchspace. + */ + while(ucScratch-- > 0) + { + *pxTopOfStack-- = ( portSTACK_TYPE ) 0; + } + + /* + * The only function return address so far is the address of the task entry. + * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the + * stack, too. TOSU is always written as zero here because wizC does not allow + * functionpointers to point above 64kB in ROM. + */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0; +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( ( unsigned portSHORT ) pxCode >> 8 ) & 0x00ff ); + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pxCode & 0x00ff ); + + /* + * Store the number of return addresses on the hardware stack. + * So far only the address of the task entry point. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 1; + + /* + * The code generated by wizC does not maintain separate + * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ) +{ + /* + * Fetch the size of compiler's scratchspace. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movlb usCalcMinStackSize>>8 + movwf usCalcMinStackSize,BANKED + _Pragma("asmend") + + /* + * Add minimum needed stackspace + */ + usCalcMinStackSize += ( portSTACK_FSR_BYTES ) + + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE ) + + ( portSTACK_OTHER_BYTES ); + + return(usCalcMinStackSize); +} + +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + extern void portSetupTick( void ); + + /* + * Setup a timer for the tick ISR for the preemptive scheduler. + */ + portSetupTick(); + + /* + * Restore the context of the first task to run. + */ + portRESTORE_CONTEXT(); + + /* + * This point should never be reached during execution. + */ + return pdTRUE; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* + * It is unlikely that the scheduler for the PIC port will get stopped + * once running. When called a reset is done which is probably the + * most valid action. + */ + _Pragma(asmline reset); +} + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* + * Switch to the highest priority task that is ready to run. + */ + vTaskSwitchContext(); + + /* + * Start executing the task we have just switched to. + */ + portRESTORE_CONTEXT(); +} + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( unsigned portSHORT usWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( ( malloc_t ) usWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} + +void vPortFree( void *pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } +} diff --git a/Source/portable/WizC/PIC18/portmacro.h b/Source/portable/WizC/PIC18/portmacro.h new file mode 100644 index 000000000..3b9950561 --- /dev/null +++ b/Source/portable/WizC/PIC18/portmacro.h @@ -0,0 +1,423 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if !defined(_SERIES) || _SERIES != 18 + #error "WizC supports FreeRTOS on the Microchip PIC18-series only" +#endif + +#if !defined(QUICKCALL) || QUICKCALL != 1 + #error "QuickCall must be enabled (see ProjectOptions/Optimisations)" +#endif + +#include +#include + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE portFLOAT +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned char +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) ( 0xFFFF ) +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) ( 0xFFFFFFFF ) +#endif + +#define portBYTE_ALIGNMENT 1 + +/*-----------------------------------------------------------*/ + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be forced when the interrupted task is switched back in. + */ +#define portINTERRUPTS_FORCED (0x01) + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be unchanged when the interrupted task is switched back in. + */ +#define portINTERRUPTS_UNCHANGED (0x00) + +/* Initial interrupt enable state for newly created tasks. This value is + * used when a task switches in for the first time. + */ +#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED) + +/* + * Macros to modify the global interrupt enable bit in INTCON. + */ +#define portDISABLE_INTERRUPTS() \ + do \ + { \ + bGIE=0; \ + } while(bGIE) // MicroChip recommends this check! + +#define portENABLE_INTERRUPTS() \ + do \ + { \ + bGIE=1; \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * Critical section macros. + */ +extern unsigned portCHAR ucCriticalNesting; + +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portCHAR ) 0 ) + +#define portENTER_CRITICAL() \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + /* \ + * Now interrupts are disabled ucCriticalNesting \ + * can be accessed directly. Increment \ + * ucCriticalNesting to keep a count of how \ + * many times portENTER_CRITICAL() has been called. \ + */ \ + ucCriticalNesting++; \ + } while(0) + +#define portEXIT_CRITICAL() \ + do \ + { \ + if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \ + { \ + /* \ + * Decrement the nesting count as we are leaving a \ + * critical section. \ + */ \ + ucCriticalNesting--; \ + } \ + \ + /* \ + * If the nesting level has reached zero then \ + * interrupts should be re-enabled. \ + */ \ + if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * The minimal stacksize is calculated on the first reference of + * portMINIMAL_STACK_SIZE. Some input to this calculation is + * compiletime determined, other input is port-defined (see port.c) + */ +extern unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ); +extern unsigned portSHORT usCalcMinStackSize; + +#define portMINIMAL_STACK_SIZE \ + ((usCalcMinStackSize == 0) \ + ? usPortCALCULATE_MINIMAL_STACK_SIZE() \ + : usCalcMinStackSize ) + +/* + * WizC uses a downgrowing stack + */ +#define portSTACK_GROWTH ( -1 ) + +/*-----------------------------------------------------------*/ + +/* + * Macro's that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU + * are only saved/restored on devices with more than 64kB (32k Words) ROM. + * + * The stackpointer is helt by WizC in FSR2 and points to the first free byte. + * WizC uses a "downgrowing" stack. There is no framepointer. + * + * We keep track of the interruptstatus using ucCriticalNesting. When this + * value equals zero, interrupts have to be enabled upon exit from the + * portRESTORE_CONTEXT macro. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save + * ucCriticalNesting with value zero. This means the interrupts will again be + * re-enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to keep the current value of ucCritialNesting so it is restored + * with its current value. This allows a yield from within a critical section. + * + * The compiler uses some locations at the bottom of RAM for temporary + * storage. The compiler may also have been instructed to optimize + * function-parameters and local variables to global storage. The compiler + * uses an area called LocOpt for this wizC feature. + * The total overheadstorage has to be saved in it's entirety as part of + * a task context. These macro's store/restore from data address 0x0000 to + * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1). + * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated + * assembler definitions. + */ + +#define portSAVE_CONTEXT( ucInterruptForced ) \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + _Pragma("asm") \ + ; \ + ; Push the relevant SFR's onto the task's stack \ + ; \ + movff STATUS,POSTDEC2 \ + movff WREG,POSTDEC2 \ + movff BSR,POSTDEC2 \ + movff PRODH,POSTDEC2 \ + movff PRODL,POSTDEC2 \ + movff FSR0H,POSTDEC2 \ + movff FSR0L,POSTDEC2 \ + movff FSR1H,POSTDEC2 \ + movff FSR1L,POSTDEC2 \ + movff TABLAT,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff TBLPTRU,POSTDEC2 \ + endif \ + movff TBLPTRH,POSTDEC2 \ + movff TBLPTRL,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff PCLATU,POSTDEC2 \ + endif \ + movff PCLATH,POSTDEC2 \ + ; \ + ; Store the compiler-scratch-area as described above. \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + clrf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_S1: \ + movff POSTINC0,POSTDEC2 \ + decfsz WREG,W,ACCESS \ + SMARTJUMP _rtos_S1 \ + ; \ + ; Save the pic call/return-stack belonging to the \ + ; current task by copying it to the task's software- \ + ; stack. We save the hardware stack pointer (which \ + ; is the number of addresses on the stack) in the \ + ; W-register first because we need it later and it \ + ; is modified in the save-loop by executing pop's. \ + ; After the loop the W-register is stored on the \ + ; stack, too. \ + ; \ + movf STKPTR,W,ACCESS \ + bz _rtos_s3 \ + _rtos_S2: \ + if __ROMSIZE > 0x8000 \ + movff TOSU,POSTDEC2 \ + endif \ + movff TOSH,POSTDEC2 \ + movff TOSL,POSTDEC2 \ + pop \ + tstfsz STKPTR,ACCESS \ + SMARTJUMP _rtos_S2 \ + _rtos_s3: \ + movwf POSTDEC2,ACCESS \ + ; \ + ; Next the value for ucCriticalNesting used by the \ + ; task is stored on the stack. When \ + ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \ + ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \ + ; \ + if ucInterruptForced == portINTERRUPTS_FORCED \ + clrf POSTDEC2,ACCESS \ + else \ + movff ucCriticalNesting,POSTDEC2 \ + endif \ + ; \ + ; Save the new top of the software stack in the TCB. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + movff FSR2L,POSTINC0 \ + movff FSR2H,POSTINC0 \ + _Pragma("asmend") \ + } while(0) + +/************************************************************/ + +/* + * This is the reverse of portSAVE_CONTEXT. + */ +#define portRESTORE_CONTEXT() \ + do \ + { \ + _Pragma("asm") \ + ; \ + ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + ; \ + ; De-reference FSR0 to set the address it holds into \ + ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \ + ; is used by wizC as stackpointer. \ + ; \ + movff POSTINC0,FSR2L \ + movff POSTINC0,FSR2H \ + ; \ + ; Next, the value for ucCriticalNesting used by the \ + ; task is retrieved from the stack. \ + ; \ + movff PREINC2,ucCriticalNesting \ + ; \ + ; Rebuild the pic call/return-stack. The number of \ + ; return addresses is the next item on the task stack. \ + ; Save this number in PRODL. Then fetch the addresses \ + ; and store them on the hardwarestack. \ + ; The datasheets say we can't use movff here... \ + ; \ + movff PREINC2,PRODL // Use PRODL as tempregister \ + clrf STKPTR,ACCESS \ + _rtos_R1: \ + push \ + movf PREINC2,W,ACCESS \ + movwf TOSL,ACCESS \ + movf PREINC2,W,ACCESS \ + movwf TOSH,ACCESS \ + if __ROMSIZE > 0x8000 \ + movf PREINC2,W,ACCESS \ + movwf TOSU,ACCESS \ + else \ + clrf TOSU,ACCESS \ + endif \ + decfsz PRODL,F,ACCESS \ + SMARTJUMP _rtos_R1 \ + ; \ + ; Restore the compiler's working storage area to page 0 \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + movwf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_R2: \ + decf FSR0L,F,ACCESS \ + movff PREINC2,INDF0 \ + tstfsz FSR0L,ACCESS \ + SMARTJUMP _rtos_R2 \ + ; \ + ; Restore the sfr's forming the tasks context. \ + ; We cannot yet restore bsr, w and status because \ + ; we need these registers for a final test. \ + ; \ + movff PREINC2,PCLATH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,PCLATU \ + else \ + clrf PCLATU,ACCESS \ + endif \ + movff PREINC2,TBLPTRL \ + movff PREINC2,TBLPTRH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,TBLPTRU \ + else \ + clrf TBLPTRU,ACCESS \ + endif \ + movff PREINC2,TABLAT \ + movff PREINC2,FSR1L \ + movff PREINC2,FSR1H \ + movff PREINC2,FSR0L \ + movff PREINC2,FSR0H \ + movff PREINC2,PRODL \ + movff PREINC2,PRODH \ + ; \ + ; The return from portRESTORE_CONTEXT() depends on \ + ; the value of ucCriticalNesting. When it is zero, \ + ; interrupts need to be enabled. This is done via a \ + ; retfie instruction because we need the \ + ; interrupt-enabling and the return to the restored \ + ; task to be uninterruptable. \ + ; Because bsr, status and W are affected by the test \ + ; they are restored after the test. \ + ; \ + movlb ucCriticalNesting>>8 \ + tstfsz ucCriticalNesting,BANKED \ + SMARTJUMP _rtos_R4 \ + _rtos_R3: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + retfie 0 ; Return enabling interrupts \ + _rtos_R4: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + return 0 ; Return without affecting interrupts \ + _Pragma("asmend") \ + } while(0) + +/*-----------------------------------------------------------*/ + +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) + +/*-----------------------------------------------------------*/ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +#define portNOP() _Pragma("asm") \ + nop \ + _Pragma("asmend") + +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION( xFunction, pvParameters ) \ + void pointed xFunction( void *pvParameters ) \ + _Pragma(asmfunc xFunction) + +#define portTASK_FUNCTION_PROTO portTASK_FUNCTION +/*-----------------------------------------------------------*/ + +#define inline +#define volatile +#define register + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..f472d8e26 --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -0,0 +1,255 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + portRESET_PIC() is now called last thing before the end of the preemptive + tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portSHORT sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depend on whether or not the preemptive or cooperative +kernel is being used. */ +#if configUSE_PREEMPTION == 1 + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const unsigned portSHORT usTimerDisable = 0x0000; +unsigned portSHORT usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usMaxCountRegister = 0xff5a; +const unsigned portSHORT usTimerPriorityRegister = 0xff32; +const unsigned portSHORT usTimerEnable = 0xC000; +const unsigned portSHORT usRetrigger = 0x0001; +const unsigned portSHORT usTimerHighPriority = 0x0000; +unsigned portSHORT usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const unsigned portLONG ulClockFrequency = 0x7f31a0; + +unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h new file mode 100644 index 000000000..a94426518 --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -0,0 +1,104 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/oWatcom/16BitDOS/PC/port.c b/Source/portable/oWatcom/16BitDOS/PC/port.c new file mode 100644 index 000000000..f3bf74677 --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/PC/port.c @@ -0,0 +1,294 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + prvPortResetPIC() is now called last thing before the end of the + preemptive tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +*/ + +#include +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static portSHORT sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portSHORT sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + /* This won't set the frequency quite the same as it was, + but using an integer value removes the need for any floating + point in the scheduler code. */ + prvSetTickFrequency( ( unsigned portLONG ) portDOS_TICK_RATE ); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; +unsigned portLONG ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); +} + + +/*lint +e950 */ + diff --git a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h new file mode 100644 index 000000000..024db6b0c --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -0,0 +1,100 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section definitions. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define inline +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/Source/portable/oWatcom/16BitDOS/common/portasm.h b/Source/portable/oWatcom/16BitDOS/common/portasm.h new file mode 100644 index 000000000..fbbf48aee --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/common/portasm.h @@ -0,0 +1,115 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#ifdef DEBUG_BUILD + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ + "add bp, 0x0002" + + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#else + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#endif + + diff --git a/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/Source/portable/oWatcom/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..dcd4d3542 --- /dev/null +++ b/Source/portable/oWatcom/16BitDOS/common/portcomn.c @@ -0,0 +1,146 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.4.2: + + + pvPortMalloc and vPortFree have been removed. The projects now use + the definitions from the source/portable/MemMang directory. + +Changes from V2.6.1: + + + usPortCheckFreeStackSpace() has been moved to tasks.c. +*/ + + + +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0, *pxOriginalSP; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + status register and interrupt return address. We make this the start + of the task. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* We are going to setup the stack for the new task to look like + the stack frame was setup by a compiler generated ISR. We need to know + the address of the existing stack top to place in the SP register within + the stack frame. pxOriginalSP holds SP before (simulated) pusha was + called. */ + pxOriginalSP = pxTopOfStack; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pvParameters ); /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + pxTopOfStack--; + *pxTopOfStack = DS_Reg; /* DS */ + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + + /* The AX register is pushed again twice - don't know why. */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + + + #ifdef DEBUG_BUILD + /* The compiler adds space to each ISR stack if building to + include debug information. Presumably this is used by the + debugger - we don't need to initialise it to anything just + make sure it is there. */ + pxTopOfStack--; + #endif + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + + diff --git a/Source/portable/readme.txt b/Source/portable/readme.txt new file mode 100644 index 000000000..a20d687e0 --- /dev/null +++ b/Source/portable/readme.txt @@ -0,0 +1,19 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and/or compiler. + + ++ The FreeRTOS/Source/Portable/MemMang directory contains the three sample +memory allocators as described on the http://www.FreeRTOS.org WEB site. + ++ The other directories each contain files specific to a particular +microcontroller or compiler. + + + +For example, if you are interested in the GCC port for the ATMega323 +microcontroller then the port specific files are contained in +FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only +port you are interested in then all the other directories can be +ignored. + diff --git a/Source/queue.c b/Source/queue.c new file mode 100644 index 000000000..73f062a3d --- /dev/null +++ b/Source/queue.c @@ -0,0 +1,869 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.01 + + + More use of 8bit data types. + + Function name prefixes changed where the data type returned has changed. + +Changed from V2.0.0 + + + Added the queue locking mechanism and make more use of the scheduler + suspension feature to minimise the time interrupts have to be disabled + when accessing a queue. + +Changed from V2.2.0 + + + Explicit use of 'signed' qualifier on portCHAR types added. + +Changes from V3.0.0 + + + API changes as described on the FreeRTOS.org WEB site. + +Changes from V3.2.3 + + + Added the queue functions that can be used from co-routines. + +*/ + +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. + */ +typedef struct QueueDefinition +{ + signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ + signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + + signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ + signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ + + xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ + unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ + + signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ +} xQUEUE; +/*-----------------------------------------------------------*/ + +/* + * Inside this file xQueueHandle is a pointer to a xQUEUE structure. + * To keep the definition private the API header file defines it as a + * pointer to void. + */ +typedef xQUEUE * xQueueHandle; + +/* + * Prototypes for public functions are included here so we don't have to + * include the API header file (as it defines xQueueHandle differently). These + * functions are documented in the API header file. + */ +xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); +signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); +unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); +void vQueueDelete( xQueueHandle xQueue ); +signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); +signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); +signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); + +#if configUSE_CO_ROUTINES == 1 + signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); + signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); + signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); + signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); +#endif + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ); + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); + +/* + * Macro that copies an item into the queue. This is done by copying the item + * byte for byte, not by reference. Updates the queue state to ensure it's + * integrity after the copy. + */ +#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ +{ \ + memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ + ++( pxQueue->uxMessagesWaiting ); \ + pxQueue->pcWriteTo += pxQueue->uxItemSize; \ + if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ + { \ + pxQueue->pcWriteTo = pxQueue->pcHead; \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ +{ \ + taskENTER_CRITICAL(); \ + ++( pxQueue->xRxLock ); \ + ++( pxQueue->xTxLock ); \ + taskEXIT_CRITICAL(); \ +} +/*-----------------------------------------------------------*/ + + +/*----------------------------------------------------------- + * PUBLIC QUEUE MANAGEMENT API documented in queue.h + *----------------------------------------------------------*/ + +xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) +{ +xQUEUE *pxNewQueue; +size_t xQueueSizeInBytes; + + /* Allocate the new queue structure. */ + if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) + { + pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); + if( pxNewQueue != NULL ) + { + /* Create the list of pointers to queue items. The queue is one byte + longer than asked for to make wrap checking easier/faster. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; + + pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); + if( pxNewQueue->pcHead != NULL ) + { + /* Initialise the queue members as described above where the + queue type is defined. */ + pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); + pxNewQueue->uxMessagesWaiting = 0; + pxNewQueue->pcWriteTo = pxNewQueue->pcHead; + pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + pxNewQueue->xRxLock = queueUNLOCKED; + pxNewQueue->xTxLock = queueUNLOCKED; + + /* Likewise ensure the event queues start with the correct state. */ + vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); + + return pxNewQueue; + } + else + { + vPortFree( pxNewQueue ); + } + } + } + + /* Will only reach here if we could not allocate enough memory or no memory + was required. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* Make sure other tasks do not access the queue. */ + vTaskSuspendAll(); + + /* It is important that this is the only thread/ISR that modifies the + ready or delayed lists until xTaskResumeAll() is called. Places where + the ready/delayed lists are modified include: + + + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is + suspended, vTaskDelay() cannot be called from an ISR. + + vTaskPrioritySet() - Has a critical section around the access. + + vTaskSwitchContext() - This will not get executed while the scheduler + is suspended. + + prvCheckDelayedTasks() - This will not get executed while the + scheduler is suspended. + + xTaskCreate() - Has a critical section around the access. + + vTaskResume() - Has a critical section around the access. + + xTaskResumeAll() - Has a critical section around the access. + + xTaskRemoveFromEventList - Checks to see if the scheduler is + suspended. If so then the TCB being removed from the event is + removed from the event and added to the xPendingReadyList. + */ + + /* Make sure interrupts do not access the queue event list. */ + prvLockQueue( pxQueue ); + + /* It is important that interrupts to not access the event list of the + queue being modified here. Places where the event list is modified + include: + + + xQueueSendFromISR(). This checks the lock on the queue to see if + it has access. If the queue is locked then the Tx lock count is + incremented to signify that a task waiting for data can be made ready + once the queue lock is removed. If the queue is not locked then + a task can be moved from the event list, but will not be removed + from the delayed list or placed in the ready list until the scheduler + is unlocked. + + + xQueueReceiveFromISR(). As per xQueueSendFromISR(). + */ + + /* If the queue is already full we may have to block. */ + if( prvIsQueueFull( pxQueue ) ) + { + /* The queue is full - do we want to block or just leave without + posting? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* We are going to place ourselves on the xTasksWaitingToSend event + list, and will get woken should the delay expire, or space become + available on the queue. + + As detailed above we do not require mutual exclusion on the event + list as nothing else can modify it or the ready lists while we + have the scheduler suspended and queue locked. + + It is possible that an ISR has removed data from the queue since we + checked if any was available. If this is the case then the data + will have been copied from the queue, and the queue variables + updated, but the event list will not yet have been checked to see if + anything is waiting as the queue is locked. */ + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Force a context switch now as we are blocked. We can do + this from within a critical section as the task we are + switching to has its own context. When we return here (i.e. we + unblock) we will leave the critical section as normal. + + It is possible that an ISR has caused an event on an unrelated and + unlocked queue. If this was the case then the event list for that + queue will have been updated but the ready lists left unchanged - + instead the readied task will have been added to the pending ready + list. */ + taskENTER_CRITICAL(); + { + /* We can safely unlock the queue and scheduler here as + interrupts are disabled. We must not yield with anything + locked, but we can yield from within a critical section. + + Tasks that have been placed on the pending ready list cannot + be tasks that are waiting for events on this queue. See + in comment xTaskRemoveFromEventList(). */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler may cause a yield. If so then there + is no point yielding again here. */ + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + + /* Before leaving the critical section we have to ensure + exclusive access again. */ + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + } + taskEXIT_CRITICAL(); + } + } + + /* When we are here it is possible that we unblocked as space became + available on the queue. It is also possible that an ISR posted to the + queue since we left the critical section, so it may be that again there + is no space. This would only happen if a task and ISR post onto the + same queue. */ + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyQueueData( pxQueue, pvItemToQueue ); + xReturn = pdPASS; + + /* Update the TxLock count so prvUnlockQueue knows to check for + tasks waiting for data to become available in the queue. */ + ++( pxQueue->xTxLock ); + } + else + { + xReturn = errQUEUE_FULL; + } + } + taskEXIT_CRITICAL(); + + /* We no longer require exclusive access to the queue. prvUnlockQueue + will remove any tasks suspended on a receive if either this function + or an ISR has posted onto the queue. */ + if( prvUnlockQueue( pxQueue ) ) + { + /* Resume the scheduler - making ready any tasks that were woken + by an event while the scheduler was locked. Resuming the + scheduler may cause a yield, in which case there is no point + yielding again here. */ + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + } + else + { + /* Resume the scheduler - making ready any tasks that were woken + by an event while the scheduler was locked. */ + xTaskResumeAll(); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) +{ + /* Similar to xQueueSend, except we don't block if there is no room in the + queue. Also we don't directly wake a task that was blocked on a queue + read, instead we return a flag to say whether a context switch is required + or not (i.e. has a task with a higher priority than us been woken by this + post). */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyQueueData( pxQueue, pvItemToQueue ); + + /* If the queue is locked we do not alter the event list. This will + be done when the queue is unlocked later. */ + if( pxQueue->xTxLock == queueUNLOCKED ) + { + /* We only want to wake one task per ISR, so check that a task has + not already been woken. */ + if( !xTaskPreviouslyWoken ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + return pdTRUE; + } + } + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + ++( pxQueue->xTxLock ); + } + } + + return xTaskPreviouslyWoken; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* This function is very similar to xQueueSend(). See comments within + xQueueSend() for a more detailed explanation. + + Make sure other tasks do not access the queue. */ + vTaskSuspendAll(); + + /* Make sure interrupts do not access the queue. */ + prvLockQueue( pxQueue ); + + /* If there are no messages in the queue we may have to block. */ + if( prvIsQueueEmpty( pxQueue ) ) + { + /* There are no messages in the queue, do we want to block or just + leave with nothing? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + taskENTER_CRITICAL(); + { + prvUnlockQueue( pxQueue ); + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + } + taskEXIT_CRITICAL(); + } + } + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + /* Increment the lock count so prvUnlockQueue knows to check for + tasks waiting for space to become available on the queue. */ + ++( pxQueue->xRxLock ); + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + /* We no longer require exclusive access to the queue. */ + if( prvUnlockQueue( pxQueue ) ) + { + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + } + else + { + xTaskResumeAll(); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) +{ +signed portBASE_TYPE xReturn; + + /* We cannot block from an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + /* If the queue is locked we will not modify the event list. Instead + we update the lock count so the task that unlocks the queue will know + that an ISR has removed data while the queue was locked. */ + if( pxQueue->xRxLock == queueUNLOCKED ) + { + /* We only want to wake one task per ISR, so check that a task has + not already been woken. */ + if( !( *pxTaskWoken ) ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + force a context switch. */ + *pxTaskWoken = pdTRUE; + } + } + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was removed while it was locked. */ + ++( pxQueue->xRxLock ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) +{ +unsigned portBASE_TYPE uxReturn; + + taskENTER_CRITICAL(); + uxReturn = pxQueue->uxMessagesWaiting; + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +void vQueueDelete( xQueueHandle pxQueue ) +{ + vPortFree( pxQueue->pcHead ); + vPortFree( pxQueue ); +} +/*-----------------------------------------------------------*/ + +static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ) +{ +signed portBASE_TYPE xYieldRequired = pdFALSE; + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + { + --( pxQueue->xTxLock ); + + /* See if data was added to the queue while it was locked. */ + if( pxQueue->xTxLock > queueUNLOCKED ) + { + pxQueue->xTxLock = queueUNLOCKED; + + /* Data was posted while the queue was locked. Are any tasks + blocked waiting for data to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + xYieldRequired = pdTRUE; + } + } + } + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + --( pxQueue->xRxLock ); + + if( pxQueue->xRxLock > queueUNLOCKED ) + { + pxQueue->xRxLock = queueUNLOCKED; + + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xYieldRequired = pdTRUE; + } + } + } + } + taskEXIT_CRITICAL(); + + return xYieldRequired; +} +/*-----------------------------------------------------------*/ + +static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) +{ +signed portBASE_TYPE xReturn; + + taskENTER_CRITICAL(); + xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) +{ +signed portBASE_TYPE xReturn; + + taskENTER_CRITICAL(); + xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* If the queue is already full we may have to block. A critical section + is required to prevent an interrupt removing something from the queue + between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) ) + { + /* The queue is full - do we want to block or just leave without + posting? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portNOP(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyQueueData( pxQueue, pvItemToQueue ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + /* In this instance the co-routine could be placed directly + into the ready list as we are within a critical section. + Instead the same pending ready list mechansim is used as if + the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* If the queue is already empty we may have to block. A critical section + is required to prevent an interrupt adding something to the queue + between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueEmpty( pxQueue ) ) + { + /* There are no messages in the queue, do we want to block or just + leave with nothing? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portNOP(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + /* In this instance the co-routine could be placed directly + into the ready list as we are within a critical section. + Instead the same pending ready list mechansim is used as if + the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + + + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) +{ + /* Cannot block within an ISR so if there is no space on the queue then + exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyQueueData( pxQueue, pvItemToQueue ); + + /* We only want to wake one co-routine per ISR, so check that a + co-routine has not already been woken. */ + if( !xCoRoutinePreviouslyWoken ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + } + } + } + + return xCoRoutinePreviouslyWoken; +} +#endif +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) +{ +signed portBASE_TYPE xReturn; + + /* We cannot block from an ISR, so check there is data available. If + not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( !( *pxCoRoutineWoken ) ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + } + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + diff --git a/Source/readme.txt b/Source/readme.txt new file mode 100644 index 000000000..01a878152 --- /dev/null +++ b/Source/readme.txt @@ -0,0 +1,15 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and or compiler. + ++ The FreeRTOS/Source directory contains the three files that are common to +every port. The kernel is contained within these three files. + ++ The FreeRTOS/Source/Portable directory contains the files that are specific to +a particular microcontroller and or compiler. + ++ The FreeRTOS/Source/include directory contains the real time kernel header +files. + +See the readme file in the FreeRTOS/Source/Portable directory for more +information. \ No newline at end of file diff --git a/Source/tasks.c b/Source/tasks.c new file mode 100644 index 000000000..bb21115d6 --- /dev/null +++ b/Source/tasks.c @@ -0,0 +1,1660 @@ +/* + FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to portRESTORE_CONTEXT has been removed. The first context + switch is now performed within sPortStartScheduler(). + +Changes from V1.01: + + + More use of 8bit data types. + + Function name prefixes changed where the data type returned has changed. + + configUSE_TRACE_FACILITY is no longer defined by default. + +Changes from V1.2.0 + + + Introduced ucTopReadyPriority. This tracks the highest priority ready + queue that contains a valid TCB and thus makes the context switch + slightly faster. + + + prvAddTaskToReadyQueue() has been made a macro. + +Changes from V1.2.6 + + + Added conditional compilation directives. + + Extended API. + + Rearranged function order. + + Creating a task now causes a context switch if the task being created + has a higher priority than the calling task - assuming the kernel is + running. + + vTaskDelete() now only causes a context switch if the calling task is + the task being deleted. + +Changes from V2.0.0 + + + Allow the type of the tick count to be 16 or 32 bits. + + Introduce xPendingReadyList feature to allow the time interrupts have to + be disabled to be minimised. + + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() + is now always included as it is used by the scheduler itself. + +Changes from V2.1.0 + + + Bug fix - pxCurrentTCB is now initialised before the call to + prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed + while null. + +Changed from V2.1.1 + + + Change to where lStackSize is declared within sTaskCreate() to prevent + compiler warnings with 8051 port. + +Changes from V2.2.0 + + + Explicit use of 'signed' qualifier on portCHAR types added. + + Changed odd calculation of initial pxTopOfStack value when + portSTACK_GROWTH < 0. + + Removed pcVersionNumber definition. + +Changes from V2.5.3 + + + cTaskResumeAll() modified to ensure it can be called prior to the task + lists being initialised. + +Changes from V2.5.5 + + + Added API function vTaskDelayUntil(). + + Added INCLUDE_vTaskDelay conditional compilation. + +Changes from V2.6.0 + + + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it + can be used on ARM architectures. + + tskMAX_TASK_NAME_LEN definition replaced with the port specific + configMAX_TASK_NAME_LEN definition. + + Removed the call to strcpy when copying across the task name into the + TCB. + + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called + too often in the idle task. + +Changes between V3.0.0 and V2.6.1 + + + When resuming the scheduler a yield is performed if either a tick has + been missed, or a task is moved from the pending ready list into a ready + list. Previously a yield was not performed on this second condition. + + Introduced the type portBASE_TYPE. This necessitates several API + changes. + + Removed the sUsingPreemption variable. The constant defined in + portmacro.h is now used directly. + + The idle task can now include an optional hook function - and no longer + completes its time slice if other tasks with equal priority to it are + ready to run. + + See the FreeRTOS.org documentation for more information on V2.x.x to + V3.x.x modifications. + +Changes from V3.1.1 + + + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to + be called while the scheduler is suspended. + + Corrected the task ordering within event lists. + +Changes from V3.2.0 + + + Added function xTaskGetCurrentTaskHandle(). + +Changes from V3.2.4 + + + Changed the volatile declarations on some variables to reflect the + changes to the list definitions. + + Changed the order of the TCB definition so there is commonality between + the task control block and a co-routine control block. + + Allow the scheduler to be started even if no tasks other than the idle + task has been created. This allows co-routines to run even when no tasks + have been created. + + The need for a context switch is now signalled if a task woken by an + event has a priority greater or equal to the currently running task. + Previously this was only greater than. + +Changes from V4.0.0 + + + Added the xMissedYield handling. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/* + * Macro to define the amount of stack available to the idle task. + */ +#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE + + +/* + * Default a definitions for backwards compatibility with old + * portmacro.h files. + */ +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #undef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 1 +#endif + + +/* + * Task control block. A task control block (TCB) is allocated to each task, + * and stores the context of the task. + */ +typedef struct tskTaskControlBlock +{ + volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ + xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ + xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ + unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ + portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ + unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ + signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ + unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ +} tskTCB; + +/*lint -e956 */ + +tskTCB * volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. --------------------*/ + +static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ +static xList xDelayedTaskList1; /*< Delayed tasks. */ +static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ + static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* File private variables. --------------------------------*/ +static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; +static volatile portTickType xTickCount = ( portTickType ) 0; +static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; +static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; +static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; +static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; +static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; +static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; + +/* Debugging and trace facilities private variables and macros. ------------*/ + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5 ) + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) +#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) +#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) +#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) + +/* + * Macros and private variables used by the trace facility. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) + static volatile signed portCHAR * volatile pcTraceBuffer; + static signed portCHAR *pcTraceBufferStart; + static signed portCHAR *pcTraceBufferEnd; + static signed portBASE_TYPE xTracing = pdFALSE; + +#endif + +/* + * Macro that writes a trace of scheduler activity to a buffer. This trace + * shows which task is running when and is very useful as a debugging tool. + * As this macro is called each context switch it is a good idea to undefine + * it if not using the facility. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + #define vWriteTraceToBuffer() \ + { \ + if( xTracing ) \ + { \ + static unsigned portBASE_TYPE uxPreviousTask = 255; \ + \ + if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ + { \ + if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ + { \ + uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ + *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ + pcTraceBuffer += sizeof( unsigned portLONG ); \ + *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ + pcTraceBuffer += sizeof( unsigned portLONG ); \ + } \ + else \ + { \ + xTracing = pdFALSE; \ + } \ + } \ + } \ + } + +#else + + #define vWriteTraceToBuffer() + +#endif + + +/* + * Place the task represented by pxTCB into the appropriate ready queue for + * the task. It is inserted at the end of the list. One quirk of this is + * that if the task being inserted is at the same priority as the currently + * executing task, then it will only be rescheduled after the currently + * executing task has been rescheduled. + */ +#define prvAddTaskToReadyQueue( pxTCB ) \ +{ \ + if( pxTCB->uxPriority > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = pxTCB->uxPriority; \ + } \ + vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ +} + + +/* + * Macro that looks at the list of tasks that are currently delayed to see if + * any require waking. + * + * Tasks are stored in the queue in the order of their wake time - meaning + * once one tasks has been found whose timer has not expired we need not look + * any further down the list. + */ +#define prvCheckDelayedTasks() \ +{ \ +register tskTCB *pxTCB; \ + \ + while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ + { \ + if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ + { \ + break; \ + } \ + vListRemove( &( pxTCB->xGenericListItem ) ); \ + /* Is the task waiting on an event also? */ \ + if( pxTCB->xEventListItem.pvContainer ) \ + { \ + vListRemove( &( pxTCB->xEventListItem ) ); \ + } \ + prvAddTaskToReadyQueue( pxTCB ); \ + } \ +} + +/* + * Several functions take an xTaskHandle parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) + + +/* File private functions. --------------------------------*/ + +/* + * Utility to ready a TCB for a given task. Mainly just copies the parameters + * into the TCB structure. + */ +static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ); + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) + static void prvDeleteTCB( tskTCB *pxTCB ); +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ); + +/* + * Allocates memory from the heap for a TCB and associated stack. Checks the + * allocation was successful. + */ +static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); + +/* + * Called from vTaskList. vListTasks details all the tasks currently under + * control of the scheduler. The tasks may be in one of a number of lists. + * prvListTaskWithinSingleList accepts a list and details the tasks from + * within just that list. + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); + +#endif + +/*lint +e956 */ + + + + + +/*----------------------------------------------------------- + * TASK CREATION API documented in task.h + *----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) +{ +signed portBASE_TYPE xReturn; +tskTCB * pxNewTCB; +static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ + + /* Allocate the memory required by the TCB and stack for the new task. + checking that the allocation was successful. */ + pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); + + if( pxNewTCB != NULL ) + { + portSTACK_TYPE *pxTopOfStack; + + /* Setup the newly allocated TCB with the initial state of the task. */ + prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); + + /* Calculate the top of stack address. This depends on whether the + stack grows from high memory to low (as per the 80x86) or visa versa. + portSTACK_GROWTH is used to make the result positive or negative as + required by the port. */ + #if portSTACK_GROWTH < 0 + { + pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); + } + #else + { + pxTopOfStack = pxNewTCB->pxStack; + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + but had been interrupted by the scheduler. The return address is set + to the start of the task function. Once the stack has been initialised + the top of stack variable is updated. */ + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); + + /* We are going to manipulate the task queues to add this task to a + ready list, so must make sure no interrupts occur. */ + portENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) + { + /* As this is the first task it must also be the current task. */ + pxCurrentTCB = pxNewTCB; + + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + } + } + + /* Remember the top priority to make context switching faster. Use + the priority in pxNewTCB as this has been capped to a valid value. */ + if( pxNewTCB->uxPriority > uxTopUsedPriority ) + { + uxTopUsedPriority = pxNewTCB->uxPriority; + } + + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + uxTaskNumber++; + + prvAddTaskToReadyQueue( pxNewTCB ); + + xReturn = pdPASS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + if( xReturn == pdPASS ) + { + if( ( void * ) pxCreatedTask != NULL ) + { + /* Pass the TCB out - in an anonymous way. The calling function/ + task can use this as a handle to delete the task later if + required.*/ + *pxCreatedTask = ( xTaskHandle ) pxNewTCB; + } + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < uxPriority ) + { + taskYIELD(); + } + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( xTaskHandle pxTaskToDelete ) + { + tskTCB *pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are deleting ourselves. */ + pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); + + /* Remove task from the ready list and place in the termination list. + This will stop the task from be scheduled. The idle task will check + the termination list and free up any memory allocated by the + scheduler for the TCB and stack. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Is the task waiting on an event also? */ + if( pxTCB->xEventListItem.pvContainer ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + } + + vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + there is a task that has been deleted and that it should therefore + check the xTasksWaitingTermination list. */ + ++uxTasksDeleted; + } + taskEXIT_CRITICAL(); + + /* Force a reschedule if we have just deleted the current task. */ + if( ( void * ) pxTaskToDelete == NULL ) + { + taskYIELD(); + } + } + +#endif + + + + + + +/*----------------------------------------------------------- + * TASK CONTROL API documented in task.h + *----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelayUntil == 1 ) + + void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) + { + portTickType xTimeToWake; + portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; + + vTaskSuspendAll(); + { + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + lasted called. In this case the only time we should ever + actually delay is if the wake time has also overflowed, + and the wake time is greater than the tick time. When this + is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) + { + xShouldDelay = pdTRUE; + } + } + else + { + /* The tick time has not overflowed. In this case we will + delay if either the wake time has overflowed, and/or the + tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) + { + xShouldDelay = pdTRUE; + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay ) + { + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( !xAlreadyYielded ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( portTickType xTicksToDelay ) + { + portTickType xTimeToWake; + signed portBASE_TYPE xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( portTickType ) 0 ) + { + vTaskSuspendAll(); + { + /* A task that is removed from the event list while the + scheduler is suspended will not get placed in the ready + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + xAlreadyYielded = xTaskResumeAll(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( !xAlreadyYielded ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) + { + tskTCB *pxTCB; + unsigned portBASE_TYPE uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are changing the + priority of the calling function. */ + pxTCB = prvGetTCBFromHandle( pxTask ); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) + { + tskTCB *pxTCB; + unsigned portBASE_TYPE uxCurrentPriority; + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= configMAX_PRIORITIES ) + { + uxNewPriority = configMAX_PRIORITIES - 1; + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are changing the + priority of the calling function. */ + pxTCB = prvGetTCBFromHandle( pxTask ); + uxCurrentPriority = pxTCB->uxPriority; + + if( uxCurrentPriority != uxNewPriority ) + { + pxTCB->uxPriority = uxNewPriority; + + /* If the task is in the blocked or suspended list we need do + nothing more than change it's priority variable. However, if + the task is in a ready list it needs to be removed and placed + in the queue appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) + { + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + /* The task is currently in its ready list - remove before adding + it to it's new ready list. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + } + else + { + /* We cannot access the delayed or ready lists, so will hold this + task pending until the scheduler is resumed. */ + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + } + } + taskEXIT_CRITICAL(); + + /* The priority change may have readied a task of higher + priority than the calling task. */ + taskYIELD(); + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( xTaskHandle pxTaskToSuspend ) + { + tskTCB *pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are suspending ourselves. */ + pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); + + /* Remove task from the ready/delayed list and place in the suspended list. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Is the task waiting on an event also? */ + if( pxTCB->xEventListItem.pvContainer ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + } + + vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); + } + taskEXIT_CRITICAL(); + + /* We may have just suspended the current task. */ + if( ( void * ) pxTaskToSuspend == NULL ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( xTaskHandle pxTaskToResume ) + { + tskTCB *pxTCB; + portBASE_TYPE xYieldRequired; + + /* Remove the task from whichever list it is currently in, and place + it in the ready list. */ + pxTCB = ( tskTCB * ) pxTaskToResume; + + /* The parameter cannot be NULL as it is impossible to resume the + currently executing task. */ + if( pxTCB != NULL ) + { + taskENTER_CRITICAL(); + { + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + } + else + { + /* We cannot access the delayed or ready lists, so will hold this + task pending until the scheduler is resumed. */ + xYieldRequired = pdFALSE; + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + taskEXIT_CRITICAL(); + + /* We may have just resumed a higher priority task. */ + if( xYieldRequired ) + { + /* This yield may not cause the task just resumed to run, but + will leave the lists in the correct state for the next yield. */ + taskYIELD(); + } + } + } + +#endif + + + + + +/*----------------------------------------------------------- + * PUBLIC SCHEDULER CONTROL documented in task.h + *----------------------------------------------------------*/ + + +void vTaskStartScheduler( void ) +{ +portBASE_TYPE xReturn; + + /* Add the idle task at the lowest priority. */ + xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + + if( xReturn == pdPASS ) + { + /* Interrupts are turned off here, to ensure a tick does not occur + before or during the call to xPortStartScheduler(). The stacks of + the created tasks contain a status word with interrupts switched on + so interrupts will automatically get re-enabled when the first task + starts to run. + + STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE + DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ + portDISABLE_INTERRUPTS(); + + xSchedulerRunning = pdTRUE; + xTickCount = ( portTickType ) 0; + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() ) + { + /* Should not reach here as if the scheduler is running the + function will not return. */ + } + else + { + /* Should only reach here if a task calls xTaskEndScheduler(). */ + } + } +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + /* Stop the scheduler interrupts and call the portable scheduler end + routine so the original ISRs can be restored if necessary. The port + layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + portENTER_CRITICAL(); + ++uxSchedulerSuspended; + portEXIT_CRITICAL(); +} +/*----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskResumeAll( void ) +{ +register tskTCB *pxTCB; +signed portBASE_TYPE xAlreadyYielded = pdFALSE; + + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + portENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) + { + portBASE_TYPE xYieldRequired = pdFALSE; + + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + + /* If we have moved a task that has a priority higher than + the current task then we should yield. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + } + + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does not + slip, and that any delayed tasks are resumed at the correct time. */ + if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) + { + while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) + { + vTaskIncrementTick(); + --uxMissedTicks; + } + + /* As we have processed some ticks it is appropriate to yield + to ensure the highest priority task that is ready to run is + the task actually running. */ + xYieldRequired = pdTRUE; + } + + if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) + { + xAlreadyYielded = pdTRUE; + xMissedYield = pdFALSE; + taskYIELD(); + } + } + } + } + portEXIT_CRITICAL(); + + return xAlreadyYielded; +} + + + + + + +/*----------------------------------------------------------- + * PUBLIC TASK UTILITIES documented in task.h + *----------------------------------------------------------*/ + + + +portTickType xTaskGetTickCount( void ) +{ +portTickType xTicks; + + /* Critical section required if running on a 16 bit processor. */ + taskENTER_CRITICAL(); + { + xTicks = xTickCount; + } + taskEXIT_CRITICAL(); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) +{ +unsigned portBASE_TYPE uxNumberOfTasks; + + taskENTER_CRITICAL(); + uxNumberOfTasks = uxCurrentNumberOfTasks; + taskEXIT_CRITICAL(); + + return uxNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + void vTaskList( signed portCHAR *pcWriteBuffer ) + { + unsigned portBASE_TYPE uxQueue; + + /* This is a VERY costly function that should be used for debug only. + It leaves interrupts disabled for a LONG time. */ + + taskENTER_CRITICAL(); + { + /* Run through all the lists that could potentially contain a TCB and + report the task name, state and stack high water mark. */ + + pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; + strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); + + uxQueue = uxTopUsedPriority + 1; + + do + { + uxQueue--; + + if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); + } + }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); + + if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); + } + + if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); + } + + if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); + } + + if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); + } + } + taskEXIT_CRITICAL(); + } + +#endif +/*----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) + { + portENTER_CRITICAL(); + { + pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; + pcTraceBufferStart = pcBuffer; + pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); + xTracing = pdTRUE; + } + portEXIT_CRITICAL(); + } + +#endif +/*----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + unsigned portLONG ulTaskEndTrace( void ) + { + unsigned portLONG ulBufferLength; + + portENTER_CRITICAL(); + xTracing = pdFALSE; + portEXIT_CRITICAL(); + + ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); + + return ulBufferLength; + } + +#endif + + + +/*----------------------------------------------------------- + * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES + * documented in task.h + *----------------------------------------------------------*/ + + +inline void vTaskIncrementTick( void ) +{ + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + ++xTickCount; + if( xTickCount == ( portTickType ) 0 ) + { + xList *pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedTaskList here then there is an error! */ + pxTemp = pxDelayedTaskList; + pxDelayedTaskList = pxOverflowDelayedTaskList; + pxOverflowDelayedTaskList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + prvCheckDelayedTasks(); + } + else + { + ++uxMissedTicks; + } + + #if ( configUSE_TICK_HOOK == 1 ) + { + extern void vApplicationTickHook( void ); + + vApplicationTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + void vTaskCleanUpResources( void ) + { + unsigned portSHORT usQueue; + volatile tskTCB *pxTCB; + + usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; + + /* Remove any TCB's from the ready queues. */ + do + { + usQueue--; + + while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); + + /* Remove any TCB's from the delayed queue. */ + while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + + /* Remove any TCB's from the overflow delayed queue. */ + while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + + while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + + while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + } + +#endif +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xMissedYield = pdTRUE; + return; + } + + /* Find the highest priority queue that contains ready tasks. */ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) + { + --uxTopReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the + same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); + vWriteTraceToBuffer(); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) +{ +portTickType xTimeToWake; + + /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE + SCHEDULER SUSPENDED. */ + + /* Place the event list item of the TCB in the appropriate event list. + This is placed in the list in priority order so the highest priority task + is the first to be woken by the event. */ + vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); + + /* Calculate the time at which the task should be woken if the event does + not occur. This may overflow but this doesn't matter. */ + xTimeToWake = xTickCount + xTicksToWait; + + /* We must remove ourselves from the ready list before adding ourselves + to the blocked list as the same list item is used for both lists. We have + exclusive access to the ready lists as the scheduler is locked. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) +{ +tskTCB *pxUnblockedTCB; +portBASE_TYPE xReturn; + + /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE + SCHEDULER SUSPENDED. It can also be called from within an ISR. */ + + /* The event list is sorted in priority order, so we can remove the + first in the list, remove the TCB from the delayed list, and add + it to the ready list. + + If an event is for a queue that is locked then this function will never + get called - the lock count on the queue will get modified instead. This + means we can always expect exclusive access to the event list here. */ + pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + vListRemove( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxUnblockedTCB ); + } + else + { + /* We cannot access the delayed or ready lists, so will hold this + task pending until the scheduler is resumed. */ + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has + a higher priority than the calling task. This allows + the calling task to know if it should force a context + switch now. */ + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + + + + + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* See if any tasks have been deleted. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + see if any other task has become available. If we are using + preemption we don't need to do this as any task becoming available + will automatically get the processor anyway. */ + taskYIELD(); + } + #endif + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + timesliced. If a task that is sharing the idle priority is ready + to run then the idle task should yield before the end of the + timeslice. + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) + { + taskYIELD(); + } + } + #endif + + #if ( configUSE_IDLE_HOOK == 1 ) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + allows the application designer to add background functionality + without the overhead of a separate task. + NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } + #endif + } +} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ + + + + + + + +/*----------------------------------------------------------- + * File private functions documented at the top of the file. + *----------------------------------------------------------*/ + + + +static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) +{ + pxTCB->usStackDepth = usStackDepth; + + /* Store the function name in the TCB. */ + strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); + pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; + + /* This is used as an array index so must ensure it's not too large. */ + if( uxPriority >= configMAX_PRIORITIES ) + { + uxPriority = configMAX_PRIORITIES - 1; + } + + pxTCB->uxPriority = uxPriority; + + vListInitialiseItem( &( pxTCB->xGenericListItem ) ); + vListInitialiseItem( &( pxTCB->xEventListItem ) ); + + /* Set the pxTCB as a link back from the xListItem. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); + listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ +unsigned portBASE_TYPE uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( ( xList * ) &xDelayedTaskList1 ); + vListInitialise( ( xList * ) &xDelayedTaskList2 ); + vListInitialise( ( xList * ) &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( ( xList * ) &xTasksWaitingTermination ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( ( xList * ) &xSuspendedTaskList ); + } + #endif + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + { + portBASE_TYPE xListIsEmpty; + + /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called + too often in the idle task. */ + if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) + { + vTaskSuspendAll(); + xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); + xTaskResumeAll(); + + if( !xListIsEmpty ) + { + tskTCB *pxTCB; + + portENTER_CRITICAL(); + { + pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); + vListRemove( &( pxTCB->xGenericListItem ) ); + --uxCurrentNumberOfTasks; + --uxTasksDeleted; + } + portEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + } + } + #endif +} +/*-----------------------------------------------------------*/ + +static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) +{ +tskTCB *pxNewTCB; + + /* Allocate space for the TCB. Where the memory comes from depends on + the implementation of the port malloc function. */ + pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); + + if( pxNewTCB != NULL ) + { + /* Allocate space for the stack used by the task being created. + The base of the stack memory stored in the TCB so the task can + be deleted later if required. */ + pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + else + { + /* Just to help debugging. */ + memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); + } + } + + return pxNewTCB; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) + { + volatile tskTCB *pxNextTCB, *pxFirstTCB; + static portCHAR pcStatusString[ 50 ]; + unsigned portSHORT usStackRemaining; + + /* Write the details of all the TCB's in pxList into the buffer. */ + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); + usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); + sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); + strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); + + } while( pxNextTCB != pxFirstTCB ); + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) + { + register unsigned portSHORT usCount = 0; + + while( *pucStackByte == tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + usCount++; + } + + usCount /= sizeof( portSTACK_TYPE ); + + return usCount; + } +#endif +/*-----------------------------------------------------------*/ + + + +#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) + + static void prvDeleteTCB( tskTCB *pxTCB ) + { + /* Free up the memory allocated by the scheduler for the task. It is up to + the task to free any memory allocated at the application level. */ + vPortFree( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + +#endif + + +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) + + xTaskHandle xTaskGetCurrentTaskHandle( void ) + { + xTaskHandle xReturn; + + portENTER_CRITICAL(); + { + xReturn = ( xTaskHandle ) pxCurrentTCB; + } + portEXIT_CRITICAL(); + + return xReturn; + } + +#endif + + + + + diff --git a/TraceCon/readme.txt b/TraceCon/readme.txt new file mode 100644 index 000000000..ae78ac933 --- /dev/null +++ b/TraceCon/readme.txt @@ -0,0 +1,6 @@ +Tracecon.exe is a very simplistic utility for converting the trace data captured by the scheduler into a tab delimited text file. The text file can be opened using a spread sheet program as described on www.FreeRTOS.org. + +Tracecon should be executed from a command prompt. It looks for a file called Trace.bin in the current directory and creates a file called trace.txt. + +Use the big endian version for file captured on big endian targets. + diff --git a/TraceCon/tracecon_big_endian_untested.exe b/TraceCon/tracecon_big_endian_untested.exe new file mode 100644 index 000000000..3b5d0b079 Binary files /dev/null and b/TraceCon/tracecon_big_endian_untested.exe differ diff --git a/TraceCon/tracecon_little_endian.exe b/TraceCon/tracecon_little_endian.exe new file mode 100644 index 000000000..171e0d03b Binary files /dev/null and b/TraceCon/tracecon_little_endian.exe differ diff --git a/readme.txt b/readme.txt new file mode 100644 index 000000000..49eecd6cd --- /dev/null +++ b/readme.txt @@ -0,0 +1,19 @@ +The download includes the kernel source code, and a demo application for EVERY +RTOS port. See http://www.freertos.org/a00017.html for full details of the +directory structure and information on locating the files you require. + +The easiest way to use FreeRTOS is start start with one of the demo application +projects. Once this is running the project can be modified to include your own +source files. This way the correct files and compiler options will be +automatically included in your application. + ++ The Source directory contains the real time kernel source files for every +port. The kernel itself is only 3 files. + ++ The Demo directory contains the demo application source files for every +port. + ++ The TraceCon directory contains the trace visualisation exe file. + +See the readme files in the respective directories for further information. +