From: Marek Vasut Date: Sat, 1 Aug 2015 18:04:33 +0000 (+0200) Subject: ddr: altera: sdram: Clean up set_sdr_fifo_cfg() X-Git-Tag: v2015.10-rc2~207 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1009e396ddef43da67924d252e9f0dac746ba738;p=u-boot ddr: altera: sdram: Clean up set_sdr_fifo_cfg() Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. Signed-off-by: Marek Vasut --- diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index d8d04f4ed2..8db8dde5dd 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -405,14 +405,14 @@ static void set_sdr_static_cfg(void) static void set_sdr_fifo_cfg(void) { - debug("Configuring FIFOCFG\n"); - clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK, - CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << - SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB); - - clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK, - CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + const u32 fifo_cfg = + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB); + + debug("Configuring FIFOCFG\n"); + writel(fifo_cfg, &sdr_ctrl->fifo_cfg); } static void set_sdr_mp_weight(void)