From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Date: Tue, 3 Jul 2012 20:02:58 +0000 (+0000)
Subject: EXYNOS5: CLOCK: Add BPLL support
X-Git-Tag: v2012.10-rc1~205
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=10bc1a7f49b2efec3eddca18949d28ad053f40bb;p=u-boot

EXYNOS5: CLOCK: Add BPLL support

This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 366c35ae08..5b7e0ff025 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq, pll_div2_sel,  mpll_fout_sel;
+	unsigned int freq, pll_div2_sel, fout_sel;
 
 	switch (pllreg) {
 	case APLL:
@@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 		r = readl(&clk->vpll_con0);
 		k = readl(&clk->vpll_con1);
 		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
 	default:
 		printf("Unsupported PLL (%d)\n", pllreg);
 		return 0;
@@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	 * MPLL_CON: MIDV [25:16]
 	 * EPLL_CON: MIDV [24:16]
 	 * VPLL_CON: MIDV [24:16]
+	 * BPLL_CON: MIDV [25:16]
 	 */
-	if (pllreg == APLL || pllreg == MPLL)
+	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
 		mask = 0x3ff;
 	else
 		mask = 0x1ff;
@@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 		fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
-	/* According to the user manual, in EVT1 MPLL always gives
+	/* According to the user manual, in EVT1 MPLL and BPLL always gives
 	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
-	if (pllreg == MPLL) {
+	if (pllreg == MPLL || pllreg == BPLL) {
 		pll_div2_sel = readl(&clk->pll_div2_sel);
-		mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
-				& MPLL_FOUT_SEL_MASK;
-		if (mpll_fout_sel == 0)
+
+		switch (pllreg) {
+		case MPLL:
+			fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+					& MPLL_FOUT_SEL_MASK;
+			break;
+		case BPLL:
+			fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
+					& BPLL_FOUT_SEL_MASK;
+			break;
+		}
+
+		if (fout_sel == 0)
 			fout /= 2;
 	}
 
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 72dc655ec1..552902573f 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -27,6 +27,7 @@
 #define EPLL	2
 #define HPLL	3
 #define VPLL	4
+#define BPLL	5
 
 unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index bf41c1959f..fce38efbb2 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -599,4 +599,6 @@ struct exynos5_clock {
 
 #define MPLL_FOUT_SEL_SHIFT	4
 #define MPLL_FOUT_SEL_MASK	0x1
+#define BPLL_FOUT_SEL_SHIFT	0
+#define BPLL_FOUT_SEL_MASK	0x1
 #endif