From: Stefan Roese Date: Fri, 10 Mar 2017 14:40:31 +0000 (+0100) Subject: arm: mvebu: theadorable: Add board-specific PEX detection pulse width X-Git-Tag: v2017.05-rc1~17^2~3 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1304f4bb8ed0971ca28e8b519b831c9f99295286;p=u-boot arm: mvebu: theadorable: Add board-specific PEX detection pulse width Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits). In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected. Signed-off-by: Stefan Roese Cc: Adam Shobash Cc: Nadav Haklai Cc: Konstantin Porotchkin Signed-off-by: Stefan Roese --- diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index d621682d07..d4242170c7 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { }, }; +/* + * Define a board-specific detection pulse-width array for the SerDes PCIe + * interfaces. If not defined in the board code, the default of currently 2 + * is used. Values from 0...3 are possible (2 bits). + */ +u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 }; + MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) { /* Only one mode supported for this board */