From: rtel Date: Tue, 7 Mar 2017 04:06:10 +0000 (+0000) Subject: Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across... X-Git-Tag: V10.0.0~32 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=13421c579a500c8430593a20cef384ba2a092f9d;p=freertos Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2487 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c index 3933d277f..1bacd3fbc 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c @@ -448,7 +448,7 @@ void FreeRTOS_Tick_Handler( void ) { uint32_t ulMaskBits; - __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) ); + __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" ); configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); } #endif /* configASSERT_DEFINED */ @@ -460,7 +460,7 @@ void FreeRTOS_Tick_Handler( void ) updated. */ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb sy \n" - "isb sy \n" ); + "isb sy \n" ::: "memory" ); /* Ok to enable interrupts after the interrupt source has been cleared. */ configCLEAR_TICK_INTERRUPT(); @@ -514,7 +514,7 @@ uint32_t ulReturn; ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb sy \n" - "isb sy \n" ); + "isb sy \n" ::: "memory" ); } portENABLE_INTERRUPTS(); diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h index 5c7af61e9..78aed1e48 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h @@ -129,9 +129,9 @@ extern uint64_t ullPortYieldRequired; \ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) #if defined( GUEST ) - #define portYIELD() __asm volatile ( "SVC 0" ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) #else - #define portYIELD() __asm volatile ( "SMC 0" ) + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) #endif /*----------------------------------------------------------- * Critical section control @@ -144,12 +144,12 @@ extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); extern void vPortInstallFreeRTOSVectorTable( void ); #define portDISABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFSET, #2" ); \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ __asm volatile ( "DSB SY" ); \ __asm volatile ( "ISB SY" ); #define portENABLE_INTERRUPTS() \ - __asm volatile ( "MSR DAIFCLR, #2" ); \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ __asm volatile ( "DSB SY" ); \ __asm volatile ( "ISB SY" ); diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c index 4447dcbac..90e626e79 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c @@ -156,12 +156,12 @@ mode. */ determined priority level. Sometimes it is necessary to turn interrupt off in the CPU itself before modifying certain hardware registers. */ #define portCPU_IRQ_DISABLE() \ - __asm volatile ( "CPSID i" ); \ + __asm volatile ( "CPSID i" ::: "memory" ); \ __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); #define portCPU_IRQ_ENABLE() \ - __asm volatile ( "CPSIE i" ); \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); @@ -209,18 +209,18 @@ static void prvTaskExitError( void ); /* * If the application provides an implementation of vApplicationIRQHandler(), * then it will get called directly without saving the FPU registers on - * interrupt entry, and this weak implementation of + * interrupt entry, and this weak implementation of * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - * it should never actually get called so its implementation contains a * call to configASSERT() that will always fail. * - * If the application provides its own implementation of - * vApplicationFPUSafeIRQHandler() then the implementation of + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of * vApplicationIRQHandler() provided in portASM.S will save the FPU registers * before calling it. * * Therefore, if the application writer wants FPU registers to be saved on - * interrupt entry their IRQ handler must be called + * interrupt entry their IRQ handler must be called * vApplicationFPUSafeIRQHandler(), and if the application writer does not want * FPU registers to be saved on interrupt entry their IRQ handler must be * called vApplicationIRQHandler(). @@ -344,7 +344,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined. } #endif - + return pxTopOfStack; } /*-----------------------------------------------------------*/ @@ -404,7 +404,7 @@ uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a Privileged mode for the scheduler to start. */ - __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -501,7 +501,7 @@ void FreeRTOS_Tick_Handler( void ) portCPU_IRQ_DISABLE(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n" ); + "isb \n" ::: "memory" ); portCPU_IRQ_ENABLE(); /* Increment the RTOS tick. */ @@ -527,7 +527,7 @@ void FreeRTOS_Tick_Handler( void ) ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); } #endif /* configUSE_TASK_FPU_SUPPORT */ @@ -559,7 +559,7 @@ uint32_t ulReturn; ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n" ); + "isb \n" ::: "memory" ); } portCPU_IRQ_ENABLE(); diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h index 11b058d4c..36b6562b7 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h @@ -127,7 +127,7 @@ extern uint32_t ulPortYieldRequired; \ } #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm volatile ( "SWI 0" ); +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); /*----------------------------------------------------------- diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c index b70a49af2..559883f58 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c @@ -79,15 +79,15 @@ #define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) #define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) #define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) -#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portMIN_INTERRUPT_PRIORITY ( 255UL ) -#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) -#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR ( 0x01000000 ) @@ -243,7 +243,7 @@ void vPortYield( void ) /* Barriers are normally not required but do ensure the code is completely within the specified behaviour for the architecture. */ - __asm volatile( "dsb" ); + __asm volatile( "dsb" ::: "memory" ); __asm volatile( "isb" ); } /*-----------------------------------------------------------*/ @@ -252,7 +252,7 @@ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; - __asm volatile( "dsb" ); + __asm volatile( "dsb" ::: "memory" ); __asm volatile( "isb" ); } /*-----------------------------------------------------------*/ @@ -274,6 +274,7 @@ uint32_t ulSetInterruptMaskFromISR( void ) " mrs r0, PRIMASK \n" " cpsid i \n" " bx lr " + ::: "memory" ); /* To avoid compiler warnings. This line will never be reached. */ @@ -286,6 +287,7 @@ void vClearInterruptMaskFromISR( uint32_t ulMask ) __asm volatile( " msr PRIMASK, r0 \n" " bx lr " + ::: "memory" ); /* Just to avoid compiler warning. */ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h index f6eb71f94..81537783c 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h @@ -136,8 +136,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__((naked) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) -#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ) -#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c index f61ce66ea..ba512f0b4 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c @@ -436,7 +436,7 @@ void xPortPendSVHandler( void ) " mov r0, #0 \n" " msr basepri, r0 \n" " ldmia sp!, {r3, r14} \n" - " \n" /* Restore the context, including the critical nesting count. */ + " \n" /* Restore the context, including the critical nesting count. */ " ldr r1, [r3] \n" " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ @@ -501,7 +501,7 @@ void xPortSysTickHandler( void ) /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ - __asm volatile( "cpsid i" ); + __asm volatile( "cpsid i" ::: "memory" ); __asm volatile( "dsb" ); __asm volatile( "isb" ); @@ -522,7 +522,7 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); + __asm volatile( "cpsie i" ::: "memory" ); } else { @@ -545,7 +545,7 @@ void xPortSysTickHandler( void ) configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); if( xModifiableIdleTime > 0 ) { - __asm volatile( "dsb" ); + __asm volatile( "dsb" ::: "memory" ); __asm volatile( "wfi" ); __asm volatile( "isb" ); } @@ -553,10 +553,10 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); - - /* Disable the SysTick clock without reading the - portNVIC_SYSTICK_CTRL_REG register to ensure the + __asm volatile( "cpsie i" ::: "memory" ); + + /* Disable the SysTick clock without reading the + portNVIC_SYSTICK_CTRL_REG register to ensure the portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); @@ -661,7 +661,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h index 34a4cb5d7..7d9cedb02 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h @@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t; \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ - __asm volatile( "dsb" ); \ + __asm volatile( "dsb" ::: "memory" ); \ __asm volatile( "isb" ); \ } @@ -173,7 +173,7 @@ not necessary for to use this port. They are defined so the common demo files { uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); return ucReturn; } @@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); if( ulCurrentInterrupt == 0 ) { @@ -236,11 +236,11 @@ uint32_t ulNewBASEPRI; __asm volatile ( - " mov %0, %1 \n" \ + " mov %0, %1 \n" \ " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } @@ -253,11 +253,11 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile ( " mrs %0, basepri \n" \ - " mov %1, %2 \n" \ + " mov %1, %2 \n" \ " msr basepri, %1 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler @@ -270,7 +270,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h index bf589c0ab..1813e4ee5 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -132,7 +132,7 @@ typedef unsigned long UBaseType_t; #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" ) +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) typedef struct MPU_REGION_REGISTERS { @@ -159,7 +159,7 @@ typedef struct MPU_SETTINGS /* Scheduler utilities. */ -#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) ) +#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" ) #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -167,7 +167,7 @@ typedef struct MPU_SETTINGS \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ - __asm volatile( "dsb" ); \ + __asm volatile( "dsb" ::: "memory" ); \ __asm volatile( "isb" ); \ } @@ -208,7 +208,7 @@ not necessary for to use this port. They are defined so the common demo files { uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); return ucReturn; } @@ -251,7 +251,7 @@ portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged __asm volatile ( " mrs r0, control \n" \ " orr r0, #1 \n" \ " msr control, r0 \n" \ - :::"r0" ); + :::"r0", "memory" ); } } /*-----------------------------------------------------------*/ @@ -262,7 +262,7 @@ uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); if( ulCurrentInterrupt == 0 ) { @@ -288,7 +288,7 @@ uint32_t ulNewBASEPRI; " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } @@ -305,7 +305,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI; " msr basepri, %1 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler @@ -318,7 +318,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c index 75f8f22d3..54cb9a754 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c @@ -563,7 +563,7 @@ void xPortSysTickHandler( void ) /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ - __asm volatile( "cpsid i" ); + __asm volatile( "cpsid i" ::: "memory" ); __asm volatile( "dsb" ); __asm volatile( "isb" ); @@ -584,7 +584,7 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); + __asm volatile( "cpsie i" ::: "memory" ); } else { @@ -607,7 +607,7 @@ void xPortSysTickHandler( void ) configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); if( xModifiableIdleTime > 0 ) { - __asm volatile( "dsb" ); + __asm volatile( "dsb" ::: "memory" ); __asm volatile( "wfi" ); __asm volatile( "isb" ); } @@ -622,7 +622,7 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); + __asm volatile( "cpsie i" ::: "memory" ); if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) { @@ -735,7 +735,7 @@ static void vPortEnableVFP( void ) uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h index 34a4cb5d7..8aca22292 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h @@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t; \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ - __asm volatile( "dsb" ); \ + __asm volatile( "dsb" ::: "memory" ); \ __asm volatile( "isb" ); \ } @@ -173,7 +173,7 @@ not necessary for to use this port. They are defined so the common demo files { uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); return ucReturn; } @@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); if( ulCurrentInterrupt == 0 ) { @@ -240,7 +240,7 @@ uint32_t ulNewBASEPRI; " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } @@ -257,7 +257,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI; " msr basepri, %1 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler @@ -270,7 +270,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h index bf589c0ab..1813e4ee5 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -132,7 +132,7 @@ typedef unsigned long UBaseType_t; #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" ) +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) typedef struct MPU_REGION_REGISTERS { @@ -159,7 +159,7 @@ typedef struct MPU_SETTINGS /* Scheduler utilities. */ -#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) ) +#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" ) #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -167,7 +167,7 @@ typedef struct MPU_SETTINGS \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ - __asm volatile( "dsb" ); \ + __asm volatile( "dsb" ::: "memory" ); \ __asm volatile( "isb" ); \ } @@ -208,7 +208,7 @@ not necessary for to use this port. They are defined so the common demo files { uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); return ucReturn; } @@ -251,7 +251,7 @@ portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged __asm volatile ( " mrs r0, control \n" \ " orr r0, #1 \n" \ " msr control, r0 \n" \ - :::"r0" ); + :::"r0", "memory" ); } } /*-----------------------------------------------------------*/ @@ -262,7 +262,7 @@ uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); if( ulCurrentInterrupt == 0 ) { @@ -288,7 +288,7 @@ uint32_t ulNewBASEPRI; " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } @@ -305,7 +305,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI; " msr basepri, %1 \n" \ " isb \n" \ " dsb \n" \ - :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler @@ -318,7 +318,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c index 0a8f2d24e..132333daa 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c @@ -553,7 +553,7 @@ void xPortSysTickHandler( void ) /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ - __asm volatile( "cpsid i" ); + __asm volatile( "cpsid i" ::: "memory" ); __asm volatile( "dsb" ); __asm volatile( "isb" ); @@ -574,7 +574,7 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); + __asm volatile( "cpsie i" ::: "memory" ); } else { @@ -597,7 +597,7 @@ void xPortSysTickHandler( void ) configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); if( xModifiableIdleTime > 0 ) { - __asm volatile( "dsb" ); + __asm volatile( "dsb" ::: "memory" ); __asm volatile( "wfi" ); __asm volatile( "isb" ); } @@ -612,7 +612,7 @@ void xPortSysTickHandler( void ) /* Re-enable interrupts - see comments above the cpsid instruction() above. */ - __asm volatile( "cpsie i" ); + __asm volatile( "cpsie i" ::: "memory" ); if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) { @@ -725,7 +725,7 @@ static void vPortEnableVFP( void ) uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h index 30b0081fa..3b9a9e4a2 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t; \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ - __asm volatile( "dsb" ); \ + __asm volatile( "dsb" ::: "memory" ); \ __asm volatile( "isb" ); \ } @@ -173,7 +173,7 @@ not necessary for to use this port. They are defined so the common demo files { uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); return ucReturn; } @@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ - __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); if( ulCurrentInterrupt == 0 ) { @@ -242,7 +242,7 @@ uint32_t ulNewBASEPRI; " isb \n" \ " dsb \n" \ " cpsie i \n" \ - :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } @@ -261,7 +261,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI; " isb \n" \ " dsb \n" \ " cpsie i \n" \ - :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler @@ -274,7 +274,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( - " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c index 82c4d2711..351d42203 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c @@ -156,12 +156,12 @@ mode. */ determined priority level. Sometimes it is necessary to turn interrupt off in the CPU itself before modifying certain hardware registers. */ #define portCPU_IRQ_DISABLE() \ - __asm volatile ( "CPSID i" ); \ + __asm volatile ( "CPSID i" ::: "memory" ); \ __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); #define portCPU_IRQ_ENABLE() \ - __asm volatile ( "CPSIE i" ); \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ __asm volatile ( "DSB" ); \ __asm volatile ( "ISB" ); @@ -171,8 +171,8 @@ the CPU itself before modifying certain hardware registers. */ { \ portCPU_IRQ_DISABLE(); \ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm( "DSB \n" \ - "ISB \n" ); \ + __asm volatile ( "DSB \n" \ + "ISB \n" ); \ portCPU_IRQ_ENABLE(); \ } @@ -367,7 +367,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */ /* Only continue if the CPU is not in User mode. The CPU must be in a Privileged mode for the scheduler to start. */ - __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); @@ -464,7 +464,7 @@ void FreeRTOS_Tick_Handler( void ) portCPU_IRQ_DISABLE(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n" ); + "isb \n" ::: "memory" ); portCPU_IRQ_ENABLE(); /* Increment the RTOS tick. */ @@ -488,7 +488,7 @@ uint32_t ulInitialFPSCR = 0; ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); } /*-----------------------------------------------------------*/ @@ -518,7 +518,7 @@ uint32_t ulReturn; ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __asm volatile ( "dsb \n" - "isb \n" ); + "isb \n" ::: "memory" ); } portCPU_IRQ_ENABLE(); diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h index be7455140..08ac40756 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h +++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h @@ -123,7 +123,7 @@ extern uint32_t ulPortYieldRequired; \ } #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -#define portYIELD() __asm volatile ( "SWI 0" ); +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); /*-----------------------------------------------------------