From: Jagan Teki Date: Mon, 20 Nov 2017 18:32:14 +0000 (+0530) Subject: i.MX6UL: icore: Add SPL_OF_CONTROL support X-Git-Tag: v2018.01-rc1~66^2~4 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=152038ea1886782fff6f1c7ca5f3aaa2da9a66fb;p=u-boot i.MX6UL: icore: Add SPL_OF_CONTROL support Add OF_CONTROL support for SPL code. Signed-off-by: Jagan Teki --- diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts index 07c21cb0a2..15e3f94153 100644 --- a/arch/arm/dts/imx6ul-geam-kit.dts +++ b/arch/arm/dts/imx6ul-geam-kit.dts @@ -87,6 +87,7 @@ }; &usdhc1 { + u-boot,dm-spl; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; @@ -134,6 +135,7 @@ }; pinctrl_usdhc1: usdhc1grp { + u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 @@ -145,6 +147,7 @@ }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 @@ -156,6 +159,7 @@ }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 diff --git a/arch/arm/dts/imx6ul-isiot-emmc.dts b/arch/arm/dts/imx6ul-isiot-emmc.dts index 677de96473..a611e3bba5 100644 --- a/arch/arm/dts/imx6ul-isiot-emmc.dts +++ b/arch/arm/dts/imx6ul-isiot-emmc.dts @@ -50,6 +50,7 @@ }; &usdhc2 { + u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; @@ -60,6 +61,7 @@ &iomuxc { pinctrl_usdhc2: usdhc2grp { + u-boot,dm-spl; fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi index 9a3c35c56a..5007a88f45 100644 --- a/arch/arm/dts/imx6ul-isiot.dtsi +++ b/arch/arm/dts/imx6ul-isiot.dtsi @@ -82,6 +82,7 @@ }; &usdhc1 { + u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; @@ -128,6 +129,7 @@ }; pinctrl_usdhc1: usdhc1grp { + u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index def5f8cac9..7affab866f 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -134,6 +134,7 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + u-boot,dm-spl; pmu { compatible = "arm,cortex-a7-pmu"; @@ -185,6 +186,7 @@ #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; + u-boot,dm-spl; spba-bus@02000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -415,6 +417,7 @@ #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, <&iomuxc 16 33 16>; + u-boot,dm-spl; }; gpio2: gpio@020a0000 { @@ -451,6 +454,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; + u-boot,dm-spl; }; gpio5: gpio@020ac000 { @@ -649,6 +653,7 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; + u-boot,dm-spl; }; gpr: iomuxc-gpr@020e4000 { @@ -729,6 +734,7 @@ #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; + u-boot,dm-spl; usbotg1: usb@02184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index b78ebc1e04..412e48e12a 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -316,6 +316,11 @@ config TARGET_MX6UL_GEAM select DM_MMC select DM_THERMAL select SUPPORT_SPL + select SPL_DM if SPL + select SPL_OF_CONTROL if SPL + select SPL_SEPARATE_BSS if SPL + select SPL_PINCTRL if SPL + config TARGET_MX6UL_ISIOT bool "Support Engicam Is.IoT MX6UL" select BOARD_LATE_INIT @@ -328,6 +333,10 @@ config TARGET_MX6UL_ISIOT select DM_MMC select DM_THERMAL select SUPPORT_SPL + select SPL_DM if SPL + select SPL_OF_CONTROL if SPL + select SPL_SEPARATE_BSS if SPL + select SPL_PINCTRL if SPL config TARGET_MX6ULL_14X14_EVK bool "Support mx6ull_14x14_evk" diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c index 15bd8b2c30..23e7e4b0b9 100644 --- a/board/engicam/geam6ul/geam6ul.c +++ b/board/engicam/geam6ul/geam6ul.c @@ -7,7 +7,6 @@ */ #include -#include #include #include @@ -89,83 +88,3 @@ void setup_gpmi_nand(void) setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); } #endif /* CONFIG_NAND_MXS */ - -#ifdef CONFIG_SPL_BUILD -/* MMC board initialization is needed till adding DM support in SPL */ -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) -#include -#include - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - - /* VSELECT */ - IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* CD */ - IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* RST_B */ - IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) - -struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc1_pads); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} -#endif /* CONFIG_FSL_ESDHC */ -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 9afa8e4065..05d23c2df2 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -101,106 +101,6 @@ int board_mmc_get_env_dev(int devno) #ifdef CONFIG_SPL_BUILD #include -/* MMC board initialization is needed till adding DM support in SPL */ -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) -#include -#include - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - - /* VSELECT */ - IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* CD */ - IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* RST_B */ - IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) -#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) - -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 4}, - {USDHC2_BASE_ADDR, 0, 8}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc1_pads); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - SETUP_IOMUX_PADS(usdhc2_pads); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} - #ifdef CONFIG_ENV_IS_IN_MMC void board_boot_order(u32 *spl_boot_list) { @@ -226,5 +126,4 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = boot_dev; } #endif -#endif /* CONFIG_FSL_ESDHC */ #endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index ce7c288803..c147d4a07f 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -40,3 +40,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 94af53e9c7..5f8a574b93 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -38,3 +38,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig index 0a990d7f75..367dfa1809 100644 --- a/configs/imx6ul_isiot_mmc_defconfig +++ b/configs/imx6ul_isiot_mmc_defconfig @@ -40,3 +40,4 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index b88afd7ec6..0c45e066d8 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -215,19 +215,6 @@ # endif # include "imx6_spl.h" -# ifdef CONFIG_SPL_BUILD -# if defined(CONFIG_IMX6UL) -# if defined(CONFIG_TARGET_MX6UL_ISIOT) -# define CONFIG_SYS_FSL_USDHC_NUM 2 -# else -# define CONFIG_SYS_FSL_USDHC_NUM 1 -# endif - -# define CONFIG_SYS_FSL_ESDHC_ADDR 0 -# undef CONFIG_DM_GPIO -# undef CONFIG_DM_MMC -# endif /* CONFIG_IMX6UL */ -# endif /* CONFIG_SPL_BUILD */ #endif #endif /* __IMX6_ENGICAM_CONFIG_H */