From: Ajay Kumar <ajaykumar.rs@samsung.com>
Date: Tue, 8 Jan 2013 20:42:23 +0000 (+0000)
Subject: EXYNOS5: Change parent clock of FIMD to MPLL
X-Git-Tag: v2013.01~6^2~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1673f199d917e0649098e0cb7ef5b375b96bd6cb;p=u-boot

EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe0d9..abc327262a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
 
 	/*