From: Eugeniy Paltsev Date: Wed, 21 Mar 2018 12:58:46 +0000 (+0300) Subject: ARC: Cache: Move I$ entire operation to a separate function X-Git-Tag: v2018.05-rc1~10^2~20 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=16aeee81d9baa403f80cb0ac9bea1141243ab97d;p=u-boot ARC: Cache: Move I$ entire operation to a separate function Move instruction cache entire operation to a separate function because we are planing to use it in other places like sync_icache_dcache_all(). Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 04f1d9d59b..26f0a1ff9b 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -315,20 +315,27 @@ void icache_disable(void) IC_CTRL_CACHE_DISABLE); } -void invalidate_icache_all(void) +/* IC supports only invalidation */ +static inline void __ic_entire_invalidate(void) { + if (!icache_status()) + return; + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ - if (icache_status()) { - write_aux_reg(ARC_AUX_IC_IVIC, 1); - /* - * As per ARC HS databook (see chapter 5.3.3.2) - * it is required to add 3 NOPs after each write to IC_IVIC. - */ - __builtin_arc_nop(); - __builtin_arc_nop(); - __builtin_arc_nop(); - read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ - } + write_aux_reg(ARC_AUX_IC_IVIC, 1); + /* + * As per ARC HS databook (see chapter 5.3.3.2) + * it is required to add 3 NOPs after each write to IC_IVIC. + */ + __builtin_arc_nop(); + __builtin_arc_nop(); + __builtin_arc_nop(); + read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ +} + +void invalidate_icache_all(void) +{ + __ic_entire_invalidate(); #ifdef CONFIG_ISA_ARCV2 if (slc_exists)