From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 7 Oct 2015 14:42:56 +0000 (+0200)
Subject: net: zynq: Add support for different PHY interface types
X-Git-Tag: v2016.01-rc2~243^2~13
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=16ce6de87ecddc73943cd192195bb20148e80622;p=u-boot

net: zynq: Add support for different PHY interface types

MII is setup by default for all cases. The most of boards are using
RGMII but PHY drivers are not doing any specific setting that's why MII
setting was working fine. With TI DP83867 is necessary to setup
paramaters based on interface type.

Use one setting per board for it which is something what will be removed
when driver is moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index e3af8dc930..ac3dd8b70f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -156,6 +156,7 @@ struct zynq_gem_priv {
 	int phyaddr;
 	u32 emio;
 	int init;
+	phy_interface_t interface;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };
@@ -359,7 +360,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 
 	/* interface - look at tsec */
 	phydev = phy_connect(priv->bus, priv->phyaddr, dev,
-			     PHY_INTERFACE_MODE_MII);
+			     priv->interface);
 
 	phydev->supported = supported | ADVERTISED_Pause |
 			    ADVERTISED_Asym_Pause;
@@ -546,6 +547,12 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
 	priv->phyaddr = phy_addr;
 	priv->emio = emio;
 
+#ifndef CONFIG_ZYNQ_GEM_INTERFACE
+	priv->interface = PHY_INTERFACE_MODE_MII;
+#else
+	priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
+#endif
+
 	sprintf(dev->name, "Gem.%lx", base_addr);
 
 	dev->iobase = base_addr;