From: Alex Porosanu Date: Tue, 5 May 2015 13:48:34 +0000 (+0300) Subject: drivers/crypto/fsl: change starting entropy delay value X-Git-Tag: v2015.10-rc2~424^2~12 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=17649e1b94b450f1ab0de7fa14553f390285f291;p=u-boot drivers/crypto/fsl: change starting entropy delay value The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process. This patch changes the starting value of the length of the entropy sample to 3200 system clocks. In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block. Signed-off-by: Alex Porosanu Acked-by: Ruchika Gupta Reviewed-by: York Sun --- diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 14f6633e32..c84b6ad8d8 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -35,7 +35,7 @@ struct rng4tst { u32 rtmctl; /* misc. control register */ u32 rtscmisc; /* statistical check misc. register */ u32 rtpkrrng; /* poker range register */ -#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MIN 3200 #define RTSDCTL_ENT_DLY_MAX 12800 union { u32 rtpkrmax; /* PRGM=1: poker max. limit register */