From: Liu Gang <Gang.Liu@freescale.com>
Date: Fri, 28 Jun 2013 09:58:37 +0000 (+0800)
Subject: powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
X-Git-Tag: v2013.10-rc1~33^2~14
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=17b8614754e9adc531d3f1bc3db66bf680a09447;p=u-boot

powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE

When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

	SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index cfc3a60d2f..ad57a9cfa7 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -33,7 +33,8 @@
 #define MINIMAL_SPL
 #endif
 
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
+	!defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define NOR_BOOT
 #endif