From: Heiko Schocher Date: Wed, 18 Jan 2017 07:05:49 +0000 (+0100) Subject: serial, ns16550: bugfix: ns16550 fifo not enabled X-Git-Tag: v2017.03-rc1~92 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=17fa032671f7981628fe16b30399638842a4b1bb;p=u-boot serial, ns16550: bugfix: ns16550 fifo not enabled commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher Signed-off-by: Ladislav Michl Tested-by: Adam Ford Reviewed-by: Tom Rini --- diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 399b07c542..f744398ca7 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -45,10 +45,14 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata lpc32xx_uart[] = { - { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART3_BASE, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = UART4_BASE, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = UART5_BASE, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = UART6_BASE, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; #if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 73824df18f..190310fd00 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -40,14 +40,20 @@ DECLARE_GLOBAL_DATA_PTR; #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # endif # endif }; diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 3d1d26d13d..b3a041b539 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -219,6 +219,7 @@ static struct ns16550_platdata ns16550_com1_pdata = { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(ns16550_com1) = { diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index ae7959b1eb..5a3498f570 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -32,7 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(igep_uart) = { diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index 0662449c38..b2b8f8861f 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -31,7 +31,8 @@ const omap3_sysinfo sysinfo = { static const struct ns16550_platdata serial_omap_platdata = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(sniper_serial) = { diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 21b3fdcf49..b2fcc28f8b 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; static const struct ns16550_platdata omap3logic_serial = { .base = OMAP34XX_UART1, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(omap3logic_uart) = { diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 2821ee2267..0fad23af62 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -47,7 +47,8 @@ static const u32 gpmc_lab_enet[] = { static const struct ns16550_platdata zoom1_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(zoom1_uart) = { diff --git a/board/overo/overo.c b/board/overo/overo.c index 40f13e5876..5e447262bc 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -70,7 +70,8 @@ static struct { static const struct ns16550_platdata overo_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(overo_uart) = { diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index 77e4482906..793aa90231 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -93,7 +93,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) static const struct ns16550_platdata cairo_serial = { .base = OMAP34XX_UART2, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(cairo_uart) = { diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index cfdab3e342..23c79333a2 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -75,7 +75,8 @@ static struct { static const struct ns16550_platdata beagle_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(beagle_uart) = { diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index f785dbe6d7..b2f060b2dd 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -48,7 +48,8 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { static const struct ns16550_platdata devkit8000_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, - .clock = V_NS16550_CLK + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(devkit8000_uart) = { diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9b423a591d..2df4a1f04f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -20,9 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ -#define UART_FCRVAL (UART_FCR_FIFO_EN | \ - UART_FCR_RXSR | \ - UART_FCR_TXSR) /* Clear & enable FIFOs */ #ifndef CONFIG_DM_SERIAL #ifdef CONFIG_SYS_NS16550_PORT_MAPPED @@ -138,7 +135,7 @@ static u32 ns16550_getfcr(NS16550_t port) #else static u32 ns16550_getfcr(NS16550_t port) { - return UART_FCRVAL; + return UART_FCR_DEFVAL; } #endif @@ -275,7 +272,7 @@ static inline void _debug_uart_init(void) CONFIG_BAUDRATE); serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); serial_dout(&com_port->mcr, UART_MCRVAL); - serial_dout(&com_port->fcr, UART_FCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); serial_dout(&com_port->dll, baud_divisor & 0xff); @@ -440,7 +437,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - plat->fcr = UART_FCRVAL; + plat->fcr = UART_FCR_DEFVAL; if (port_type == PORT_JZ4780) plat->fcr |= UART_FCR_UME; diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 6bac95a414..c06afc58f7 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -27,6 +27,7 @@ static int rockchip_serial_probe(struct udevice *dev) plat->plat.base = plat->dtplat.reg[0]; plat->plat.reg_shift = plat->dtplat.reg_shift; plat->plat.clock = plat->dtplat.clock_frequency; + plat->plat.fcr = UART_FCR_DEFVAL; dev->platdata = &plat->plat; return ns16550_serial_probe(dev); diff --git a/include/ns16550.h b/include/ns16550.h index 7c97036831..5fcbcd2e74 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -121,6 +121,11 @@ typedef struct NS16550 *NS16550_t; /* Ingenic JZ47xx specific UART-enable bit. */ #define UART_FCR_UME 0x10 +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR) + /* * These are the definitions for the Modem Control Register */