From: rtel Date: Wed, 8 Mar 2017 18:38:02 +0000 (+0000) Subject: Add CEC and MEC 17xx demo that is completely statically allocated. NOT FULLY TESTED... X-Git-Tag: V10.0.0~31 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=1800153d4de387fe931406b1cdee66655116c0cf;p=freertos Add CEC and MEC 17xx demo that is completely statically allocated. NOT FULLY TESTED YET. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2488 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_armcc.h new file mode 100644 index 000000000..f2bb66a09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_gcc.h new file mode 100644 index 000000000..a144be795 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/cmsis_gcc.h @@ -0,0 +1,1366 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ + + +#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cm4.h new file mode 100644 index 000000000..01cb73bf3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmFunc.h new file mode 100644 index 000000000..ca319a55c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmInstr.h new file mode 100644 index 000000000..a0a506458 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmSimd.h new file mode 100644 index 000000000..4d76bf901 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/CMSIS/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..b45442bdc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/FreeRTOSConfig.h @@ -0,0 +1,210 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The demo configures the kernel to be as simple as possible; FreeRTOSConfig.h + * excludes most features, including dynamic memory allocation. + */ + + +#define configUSE_PREEMPTION 1 +#define configTICK_RATE_HZ ( 1000 ) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_QUEUE_SETS 0 +#define configCPU_CLOCK_HZ 48000000 +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 0 +#define configQUEUE_REGISTRY_SIZE 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 0 +#define configUSE_TICKLESS_IDLE 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* The simple demo does not use any hook functions. See +http://www.FreeRTOS.org/a00016.html */ +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 + +/* This demo is configured to use static allocation only. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +#define xPortSysTickHandler SysTick_Handler + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +#ifdef __cplusplus +} +#endif + + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/JLinkSettings.ini new file mode 100644 index 000000000..706cf39a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Unspecified" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx new file mode 100644 index 000000000..b6ecb5171 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx @@ -0,0 +1,562 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c;*.S + + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RTOSDemo_GCC + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + + + + + + + + + + init_app.ini + BIN\UL2CM3.DLL + + + + 0 + JL2CM3 + -U59101789 -O3047 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8006 -TDT0 -TDC1F -TIE1 -TIP8 -TB1 -TFE0 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=1377,131,1842,431,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + -UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) + + + + + 0 + 0 + 2428 + 1 +
926184
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Source\tasks.c + + \\RTOSDemo\../../../Source/tasks.c\2428 + + + 1 + 0 + 851 + 1 +
953140
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Demo\CORTEX_MPU_MEC1701_Keil_GCC\main.c + + \\RTOSDemo\../main.c\851 + + + 2 + 0 + 307 + 1 +
939148
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Source\portable\GCC\ARM_CM4_MPU\port.c + + \\RTOSDemo\../../../Source/portable/GCC/ARM_CM4_MPU/port.c\307 + + + 3 + 0 + 916 + 1 +
953232
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Demo\CORTEX_MPU_MEC1701_Keil_GCC\main.c + + \\RTOSDemo\../main.c\916 + + + + + 0 + 1 + xTickCount + + + 1 + 1 + pxCurrentTCB + + + 2 + 1 + *pcString + + + 3 + 1 + &xSchedulerRunning + + + 4 + 1 + xSchedulerRunning + + + + + 1 + 2 + 0x100000 + 4 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + 1 + 0 + 2 + 10000000 + + + + + + System + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\system.c + system.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\startup_ARMCM4.S + startup_ARMCM4.S + 0 + 0 + + + + + main_and_config + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 2 + 4 + 5 + 0 + 0 + 0 + ..\FreeRTOSConfig.h + FreeRTOSConfig.h + 0 + 0 + + + + + FreeRTOS_Source + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\Source\event_groups.c + event_groups.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Source\list.c + list.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Source\queue.c + queue.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Source\tasks.c + tasks.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Source\timers.c + timers.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\Common\mpu_wrappers.c + mpu_wrappers.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\GCC\ARM_CM4_MPU\port.c + port.c + 0 + 0 + + + + + peripheral_library + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_api.c + btimer_api.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_perphl.c + btimer_perphl.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_api.c + interrupt_api.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_ecia_perphl.c + interrupt_ecia_perphl.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_nvic_perphl.c + interrupt_nvic_perphl.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_api.c + pcr_api.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_perphl.c + pcr_perphl.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\peripheral_library\system_internal.c + system_internal.c + 0 + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx new file mode 100644 index 000000000..34fad3804 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx @@ -0,0 +1,398 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo_GCC + 0x3 + ARM-GNU + + + ARMCM4_FP + ARM + ARM.CMSIS.5.0.1 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + RTOSDemo + 1 + 0 + 0 + 1 + 0 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x200000 + 0x4000 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 3 + 1 + + -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections -O0 -g + + + ..;..\..\..\Source\include;..\..\..\Source\portable\GCC\ARM_CM4_MPU;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full;..\peripheral_library\interrupt + + + + 0 + 1 + + + + + + + + + 1 + 0 + 1 + 0 + 0 + + + + + + -Xlinker --gc-sections + .\sections.ld + + + + + + System + + + system.c + 1 + .\system.c + + + startup_ARMCM4.S + 2 + .\startup_ARMCM4.S + + + + + main_and_config + + + main.c + 1 + ..\main.c + + + FreeRTOSConfig.h + 5 + ..\FreeRTOSConfig.h + + + + + FreeRTOS_Source + + + event_groups.c + 1 + ..\..\..\Source\event_groups.c + + + list.c + 1 + ..\..\..\Source\list.c + + + queue.c + 1 + ..\..\..\Source\queue.c + + + tasks.c + 1 + ..\..\..\Source\tasks.c + + + timers.c + 1 + ..\..\..\Source\timers.c + + + mpu_wrappers.c + 1 + ..\..\..\Source\portable\Common\mpu_wrappers.c + + + port.c + 1 + ..\..\..\Source\portable\GCC\ARM_CM4_MPU\port.c + + + + + peripheral_library + + + btimer_api.c + 1 + ..\peripheral_library\basic_timer\btimer_api.c + + + btimer_perphl.c + 1 + ..\peripheral_library\basic_timer\btimer_perphl.c + + + interrupt_api.c + 1 + ..\peripheral_library\interrupt\interrupt_api.c + + + interrupt_ecia_perphl.c + 1 + ..\peripheral_library\interrupt\interrupt_ecia_perphl.c + + + interrupt_nvic_perphl.c + 1 + ..\peripheral_library\interrupt\interrupt_nvic_perphl.c + + + pcr_api.c + 1 + ..\peripheral_library\pcr\pcr_api.c + + + pcr_perphl.c + 1 + ..\peripheral_library\pcr\pcr_perphl.c + + + system_internal.c + 1 + ..\peripheral_library\system_internal.c + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app.ini new file mode 100644 index 000000000..a98d32f13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app.ini @@ -0,0 +1,8 @@ +//Initialization file for the application code +RESET +T +T +T +//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine +eval PC = Reset_Handler; +T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app_simulator.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app_simulator.ini new file mode 100644 index 000000000..34ec3f83d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/init_app_simulator.ini @@ -0,0 +1,10 @@ +//Initialization file for the application code +//RESET +//T +//T +//T +//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine +MAP 0xE0000, 0x118000 Read // map ROM +MAP 0x118000, 0x120000 Read WRITE // map RAM +eval PC = Reset_Handler; +//T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/sections.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/sections.ld new file mode 100644 index 000000000..644cd6230 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/sections.ld @@ -0,0 +1,373 @@ +/* + * Memory Spaces Definitions. + * + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + * + * The values below can be addressed in further linker scripts + * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'. + */ + +MEMORY +{ + /* Due to restrictions in the MPU, the size of memory regions must be a power + of two, and start on a boundary equal to their size. */ + ROM (rx) : ORIGIN = 0xE0000, LENGTH = 0x20000 + RAM (rw) : ORIGIN = 0x100000, LENGTH = 0x20000 +} + +/* Variables used by FreeRTOS-MPU. */ +_Privileged_Functions_Region_Size = 32K; +_Privileged_Data_Region_Size = 512; + +__FLASH_segment_start__ = ORIGIN( ROM ); +__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( ROM ); + +__privileged_functions_start__ = ORIGIN( ROM ); +__privileged_functions_end__ = __privileged_functions_start__ + _Privileged_Functions_Region_Size; + +__SRAM_segment_start__ = ORIGIN( RAM ); +__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM ); + +__privileged_data_start__ = ORIGIN( RAM ); +__privileged_data_end__ = ORIGIN( RAM ) + _Privileged_Data_Region_Size; + + +/* + * The '__stack' definition is required by crt0, do not remove it. + */ +__stack = ORIGIN(RAM) + LENGTH(RAM); +_estack = __stack; + +/* + * Default stack sizes. + * These are used by the startup in order to allocate stacks + * for the different modes. + */ + +__Main_Stack_Size = 2048 ; + +PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ; + +__Main_Stack_Limit = __stack - __Main_Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the command line. */ +PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ; + +/* + * There will be a link error if there is not this amount of + * RAM free at the end. + */ +_Minimum_Stack_Size = 1024 ; + +/* + * Default heap definitions. + * The heap start immediately after the last statically allocated + * .sbss/.noinit section, and extends up to the main stack limit. + */ +PROVIDE ( _Heap_Begin = _end_noinit ) ; +PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ; + +/* + * The entry point is informative, for debuggers and simulators, + * since the Cortex-M vector points to it anyway. + */ +ENTRY(_start) + +/* Sections Definitions */ + +SECTIONS +{ + /* + * For Cortex-M devices, the beginning of the startup code is stored in + * the .isr_vector section, which goes to ROM + */ + .isr_vector : + { + . = ALIGN(4); + _isr_vector = .; + KEEP(*(.isr_vector)) + } >ROM + + privileged_functions : + { + . = ALIGN(4); + *(privileged_functions) + + /* Non privileged code is after _Privileged_Functions_Region_Size. */ + __privileged_functions_actual_end__ = .; + . = _Privileged_Functions_Region_Size; + } > ROM + + + .text : + { + . = ALIGN(4); + + + /* + * This section is here for convenience, to store the + * startup code at the beginning of the flash area, hoping that + * this will increase the readability of the listing. + */ + KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */ + + . = ALIGN(4); + + /* + * These are the old initialisation sections, intended to contain + * naked code, with the prologue/epilogue added by crti.o/crtn.o + * when linking with startup files. The standalone startup code + * currently does not run these, better use the init arrays below. + */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + + /* + * The preinit code, i.e. an array of pointers to initialisation + * functions to be performed before constructors. + */ + PROVIDE_HIDDEN (__preinit_array_start = .); + + /* + * Used to run the SystemInit() before anything else. + */ + KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*)) + + /* + * Used for other platform inits. + */ + KEEP(*(.preinit_array_platform .preinit_array_platform.*)) + + /* + * The application inits. If you need to enforce some order in + * execution, create new sections, as before. + */ + KEEP(*(.preinit_array .preinit_array.*)) + + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + + /* + * The init code, i.e. an array of pointers to static constructors. + */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + + /* + * The fini code, i.e. an array of pointers to static destructors. + */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + + . = ALIGN(4); + + *(.text*) /* all remaining code */ + + *(vtable) /* C++ virtual tables */ + + } >ROM + + .rodata : + { + *(.rodata*) /* read-only data (constants) */ + } >ROM + + .glue : + { + KEEP(*(.eh_frame*)) + + /* + * Stub sections generated by the linker, to glue together + * ARM and Thumb code. .glue_7 is used for ARM code calling + * Thumb code, and .glue_7t is used for Thumb code calling + * ARM code. Apparently always generated by the linker, for some + * architectures, so better leave them here. + */ + *(.glue_7) + *(.glue_7t) + } >ROM + + /* ARM magic sections */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + . = ALIGN(4); + _etext = .; + __etext = .; + + /* + * This address is used by the startup code to + * initialise the .data section. + */ + _sidata = _etext; + + /* MEMORY_ARRAY */ + /* + .ROarraySection : + { + *(.ROarraySection .ROarraySection.*) + } >MEMORY_ARRAY + */ + + + privileged_data : + { + *(privileged_data) + /* Non kernel data is kept out of the first _Privileged_Data_Region_Size + bytes of SRAM. */ + __privileged_data_actual_end__ = .; + . = _Privileged_Data_Region_Size; + } > RAM + + /* + * The initialised data section. + * The program executes knowing that the data is in the RAM + * but the loader puts the initial values in the ROM (inidata). + * It is one task of the startup to copy the initial values from + * ROM to RAM. + */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + + /* This is used by the startup code to initialise the .data section */ + _sdata = . ; /* STM specific definition */ + __data_start__ = . ; + *(.data_begin .data_begin.*) + + *(.data .data.*) + + *(.data_end .data_end.*) + . = ALIGN(4); + + /* This is used by the startup code to initialise the .data section */ + _edata = . ; /* STM specific definition */ + __data_end__ = . ; + + } >RAM + + + /* + * The uninitialised data section. NOLOAD is used to avoid + * the "section `.bss' type changed to PROGBITS" warning + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; /* standard newlib definition */ + _sbss = .; /* STM specific definition */ + *(.bss_begin .bss_begin.*) + + *(.bss .bss.*) + *(COMMON) + + *(.bss_end .bss_end.*) + . = ALIGN(4); + __bss_end__ = .; /* standard newlib definition */ + _ebss = . ; /* STM specific definition */ + } >RAM + + .noinit (NOLOAD) : + { + . = ALIGN(4); + _noinit = .; + + *(.noinit .noinit.*) + + . = ALIGN(4) ; + _end_noinit = .; + } > RAM + + /* Mandatory to be word aligned, _sbrk assumes this */ + PROVIDE ( end = _end_noinit ); /* was _ebss */ + PROVIDE ( _end = _end_noinit ); + PROVIDE ( __end = _end_noinit ); + PROVIDE ( __end__ = _end_noinit ); + PROVIDE ( ROM_DATA_START = __data_start__ ); + + /* + * Used for validation only, do not allocate anything here! + * + * This is just to check that there is enough RAM left for the Main + * stack. It should generate an error if it's full. + */ + ._check_stack : + { + . = ALIGN(4); + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + } >RAM + + /* After that there are only debugging sections. */ + + /* This can remove the debugging information from the standard libraries */ + /* + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S new file mode 100644 index 000000000..77f656b20 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S @@ -0,0 +1,475 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 16 August 2013 + * +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv7e-m + + .extern __SRAM_segment_end__ + + .section .isr_vector,"a",%progbits + .align 4 + .globl __isr_vector + .global __Vectors + +__Vectors: +__isr_vector: + .long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08 + .long NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09 + .long NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10 + .long NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11 + .long NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12 + .long NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13 + .long NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14 + .long NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15 + .long NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16 + .long NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17 + .long NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18 + .long NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19 + .long NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20 + .long NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21 + .long NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23 + .long NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24 + .long NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25 + .long NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26 + .long 0 // 88h: 18, RSVD + .long 0 // 8Ch: 19, RSVD + .long NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0 + .long NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1 + .long NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2 + .long NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3 + .long NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0 + .long NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1 + .long NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2 + .long NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3 + .long NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4 + .long NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5 + .long NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6 + .long NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7 + .long NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8 + .long NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9 + .long NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10 + .long NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11 + .long NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12 + .long NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13 + .long 0 // D8h: 38, Unused + .long 0 // DCh: 39, Unused + .long NVIC_Handler_UART0 // E0h: 40, UART0 + .long NVIC_Handler_UART1 // E4h: 41, UART1 + .long NVIC_Handler_EMI0 // E8h: 42, EMI0 + .long NVIC_Handler_EMI1 // ECh: 43, EMI0 + .long NVIC_Handler_EMI2 // F0h: 44, EMI0 + .long NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF + .long NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF + .long NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF + .long NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF + .long NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF + .long NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF + .long NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF + .long NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF + .long NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF + .long NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF + .long NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL + .long NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN + .long NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS + .long NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF + .long NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF + .long NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC + .long NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data + .long NVIC_Handler_P80A // 138h: 62, Port 80h A + .long NVIC_Handler_P80B // 13Ch: 63, Port 80h B + .long 0 // 140h: 64, Reserved + .long NVIC_Handler_PKE_ERR // 144h: 65, PKE Error + .long NVIC_Handler_PKE_END // 148h: 66, PKE End + .long NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen + .long NVIC_Handler_AES // 150h: 68, AES + .long NVIC_Handler_HASH // 154h: 69, HASH + .long NVIC_Handler_PECI // 158h: 70, PECI + .long NVIC_Handler_TACH0 // 15Ch: 71, TACH0 + .long NVIC_Handler_TACH1 // 160h: 72, TACH1 + .long NVIC_Handler_TACH2 // 164h: 73, TACH2 + .long NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail + .long NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall + .long NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail + .long NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall + .long NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL + .long NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT + .long NVIC_Handler_RCID0 // 180h: 80, RCID 0 + .long NVIC_Handler_RCID1 // 184h: 81, RCID 1 + .long NVIC_Handler_RCID2 // 188h: 82, RCID 2 + .long NVIC_Handler_LED0 // 18Ch: 83, LED0 + .long NVIC_Handler_LED1 // 190h: 84, LED1 + .long NVIC_Handler_LED2 // 194h: 85, LED2 + .long NVIC_Handler_LED3 // 198h: 86, LED2 + .long NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor + .long NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status + .long NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status + .long NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error + .long NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0 + .long NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX + .long NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX + .long NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX + .long NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX + .long NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear + .long NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error + .long NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear + .long NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error + .long NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0 + .long NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1 + .long NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2 + .long NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan + .long NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1 + .long NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2 + .long NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR + .long NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1 + .long NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2 + .long NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan + .long NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset + .long NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer + .long NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0 + .long NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1 + .long NVIC_Handler_WK // 208h: 114, Week Alarm + .long NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week + .long NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec + .long NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec + .long NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin + .long NVIC_Handler_RTC // 21Ch: 119, RTC + .long NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM + .long NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input + .long NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0 + .long NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1 + .long NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2 + .long NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3 + .long NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4 + .long NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5 + .long NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6 + .long NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake + .long NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake + .long NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake + .long NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake + .long NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake + .long NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor + .long NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan + .long NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0 + .long NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1 + .long NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2 + .long NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3 + .long NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0 + .long NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1 + .long NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0 + .long NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1 + .long NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2 + .long NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3 + .long NVIC_Handler_CAPTMR // 288h: 146, Capture Timer + .long NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event + .long NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event + .long NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event + .long NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event + .long NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event + .long NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event + .long NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event + .long NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event + + + .text + .thumb + .thumb_func + .align 2 + .globl _start + .extern main + .globl Reset_Handler + .type Reset_Handler, %function +_start: +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr sp, =__SRAM_segment_end__ + sub sp, sp, #4 + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ + + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 + +#ifndef __NO_SYSTEM_INIT +/* bl SystemInit */ +#endif + + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler +/* def_irq_handler SVC_Handler */ + def_irq_handler DebugMon_Handler +/* def_irq_handler PendSV_Handler */ +/* def_irq_handler SysTick_Handler */ + def_irq_handler DEF_IRQHandler + + def_irq_handler NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08 + def_irq_handler NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09 + def_irq_handler NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10 + def_irq_handler NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11 + def_irq_handler NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12 + def_irq_handler NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13 + def_irq_handler NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14 + def_irq_handler NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15 + def_irq_handler NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16 + def_irq_handler NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17 + def_irq_handler NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18 + def_irq_handler NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19 + def_irq_handler NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20 + def_irq_handler NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21 + def_irq_handler NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23 + def_irq_handler NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24 + def_irq_handler NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25 + def_irq_handler NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26 + def_irq_handler NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0 + def_irq_handler NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1 + def_irq_handler NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2 + def_irq_handler NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3 + def_irq_handler NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0 + def_irq_handler NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1 + def_irq_handler NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2 + def_irq_handler NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3 + def_irq_handler NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4 + def_irq_handler NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5 + def_irq_handler NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6 + def_irq_handler NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7 + def_irq_handler NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8 + def_irq_handler NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9 + def_irq_handler NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10 + def_irq_handler NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11 + def_irq_handler NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12 + def_irq_handler NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13 + def_irq_handler NVIC_Handler_UART0 // E0h: 40, UART0 + def_irq_handler NVIC_Handler_UART1 // E4h: 41, UART1 + def_irq_handler NVIC_Handler_EMI0 // E8h: 42, EMI0 + def_irq_handler NVIC_Handler_EMI1 // ECh: 43, EMI0 + def_irq_handler NVIC_Handler_EMI2 // F0h: 44, EMI0 + def_irq_handler NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF + def_irq_handler NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF + def_irq_handler NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF + def_irq_handler NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF + def_irq_handler NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF + def_irq_handler NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF + def_irq_handler NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF + def_irq_handler NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF + def_irq_handler NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF + def_irq_handler NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF + def_irq_handler NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL + def_irq_handler NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN + def_irq_handler NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS + def_irq_handler NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF + def_irq_handler NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF + def_irq_handler NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC + def_irq_handler NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data + def_irq_handler NVIC_Handler_P80A // 138h: 62, Port 80h A + def_irq_handler NVIC_Handler_P80B // 13Ch: 63, Port 80h B + def_irq_handler NVIC_Handler_PKE_ERR // 144h: 65, PKE Error + def_irq_handler NVIC_Handler_PKE_END // 148h: 66, PKE End + def_irq_handler NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen + def_irq_handler NVIC_Handler_AES // 150h: 68, AES + def_irq_handler NVIC_Handler_HASH // 154h: 69, HASH + def_irq_handler NVIC_Handler_PECI // 158h: 70, PECI + def_irq_handler NVIC_Handler_TACH0 // 15Ch: 71, TACH0 + def_irq_handler NVIC_Handler_TACH1 // 160h: 72, TACH1 + def_irq_handler NVIC_Handler_TACH2 // 164h: 73, TACH2 + def_irq_handler NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail + def_irq_handler NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall + def_irq_handler NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail + def_irq_handler NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall + def_irq_handler NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL + def_irq_handler NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT + def_irq_handler NVIC_Handler_RCID0 // 180h: 80, RCID 0 + def_irq_handler NVIC_Handler_RCID1 // 184h: 81, RCID 1 + def_irq_handler NVIC_Handler_RCID2 // 188h: 82, RCID 2 + def_irq_handler NVIC_Handler_LED0 // 18Ch: 83, LED0 + def_irq_handler NVIC_Handler_LED1 // 190h: 84, LED1 + def_irq_handler NVIC_Handler_LED2 // 194h: 85, LED2 + def_irq_handler NVIC_Handler_LED3 // 198h: 86, LED2 + def_irq_handler NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor + def_irq_handler NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status + def_irq_handler NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status + def_irq_handler NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error + def_irq_handler NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0 + def_irq_handler NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX + def_irq_handler NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX + def_irq_handler NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX + def_irq_handler NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX + def_irq_handler NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear + def_irq_handler NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error + def_irq_handler NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear + def_irq_handler NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error + def_irq_handler NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0 + def_irq_handler NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1 + def_irq_handler NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2 + def_irq_handler NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan + def_irq_handler NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1 + def_irq_handler NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2 + def_irq_handler NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR + def_irq_handler NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1 + def_irq_handler NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2 + def_irq_handler NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan + def_irq_handler NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset + def_irq_handler NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer + def_irq_handler NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0 + def_irq_handler NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1 + def_irq_handler NVIC_Handler_WK // 208h: 114, Week Alarm + def_irq_handler NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week + def_irq_handler NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec + def_irq_handler NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec + def_irq_handler NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin + def_irq_handler NVIC_Handler_RTC // 21Ch: 119, RTC + def_irq_handler NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM + def_irq_handler NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input + def_irq_handler NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0 + def_irq_handler NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1 + def_irq_handler NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2 + def_irq_handler NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3 + def_irq_handler NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4 + def_irq_handler NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5 + def_irq_handler NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6 + def_irq_handler NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake + def_irq_handler NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake + def_irq_handler NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake + def_irq_handler NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake + def_irq_handler NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake + def_irq_handler NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor + def_irq_handler NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan + def_irq_handler NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0 + def_irq_handler NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1 + def_irq_handler NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2 + def_irq_handler NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3 + def_irq_handler NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0 + def_irq_handler NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1 + def_irq_handler NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0 + def_irq_handler NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1 + def_irq_handler NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2 + def_irq_handler NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3 + def_irq_handler NVIC_Handler_CAPTMR // 288h: 146, Capture Timer + def_irq_handler NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event + def_irq_handler NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event + def_irq_handler NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event + def_irq_handler NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event + def_irq_handler NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event + def_irq_handler NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event + def_irq_handler NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event + def_irq_handler NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event + + .end diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/system.c new file mode 100644 index 000000000..68af5a0c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/GCC_Specific/system.c @@ -0,0 +1,73 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup pwm pwm_c_wrapper + * @{ + */ +/** @file pwm_c_wrapper.cpp + \brief the pwm component C wrapper + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/GCC_Specific/system.c $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2016/09/22 08:03:49 $ + * AUTHOR: $Author: pramans $ + * + * Revision history (latest first): + * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) + * #2 2011/03/25 martin_y support FPGA build 058 apps + * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200 + *********************************************************************************** + */ +/* Imported Header File */ +//#include "common.h" +//#include "build.h" +#include + +#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 +#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) +#define CPU_CLOCK_DIVIDER 1 + +/******************************************************************************/ +/** system_set_ec_clock +* Set CPU speed +* @param void +* @return void +*******************************************************************************/ + +void system_set_ec_clock(void) +{ + + /* Set ARC CPU Clock Divider to determine the CPU speed */ + /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */ + MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER; + +} /* End system_set_ec_clock() */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/JLinkSettings.ini new file mode 100644 index 000000000..706cf39a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Unspecified" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx new file mode 100644 index 000000000..2da56d6c6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx @@ -0,0 +1,442 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RTOSDemo + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + + + + + + + + + + init_app.ini + BIN\UL2CM3.DLL + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=1199,245,1664,545,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + -UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) + + + + + + 0 + 1 + pxCurrentTCB + + + + + 1 + 2 + 0xe000e284 + 4 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + System + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\startup_MPS_CM4.S + startup_MPS_CM4.S + 0 + 0 + + + + + main_and_config + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + ..\FreeRTOSConfig.h + FreeRTOSConfig.h + 0 + 0 + + + + + FreeRTOS_Source + 1 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\Source\event_groups.c + event_groups.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\Source\list.c + list.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Source\queue.c + queue.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Source\tasks.c + tasks.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Source\timers.c + timers.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c + port.c + 0 + 0 + + + + + peripheral_library + 0 + 0 + 0 + 0 + + 4 + 10 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_api.c + interrupt_api.c + 0 + 0 + + + 4 + 11 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_ecia_perphl.c + interrupt_ecia_perphl.c + 0 + 0 + + + 4 + 12 + 1 + 0 + 0 + 0 + ..\peripheral_library\interrupt\interrupt_nvic_perphl.c + interrupt_nvic_perphl.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_api.c + btimer_api.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_perphl.c + btimer_perphl.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_api.c + pcr_api.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_perphl.c + pcr_perphl.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\peripheral_library\system_internal.c + system_internal.c + 0 + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx new file mode 100644 index 000000000..7980ed890 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx @@ -0,0 +1,494 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + ARMCM4_FP + ARM + ARM.CMSIS.5.0.1 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + RTOSDemo + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xe0000 + 0x38000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x118000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + ..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full;..\peripheral_library\interrupt + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + RTOSDemo.sct + + + + + + + + + + + System + + + startup_MPS_CM4.S + 2 + .\startup_MPS_CM4.S + + + + + main_and_config + + + main.c + 1 + ..\main.c + + + FreeRTOSConfig.h + 5 + ..\FreeRTOSConfig.h + + + + + FreeRTOS_Source + + + event_groups.c + 1 + ..\..\..\Source\event_groups.c + + + list.c + 1 + ..\..\..\Source\list.c + + + queue.c + 1 + ..\..\..\Source\queue.c + + + tasks.c + 1 + ..\..\..\Source\tasks.c + + + timers.c + 1 + ..\..\..\Source\timers.c + + + port.c + 1 + ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + + + peripheral_library + + + interrupt_api.c + 1 + ..\peripheral_library\interrupt\interrupt_api.c + + + interrupt_ecia_perphl.c + 1 + ..\peripheral_library\interrupt\interrupt_ecia_perphl.c + + + interrupt_nvic_perphl.c + 1 + ..\peripheral_library\interrupt\interrupt_nvic_perphl.c + + + btimer_api.c + 1 + ..\peripheral_library\basic_timer\btimer_api.c + + + btimer_perphl.c + 1 + ..\peripheral_library\basic_timer\btimer_perphl.c + + + pcr_api.c + 1 + ..\peripheral_library\pcr\pcr_api.c + + + pcr_perphl.c + 1 + ..\peripheral_library\pcr\pcr_perphl.c + + + system_internal.c + 1 + ..\peripheral_library\system_internal.c + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/init_app.ini new file mode 100644 index 000000000..6a0e39168 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/init_app.ini @@ -0,0 +1,7 @@ +//Initialization file for the application code +RESET +T +T +T +eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine +T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/startup_MPS_CM4.S b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/startup_MPS_CM4.S new file mode 100644 index 000000000..85c6d6385 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/Keil_Specific/startup_MPS_CM4.S @@ -0,0 +1,643 @@ +;/***************************************************************************** +; * @file: startup_MPS_CM4.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * for the ARM 'Microcontroller Prototyping System' +; * @version: V1.00 +; * @date: 1. Jun. 2010 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008-2010 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD NVIC_Handler_GIRQ08 ; 40h: 0, GIRQ08 + DCD NVIC_Handler_GIRQ09 ; 44h: 1, GIRQ09 + DCD NVIC_Handler_GIRQ10 ; 48h: 2, GIRQ10 + DCD NVIC_Handler_GIRQ11 ; 4Ch: 3, GIRQ11 + DCD NVIC_Handler_GIRQ12 ; 50h: 4, GIRQ12 + DCD NVIC_Handler_GIRQ13 ; 54h: 5, GIRQ13 + DCD NVIC_Handler_GIRQ14 ; 58h: 6, GIRQ14 + DCD NVIC_Handler_GIRQ15 ; 5Ch: 7, GIRQ15 + DCD NVIC_Handler_GIRQ16 ; 60h: 8, GIRQ16 + DCD NVIC_Handler_GIRQ17 ; 64h: 9, GIRQ17 + DCD NVIC_Handler_GIRQ18 ; 68h: 10, GIRQ18 + DCD NVIC_Handler_GIRQ19 ; 6Ch: 11, GIRQ19 + DCD NVIC_Handler_GIRQ20 ; 70h: 12, GIRQ20 + DCD NVIC_Handler_GIRQ21 ; 74h: 13, GIRQ21 + DCD NVIC_Handler_GIRQ23 ; 78h: 14, GIRQ23 + DCD NVIC_Handler_GIRQ24 ; 7Ch: 15, GIRQ24 + DCD NVIC_Handler_GIRQ25 ; 80h: 16, GIRQ25 + DCD NVIC_Handler_GIRQ26 ; 84h: 17, GIRQ26 + DCD 0 ; 88h: 18, RSVD + DCD 0 ; 8Ch: 19, RSVD + DCD NVIC_Handler_I2C0 ; 90h: 20, I2C/SMBus 0 + DCD NVIC_Handler_I2C1 ; 94h: 21, I2C/SMBus 1 + DCD NVIC_Handler_I2C2 ; 98h: 22, I2C/SMBus 2 + DCD NVIC_Handler_I2C3 ; 9Ch: 23, I2C/SMBus 3 + DCD NVIC_Handler_DMA0 ; A0h: 24, DMA Channel 0 + DCD NVIC_Handler_DMA1 ; A4h: 25, DMA Channel 1 + DCD NVIC_Handler_DMA2 ; A8h: 26, DMA Channel 2 + DCD NVIC_Handler_DMA3 ; ACh: 27, DMA Channel 3 + DCD NVIC_Handler_DMA4 ; B0h: 28, DMA Channel 4 + DCD NVIC_Handler_DMA5 ; B4h: 29, DMA Channel 5 + DCD NVIC_Handler_DMA6 ; B8h: 30, DMA Channel 6 + DCD NVIC_Handler_DMA7 ; BCh: 31, DMA Channel 7 + DCD NVIC_Handler_DMA8 ; C0h: 32, DMA Channel 8 + DCD NVIC_Handler_DMA9 ; C4h: 33, DMA Channel 9 + DCD NVIC_Handler_DMA10 ; C8h: 34, DMA Channel 10 + DCD NVIC_Handler_DMA11 ; CCh: 35, DMA Channel 11 + DCD NVIC_Handler_DMA12 ; D0h: 36, DMA Channel 12 + DCD NVIC_Handler_DMA13 ; D4h: 37, DMA Channel 13 + DCD 0 ; D8h: 38, Unused + DCD 0 ; DCh: 39, Unused + DCD NVIC_Handler_UART0 ; E0h: 40, UART0 + DCD NVIC_Handler_UART1 ; E4h: 41, UART1 + DCD NVIC_Handler_EMI0 ; E8h: 42, EMI0 + DCD NVIC_Handler_EMI1 ; ECh: 43, EMI0 + DCD NVIC_Handler_EMI2 ; F0h: 44, EMI0 + DCD NVIC_Handler_ACPI_EC0_IBF ; F4h: 45, ACPI_EC0_IBF + DCD NVIC_Handler_ACPI_EC0_OBF ; F8h: 46, ACPI_EC0_OBF + DCD NVIC_Handler_ACPI_EC1_IBF ; FCh: 47, ACPI_EC1_IBF + DCD NVIC_Handler_ACPI_EC1_OBF ; 100h: 48, ACPI_EC1_OBF + DCD NVIC_Handler_ACPI_EC2_IBF ; 104h: 49, ACPI_EC0_IBF + DCD NVIC_Handler_ACPI_EC2_OBF ; 108h: 50, ACPI_EC0_OBF + DCD NVIC_Handler_ACPI_EC3_IBF ; 10Ch: 51, ACPI_EC1_IBF + DCD NVIC_Handler_ACPI_EC3_OBF ; 110h: 52, ACPI_EC1_OBF + DCD NVIC_Handler_ACPI_EC4_IBF ; 114h: 53, ACPI_EC0_IBF + DCD NVIC_Handler_ACPI_EC4_OBF ; 118h: 54, ACPI_EC0_OBF + DCD NVIC_Handler_PM1_CTL ; 11Ch: 55, ACPI_PM1_CTL + DCD NVIC_Handler_PM1_EN ; 120h: 56, ACPI_PM1_EN + DCD NVIC_Handler_PM1_STS ; 124h: 57, ACPI_PM1_STS + DCD NVIC_Handler_MIF8042_OBF ; 128h: 58, MIF8042_OBF + DCD NVIC_Handler_MIF8042_IBF ; 12Ch: 59, MIF8042_IBF + DCD NVIC_Handler_MB_H2EC ; 130h: 60, Mailbox Host to EC + DCD NVIC_Handler_MB_DATA ; 134h: 61, Mailbox Host Data + DCD NVIC_Handler_P80A ; 138h: 62, Port 80h A + DCD NVIC_Handler_P80B ; 13Ch: 63, Port 80h B + DCD 0 ; 140h: 64, Reserved + DCD NVIC_Handler_PKE_ERR ; 144h: 65, PKE Error + DCD NVIC_Handler_PKE_END ; 148h: 66, PKE End + DCD NVIC_Handler_TRNG ; 14Ch: 67, Random Num Gen + DCD NVIC_Handler_AES ; 150h: 68, AES + DCD NVIC_Handler_HASH ; 154h: 69, HASH + DCD NVIC_Handler_PECI ; 158h: 70, PECI + DCD NVIC_Handler_TACH0 ; 15Ch: 71, TACH0 + DCD NVIC_Handler_TACH1 ; 160h: 72, TACH1 + DCD NVIC_Handler_TACH2 ; 164h: 73, TACH2 + DCD NVIC_Handler_R2P0_FAIL ; 168h: 74, RPM2PWM 0 Fan Fail + DCD NVIC_Handler_R2P0_STALL ; 16Ch: 75, RPM2PWM 0 Fan Stall + DCD NVIC_Handler_R2P1_FAIL ; 170h: 76, RPM2PWM 1 Fan Fail + DCD NVIC_Handler_R2P1_STALL ; 174h: 77, RPM2PWM 1 Fan Stall + DCD NVIC_Handler_ADC_SNGL ; 178h: 78, ADC_SNGL + DCD NVIC_Handler_ADC_RPT ; 17Ch: 79, ADC_RPT + DCD NVIC_Handler_RCID0 ; 180h: 80, RCID 0 + DCD NVIC_Handler_RCID1 ; 184h: 81, RCID 1 + DCD NVIC_Handler_RCID2 ; 188h: 82, RCID 2 + DCD NVIC_Handler_LED0 ; 18Ch: 83, LED0 + DCD NVIC_Handler_LED1 ; 190h: 84, LED1 + DCD NVIC_Handler_LED2 ; 194h: 85, LED2 + DCD NVIC_Handler_LED3 ; 198h: 86, LED2 + DCD NVIC_Handler_PHOT ; 19Ch: 87, ProcHot Monitor + DCD NVIC_Handler_PWRGD0 ; 1A0h: 88, PowerGuard 0 Status + DCD NVIC_Handler_PWRGD1 ; 1A4h: 89, PowerGuard 1 Status + DCD NVIC_Handler_LPCBERR ; 1A8h: 90, LPC Bus Error + DCD NVIC_Handler_QMSPI0 ; 1ACh: 91, QMSPI 0 + DCD NVIC_Handler_GPSPI0_TX ; 1B0h: 92, GP-SPI0 TX + DCD NVIC_Handler_GPSPI0_RX ; 1B4h: 93, GP-SPI0 RX + DCD NVIC_Handler_GPSPI1_TX ; 1B8h: 94, GP-SPI1 TX + DCD NVIC_Handler_GPSPI1_RX ; 1BCh: 95, GP-SPI1 RX + DCD NVIC_Handler_BC0_BUSY ; 1C0h: 96, BC-Link0 Busy-Clear + DCD NVIC_Handler_BC0_ERR ; 1C4h: 97, BC-Link0 Error + DCD NVIC_Handler_BC1_BUSY ; 1C8h: 98, BC-Link1 Busy-Clear + DCD NVIC_Handler_BC1_ERR ; 1CCh: 99, BC-Link1 Error + DCD NVIC_Handler_PS2_0 ; 1D0h: 100, PS2_0 + DCD NVIC_Handler_PS2_1 ; 1D4h: 101, PS2_1 + DCD NVIC_Handler_PS2_2 ; 1D8h: 102, PS2_2 + DCD NVIC_Handler_ESPI_PC ; 1DCh: 103, eSPI Periph Chan + DCD NVIC_Handler_ESPI_BM1 ; 1E0h: 104, eSPI Bus Master 1 + DCD NVIC_Handler_ESPI_BM2 ; 1E4h: 105, eSPI Bus Master 2 + DCD NVIC_Handler_ESPI_LTR ; 1E8h: 106, eSPI LTR + DCD NVIC_Handler_ESPI_OOB_UP ; 1ECh: 107, eSPI Bus Master 1 + DCD NVIC_Handler_ESPI_OOB_DN ; 1F0h: 108, eSPI Bus Master 2 + DCD NVIC_Handler_ESPI_FLASH ; 1F4h: 109, eSPI Flash Chan + DCD NVIC_Handler_ESPI_RESET ; 1F8h: 110, eSPI Reset + DCD NVIC_Handler_RTMR ; 1FCh: 111, RTOS Timer + DCD NVIC_Handler_HTMR0 ; 200h: 112, Hibernation Timer 0 + DCD NVIC_Handler_HTMR1 ; 204h: 113, Hibernation Timer 1 + DCD NVIC_Handler_WK ; 208h: 114, Week Alarm + DCD NVIC_Handler_WKSUB ; 20Ch: 115, Week Alarm, sub week + DCD NVIC_Handler_WKSEC ; 210h: 116, Week Alarm, one sec + DCD NVIC_Handler_WKSUBSEC ; 214h: 117, Week Alarm, sub sec + DCD NVIC_Handler_SYSPWR ; 218h: 118, System Power Present pin + DCD NVIC_Handler_RTC ; 21Ch: 119, RTC + DCD NVIC_Handler_RTC_ALARM ; 220h: 120, RTC_ALARM + DCD NVIC_Handler_VCI_OVRD_IN ; 224h: 121, VCI Override Input + DCD NVIC_Handler_VCI_IN0 ; 228h: 122, VCI Input 0 + DCD NVIC_Handler_VCI_IN1 ; 22Ch: 123, VCI Input 1 + DCD NVIC_Handler_VCI_IN2 ; 230h: 124, VCI Input 2 + DCD NVIC_Handler_VCI_IN3 ; 234h: 125, VCI Input 3 + DCD NVIC_Handler_VCI_IN4 ; 238h: 126, VCI Input 4 + DCD NVIC_Handler_VCI_IN5 ; 23Ch: 127, VCI Input 5 + DCD NVIC_Handler_VCI_IN6 ; 240h: 128, VCI Input 6 + DCD NVIC_Handler_PS20A_WAKE ; 244h: 129, PS2 Port 0A Wake + DCD NVIC_Handler_PS20B_WAKE ; 248h: 130, PS2 Port 0B Wake + DCD NVIC_Handler_PS21A_WAKE ; 24Ch: 131, PS2 Port 1A Wake + DCD NVIC_Handler_PS21B_WAKE ; 250h: 132, PS2 Port 1B Wake + DCD NVIC_Handler_PS21_WAKE ; 254h: 133, PS2 Port 1 Wake + DCD NVIC_Handler_ENVMON ; 258h: 134, Thernal Monitor + DCD NVIC_Handler_KEYSCAN ; 25Ch: 135, Key Scan + DCD NVIC_Handler_BTMR16_0 ; 260h: 136, 16-bit Basic Timer 0 + DCD NVIC_Handler_BTMR16_1 ; 264h: 137, 16-bit Basic Timer 1 + DCD NVIC_Handler_BTMR16_2 ; 268h: 138, 16-bit Basic Timer 2 + DCD NVIC_Handler_BTMR16_3 ; 26Ch: 139, 16-bit Basic Timer 3 + DCD NVIC_Handler_BTMR32_0 ; 270h: 140, 32-bit Basic Timer 0 + DCD NVIC_Handler_BTMR32_1 ; 274h: 141, 32-bit Basic Timer 1 + DCD NVIC_Handler_EVTMR0 ; 278h: 142, Event Counter/Timer 0 + DCD NVIC_Handler_EVTMR1 ; 27Ch: 143, Event Counter/Timer 1 + DCD NVIC_Handler_EVTMR2 ; 280h: 144, Event Counter/Timer 2 + DCD NVIC_Handler_EVTMR3 ; 284h: 145, Event Counter/Timer 3 + DCD NVIC_Handler_CAPTMR ; 288h: 146, Capture Timer + DCD NVIC_Handler_CAP0 ; 28Ch: 147, Capture 0 Event + DCD NVIC_Handler_CAP1 ; 290h: 148, Capture 1 Event + DCD NVIC_Handler_CAP2 ; 294h: 149, Capture 2 Event + DCD NVIC_Handler_CAP3 ; 298h: 150, Capture 3 Event + DCD NVIC_Handler_CAP4 ; 29Ch: 151, Capture 4 Event + DCD NVIC_Handler_CAP5 ; 2A0h: 152, Capture 5 Event + DCD NVIC_Handler_CMP0 ; 2A4h: 153, Compare 0 Event + DCD NVIC_Handler_CMP1 ; 2A8h: 154, Compare 1 Event + ; Project build information + + AREA |.text|, CODE, READONLY +; AREA RESET, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + ; Remap vector table + LDR R0, =__Vectors + LDR R1, =0xE000ED08 + STR R0, [r1] + NOP + + IF {CPU} = "Cortex-M4.fp" + LDR R0, =0xE000ED88 ; Enable CP10,CP11 + LDR R1,[R0] + ORR R1,R1,#(0xF << 20) + STR R1,[R0] + ENDIF + + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT NVIC_Handler_GIRQ08 [WEAK] + EXPORT NVIC_Handler_GIRQ09 [WEAK] + EXPORT NVIC_Handler_GIRQ10 [WEAK] + EXPORT NVIC_Handler_GIRQ11 [WEAK] + EXPORT NVIC_Handler_GIRQ12 [WEAK] + EXPORT NVIC_Handler_GIRQ13 [WEAK] + EXPORT NVIC_Handler_GIRQ14 [WEAK] + EXPORT NVIC_Handler_GIRQ15 [WEAK] + EXPORT NVIC_Handler_GIRQ16 [WEAK] + EXPORT NVIC_Handler_GIRQ17 [WEAK] + EXPORT NVIC_Handler_GIRQ18 [WEAK] + EXPORT NVIC_Handler_GIRQ19 [WEAK] + EXPORT NVIC_Handler_GIRQ20 [WEAK] + EXPORT NVIC_Handler_GIRQ21 [WEAK] + EXPORT NVIC_Handler_GIRQ23 [WEAK] + EXPORT NVIC_Handler_GIRQ24 [WEAK] + EXPORT NVIC_Handler_GIRQ25 [WEAK] + EXPORT NVIC_Handler_GIRQ26 [WEAK] + + EXPORT NVIC_Handler_I2C0 [WEAK] + EXPORT NVIC_Handler_I2C1 [WEAK] + EXPORT NVIC_Handler_I2C2 [WEAK] + EXPORT NVIC_Handler_I2C3 [WEAK] + EXPORT NVIC_Handler_DMA0 [WEAK] + EXPORT NVIC_Handler_DMA1 [WEAK] + EXPORT NVIC_Handler_DMA2 [WEAK] + EXPORT NVIC_Handler_DMA3 [WEAK] + EXPORT NVIC_Handler_DMA4 [WEAK] + EXPORT NVIC_Handler_DMA5 [WEAK] + EXPORT NVIC_Handler_DMA6 [WEAK] + EXPORT NVIC_Handler_DMA7 [WEAK] + EXPORT NVIC_Handler_DMA8 [WEAK] + EXPORT NVIC_Handler_DMA9 [WEAK] + EXPORT NVIC_Handler_DMA10 [WEAK] + EXPORT NVIC_Handler_DMA11 [WEAK] + EXPORT NVIC_Handler_DMA12 [WEAK] + EXPORT NVIC_Handler_DMA13 [WEAK] + + EXPORT NVIC_Handler_UART0 [WEAK] + EXPORT NVIC_Handler_UART1 [WEAK] + EXPORT NVIC_Handler_EMI0 [WEAK] + EXPORT NVIC_Handler_EMI1 [WEAK] + EXPORT NVIC_Handler_EMI2 [WEAK] + EXPORT NVIC_Handler_ACPI_EC0_IBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC0_OBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC1_IBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC1_OBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC2_IBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC2_OBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC3_IBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC3_OBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC4_IBF [WEAK] + EXPORT NVIC_Handler_ACPI_EC4_OBF [WEAK] + EXPORT NVIC_Handler_PM1_CTL [WEAK] + EXPORT NVIC_Handler_PM1_EN [WEAK] + EXPORT NVIC_Handler_PM1_STS [WEAK] + EXPORT NVIC_Handler_MIF8042_OBF [WEAK] + EXPORT NVIC_Handler_MIF8042_IBF [WEAK] + EXPORT NVIC_Handler_MB_H2EC [WEAK] + EXPORT NVIC_Handler_MB_DATA [WEAK] + EXPORT NVIC_Handler_P80A [WEAK] + EXPORT NVIC_Handler_P80B [WEAK] + + EXPORT NVIC_Handler_PKE_ERR [WEAK] + EXPORT NVIC_Handler_PKE_END [WEAK] + EXPORT NVIC_Handler_TRNG [WEAK] + EXPORT NVIC_Handler_AES [WEAK] + EXPORT NVIC_Handler_HASH [WEAK] + EXPORT NVIC_Handler_PECI [WEAK] + EXPORT NVIC_Handler_TACH0 [WEAK] + EXPORT NVIC_Handler_TACH1 [WEAK] + EXPORT NVIC_Handler_TACH2 [WEAK] + EXPORT NVIC_Handler_R2P0_FAIL [WEAK] + EXPORT NVIC_Handler_R2P0_STALL [WEAK] + EXPORT NVIC_Handler_R2P1_FAIL [WEAK] + EXPORT NVIC_Handler_R2P1_STALL [WEAK] + EXPORT NVIC_Handler_ADC_SNGL [WEAK] + EXPORT NVIC_Handler_ADC_RPT [WEAK] + EXPORT NVIC_Handler_RCID0 [WEAK] + EXPORT NVIC_Handler_RCID1 [WEAK] + EXPORT NVIC_Handler_RCID2 [WEAK] + EXPORT NVIC_Handler_LED0 [WEAK] + EXPORT NVIC_Handler_LED1 [WEAK] + EXPORT NVIC_Handler_LED2 [WEAK] + EXPORT NVIC_Handler_LED3 [WEAK] + EXPORT NVIC_Handler_PHOT [WEAK] + EXPORT NVIC_Handler_PWRGD0 [WEAK] + EXPORT NVIC_Handler_PWRGD1 [WEAK] + EXPORT NVIC_Handler_LPCBERR [WEAK] + EXPORT NVIC_Handler_QMSPI0 [WEAK] + EXPORT NVIC_Handler_GPSPI0_TX [WEAK] + EXPORT NVIC_Handler_GPSPI0_RX [WEAK] + EXPORT NVIC_Handler_GPSPI1_TX [WEAK] + EXPORT NVIC_Handler_GPSPI1_RX [WEAK] + EXPORT NVIC_Handler_BC0_BUSY [WEAK] + EXPORT NVIC_Handler_BC0_ERR [WEAK] + EXPORT NVIC_Handler_BC1_BUSY [WEAK] + EXPORT NVIC_Handler_BC1_ERR [WEAK] + EXPORT NVIC_Handler_PS2_0 [WEAK] + EXPORT NVIC_Handler_PS2_1 [WEAK] + EXPORT NVIC_Handler_PS2_2 [WEAK] + EXPORT NVIC_Handler_ESPI_PC [WEAK] + EXPORT NVIC_Handler_ESPI_BM1 [WEAK] + EXPORT NVIC_Handler_ESPI_BM2 [WEAK] + EXPORT NVIC_Handler_ESPI_LTR [WEAK] + EXPORT NVIC_Handler_ESPI_OOB_UP [WEAK] + EXPORT NVIC_Handler_ESPI_OOB_DN [WEAK] + EXPORT NVIC_Handler_ESPI_FLASH [WEAK] + EXPORT NVIC_Handler_ESPI_RESET [WEAK] + EXPORT NVIC_Handler_RTMR [WEAK] + EXPORT NVIC_Handler_HTMR0 [WEAK] + EXPORT NVIC_Handler_HTMR1 [WEAK] + EXPORT NVIC_Handler_WK [WEAK] + EXPORT NVIC_Handler_WKSUB [WEAK] + EXPORT NVIC_Handler_WKSEC [WEAK] + EXPORT NVIC_Handler_WKSUBSEC [WEAK] + EXPORT NVIC_Handler_SYSPWR [WEAK] + EXPORT NVIC_Handler_RTC [WEAK] + EXPORT NVIC_Handler_RTC_ALARM [WEAK] + EXPORT NVIC_Handler_VCI_OVRD_IN [WEAK] + EXPORT NVIC_Handler_VCI_IN0 [WEAK] + EXPORT NVIC_Handler_VCI_IN1 [WEAK] + EXPORT NVIC_Handler_VCI_IN2 [WEAK] + EXPORT NVIC_Handler_VCI_IN3 [WEAK] + EXPORT NVIC_Handler_VCI_IN4 [WEAK] + EXPORT NVIC_Handler_VCI_IN5 [WEAK] + EXPORT NVIC_Handler_VCI_IN6 [WEAK] + EXPORT NVIC_Handler_PS20A_WAKE [WEAK] + EXPORT NVIC_Handler_PS20B_WAKE [WEAK] + EXPORT NVIC_Handler_PS21A_WAKE [WEAK] + EXPORT NVIC_Handler_PS21B_WAKE [WEAK] + EXPORT NVIC_Handler_PS21_WAKE [WEAK] + EXPORT NVIC_Handler_ENVMON [WEAK] + EXPORT NVIC_Handler_KEYSCAN [WEAK] + EXPORT NVIC_Handler_BTMR16_0 [WEAK] + EXPORT NVIC_Handler_BTMR16_1 [WEAK] + EXPORT NVIC_Handler_BTMR16_2 [WEAK] + EXPORT NVIC_Handler_BTMR16_3 [WEAK] + EXPORT NVIC_Handler_BTMR32_0 [WEAK] + EXPORT NVIC_Handler_BTMR32_1 [WEAK] + EXPORT NVIC_Handler_EVTMR0 [WEAK] + EXPORT NVIC_Handler_EVTMR1 [WEAK] + EXPORT NVIC_Handler_EVTMR2 [WEAK] + EXPORT NVIC_Handler_EVTMR3 [WEAK] + EXPORT NVIC_Handler_CAPTMR [WEAK] + EXPORT NVIC_Handler_CAP0 [WEAK] + EXPORT NVIC_Handler_CAP1 [WEAK] + EXPORT NVIC_Handler_CAP2 [WEAK] + EXPORT NVIC_Handler_CAP3 [WEAK] + EXPORT NVIC_Handler_CAP4 [WEAK] + EXPORT NVIC_Handler_CAP5 [WEAK] + EXPORT NVIC_Handler_CMP0 [WEAK] + EXPORT NVIC_Handler_CMP1 [WEAK] + +NVIC_Handler_GIRQ08 +NVIC_Handler_GIRQ09 +NVIC_Handler_GIRQ10 +NVIC_Handler_GIRQ11 +NVIC_Handler_GIRQ12 +NVIC_Handler_GIRQ13 +NVIC_Handler_GIRQ14 +NVIC_Handler_GIRQ15 +NVIC_Handler_GIRQ16 +NVIC_Handler_GIRQ17 +NVIC_Handler_GIRQ18 +NVIC_Handler_GIRQ19 +NVIC_Handler_GIRQ20 +NVIC_Handler_GIRQ21 +NVIC_Handler_GIRQ23 +NVIC_Handler_GIRQ24 +NVIC_Handler_GIRQ25 +NVIC_Handler_GIRQ26 + +NVIC_Handler_I2C0 +NVIC_Handler_I2C1 +NVIC_Handler_I2C2 +NVIC_Handler_I2C3 +NVIC_Handler_DMA0 +NVIC_Handler_DMA1 +NVIC_Handler_DMA2 +NVIC_Handler_DMA3 +NVIC_Handler_DMA4 +NVIC_Handler_DMA5 +NVIC_Handler_DMA6 +NVIC_Handler_DMA7 +NVIC_Handler_DMA8 +NVIC_Handler_DMA9 +NVIC_Handler_DMA10 +NVIC_Handler_DMA11 +NVIC_Handler_DMA12 +NVIC_Handler_DMA13 + +NVIC_Handler_UART0 +NVIC_Handler_UART1 +NVIC_Handler_EMI0 +NVIC_Handler_EMI1 +NVIC_Handler_EMI2 +NVIC_Handler_ACPI_EC0_IBF +NVIC_Handler_ACPI_EC0_OBF +NVIC_Handler_ACPI_EC1_IBF +NVIC_Handler_ACPI_EC1_OBF +NVIC_Handler_ACPI_EC2_IBF +NVIC_Handler_ACPI_EC2_OBF +NVIC_Handler_ACPI_EC3_IBF +NVIC_Handler_ACPI_EC3_OBF +NVIC_Handler_ACPI_EC4_IBF +NVIC_Handler_ACPI_EC4_OBF +NVIC_Handler_PM1_CTL +NVIC_Handler_PM1_EN +NVIC_Handler_PM1_STS +NVIC_Handler_MIF8042_OBF +NVIC_Handler_MIF8042_IBF +NVIC_Handler_MB_H2EC +NVIC_Handler_MB_DATA +NVIC_Handler_P80A +NVIC_Handler_P80B + +NVIC_Handler_PKE_ERR +NVIC_Handler_PKE_END +NVIC_Handler_TRNG +NVIC_Handler_AES +NVIC_Handler_HASH +NVIC_Handler_PECI +NVIC_Handler_TACH0 +NVIC_Handler_TACH1 +NVIC_Handler_TACH2 +NVIC_Handler_R2P0_FAIL +NVIC_Handler_R2P0_STALL +NVIC_Handler_R2P1_FAIL +NVIC_Handler_R2P1_STALL +NVIC_Handler_ADC_SNGL +NVIC_Handler_ADC_RPT +NVIC_Handler_RCID0 +NVIC_Handler_RCID1 +NVIC_Handler_RCID2 +NVIC_Handler_LED0 +NVIC_Handler_LED1 +NVIC_Handler_LED2 +NVIC_Handler_LED3 +NVIC_Handler_PHOT +NVIC_Handler_PWRGD0 +NVIC_Handler_PWRGD1 +NVIC_Handler_LPCBERR +NVIC_Handler_QMSPI0 +NVIC_Handler_GPSPI0_TX +NVIC_Handler_GPSPI0_RX +NVIC_Handler_GPSPI1_TX +NVIC_Handler_GPSPI1_RX +NVIC_Handler_BC0_BUSY +NVIC_Handler_BC0_ERR +NVIC_Handler_BC1_BUSY +NVIC_Handler_BC1_ERR +NVIC_Handler_PS2_0 +NVIC_Handler_PS2_1 +NVIC_Handler_PS2_2 +NVIC_Handler_ESPI_PC +NVIC_Handler_ESPI_BM1 +NVIC_Handler_ESPI_BM2 +NVIC_Handler_ESPI_LTR +NVIC_Handler_ESPI_OOB_UP +NVIC_Handler_ESPI_OOB_DN +NVIC_Handler_ESPI_FLASH +NVIC_Handler_ESPI_RESET +NVIC_Handler_RTMR +NVIC_Handler_HTMR0 +NVIC_Handler_HTMR1 +NVIC_Handler_WK +NVIC_Handler_WKSUB +NVIC_Handler_WKSEC +NVIC_Handler_WKSUBSEC +NVIC_Handler_SYSPWR +NVIC_Handler_RTC +NVIC_Handler_RTC_ALARM +NVIC_Handler_VCI_OVRD_IN +NVIC_Handler_VCI_IN0 +NVIC_Handler_VCI_IN1 +NVIC_Handler_VCI_IN2 +NVIC_Handler_VCI_IN3 +NVIC_Handler_VCI_IN4 +NVIC_Handler_VCI_IN5 +NVIC_Handler_VCI_IN6 +NVIC_Handler_PS20A_WAKE +NVIC_Handler_PS20B_WAKE +NVIC_Handler_PS21A_WAKE +NVIC_Handler_PS21B_WAKE +NVIC_Handler_PS21_WAKE +NVIC_Handler_ENVMON +NVIC_Handler_KEYSCAN +NVIC_Handler_BTMR16_0 +NVIC_Handler_BTMR16_1 +NVIC_Handler_BTMR16_2 +NVIC_Handler_BTMR16_3 +NVIC_Handler_BTMR32_0 +NVIC_Handler_BTMR32_1 +NVIC_Handler_EVTMR0 +NVIC_Handler_EVTMR1 +NVIC_Handler_EVTMR2 +NVIC_Handler_EVTMR3 +NVIC_Handler_CAPTMR +NVIC_Handler_CAP0 +NVIC_Handler_CAP1 +NVIC_Handler_CAP2 +NVIC_Handler_CAP3 +NVIC_Handler_CAP4 +NVIC_Handler_CAP5 +NVIC_Handler_CMP0 +NVIC_Handler_CMP1 + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/main.c new file mode 100644 index 000000000..76b54018e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/main.c @@ -0,0 +1,309 @@ +/* + FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/* + * This is a simple example that creates two tasks and one queue. One task + * periodically sends a value to the other, which then prints out a message. + * Normally such a simple example would toggle an LED, so the message that is + * printed out is "toggle". + * + * The demo configures the kernel to be as simple as possible; FreeRTOSConfig.h + * excludes most features, including dynamic memory allocation. + */ + +/* Microchip includes. */ +#include "common.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH_IN_ITEMS ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Configures the clocks ready to run the demo. + */ +static void prvSetupHardware( void ); + +/* + * Simple routine to print a string to ITM for viewing in the Keil serial debug + * viewer. + */ +static void prvITMPrintString( const char *pcString ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* configSUPPORT_STATIC_ALLOCATION is 1 and configSUPPORT_DYNAMIC_ALLOCATION is +0 so the queue structure and the queue storage area can only be statically +allocated. See http://TBD for more information. +The queue storage area is dimensioned to hold just one 32-bit value. */ +static StaticQueue_t xStaticQueue; +static uint8_t ucQueueStorageArea[ mainQUEUE_LENGTH_IN_ITEMS * sizeof( uint32_t ) ]; + +/* Holds the handle of the created queue. */ +static QueueHandle_t xQueue = NULL; + +/* configSUPPORT_STATIC_ALLOCATION is 1 and configSUPPORT_DYNAMIC_ALLOCATION is +0 so the task structure and the stacks used by the tasks can only be statically +allocated. See http://TBD for more information. */ +StaticTask_t xRxTCBBuffer, xTxTCBBuffer; +static StackType_t uxRxStackBuffer[ configMINIMAL_STACK_SIZE ], uxTxStackBuffer[ configMINIMAL_STACK_SIZE ]; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Set up the hardware ready to run the demo. */ + prvSetupHardware(); + prvITMPrintString( "Starting\r\n" ); + + /* Create the queue. xQueueCreateStatic() has two more parameters than the + xQueueCreate() function. The first new parameter is a pointer to the + pre-allocated queue storage area. The second new parameter is a pointer to + the StaticQueue_t structure that will hold the queue state information in + an anonymous way. */ + xQueue = xQueueCreateStatic( mainQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */ + sizeof( uint32_t ), /* The size of each item. */ + ucQueueStorageArea, /* The buffer used to hold items within the queue. */ + &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */ + + /* Create the two tasks as described in the comments at the top of this + file. */ + xTaskCreateStatic( prvQueueReceiveTask, /* Function that implements the task. */ + "Rx", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority of the task. */ + &( uxRxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xRxTCBBuffer ); /* The variable that will hold that task's TCB. */ + + xTaskCreateStatic( prvQueueSendTask, /* Function that implements the task. */ + "Tx", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + mainQUEUE_SEND_TASK_PRIORITY, /* The priority of the task. */ + &( uxTxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xTxTCBBuffer ); /* The variable that will hold that task's TCB. */ + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If dynamic memory allocation was used then the following code line would + be reached if there was insufficient heap memory available to create either + the timer or idle tasks. As this project is using static memory allocation + then the following line should never be reached. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + /* Output a string in lieu of using an LED. */ + prvITMPrintString( "Toggle!\r\n" ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + SystemInit(); + SystemCoreClockUpdate(); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an +implementation of vApplicationGetIdleTaskMemory() to provide the memory that is +used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xIdleTaskTCB; +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the +application must provide an implementation of vApplicationGetTimerTaskMemory() +to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xTimerTaskTCB; +static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ + +static void prvITMPrintString( const char *pcString ) +{ + while( *pcString != 0x00 ) + { + ITM_SendChar( *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/ARM_REG.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/ARM_REG.h new file mode 100644 index 000000000..04ae1bd1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/ARM_REG.h @@ -0,0 +1,194 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * ARM_REG.h + * This is the header to define Cortex-M3 system control & status registers + ********************************************************************************** + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/ARM_REG.h $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2016/09/22 08:03:49 $ + * AUTHOR: $Author: pramans $ + * + * Revision history (latest first): + * #xx + *********************************************************************************** + */ + +/******************************************************************************/ +/** @defgroup ARM_REG ARM_REG + * @{ + */ + +/** @file ARM_REG.h +* \brief ARM Cortex-M3 registers header file +* \author KBCEC Team +* +* This file contains ARM Cortex-M3 system control & status registers. +******************************************************************************/ +#ifndef ARM_REG_H_ +#define ARM_REG_H_ + +#define REG8(x) (*((volatile unsigned char *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned long *)(x))) + +/* NVIC Registers */ +#define NVIC_INT_TYPE REG32(0xE000E004) +#define NVIC_AUX_ACTLR REG32(0xE000E008) + #define WR_BUF_DISABLE (1 << 1) +#define NVIC_ST_CTRL REG32(0xE000E010) + #define ST_ENABLE (1 << 0) + #define ST_TICKINT (1 << 1) + #define ST_CLKSOURCE (1 << 2) + #define ST_COUNTFLAG (1 << 3) +#define NVIC_ST_RELOAD REG32(0xE000E014) +#define NVIC_ST_CURRENT REG32(0xE000E018) +#define NVIC_ST_CALIB REG32(0xE000E01C) +#define NVIC_ENABLE0 REG32(0xE000E100) +#define NVIC_ENABLE1 REG32(0xE000E104) +#define NVIC_ENABLE2 REG32(0xE000E108) +#define NVIC_ENABLE3 REG32(0xE000E10C) +#define NVIC_ENABLE4 REG32(0xE000E110) +#define NVIC_ENABLE5 REG32(0xE000E114) +#define NVIC_ENABLE6 REG32(0xE000E118) +#define NVIC_ENABLE7 REG32(0xE000E11C) +#define NVIC_DISABLE0 REG32(0xE000E180) +#define NVIC_DISABLE1 REG32(0xE000E184) +#define NVIC_DISABLE2 REG32(0xE000E188) +#define NVIC_DISABLE3 REG32(0xE000E18C) +#define NVIC_DISABLE4 REG32(0xE000E190) +#define NVIC_DISABLE5 REG32(0xE000E194) +#define NVIC_DISABLE6 REG32(0xE000E198) +#define NVIC_DISABLE7 REG32(0xE000E19C) +#define NVIC_PEND0 REG32(0xE000E200) +#define NVIC_PEND1 REG32(0xE000E204) +#define NVIC_PEND2 REG32(0xE000E208) +#define NVIC_PEND3 REG32(0xE000E20C) +#define NVIC_PEND4 REG32(0xE000E210) +#define NVIC_PEND5 REG32(0xE000E214) +#define NVIC_PEND6 REG32(0xE000E218) +#define NVIC_PEND7 REG32(0xE000E21C) +#define NVIC_UNPEND0 REG32(0xE000E280) +#define NVIC_UNPEND1 REG32(0xE000E284) +#define NVIC_UNPEND2 REG32(0xE000E288) +#define NVIC_UNPEND3 REG32(0xE000E28C) +#define NVIC_UNPEND4 REG32(0xE000E290) +#define NVIC_UNPEND5 REG32(0xE000E294) +#define NVIC_UNPEND6 REG32(0xE000E298) +#define NVIC_UNPEND7 REG32(0xE000E29C) +#define NVIC_ACTIVE0 REG32(0xE000E300) +#define NVIC_ACTIVE1 REG32(0xE000E304) +#define NVIC_ACTIVE2 REG32(0xE000E308) +#define NVIC_ACTIVE3 REG32(0xE000E30C) +#define NVIC_ACTIVE4 REG32(0xE000E310) +#define NVIC_ACTIVE5 REG32(0xE000E314) +#define NVIC_ACTIVE6 REG32(0xE000E318) +#define NVIC_ACTIVE7 REG32(0xE000E31C) +#define NVIC_PRI0 REG32(0xE000E400) +#define NVIC_PRI1 REG32(0xE000E404) +#define NVIC_PRI2 REG32(0xE000E408) +#define NVIC_PRI3 REG32(0xE000E40C) +#define NVIC_PRI4 REG32(0xE000E410) +#define NVIC_PRI5 REG32(0xE000E414) +#define NVIC_PRI6 REG32(0xE000E418) +#define NVIC_PRI7 REG32(0xE000E41C) +#define NVIC_PRI8 REG32(0xE000E420) +#define NVIC_PRI9 REG32(0xE000E424) +#define NVIC_PRI10 REG32(0xE000E428) +#define NVIC_PRI11 REG32(0xE000E42C) +#define NVIC_PRI12 REG32(0xE000E430) +#define NVIC_PRI13 REG32(0xE000E434) +#define NVIC_PRI14 REG32(0xE000E438) +#define NVIC_PRI15 REG32(0xE000E43C) +#define NVIC_PRI16 REG32(0xE000E440) +#define NVIC_PRI17 REG32(0xE000E444) +#define NVIC_PRI18 REG32(0xE000E448) +#define NVIC_PRI19 REG32(0xE000E44C) +#define NVIC_PRI20 REG32(0xE000E450) +#define NVIC_PRI21 REG32(0xE000E454) +#define NVIC_PRI22 REG32(0xE000E458) +#define NVIC_PRI23 REG32(0xE000E45C) +#define NVIC_PRI24 REG32(0xE000E460) +#define NVIC_PRI25 REG32(0xE000E464) +#define NVIC_PRI26 REG32(0xE000E468) +#define NVIC_PRI27 REG32(0xE000E46C) +#define NVIC_PRI28 REG32(0xE000E470) +#define NVIC_PRI29 REG32(0xE000E474) +#define NVIC_PRI30 REG32(0xE000E478) +#define NVIC_PRI31 REG32(0xE000E47C) +#define NVIC_PRI32 REG32(0xE000E480) +#define NVIC_PRI33 REG32(0xE000E484) +#define NVIC_PRI34 REG32(0xE000E488) +#define NVIC_PRI35 REG32(0xE000E48C) +#define NVIC_PRI36 REG32(0xE000E490) +#define NVIC_PRI37 REG32(0xE000E494) +#define NVIC_PRI38 REG32(0xE000E498) +#define NVIC_PRI39 REG32(0xE000E49C) +#define NVIC_PRI40 REG32(0xE000E4A0) +#define NVIC_PRI41 REG32(0xE000E4A4) +#define NVIC_PRI42 REG32(0xE000E4A8) +#define NVIC_PRI43 REG32(0xE000E4AC) +#define NVIC_PRI44 REG32(0xE000E4B0) +#define NVIC_PRI45 REG32(0xE000E4B4) +#define NVIC_PRI46 REG32(0xE000E4B8) +#define NVIC_PRI47 REG32(0xE000E4BC) +#define NVIC_PRI48 REG32(0xE000E4C0) +#define NVIC_PRI49 REG32(0xE000E4C4) +#define NVIC_PRI50 REG32(0xE000E4C8) +#define NVIC_PRI51 REG32(0xE000E4CC) +#define NVIC_PRI52 REG32(0xE000E4D0) +#define NVIC_PRI53 REG32(0xE000E4D4) +#define NVIC_PRI54 REG32(0xE000E4D8) +#define NVIC_PRI55 REG32(0xE000E4DC) +#define NVIC_PRI56 REG32(0xE000E4E0) +#define NVIC_PRI57 REG32(0xE000E4E4) +#define NVIC_PRI58 REG32(0xE000E4E8) +#define NVIC_PRI59 REG32(0xE000E4EC) +#define NVIC_CPUID REG32(0xE000ED00) +#define NVIC_INT_CTRL REG32(0xE000ED04) +#define NVIC_VECT_TABLE REG32(0xE000ED08) +#define NVIC_AP_INT_RST REG32(0xE000ED0C) +#define NVIC_SYS_CTRL REG32(0xE000ED10) +#define NVIC_CFG_CTRL REG32(0xE000ED14) +#define NVIC_SYS_H_PRI1 REG32(0xE000ED18) +#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C) +#define NVIC_SYS_H_PRI3 REG32(0xE000ED20) +#define NVIC_SYS_H_CTRL REG32(0xE000ED24) +#define NVIC_FAULT_STA REG32(0xE000ED28) +#define NVIC_HARD_F_STA REG32(0xE000ED2C) +#define NVIC_DBG_F_STA REG32(0xE000ED30) +#define NVIC_MM_F_ADR REG32(0xE000ED34) +#define NVIC_BUS_F_ADR REG32(0xE000ED38) +#define NVIC_SW_TRIG REG32(0xE000EF00) + +/* MPU Registers */ +#define MPU_TYPE REG32(0xE000ED90) +#define MPU_CTRL REG32(0xE000ED94) +#define MPU_RG_NUM REG32(0xE000ED98) +#define MPU_RG_ADDR REG32(0xE000ED9C) +#define MPU_RG_AT_SZ REG32(0xE000EDA0) + + +#endif /* #ifndef ARM_REG_H_ */ + +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/MCHP_device_header.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/MCHP_device_header.h new file mode 100644 index 000000000..d3702d98e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/MCHP_device_header.h @@ -0,0 +1,2214 @@ + +/****************************************************************************************************//** + * @file MCHP_device_header.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * MCHP_device_header from Microchip Technology Inc.. + * + * @version V1.0 + * @date 5. November 2015 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'MCHP_device_header.svd' Version 1.0, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + + +/** @addtogroup Microchip Technology Inc. + * @{ + */ + +/** @addtogroup MCHP_device_header + * @{ + */ + +#ifndef MCHP_DEVICE_HEADER_H +#define MCHP_DEVICE_HEADER_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ----------------Device Specific Interrupt Numbers---------------- */ + GPIO_140_176_IRQn = 0, /*!< 0 GPIO[140:176], GIRQ08 */ + GPIO_100_137_IRQn = 1, /*!< 1 GPIO[100:137], GIRQ09 */ + GPIO_040_076_IRQn = 2, /*!< 2 GPIO[040:076], GIRQ10 */ + GPIO_000_036_IRQn = 3, /*!< 3 GPIO[000:036], GIRQ11 */ + GPIO_200_236_IRQn = 4, /*!< 4 GPIO[200:236], GIRQ12 */ + MSVW00_06_IRQn = 15, /*!< 15 MSVW[00:06]_SRC[0:3], GIRQ 24 */ + MSVW07_10_IRQn = 16, /*!< 16 MSVW[07:10]_SRC[0:3], GIRQ 25 */ + GPIO_240_257_IRQn = 17, /*!< 17 GPIO[240:257], GIRQ26 */ + SMB0_IRQn = 20, /*!< 20 SMB0, GIRQ 13.0 */ + SMB1_IRQn = 21, /*!< 21 SMB1 */ + SMB2_IRQn = 22, /*!< 22 SMB2 */ + SMB3_IRQn = 23, /*!< 23 SMB3 */ + DMA0_IRQn = 24, /*!< 24 DMA0, GIRQ14.0 */ + DMA1_IRQn = 25, /*!< 25 DMA1 */ + DMA2_IRQn = 26, /*!< 26 DMA2 */ + DMA3_IRQn = 27, /*!< 27 DMA3 */ + DMA4_IRQn = 28, /*!< 28 DMA4 */ + DMA5_IRQn = 29, /*!< 29 DMA5 */ + DMA6_IRQn = 30, /*!< 30 DMA6 */ + DMA7_IRQn = 31, /*!< 31 DMA7 */ + DMA8_IRQn = 32, /*!< 32 DMA8 */ + DMA9_IRQn = 33, /*!< 33 DMA9 */ + DMA10_IRQn = 34, /*!< 34 DMA10 */ + DMA11_IRQn = 35, /*!< 35 DMA11 */ + DMA12_IRQn = 36, /*!< 36 DMA12 */ + DMA13_IRQn = 37, /*!< 37 DMA13 */ + UART_0_IRQn = 40, /*!< 40 UART 0, GIRQ 15.0 */ + UART_1_IRQn = 41, /*!< 41 UART 1, GIRQ 15.1 */ + EMI_0_IRQn = 42, /*!< 42 EMI_0, GIRQ 15.2 */ + EMI_1_IRQn = 43, /*!< 43 EMI_1, GIRQ 15.3 */ + EMI_2_IRQn = 44, /*!< 44 EMI_2, GIRQ 15.4 */ + ACPIEC0_IBF_IRQn = 45, /*!< 45 ACPIEC[0] IBF, GIRQ 15.5 */ + ACPIEC0_OBF_IRQn = 46, /*!< 46 ACPIEC[0] OBF, GIRQ 15.6 */ + ACPIEC1_IBF_IRQn = 47, /*!< 47 ACPIEC[1] IBF, GIRQ 15.7 */ + ACPIEC1_OBF_IRQn = 48, /*!< 48 ACPIEC[1] OBF, GIRQ 15.8 */ + ACPIEC2_IBF_IRQn = 49, /*!< 49 ACPIEC[2] IBF, GIRQ 15.9 */ + ACPIEC2_OBF_IRQn = 50, /*!< 50 ACPIEC[2] OBF, GIRQ 15.10 */ + ACPIEC3_IBF_IRQn = 51, /*!< 51 ACPIEC[3] IBF, GIRQ 15.11 */ + ACPIEC3_OBF_IRQn = 52, /*!< 52 ACPIEC[3] OBF, GIRQ 15.12 */ + ACPIEC4_IBF_IRQn = 53, /*!< 53 ACPIEC[4] IBF, GIRQ 15.13 */ + ACPIEC4_OBF_IRQn = 54, /*!< 54 ACPIEC[4] OBF, GIRQ 15.14 */ + ACPIPM1_CTL_IRQn = 55, /*!< 55 ACPIPM1_CTL, GIRQ 15.10 */ + ACPIPM1_EN_IRQn = 56, /*!< 56 ACPIPM1_EN, GIRQ 15.11 */ + ACPIPM1_STS_IRQn = 57, /*!< 57 ACPIPM1_STS, GIRQ 15.12 */ + KBC8042_OBF_IRQn = 58, /*!< 58 8042EM OBF, GIRQ 15.18 */ + KBC8042_IBF_IRQn = 59, /*!< 59 8042EM IBF, GIRQ 15.19 */ + MAILBOX_IRQn = 60, /*!< 60 MAILBOX, GIRQ 15.20 */ + MAILBOX_DATA_IRQn = 61, /*!< 61 MAILBOX DATA, GIRQ 15.21 */ + PORT80_DEBUG_0_IRQn = 62, /*!< 62 PORT80_DEBUG_0, GIRQ 15.22 */ + PORT80_DEBUG_1_IRQn = 63, /*!< 63 PORT80_DEBUG_1, GIRQ 15.23 */ + ASIF_INT_IRQn = 64, /*!< 64 ASIF_INT, GIRQ 15.24 */ + PECIHOST_IRQn = 70, /*!< 70 PECIHOST, GIRQ 17.0 */ + TACH_0_IRQn = 71, /*!< 71 TACH_0, GIRQ 17.1 */ + TACH_1_IRQn = 72, /*!< 72 TACH_1, GIRQ 17.2 */ + TACH_2_IRQn = 73, /*!< 73 TACH_2, GIRQ 17.3 */ + RPM2PWM_0_FAIL_IRQn = 74, /*!< 74 RPM2PWM_0 Fail, GIRQ 17.4 */ + RPM2PWM_0_STALL_IRQn = 75, /*!< 75 RPM2PWM_0 Stall, GIRQ 17.5 */ + RPM2PWM_1_FAIL_IRQn = 76, /*!< 76 RPM2PWM_1 Fail, GIRQ 17.6 */ + RPM2PWM_1_STALL_IRQn = 77, /*!< 77 RPM2PWM_1 Stall, GIRQ 17.7 */ + ADC_SNGL_IRQn = 78, /*!< 78 ADC_SNGL, GIRQ 17.8 */ + ADC_RPT_IRQn = 79, /*!< 79 ADC_RPT, GIRQ 17.9 */ + RC_ID_0_IRQn = 80, /*!< 80 RC_ID_0, GIRQ 17.10 */ + RC_ID_1_IRQn = 81, /*!< 81 RC_ID_1, GIRQ 17.11 */ + RC_ID_2_IRQn = 82, /*!< 82 RC_ID_2, GIRQ 17.12 */ + LED_0_IRQn = 83, /*!< 83 Breathing LED 0, GIRQ 17.13 */ + LED_1_IRQn = 84, /*!< 84 Breathing LED 1, GIRQ 17.14 */ + LED_2_IRQn = 85, /*!< 85 Breathing LED 2, GIRQ 17.15 */ + LED_3_IRQn = 86, /*!< 86 Breathing LED 3, GIRQ 17.16 */ + PROCHOT_MON_IRQn = 87, /*!< 87 PROCHOT_MON, GIRQ 17.17 */ + POWERGUARD_0_IRQn = 88, /*!< 88 POWERGUARD_0, GIRQ 17.18 */ + POWERGUARD_1_IRQn = 89, /*!< 89 POWERGUARD_1, GIRQ 17.19 */ + LPC_IRQn = 90, /*!< 90 LPC (GIRQ 18.0) */ + QMSPI_IRQn = 91, /*!< 91 QMSPI, GIRQ 18.1 */ + SPI0_TX_IRQn = 92, /*!< 92 SPI0 TX, GIRQ 18.2 */ + SPI0_RX_IRQn = 93, /*!< 93 SPI0 RX, GIRQ 18.3 */ + SPI1_TX_IRQn = 94, /*!< 94 SPI1 TX, GIRQ 18.4 */ + SPI1_RX_IRQn = 95, /*!< 95 SPI1 RX, GIRQ 18.5 */ + BCM_BUSY_CLR_0_IRQn = 96, /*!< 96 BCM_BUSY_CLR_0, GIRQ 18.6 */ + BCM_ERR_0_IRQn = 97, /*!< 97 BCM_ERR_0, GIRQ 18.7 */ + BCM_BUSY_CLR_1_IRQn = 98, /*!< 98 BCM_BUSY_CLR_1, GIRQ 18.8 */ + BCM_ERR_1_IRQn = 99, /*!< 99 BCM_ERR_1, GIRQ 18.9 */ + PS2_0_ACT_IRQn = 100, /*!< 100 PS2 Controller 0 Activity, GIRQ 17.14 */ + PS2_1_ACT_IRQn = 101, /*!< 101 PS2 Controller 1 Activity, GIRQ 17.15 */ + PS2_2_ACT_IRQn = 102, /*!< 102 PS2 Controller 2 Activity, GIRQ 17.16 */ + INTR_PC_IRQn = 103, /*!< 103 PC, GIRQ 19.0 */ + INTR_BM1_IRQn = 104, /*!< 104 BM1, GIRQ 19.1 */ + INTR_BM2_IRQn = 105, /*!< 105 BM2, GIRQ 19.2 */ + INTR_LTR_IRQn = 106, /*!< 106 LTR, GIRQ 19.3 */ + INTR_OOB_UP_IRQn = 107, /*!< 107 OOB_UP, GIRQ 19.4 */ + INTR_OOB_DOWN_IRQn = 108, /*!< 108 OOB_DOWN, GIRQ 19.5 */ + INTR_FLASH_IRQn = 109, /*!< 109 FLASH, GIRQ 19.6 */ + ESPI_RESET_IRQn = 110, /*!< 110 ESPI_RESET, GIRQ 19.7 */ + RTOS_TIMER_IRQn = 111, /*!< 111 RTOS_TIMER, GIRQ 21.0 */ + HTIMER0_IRQn = 112, /*!< 112 HTIMER0, GIRQ 21.1 */ + HTIMER1_IRQn = 113, /*!< 113 HTIMER1, GIRQ 21.2 */ + WEEK_ALARM_IRQn = 114, /*!< 114 WEEK_ALARM_INT, GIRQ 21.3 */ + SUB_WEEK_ALARM_IRQn = 115, /*!< 115 SUB_WEEK_ALARM_INT, GIRQ 21.4 */ + ONE_SECOND_IRQn = 116, /*!< 116 ONE_SECOND, GIRQ 21.5 */ + SUB_SECOND_IRQn = 117, /*!< 117 SUB_SECOND, GIRQ 21.6 */ + SYSPWR_PRES_IRQn = 118, /*!< 118 SYSPWR_PRES, GIRQ 21.7 */ + RTC_IRQn = 119, /*!< 119 RTC, GIRQ 21.8 */ + RTC_ALARM_IRQn = 120, /*!< 120 RTC ALARM, GIRQ 21.9 */ + VCI_OVRD_IN_IRQn = 121, /*!< 121 VCI_OVRD_IN, GIRQ 21.10 */ + VCI_IN0_IRQn = 122, /*!< 122 VCI_IN0, GIRQ 21.11 */ + VCI_IN1_IRQn = 123, /*!< 123 VCI_IN1, GIRQ 21.12 */ + VCI_IN2_IRQn = 124, /*!< 124 VCI_IN2, GIRQ 21.13 */ + VCI_IN3_IRQn = 125, /*!< 125 VCI_IN3, GIRQ 21.14 */ + VCI_IN4_IRQn = 126, /*!< 126 VCI_IN4, GIRQ 21.15 */ + VCI_IN5_IRQn = 127, /*!< 127 VCI_IN5, GIRQ 21.16 */ + VCI_IN6_IRQn = 128, /*!< 128 VCI_IN6, GIRQ 21.17 */ + PS2_0A_WK_IRQn = 129, /*!< 129 PS2 Controller 0 Port A Wake, GIRQ 21.18 */ + PS2_0B_WK_IRQn = 130, /*!< 130 PS2 Controller 0 Port B Wake, GIRQ 21.19 */ + PS2_1A_WK_IRQn = 131, /*!< 131 PS2 Controller 1 Port A Wake, GIRQ 21.20 */ + PS2_1B_WK_IRQn = 132, /*!< 132 PS2 Controller 1 Port B Wake, GIRQ 21.21 */ + PS2_2_WK_IRQn = 133, /*!< 133 PS2 Controller 2 Wake, GIRQ 21.22 */ + KSC_INT_IRQn = 135, /*!< 135 KSC, GIRQ 21.25 */ + TIMER0_IRQn = 136, /*!< 136 TIMER_16_0, GIRQ 23.0 */ + TIMER1_IRQn = 137, /*!< 137 TIMER_16_1, GIRQ 23.1 */ + TIMER2_IRQn = 138, /*!< 138 TIMER_16_2, GIRQ 23.2 */ + TIMER3_IRQn = 139, /*!< 139 TIMER_16_3, GIRQ 23.3 */ + TIMER4_IRQn = 140, /*!< 140 TIMER_32_0, GIRQ 23.4 */ + TIMER5_IRQn = 141, /*!< 141 TIMER_32_1, GIRQ 23.5 */ + COUNTER_TIMER_0_IRQn = 142, /*!< 142 COUNTER_TIMER_0, GIRQ 23.6 */ + COUNTER_TIMER_1_IRQn = 143, /*!< 143 COUNTER_TIMER_1, GIRQ 23.7 */ + COUNTER_TIMER_2_IRQn = 144, /*!< 144 COUNTER_TIMER_2, GIRQ 23.8 */ + COUNTER_TIMER_3_IRQn = 145, /*!< 145 COUNTER_TIMER_3, GIRQ 23.9 */ + CAPTURE_TIMER_IRQn = 146, /*!< 146 CAPTURE_TIMER, GIRQ 23.10 */ + CAPTURE_0_IRQn = 147, /*!< 147 CAPTURE_0, GIRQ 23.11 */ + CAPTURE_1_IRQn = 148, /*!< 148 CAPTURE_1, GIRQ 23.12 */ + CAPTURE_2_IRQn = 149, /*!< 149 CAPTURE_2, GIRQ 23.13 */ + CAPTURE_3_IRQn = 150, /*!< 150 CAPTURE_3, GIRQ 23.14 */ + CAPTURE_4_IRQn = 151, /*!< 151 CAPTURE_4, GIRQ 23.15 */ + CAPTURE_5_IRQn = 152, /*!< 152 CAPTURE_5, GIRQ 23.16 */ + COMPARE_0_IRQn = 153, /*!< 153 COMPARE_0, GIRQ 23.17 */ + COMPARE_1_IRQn = 154, /*!< 154 COMPARE_1, GIRQ 23.18 */ + EEPROM_IRQn = 155, /*!< 155 EEPROM, GIRQ 18.13 */ + VWIRE_ENABLE_IRQn = 156, /*!< 156 VWIRE_ENABLE, GIRQ 19.8 */ + MAX_IRQn +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + +/* ================================================================================ */ +/* ================ Custom Defines (added manually) ================ */ +/* ================================================================================ */ + +/* Register Union */ +typedef union +{ + uint32_t w; + uint16_t h[2]; + uint8_t b[4]; +} REG32_U; + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ PCR ================ */ +/* ================================================================================ */ + + +/** + * @brief The Power, Clocks, and Resets (PCR) Section identifies all the power supplies, + clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR) + */ + +typedef struct { /*!< (@ 0x40080100) PCR Structure */ + + union { + __IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control */ + + struct { + __IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode */ + uint32_t : 1; + __IO uint32_t TEST : 1; /*!< [2..2] Test bit */ + __IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode */ + } SYS_SLP_CNTRL_b; /*!< [4] BitSize */ + }; + + union { + __IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Register [7:0] Processor + Clock Divide Value (PROC_DIV) + 1: divide 48 MHz Ring Oscillator by 1. + 2: divide 48 MHz Ring Oscillator by 2. + 3: divide 48 MHz Ring Oscillator by 3. + 4: divide 48 MHz Ring Oscillator by 4. + 16: divide 48 MHz Ring Oscillator by 16. + 48: divide 48 MHz Ring Oscillator by 48. + No other values are supported. */ + + struct { + __IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate */ + } PROC_CLK_CNTRL_b; /*!< [8] BitSize */ + }; + + union { + __IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock domain */ + + struct { + __IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Clock off */ + } SLOW_CLK_CNTRL_b; /*!< [10] BitSize */ + }; + + union { + __IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register */ + + struct { + __IO uint32_t TEST : 8; /*!< [0..7] Test bits */ + __IO uint32_t PLL_LOCK : 1; /*!< [8..8] PLL Lock Status */ + } OSC_ID_b; /*!< [9] BitSize */ + }; + + union { + __IO uint32_t PCR_PWR_RST_STS; /*!< (@ 0x40080110) PCR Power Reset Status Register */ + + struct { + uint32_t : 2; + __I uint32_t VCC_PWRGD_STATUS: 1; /*!< [2..2] Indicates the status of VCC_PWRGD. 0 = PWRGD not asserted. + 1 = PWRGD asserte. */ + __I uint32_t RESET_HOST_STATUS: 1; /*!< [3..3] Indicates the status of RESET_VCC. 0 = reset active. + 1 = reset not active. */ + uint32_t : 1; + __IO uint32_t VBAT_RESET_STATUS: 1; /*!< [5..5] VBAT reset status 0 = No reset occurred while VTR was + off or since the last time this bit was cleared. 1 = A reset + occurred.(R/WC) */ + __IO uint32_t VTR_RESET_STATUS: 1; /*!< [6..6] Indicates the status of VTR_RESET.(R/WC) + 0 = No reset occurred since the last time this bit was cleared. + 1 = A reset occurred. */ + __IO uint32_t JTAG_RESET_STATUS: 1; /*!< [7..7] Indicates s RESET_SYS was triggered by a JTAG action.(R/WC) + 0 = No JTAG reset occurred since the last time this bit was + cleared. + 1 = A reset occurred because of a JATAG command. */ + uint32_t : 2; + __I uint32_t _32K_ACTIVE: 1; /*!< [10..10] 32K_ACTIVE (32K_ACTIVE) */ + __I uint32_t PCICLK_ACTIVE: 1; /*!< [11..11] PCICLK_ACTIVE (PCICLK_ACTIVE) */ + __I uint32_t ESPI_CLK_ACTIVE: 1; /*!< [12..12] ESPI_CLK_ACTIVE */ + } PCR_PWR_RST_STS_b; /*!< [13] BitSize */ + }; + + union { + __IO uint32_t PWR_RST_CNTRL; /*!< (@ 0x40080114) Power Reset Control Register */ + + struct { + __IO uint32_t PWR_INV : 1; /*!< [0..0] Used by FW to control internal RESET_VCC signal function + and external PWROK pin. This bit is read-only when VCC_PWRGD + is de-asserted low. */ + uint32_t : 7; + __IO uint32_t HOST_RESET_SELECT: 1; /*!< [8..8] Determines what generates the internal platform reset + signal. 1=LRESET# pin; 0=eSPI PLTRST# VWire */ + } PWR_RST_CNTRL_b; /*!< [9] BitSize */ + }; + + union { + __IO uint32_t SYS_RST; /*!< (@ 0x40080118) System Reset Register */ + + struct { + uint32_t : 8; + __IO uint32_t SOFT_SYS_RESET: 1; /*!< [8..8] A write of a 1 forces an assertion of the RESET_SYS reset + signal, resetting the device. A write of 0 has no effect. */ + } SYS_RST_b; /*!< [9] BitSize */ + }; + __I uint32_t RESERVED[5]; + + union { + __IO uint32_t SLP_EN_0; /*!< (@ 0x40080130) Sleep Enable 0 Register */ + + struct { + __IO uint32_t JTAG_STAP_SLP_EN: 1; /*!< [0..0] JTAG STAP Enable */ + __IO uint32_t EFUSE_SLP_EN: 1; /*!< [1..1] eFuse Enable */ + __IO uint32_t ISPI_SLP_EN: 1; /*!< [2..2] ISPI Enable */ + } SLP_EN_0_b; /*!< [3] BitSize */ + }; + + union { + __IO uint32_t SLP_EN_1; /*!< (@ 0x40080134) Sleep Enable 1 Register */ + + struct { + __IO uint32_t INT_SLP_EN : 1; /*!< [0..0] Interrupt Sleep Enable */ + __IO uint32_t PECI_SLP_EN: 1; /*!< [1..1] PECI Sleep Enable */ + __IO uint32_t TACH0_SLP_EN: 1; /*!< [2..2] TACH0 Sleep Enable (TACH0_SLP_EN) */ + uint32_t : 1; + __IO uint32_t PWM0_SLP_EN: 1; /*!< [4..4] PWM0 Sleep Enable (PWM0_SLP_EN) */ + __IO uint32_t PMC_SLP_EN : 1; /*!< [5..5] PMC Sleep Enable (PMC_SLP_EN) */ + __IO uint32_t DMA_SLP_EN : 1; /*!< [6..6] DMA Sleep Enable (DMA_SLP_EN) */ + __IO uint32_t TFDP_SLP_EN: 1; /*!< [7..7] TFDP Sleep Enable (TFDP_SLP_EN) */ + __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< [8..8] PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */ + __IO uint32_t WDT_SLP_EN : 1; /*!< [9..9] WDT Sleep Enable (WDT_SLP_EN) */ + __IO uint32_t SMB0_SLP_EN: 1; /*!< [10..10] SMB0 Sleep Enable (SMB0_SLP_EN) */ + __IO uint32_t TACH1_SLP_EN: 1; /*!< [11..11] TACH1 Sleep Enable (TACH1_SLP_EN) */ + __IO uint32_t TACH2_SLP_EN: 1; /*!< [12..12] TACH2 Sleep Enable (TACH2_SLP_EN) */ + uint32_t : 7; + __IO uint32_t PWM1_SLP_EN: 1; /*!< [20..20] PWM1 Sleep Enable (PWM1_SLP_EN) */ + __IO uint32_t PWM2_SLP_EN: 1; /*!< [21..21] PWM2 Sleep Enable (PWM2_SLP_EN) */ + __IO uint32_t PWM3_SLP_EN: 1; /*!< [22..22] PWM3 Sleep Enable (PWM3_SLP_EN) */ + __IO uint32_t PWM4_SLP_EN: 1; /*!< [23..23] PWM4 Sleep Enable (PWM4_SLP_EN) */ + __IO uint32_t PWM5_SLP_EN: 1; /*!< [24..24] PWM3 Sleep Enable (PWM5_SLP_EN) */ + __IO uint32_t PWM6_SLP_EN: 1; /*!< [25..25] PWM3 Sleep Enable (PWM6_SLP_EN) */ + __IO uint32_t PWM7_SLP_EN: 1; /*!< [26..26] PWM3 Sleep Enable (PWM7_SLP_EN) */ + __IO uint32_t PWM8_SLP_EN: 1; /*!< [27..27] PWM3 Sleep Enable (PWM8_SLP_EN) */ + uint32_t : 1; + __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< [29..29] EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */ + __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< [30..30] TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */ + __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< [31..31] TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */ + } SLP_EN_1_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t SLP_EN_2; /*!< (@ 0x40080138) Sleep Enable 2 Register */ + + struct { + __IO uint32_t LPC_SLP_EN : 1; /*!< [0..0] LPC Sleep Enable (LPC_SLP_EN) */ + __IO uint32_t UART_0_SLP_EN: 1; /*!< [1..1] UART 0 Sleep Enable */ + __IO uint32_t UART_1_SLP_EN: 1; /*!< [2..2] UART 1 Sleep Enable */ + uint32_t : 9; + __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_SLP_EN) */ + __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< [13..13] ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */ + __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< [14..14] ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */ + __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< [15..15] ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */ + __IO uint32_t KBCEM_SLP_EN: 1; /*!< [16..16] 8042EM Sleep Enable (8042EM_SLP_EN) */ + __IO uint32_t MBX_SLP_EN : 1; /*!< [17..17] Mailbox Sleep Enable (8042EM_SLP_EN) */ + __IO uint32_t RTC_SLP_EN : 1; /*!< [18..18] RTC Sleep Enable (RTC_SLP_EN) */ + __IO uint32_t ESPI_SLP_EN: 1; /*!< [19..19] eSPI Sleep Enable */ + uint32_t : 1; + __IO uint32_t ACPI_EC_2_SLP_EN: 1; /*!< [21..21] ACPI EC 2 Sleep Enable (ACPI_EC_2_SLP_EN) */ + __IO uint32_t ACPI_EC_3_SLP_EN: 1; /*!< [22..22] ACPI EC 3 Sleep Enable (ACPI_EC_3_SLP_EN) */ + __IO uint32_t ACPI_EC_4_SLP_EN: 1; /*!< [23..23] ACPI EC 4 Sleep Enable (ACPI_EC_4_SLP_EN) */ + __IO uint32_t ASIF_SLP_EN: 1; /*!< [24..24] ASIF Sleep Enable */ + __IO uint32_t PORT80_0_SLP_EN: 1; /*!< [25..25] Port 80 0 Sleep Enable */ + __IO uint32_t PORT80_1_SLP_EN: 1; /*!< [26..26] Port 80 1 Sleep Enable */ + } SLP_EN_2_b; /*!< [27] BitSize */ + }; + + union { + __IO uint32_t SLP_EN_3; /*!< (@ 0x4008013C) Sleep Enable 3 Register */ + + struct { + uint32_t : 3; + __IO uint32_t ADC_SLP_EN : 1; /*!< [3..3] ADC Sleep Enable (ADC_SLP_EN) */ + uint32_t : 1; + __IO uint32_t PS2_0_SLP_EN: 1; /*!< [5..5] PS2_0 Sleep Enable (PS2_0_SLP_EN) */ + __IO uint32_t PS2_1_SLP_EN: 1; /*!< [6..6] PS2_1 Sleep Enable (PS2_1_SLP_EN) */ + __IO uint32_t PS2_2_SLP_EN: 1; /*!< [7..7] PS2_2 Sleep Enable (PS2_2_SLP_EN) */ + uint32_t : 1; + __IO uint32_t GP_SPI0_SLP_EN: 1; /*!< [9..9] GP SPI0 Sleep Enable (GP_SPI0_SLP_EN) */ + __IO uint32_t HTIMER_0_SLP_EN: 1; /*!< [10..10] HTIMER 0 Sleep Enable (HTIMER_0_SLP_EN) */ + __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< [11..11] KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */ + __IO uint32_t RPMPWM_SLP_EN: 1; /*!< [12..12] RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */ + __IO uint32_t SMB1_SLP_EN: 1; /*!< [13..13] SMB1 Sleep Enable (SMB1_SLP_EN) */ + __IO uint32_t SMB2_SLP_EN: 1; /*!< [14..14] SMB2 Sleep Enable (SMB2_SLP_EN) */ + __IO uint32_t SMB3_SLP_EN: 1; /*!< [15..15] SMB3 Sleep Enable (SMB3_SLP_EN) */ + __IO uint32_t LED0_SLP_EN: 1; /*!< [16..16] LED0 Sleep Enable (LED0_SLP_EN) */ + __IO uint32_t LED1_SLP_EN: 1; /*!< [17..17] LED1 Sleep Enable (LED1_SLP_EN) */ + __IO uint32_t LED2_SLP_EN: 1; /*!< [18..18] LED2 Sleep Enable (LED2_SLP_EN) */ + __IO uint32_t BCM0_SLP_EN: 1; /*!< [19..19] BCM 0 Sleep Enable (BCM0_SLP_EN) */ + __IO uint32_t GP_SPI1_SLP_EN: 1; /*!< [20..20] GP SPI1 Sleep Enable (GP_SPI1_SLP_EN) */ + __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< [21..21] TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */ + __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< [22..22] TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */ + __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< [23..23] TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */ + __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< [24..24] TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */ + __IO uint32_t LED3_SLP_EN: 1; /*!< [25..25] LED3 Sleep Enable (LED3_SLP_EN) */ + __IO uint32_t PKE_SLP_EN : 1; /*!< [26..26] PKE Sleep Enable */ + __IO uint32_t RNG_SLP_EN : 1; /*!< [27..27] RNG Sleep Enable */ + __IO uint32_t AES_HASH_SLP_EN: 1; /*!< [28..28] AES_HASH Sleep Enable */ + __IO uint32_t HTIMER_1_SLP_EN: 1; /*!< [29..29] HTIMER 1 Sleep Enable (HTIMER_1_SLP_EN) */ + __IO uint32_t CCTIMER_SLP_EN: 1; /*!< [30..30] Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN) + */ + __IO uint32_t PWM9_SLP_EN: 1; /*!< [31..31] PWM9 Sleep Enable (PWM9_SLP_EN) */ + } SLP_EN_3_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t SLP_EN_4; /*!< (@ 0x40080140) Sleep Enable 4 Register */ + + struct { + __IO uint32_t PWM10_SLP_EN: 1; /*!< [0..0] PWM10 Sleep Enable (PWM10_SLP_EN) */ + __IO uint32_t PWM11_SLP_EN: 1; /*!< [1..1] PWM11 Sleep Enable (PWM11_SLP_EN) */ + __IO uint32_t CNT_TMER0_SLP_EN: 1; /*!< [2..2] CNT_TMER0 Sleep Enable (CNT_TMER0_SLP_EN) */ + __IO uint32_t CNT_TMER1_SLP_EN: 1; /*!< [3..3] CNT_TMER1 Sleep Enable (CNT_TMER1_SLP_EN) */ + __IO uint32_t CNT_TMER2_SLP_EN: 1; /*!< [4..4] CNT_TMER2 Sleep Enable (CNT_TMER2_SLP_EN) */ + __IO uint32_t CNT_TMER3_SLP_EN: 1; /*!< [5..5] CNT_TMER3 Sleep Enable (CNT_TMER3_SLP_EN) */ + __IO uint32_t RTOS_SLP_EN: 1; /*!< [6..6] PWM6 Sleep Enable (RTOS_SLP_EN) */ + __IO uint32_t RPMPWM1_SLP_EN: 1; /*!< [7..7] RPMPWM 1 Sleep Enable (RPMPWM1_SLP_EN) */ + __IO uint32_t QSPI_SLP_EN: 1; /*!< [8..8] Quad SPI Sleep Enable */ + __IO uint32_t BCM1_SLP_EN: 1; /*!< [9..9] BCM 1 Sleep Enable (BCM1_SLP_EN) */ + __IO uint32_t RC_ID0_SLP_EN: 1; /*!< [10..10] RC_ID0 Sleep Enable (RC_ID0_SLP_EN) */ + __IO uint32_t RC_ID1_SLP_EN: 1; /*!< [11..11] RC_ID1 Sleep Enable (RC_ID1_SLP_EN) */ + __IO uint32_t RC_ID2_SLP_EN: 1; /*!< [12..12] RC_ID2 Sleep Enable (RC_ID2_SLP_EN) */ + uint32_t : 2; + __IO uint32_t FCL_SLP_EN : 1; /*!< [15..15] FCL Sleep Enable (FCL_SLP_EN) */ + } SLP_EN_4_b; /*!< [16] BitSize */ + }; + __I uint32_t RESERVED1[3]; + + union { + __IO uint32_t CLK_REQ_0; /*!< (@ 0x40080150) Clock Required 0 Register */ + + struct { + __IO uint32_t JTAG_STAP_CLK_REQ: 1; /*!< [0..0] JTAG STAP Enable */ + __IO uint32_t EFUSE_CLK_REQ: 1; /*!< [1..1] eFuse Enable */ + __IO uint32_t ISPI_CLK_REQ: 1; /*!< [2..2] ISPI Clock Required */ + } CLK_REQ_0_b; /*!< [3] BitSize */ + }; + + union { + __IO uint32_t CLK_REQ_1; /*!< (@ 0x40080154) Clock Required 1 Register */ + + struct { + __IO uint32_t INT_CLK_REQ: 1; /*!< [0..0] Interrupt Clock Required */ + __IO uint32_t PECI_CLK_REQ: 1; /*!< [1..1] PECI Clock Required */ + __IO uint32_t TACH0_CLK_REQ: 1; /*!< [2..2] TACH0 Clock Required (TACH0_CLK_REQ) */ + uint32_t : 1; + __IO uint32_t PWM0_CLK_REQ: 1; /*!< [4..4] PWM0 Clock Required (PWM0_CLK_REQ) */ + __IO uint32_t PMC_CLK_REQ: 1; /*!< [5..5] PMC Clock Required (PMC_CLK_REQ) */ + __IO uint32_t DMA_CLK_REQ: 1; /*!< [6..6] DMA Clock Required (DMA_CLK_REQ) */ + __IO uint32_t TFDP_CLK_REQ: 1; /*!< [7..7] TFDP Clock Required (TFDP_CLK_REQ) */ + __IO uint32_t PROCESSOR_CLK_REQ: 1; /*!< [8..8] PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */ + __IO uint32_t WDT_CLK_REQ: 1; /*!< [9..9] WDT Clock Required (WDT_CLK_REQ) */ + __IO uint32_t SMB0_CLK_REQ: 1; /*!< [10..10] SMB0 Clock Required (SMB0_CLK_REQ) */ + __IO uint32_t TACH1_CLK_REQ: 1; /*!< [11..11] TACH1 Clock Required (TACH1_CLK_REQ) */ + __IO uint32_t TACH2_CLK_REQ: 1; /*!< [12..12] TACH2 Clock Required (TACH2_CLK_REQ) */ + uint32_t : 7; + __IO uint32_t PWM1_CLK_REQ: 1; /*!< [20..20] PWM1 Clock Required (PWM1_CLK_REQ) */ + __IO uint32_t PWM2_CLK_REQ: 1; /*!< [21..21] PWM2 Clock Required (PWM2_CLK_REQ) */ + __IO uint32_t PWM3_CLK_REQ: 1; /*!< [22..22] PWM3 Clock Required (PWM3_CLK_REQ) */ + __IO uint32_t PWM4_CLK_REQ: 1; /*!< [23..23] PWM4 Clock Required (PWM4_CLK_REQ) */ + __IO uint32_t PWM5_CLK_REQ: 1; /*!< [24..24] PWM3 Clock Required (PWM5_CLK_REQ) */ + __IO uint32_t PWM6_CLK_REQ: 1; /*!< [25..25] PWM3 Clock Required (PWM6_CLK_REQ) */ + __IO uint32_t PWM7_CLK_REQ: 1; /*!< [26..26] PWM3 Clock Required (PWM7_CLK_REQ) */ + __IO uint32_t PWM8_CLK_REQ: 1; /*!< [27..27] PWM3 Clock Required (PWM8_CLK_REQ) */ + uint32_t : 1; + __IO uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< [29..29] EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */ + __IO uint32_t TIMER16_0_CLK_REQ: 1; /*!< [30..30] TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */ + __IO uint32_t TIMER16_1_CLK_REQ: 1; /*!< [31..31] TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */ + } CLK_REQ_1_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t CLK_REQ_2; /*!< (@ 0x40080158) Clock Required 2 Register */ + + struct { + __IO uint32_t LPC_CLK_REQ: 1; /*!< [0..0] LPC Clock Required (LPC_CLK_REQ) */ + __IO uint32_t UART_0_CLK_REQ: 1; /*!< [1..1] UART 0 Clock Required */ + __IO uint32_t UART_1_CLK_REQ: 1; /*!< [2..2] UART 1 Clock Required */ + uint32_t : 9; + __IO uint32_t GLBL_CFG_CLK_REQ: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_CLK_REQ) */ + __IO uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< [13..13] ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */ + __IO uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< [14..14] ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */ + __IO uint32_t ACPI_PM1_CLK_REQ: 1; /*!< [15..15] ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */ + __IO uint32_t KBCEM_CLK_REQ: 1; /*!< [16..16] 8042EM Clock Required (8042EM_CLK_REQ) */ + __IO uint32_t MBX_CLK_REQ: 1; /*!< [17..17] Mailbox Clock Required (8042EM_CLK_REQ) */ + __IO uint32_t RTC_CLK_REQ: 1; /*!< [18..18] RTC Clock Required (RTC_CLK_REQ) */ + __IO uint32_t ESPI_CLK_REQ: 1; /*!< [19..19] eSPI Clock Required */ + uint32_t : 1; + __IO uint32_t ACPI_EC_2_CLK_REQ: 1; /*!< [21..21] ACPI EC 2 Clock Required (ACPI_EC_2_CLK_REQ) */ + __IO uint32_t ACPI_EC_3_CLK_REQ: 1; /*!< [22..22] ACPI EC 3 Clock Required (ACPI_EC_3_CLK_REQ) */ + __IO uint32_t ACPI_EC_4_CLK_REQ: 1; /*!< [23..23] ACPI EC 4 Clock Required (ACPI_EC_4_CLK_REQ) */ + __IO uint32_t ASIF_CLK_REQ: 1; /*!< [24..24] ASIF Clock Required */ + __IO uint32_t PORT80_0_CLK_REQ: 1; /*!< [25..25] Port 80 0 Clock Required */ + __IO uint32_t PORT80_1_CLK_REQ: 1; /*!< [26..26] Port 80 1 Clock Required */ + } CLK_REQ_2_b; /*!< [27] BitSize */ + }; + + union { + __IO uint32_t CLK_REQ_3; /*!< (@ 0x4008015C) Clock Required 3 Register */ + + struct { + uint32_t : 3; + __IO uint32_t ADC_CLK_REQ: 1; /*!< [3..3] ADC Clock Required (ADC_CLK_REQ) */ + uint32_t : 1; + __IO uint32_t PS2_0_CLK_REQ: 1; /*!< [5..5] PS2_0 Clock Required (PS2_0_CLK_REQ) */ + __IO uint32_t PS2_1_CLK_REQ: 1; /*!< [6..6] PS2_1 Clock Required (PS2_1_CLK_REQ) */ + __IO uint32_t PS2_2_CLK_REQ: 1; /*!< [7..7] PS2_2 Clock Required (PS2_2_CLK_REQ) */ + uint32_t : 1; + __IO uint32_t GP_SPI0_CLK_REQ: 1; /*!< [9..9] GP SPI0 Clock Required (GP_SPI0_CLK_REQ) */ + __IO uint32_t HTIMER_0_CLK_REQ: 1; /*!< [10..10] HTIMER 0 Clock Required (HTIMER_0_CLK_REQ) */ + __IO uint32_t KEYSCAN_CLK_REQ: 1; /*!< [11..11] KEYSCAN Clock Required (KEYSCAN_CLK_REQ) */ + __IO uint32_t RPMPWM0_CLK_REQ: 1; /*!< [12..12] RPM-PWM 0 Clock Required (RPMPWM0_CLK_REQ) */ + __IO uint32_t SMB1_CLK_REQ: 1; /*!< [13..13] SMB1 Clock Required (SMB1_CLK_REQ) */ + __IO uint32_t SMB2_CLK_REQ: 1; /*!< [14..14] SMB2 Clock Required (SMB2_CLK_REQ) */ + __IO uint32_t SMB3_CLK_REQ: 1; /*!< [15..15] SMB3 Clock Required (SMB3_CLK_REQ) */ + __IO uint32_t LED0_CLK_REQ: 1; /*!< [16..16] LED0 Clock Required (LED0_CLK_REQ) */ + __IO uint32_t LED1_CLK_REQ: 1; /*!< [17..17] LED1 Clock Required (LED1_CLK_REQ) */ + __IO uint32_t LED2_CLK_REQ: 1; /*!< [18..18] LED2 Clock Required (LED2_CLK_REQ) */ + __IO uint32_t BCM0_CLK_REQ: 1; /*!< [19..19] BCM 0 Clock Required (BCM0_CLK_REQ) */ + __IO uint32_t GP_SPI1_CLK_REQ: 1; /*!< [20..20] GP SPI1 Clock Required (GP_SPI1_CLK_REQ) */ + __IO uint32_t TIMER16_2_CLK_REQ: 1; /*!< [21..21] TIMER16_2_Clock Required (TIMER16_2_CLK_REQ) */ + __IO uint32_t TIMER16_3_CLK_REQ: 1; /*!< [22..22] TIMER16_3 Clock Required (TIMER16_3_CLK_REQ) */ + __IO uint32_t TIMER32_0_CLK_REQ: 1; /*!< [23..23] TIMER32_0 Clock Required (TIMER32_0_CLK_REQ) */ + __IO uint32_t TIMER32_1_CLK_REQ: 1; /*!< [24..24] TIMER32_1 Clock Required (TIMER32_1_CLK_REQ) */ + __IO uint32_t LED3_CLK_REQ: 1; /*!< [25..25] LED3 Clock Required (LED3_CLK_REQ) */ + __IO uint32_t PKE_CLK_REQ: 1; /*!< [26..26] PKE Clock Required */ + __IO uint32_t RNG_CLK_REQ: 1; /*!< [27..27] RNG Clock Required */ + __IO uint32_t AES_HASH_CLK_REQ: 1; /*!< [28..28] AES_HASH Clock Required */ + __IO uint32_t HTIMER_1_CLK_REQ: 1; /*!< [29..29] HTIMER 1 Clock Required (HTIMER_1_CLK_REQ) */ + __IO uint32_t CCTIMER_CLK_REQ: 1; /*!< [30..30] Capture Compare Timer Clock Required (CCTIMER_CLK_REQ) + */ + __IO uint32_t PWM9_CLK_REQ: 1; /*!< [31..31] PWM9 Clock Required (PWM9_CLK_REQ) */ + } CLK_REQ_3_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t CLK_REQ_4; /*!< (@ 0x40080160) Clock Required 4 Register */ + + struct { + __IO uint32_t PWM10_CLK_REQ: 1; /*!< [0..0] PWM10 Clock Required (PWM10_CLK_REQ) */ + __IO uint32_t PWM11_CLK_REQ: 1; /*!< [1..1] PWM11 Clock Required (PWM11_CLK_REQ) */ + __IO uint32_t CNT_TMER0_CLK_REQ: 1; /*!< [2..2] CNT_TMER0 Clock Required (CNT_TMER0_CLK_REQ) */ + __IO uint32_t CNT_TMER1_CLK_REQ: 1; /*!< [3..3] CNT_TMER1 Clock Required (CNT_TMER1_CLK_REQ) */ + __IO uint32_t CNT_TMER2_CLK_REQ: 1; /*!< [4..4] CNT_TMER2 Clock Required (CNT_TMER2_CLK_REQ) */ + __IO uint32_t CNT_TMER3_CLK_REQ: 1; /*!< [5..5] CNT_TMER3 Clock Required (CNT_TMER3_CLK_REQ) */ + __IO uint32_t RTOS_CLK_REQ: 1; /*!< [6..6] RTOS Clock Required (RTOS_CLK_REQ) */ + __IO uint32_t RPMPWM1_CLK_REQ: 1; /*!< [7..7] RPM-PWM1 Clock Required (RPMPWM1_CLK_REQ) */ + __IO uint32_t QSPI_CLK_REQ: 1; /*!< [8..8] Quad SPI Clock Required */ + __IO uint32_t BCM1_CLK_REQ: 1; /*!< [9..9] BCM 1 Clock Required (BCM1_CLK_REQ) */ + __IO uint32_t RC_ID0_CLK_REQ: 1; /*!< [10..10] RC_ID0 Clock Required (RC_ID0_CLK_REQ) */ + __IO uint32_t RC_ID1_CLK_REQ: 1; /*!< [11..11] RC_ID1 Clock Required (RC_ID1_CLK_REQ) */ + __IO uint32_t RC_ID2_CLK_REQ: 1; /*!< [12..12] RC_ID2 Clock Required (RC_ID2_CLK_REQ) */ + uint32_t : 2; + __IO uint32_t FCL_CLK_REQ: 1; /*!< [15..15] FCL Clock Required (FCL_CLK_REQ) */ + } CLK_REQ_4_b; /*!< [16] BitSize */ + }; + __I uint32_t RESERVED2[3]; + + union { + __IO uint32_t RST_EN_0; /*!< (@ 0x40080170) Reset Enable 0 Register */ + + struct { + __IO uint32_t JTAG_STAP_RST_EN: 1; /*!< [0..0] JTAG STAP Reset Enable */ + __IO uint32_t EFUSE_RST_EN: 1; /*!< [1..1] eFuse Reset Enable */ + __IO uint32_t ISPI_RST_EN: 1; /*!< [2..2] ISPI Reset Enable */ + } RST_EN_0_b; /*!< [3] BitSize */ + }; + + union { + __IO uint32_t RST_EN_1; /*!< (@ 0x40080174) Reset Enable 1 Register */ + + struct { + __IO uint32_t INT_RST_EN : 1; /*!< [0..0] Interrupt Reset Enable */ + __IO uint32_t PECI_RST_EN: 1; /*!< [1..1] PECI Reset Enable */ + __IO uint32_t TACH0_RST_EN: 1; /*!< [2..2] TACH0 Reset Enable (TACH0_RST_EN) */ + uint32_t : 1; + __IO uint32_t PWM0_RST_EN: 1; /*!< [4..4] PWM0 Reset Enable (PWM0_RST_EN) */ + __IO uint32_t PMC_RST_EN : 1; /*!< [5..5] PMC Reset Enable (PMC_RST_EN) */ + __IO uint32_t DMA_RST_EN : 1; /*!< [6..6] DMA Reset Enable (DMA_RST_EN) */ + __IO uint32_t TFDP_RST_EN: 1; /*!< [7..7] TFDP Reset Enable (TFDP_RST_EN) */ + __IO uint32_t PROCESSOR_RST_EN: 1; /*!< [8..8] PROCESSOR Reset Enable (PROCESSOR_RST_EN) */ + __IO uint32_t WDT_RST_EN : 1; /*!< [9..9] WDT Reset Enable (WDT_RST_EN) */ + __IO uint32_t SMB0_RST_EN: 1; /*!< [10..10] SMB0 Reset Enable (SMB0_RST_EN) */ + __IO uint32_t TACH1_RST_EN: 1; /*!< [11..11] TACH1 Reset Enable (TACH1_RST_EN) */ + __IO uint32_t TACH2_RST_EN: 1; /*!< [12..12] TACH2 Reset Enable (TACH2_RST_EN) */ + uint32_t : 7; + __IO uint32_t PWM1_RST_EN: 1; /*!< [20..20] PWM1 Reset Enable (PWM1_RST_EN) */ + __IO uint32_t PWM2_RST_EN: 1; /*!< [21..21] PWM2 Reset Enable (PWM2_RST_EN) */ + __IO uint32_t PWM3_RST_EN: 1; /*!< [22..22] PWM3 Reset Enable (PWM3_RST_EN) */ + __IO uint32_t PWM4_RST_EN: 1; /*!< [23..23] PWM4 Reset Enable (PWM4_RST_EN) */ + __IO uint32_t PWM5_RST_EN: 1; /*!< [24..24] PWM3 Reset Enable (PWM5_RST_EN) */ + __IO uint32_t PWM6_RST_EN: 1; /*!< [25..25] PWM3 Reset Enable (PWM6_RST_EN) */ + __IO uint32_t PWM7_RST_EN: 1; /*!< [26..26] PWM3 Reset Enable (PWM7_RST_EN) */ + __IO uint32_t PWM8_RST_EN: 1; /*!< [27..27] PWM3 Reset Enable (PWM8_RST_EN) */ + uint32_t : 1; + __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< [29..29] EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */ + __IO uint32_t TIMER16_0_RST_EN: 1; /*!< [30..30] TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */ + __IO uint32_t TIMER16_1_RST_EN: 1; /*!< [31..31] TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */ + } RST_EN_1_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t RST_EN_2; /*!< (@ 0x40080178) Reset Enable 2 Register */ + + struct { + __IO uint32_t LPC_RST_EN : 1; /*!< [0..0] LPC Reset Enable (LPC_RST_EN) */ + __IO uint32_t UART_0_RST_EN: 1; /*!< [1..1] UART 0 Reset Enable */ + __IO uint32_t UART_1_RST_EN: 1; /*!< [2..2] UART 1 Reset Enable */ + uint32_t : 9; + __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_RST_EN) */ + __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< [13..13] ACPI EC 0 Reset Enable (ACPI_EC_0_RST_EN) */ + __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< [14..14] ACPI EC 1 Reset Enable (ACPI_EC_1_RST_EN) */ + __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< [15..15] ACPI PM1 Reset Enable (ACPI_PM1_RST_EN) */ + __IO uint32_t KBCEM_RST_EN: 1; /*!< [16..16] 8042EM Reset Enable (8042EM_RST_EN) */ + __IO uint32_t MBX_RST_EN : 1; /*!< [17..17] Mailbox Reset Enable (8042EM_RST_EN) */ + __IO uint32_t RTC_RST_EN : 1; /*!< [18..18] RTC Reset Enable (RTC_RST_EN) */ + __IO uint32_t ESPI_RST_EN: 1; /*!< [19..19] eSPI Reset Enable */ + uint32_t : 1; + __IO uint32_t ACPI_EC_2_RST_EN: 1; /*!< [21..21] ACPI EC 2 Reset Enable (ACPI_EC_2_RST_EN) */ + __IO uint32_t ACPI_EC_3_RST_EN: 1; /*!< [22..22] ACPI EC 3 Reset Enable (ACPI_EC_3_RST_EN) */ + __IO uint32_t ACPI_EC_4_RST_EN: 1; /*!< [23..23] ACPI EC 4 Reset Enable (ACPI_EC_4_RST_EN) */ + __IO uint32_t ASIF_RST_EN: 1; /*!< [24..24] ASIF Reset Enable */ + __IO uint32_t PORT80_0_RST_EN: 1; /*!< [25..25] Port 80 0 Reset Enable */ + __IO uint32_t PORT80_1_RST_EN: 1; /*!< [26..26] Port 80 1 Reset Enable */ + } RST_EN_2_b; /*!< [27] BitSize */ + }; + + union { + __IO uint32_t RST_EN_3; /*!< (@ 0x4008017C) Reset Enable 3 Register */ + + struct { + uint32_t : 3; + __IO uint32_t ADC_RST_EN : 1; /*!< [3..3] ADC Reset Enable (ADC_RST_EN) */ + uint32_t : 1; + __IO uint32_t PS2_0_RST_EN: 1; /*!< [5..5] PS2_0 Reset Enable (PS2_0_RST_EN) */ + __IO uint32_t PS2_1_RST_EN: 1; /*!< [6..6] PS2_1 Reset Enable (PS2_1_RST_EN) */ + __IO uint32_t PS2_2_RST_EN: 1; /*!< [7..7] PS2_2 Reset Enable (PS2_2_RST_EN) */ + uint32_t : 1; + __IO uint32_t GP_SPI0_RST_EN: 1; /*!< [9..9] GP SPI0 Reset Enable (GP_SPI0_RST_EN) */ + __IO uint32_t HTIMER_0_RST_EN: 1; /*!< [10..10] HTIMER 0 Reset Enable (HTIMER_0_RST_EN) */ + __IO uint32_t KEYSCAN_RST_EN: 1; /*!< [11..11] KEYSCAN Reset Enable (KEYSCAN_RST_EN) */ + __IO uint32_t RPMPWM0_RST_EN: 1; /*!< [12..12] RPM-PWM 0 Reset Enable (RPMPWM0_RST_EN) */ + __IO uint32_t SMB1_RST_EN: 1; /*!< [13..13] SMB1 Reset Enable (SMB1_RST_EN) */ + __IO uint32_t SMB2_RST_EN: 1; /*!< [14..14] SMB2 Reset Enable (SMB2_RST_EN) */ + __IO uint32_t SMB3_RST_EN: 1; /*!< [15..15] SMB3 Reset Enable (SMB3_RST_EN) */ + __IO uint32_t LED0_RST_EN: 1; /*!< [16..16] LED0 Reset Enable (LED0_RST_EN) */ + __IO uint32_t LED1_RST_EN: 1; /*!< [17..17] LED1 Reset Enable (LED1_RST_EN) */ + __IO uint32_t LED2_RST_EN: 1; /*!< [18..18] LED2 Reset Enable (LED2_RST_EN) */ + __IO uint32_t BCM0_RST_EN: 1; /*!< [19..19] BCM 0 Reset Enable (BCM0_RST_EN) */ + __IO uint32_t GP_SPI1_RST_EN: 1; /*!< [20..20] GP SPI1 Reset Enable (GP_SPI1_RST_EN) */ + __IO uint32_t TIMER16_2_RST_EN: 1; /*!< [21..21] TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */ + __IO uint32_t TIMER16_3_RST_EN: 1; /*!< [22..22] TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */ + __IO uint32_t TIMER32_0_RST_EN: 1; /*!< [23..23] TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */ + __IO uint32_t TIMER32_1_RST_EN: 1; /*!< [24..24] TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */ + __IO uint32_t LED3_RST_EN: 1; /*!< [25..25] LED3 Reset Enable (LED3_RST_EN) */ + __IO uint32_t PKE_RST_EN : 1; /*!< [26..26] PKE Reset Enable */ + __IO uint32_t RNG_RST_EN : 1; /*!< [27..27] RNG Reset Enable */ + __IO uint32_t AES_HASH_RST_EN: 1; /*!< [28..28] AES_HASH Reset Enable */ + __IO uint32_t HTIMER_1_RST_EN: 1; /*!< [29..29] HTIMER 1 Reset Enable (HTIMER_1_RST_EN) */ + __IO uint32_t CCTIMER_RST_EN: 1; /*!< [30..30] Capture Compare Timer Reset Enable (CCTIMER_RST_EN) + */ + __IO uint32_t PWM9_RST_EN: 1; /*!< [31..31] PWM9 Reset Enable (PWM9_RST_EN) */ + } RST_EN_3_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t RST_EN_4; /*!< (@ 0x40080180) Reset Enable 4 Register */ + + struct { + __IO uint32_t PWM10_RST_EN: 1; /*!< [0..0] PWM10 Reset Enable (PWM10_RST_EN) */ + __IO uint32_t PWM11_RST_EN: 1; /*!< [1..1] PWM11 Reset Enable (PWM11_RST_EN) */ + __IO uint32_t CNT_TMER0_RST_EN: 1; /*!< [2..2] CNT_TMER0 Reset Enable (CNT_TMER0_RST_EN) */ + __IO uint32_t CNT_TMER1_RST_EN: 1; /*!< [3..3] CNT_TMER1 Reset Enable (CNT_TMER1_RST_EN) */ + __IO uint32_t CNT_TMER2_RST_EN: 1; /*!< [4..4] CNT_TMER2 Reset Enable (CNT_TMER2_RST_EN) */ + __IO uint32_t CNT_TMER3_RST_EN: 1; /*!< [5..5] CNT_TMER3 Reset Enable (CNT_TMER3_RST_EN) */ + __IO uint32_t RTOS_RST_EN: 1; /*!< [6..6] RTOS Reset Enable (RTOS_RST_EN) */ + __IO uint32_t RPMPWM1_RST_EN: 1; /*!< [7..7] RPM-PWM1 Reset Enable (RPMPWM1_RST_EN) */ + __IO uint32_t QSPI_RST_EN: 1; /*!< [8..8] Quad SPI Reset Enable */ + __IO uint32_t BCM1_RST_EN: 1; /*!< [9..9] BCM 1 Reset Enable (BCM1_RST_EN) */ + __IO uint32_t RC_ID0_RST_EN: 1; /*!< [10..10] RC_ID0 Reset Enable (RC_ID0_RST_EN) */ + __IO uint32_t RC_ID1_RST_EN: 1; /*!< [11..11] RC_ID1 Reset Enable (RC_ID1_RST_EN) */ + __IO uint32_t RC_ID2_RST_EN: 1; /*!< [12..12] RC_ID2 Reset Enable (RC_ID2_RST_EN) */ + uint32_t : 2; + __IO uint32_t FCL_RST_EN : 1; /*!< [15..15] FCL Reset Enable (FCL_RST_EN) */ + } RST_EN_4_b; /*!< [16] BitSize */ + }; +} PCR_Type; + + +/* ================================================================================ */ +/* ================ INTS ================ */ +/* ================================================================================ */ + + +/** + * @brief The interrupt generation logic is made of 16 groups of signals, each of which + consist of a Status register, a Enable register and a Result register. The Status and Enable are + latched registers. The Result register is a bit by bit AND function of the Source and Enable registers. + All the bits of the Result register are OR'ed together and AND'ed with the corresponding bit in the Block + Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTS) + */ + +typedef struct { /*!< (@ 0x4000E000) INTS Structure */ + __IO uint32_t GIRQ08_SRC; /*!< (@ 0x4000E000) Status R/W1C */ + __IO uint32_t GIRQ08_EN_SET; /*!< (@ 0x4000E004) Write to set source enables */ + __I uint32_t GIRQ08_RESULT; /*!< (@ 0x4000E008) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ08_EN_CLR; /*!< (@ 0x4000E00C) Write to clear source enables */ + __I uint32_t RESERVED; + __IO uint32_t GIRQ09_SRC; /*!< (@ 0x4000E014) Status R/W1C */ + __IO uint32_t GIRQ09_EN_SET; /*!< (@ 0x4000E018) Write to set source enables */ + __I uint32_t GIRQ09_RESULT; /*!< (@ 0x4000E01C) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ09_EN_CLR; /*!< (@ 0x4000E020) Write to clear source enables */ + __I uint32_t RESERVED1; + __IO uint32_t GIRQ10_SRC; /*!< (@ 0x4000E028) Status R/W1C */ + __IO uint32_t GIRQ10_EN_SET; /*!< (@ 0x4000E02C) Write to set source enables */ + __I uint32_t GIRQ10_RESULT; /*!< (@ 0x4000E030) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ10_EN_CLR; /*!< (@ 0x4000E034) Write to clear source enables */ + __I uint32_t RESERVED2; + __IO uint32_t GIRQ11_SRC; /*!< (@ 0x4000E03C) Status R/W1C */ + __IO uint32_t GIRQ11_EN_SET; /*!< (@ 0x4000E040) Write to set source enables */ + __I uint32_t GIRQ11_RESULT; /*!< (@ 0x4000E044) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ11_EN_CLR; /*!< (@ 0x4000E048) Write to clear source enables */ + __I uint32_t RESERVED3; + __IO uint32_t GIRQ12_SRC; /*!< (@ 0x4000E050) Status R/W1C */ + __IO uint32_t GIRQ12_EN_SET; /*!< (@ 0x4000E054) Write to set source enables */ + __I uint32_t GIRQ12_RESULT; /*!< (@ 0x4000E058) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ12_EN_CLR; /*!< (@ 0x4000E05C) Write to clear source enables */ + __I uint32_t RESERVED4; + __IO uint32_t GIRQ13_SRC; /*!< (@ 0x4000E064) Status R/W1C */ + __IO uint32_t GIRQ13_EN_SET; /*!< (@ 0x4000E068) Write to set source enables */ + __I uint32_t GIRQ13_RESULT; /*!< (@ 0x4000E06C) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ13_EN_CLR; /*!< (@ 0x4000E070) Write to clear source enables */ + __I uint32_t RESERVED5; + __IO uint32_t GIRQ14_SRC; /*!< (@ 0x4000E078) Status R/W1C */ + __IO uint32_t GIRQ14_EN_SET; /*!< (@ 0x4000E07C) Write to set source enables */ + __I uint32_t GIRQ14_RESULT; /*!< (@ 0x4000E080) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ14_EN_CLR; /*!< (@ 0x4000E084) Write to clear source enables */ + __I uint32_t RESERVED6; + __IO uint32_t GIRQ15_SRC; /*!< (@ 0x4000E08C) Status R/W1C */ + __IO uint32_t GIRQ15_EN_SET; /*!< (@ 0x4000E090) Write to set source enables */ + __I uint32_t GIRQ15_RESULT; /*!< (@ 0x4000E094) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ15_EN_CLR; /*!< (@ 0x4000E098) Write to clear source enables */ + __I uint32_t RESERVED7; + __IO uint32_t GIRQ16_SRC; /*!< (@ 0x4000E0A0) Status R/W1C */ + __IO uint32_t GIRQ16_EN_SET; /*!< (@ 0x4000E0A4) Write to set source enables */ + __I uint32_t GIRQ16_RESULT; /*!< (@ 0x4000E0A8) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ16_EN_CLR; /*!< (@ 0x4000E0AC) Write to clear source enables */ + __I uint32_t RESERVED8; + __IO uint32_t GIRQ17_SRC; /*!< (@ 0x4000E0B4) Status R/W1C */ + __IO uint32_t GIRQ17_EN_SET; /*!< (@ 0x4000E0B8) Write to set source enables */ + __I uint32_t GIRQ17_RESULT; /*!< (@ 0x4000E0BC) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ17_EN_CLR; /*!< (@ 0x4000E0C0) Write to clear source enables */ + __I uint32_t RESERVED9; + __IO uint32_t GIRQ18_SRC; /*!< (@ 0x4000E0C8) Status R/W1C */ + __IO uint32_t GIRQ18_EN_SET; /*!< (@ 0x4000E0CC) Write to set source enables */ + __I uint32_t GIRQ18_RESULT; /*!< (@ 0x4000E0D0) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ18_EN_CLR; /*!< (@ 0x4000E0D4) Write to clear source enables */ + __I uint32_t RESERVED10; + __IO uint32_t GIRQ19_SRC; /*!< (@ 0x4000E0DC) Status R/W1C */ + __IO uint32_t GIRQ19_EN_SET; /*!< (@ 0x4000E0E0) Write to set source enables */ + __I uint32_t GIRQ19_RESULT; /*!< (@ 0x4000E0E4) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ19_EN_CLR; /*!< (@ 0x4000E0E8) Write to clear source enables */ + __I uint32_t RESERVED11; + __IO uint32_t GIRQ20_SRC; /*!< (@ 0x4000E0F0) Status R/W1C */ + __IO uint32_t GIRQ20_EN_SET; /*!< (@ 0x4000E0F4) Write to set source enables */ + __I uint32_t GIRQ20_RESULT; /*!< (@ 0x4000E0F8) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ20_EN_CLR; /*!< (@ 0x4000E0FC) Write to clear source enables */ + __I uint32_t RESERVED12; + __IO uint32_t GIRQ21_SRC; /*!< (@ 0x4000E104) Status R/W1C */ + __IO uint32_t GIRQ21_EN_SET; /*!< (@ 0x4000E108) Write to set source enables */ + __I uint32_t GIRQ21_RESULT; /*!< (@ 0x4000E10C) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ21_EN_CLR; /*!< (@ 0x4000E110) Write to clear source enables */ + __I uint32_t RESERVED13; + __IO uint32_t GIRQ22_SRC; /*!< (@ 0x4000E118) Status R/W1C */ + __IO uint32_t GIRQ22_EN_SET; /*!< (@ 0x4000E11C) Write to set source enables */ + __I uint32_t GIRQ22_RESULT; /*!< (@ 0x4000E120) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ22_EN_CLR; /*!< (@ 0x4000E124) Write to clear source enables */ + __I uint32_t RESERVED14; + __IO uint32_t GIRQ23_SRC; /*!< (@ 0x4000E12C) Status R/W1C */ + __IO uint32_t GIRQ23_EN_SET; /*!< (@ 0x4000E130) Write to set source enables */ + __I uint32_t GIRQ23_RESULT; /*!< (@ 0x4000E134) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ23_EN_CLR; /*!< (@ 0x4000E138) Write to clear source enables */ + __I uint32_t RESERVED15; + __IO uint32_t GIRQ24_SRC; /*!< (@ 0x4000E140) Status R/W1C */ + __IO uint32_t GIRQ24_EN_SET; /*!< (@ 0x4000E144) Write to set source enables */ + __I uint32_t GIRQ24_RESULT; /*!< (@ 0x4000E148) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ24_EN_CLR; /*!< (@ 0x4000E14C) Write to clear source enables */ + __I uint32_t RESERVED16; + __IO uint32_t GIRQ25_SRC; /*!< (@ 0x4000E154) Status R/W1C */ + __IO uint32_t GIRQ25_EN_SET; /*!< (@ 0x4000E158) Write to set source enables */ + __I uint32_t GIRQ25_RESULT; /*!< (@ 0x4000E15C) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ25_EN_CLR; /*!< (@ 0x4000E160) Write to clear source enables */ + __I uint32_t RESERVED17; + __IO uint32_t GIRQ26_SRC; /*!< (@ 0x4000E168) Status R/W1C */ + __IO uint32_t GIRQ26_EN_SET; /*!< (@ 0x4000E16C) Write to set source enables */ + __I uint32_t GIRQ26_RESULT; /*!< (@ 0x4000E170) Read-only bitwise OR of Source and Enable */ + __IO uint32_t GIRQ26_EN_CLR; /*!< (@ 0x4000E174) Write to clear source enables */ + __I uint32_t RESERVED18[34]; + + union { + __IO uint32_t BLOCK_ENABLE_SET; /*!< (@ 0x4000E200) Block Enable Set Register */ + + struct { + __IO uint32_t IRQ_VECTOR_ENABLE_SET: 31; /*!< [0..30] Each GIRQx bit can be individually enabled to assert + an interrupt event. + Reads always return the current value of the internal GIRQX_ENABLE + bit. The state of the GIRQX_ENABLE bit is determined by + the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_ + CLEAR bit. (0=disabled, 1=enabled) (R/WS) + 1=Interrupts in the GIRQx Source Register may be enabled + 0=No effect. */ + } BLOCK_ENABLE_SET_b; /*!< [31] BitSize */ + }; + + union { + __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< (@ 0x4000E204) Block Enable Clear Register. */ + + struct { + __IO uint32_t IRQ_VECTOR_ENABLE_CLEAR: 31; /*!< [0..30] Each GIRQx bit can be individually disabled to inhibit + an interrupt event. + Reads always return the current value of the internal GIRQX_ENABLE + bit. The state of the GIRQX_ENABLE bit is determined by + the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_ + CLEAR bit. (0=disabled, 1=enabled) (R/WC) + 1=All interrupts in the GIRQx Source Register are disabled + 0=No effect. */ + } BLOCK_ENABLE_CLEAR_b; /*!< [31] BitSize */ + }; + + union { + __I uint32_t BLOCK_IRQ_VECTOR; /*!< (@ 0x4000E208) Block IRQ Vector Register */ + + struct { + __I uint32_t IRQ_VECTOR : 25; /*!< [0..24] Each bit in this field reports the status of the group + GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt + is disabled as a group, by the Block Enable Clear Register, + then the corresponding bit will be '0'b and no interrupt will + be asserted. */ + } BLOCK_IRQ_VECTOR_b; /*!< [25] BitSize */ + }; +} INTS_Type; + + +/* ================================================================================ */ +/* ================ TIMER0 ================ */ +/* ================================================================================ */ + + +/** + * @brief This timer block offers a simple mechanism for firmware to maintain a time base. This timer may be instantiated as 16 bits or + 32 bits. The name of the timer instance indicates the size of the timer. (TIMER0) + */ + +typedef struct { /*!< (@ 0x40000C00) TIMER0 Structure */ + __IO uint32_t COUNT; /*!< (@ 0x40000C00) This is the value of the Timer counter. This + is updated by Hardware but may be set by Firmware. */ + __IO uint32_t PRE_LOAD; /*!< (@ 0x40000C04) This is the value of the Timer pre-load for the + counter. This is used by H/W when the counter is to be restarted + automatically; this will become the new value of the counter + upon restart. */ + + union { + __IO uint32_t STATUS; /*!< (@ 0x40000C08) This is the interrupt status that fires when + the timer reaches its limit */ + + struct { + __IO uint32_t EVENT_INTERRUPT: 1; /*!< [0..0] This is the interrupt status that fires when the timer + reaches its limit. This is the interrupt status that fires when + the timer reaches its limit. This may be level or a self clearing + signal cycle pulse, based on the AUTO_RESTART bit in the Timer + Control Register. If the timer is set to automatically restart, + it will provide a pulse, otherwise a level is provided.(R/WC) + */ + } STATUS_b; /*!< [1] BitSize */ + }; + + union { + __IO uint32_t INT_EN; /*!< (@ 0x40000C0C) This is the interrupt enable for the status EVENT_INTERRUPT + bit in the Timer Status Register */ + + struct { + __IO uint32_t ENABLE : 1; /*!< [0..0] This is the interrupt enable for the status EVENT_INTERRUPT + bit in the Timer Status Register. */ + } INT_EN_b; /*!< [1] BitSize */ + }; + + union { + __IO REG32_U CONTROL; /*!< (@ 0x40000C10) Timer Control Register */ + + struct { + __IO uint32_t ENABLE : 1; /*!< [0..0] This enables the block for operation. 1=This block will + function normally; + 0=This block will gate its clock and go into its lowest power + state */ + uint32_t : 1; + __IO uint32_t COUNT_UP : 1; /*!< [2..2] This selects the counter direction. When the counter + in incrementing the counter will saturate and trigger the event + when it reaches all F's. When the counter is decrementing the + counter will saturate when it reaches 0h. 1=The counter will + increment; + 0=The counter will decrement */ + __IO uint32_t AUTO_RESTART: 1; /*!< [3..3] This will select the action taken upon completing a count. + 1=The counter will automatically restart the count, using the + contents of the Timer Preload Register to load the Timer Count + Register. + The interrupt will be set in edge mode + 0=The counter will simply enter a done state and wait for further + control inputs. The interrupt will be set in level mode. */ + __IO uint32_t SOFT_RESET : 1; /*!< [4..4] This is a soft reset. This is self clearing 1 cycle after + it is written. */ + __IO uint32_t START : 1; /*!< [5..5] This bit triggers the timer counter. The counter will + operate until it hits its terminating condition. This will + clear this bit. It should be noted that when operating in restart + mode, there is no terminating condition for the counter, so + this bit will never clear. Clearing this bit will halt the timer + counter. */ + __IO uint32_t RELOAD : 1; /*!< [6..6] This bit reloads the counter without interrupting it + operation. This will not function if the timer has already + completed (when the START bit in this register is '0'). This + is used to periodically prevent the timer from firing when an + event occurs. Usage while the timer is off may result in erroneous + behaviour. */ + __IO uint32_t HALT : 1; /*!< [7..7] This is a halt bit. This will halt the timer as long + as it is active. Once the halt is inactive, the timer will + start from where it left off. 1=Timer is halted. It stops counting. + The clock divider will also be reset. 0=Timer runs normally. + */ + uint32_t : 8; + __IO uint32_t PRE_SCALE : 16; /*!< [16..31] This is used to divide down the system clock through + clock enables to lower the power consumption of the block and + allow + slow timers. Updating this value during operation may result + in erroneous clock enable pulses until the clock divider restarts. + The number of clocks per clock enable pulse is (Value + 1); + a setting of 0 runs at the full clock speed, while a setting + of 1 + runs at half speed. */ + } CONTROL_b; /*!< [32] BitSize */ + }; +} TIMER0_Type; + + +/* ================================================================================ */ +/* ================ EC_REG_BANK ================ */ +/* ================================================================================ */ + + +/** + * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK) + */ + +typedef struct { /*!< (@ 0x4000FC00) EC_REG_BANK Structure */ + __I uint32_t RESERVED; + __IO uint32_t AHB_ERROR_ADDRESS; /*!< (@ 0x4000FC04) AHB Error Address [0:0] AHB_ERR_ADDR, In priority + order: + 1. AHB address is registered when an AHB error occurs on the + processor's AHB master port and the register value was + already 0. This way only the first address to generate an exception + is captured. + 2. The processor can clear this register by writing any 32-bit + value to this register. */ + __I uint32_t RESERVED1[3]; + __IO uint8_t AHB_ERROR_CONTROL; /*!< (@ 0x4000FC14) AHB Error Control [0:0] AHB_ERROR_DISABLE, 0: + EC memory exceptions are enabled. 1: EC memory exceptions are + disabled. */ + __I uint8_t RESERVED2[3]; + __IO uint32_t INTERRUPT_CONTROL; /*!< (@ 0x4000FC18) Interrupt Control [0:0] NVIC_EN (NVIC_EN) This + bit enables Alternate NVIC IRQ's Vectors. The Alternate NVIC + Vectors provides each interrupt event with a dedicated (direct) + NVIC vector. + 0 = Alternate NVIC vectors disabled, 1= Alternate NVIC vectors + enabled */ + __IO uint32_t ETM_TRACE_ENABLE; /*!< (@ 0x4000FC1C) ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) This + bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug + Interface pins are forced to the TRACE functions. 0 = ARM TRACE + port disabled, 1= ARM TRACE port enabled */ + + union { + __IO uint32_t DEBUG_Enable; /*!< (@ 0x4000FC20) Debug Enable Register */ + + struct { + __IO uint32_t DEBUG_EN : 1; /*!< [0..0] DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug + port. + 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e., + the TRST# pin is ignored and the JTAG signals remain in their + non-JTAG state) + 1= JTAG/SWD port enabled. A high on TRST# enables JTAG or SWD, + as determined by SWD_EN. */ + __IO uint32_t DEBUG_PIN_CFG: 2; /*!< [1..2] This field determines which pins are affected by the + TRST# debug enable pin. + 3=Reserved + 2=The pins associated with the JTAG TCK and TMS switch to the + debug interface when TRST# is de-asserted high. The pins + associated with TDI and TDO remain controlled by the associated + GPIO. This setting should be used when the ARM Serial + Wire Debug (SWD) is required for debugging and the Serial Wire + Viewer is not required + 1=The pins associated with the JTAG TCK, TMS and TDO switch + to the debug interface when TRST# i */ + __IO uint32_t DEBUG_PU_EN: 1; /*!< [3..3] If this bit is set to '1b' internal pull-up resistors + are automatically enabled on the appropriate debugging port + wires whenever the debug port is enabled (the DEBUG_EN bit + in this register is '1b' and the JTAG_RST# pin is high). The + setting + of DEBUG_PIN_CFG determines which pins have pull-ups enabled + when the debug port is enabled. */ + } DEBUG_Enable_b; /*!< [4] BitSize */ + }; + __I uint32_t RESERVED3; + __IO uint32_t WDT_EVENT_COUNT; /*!< (@ 0x4000FC28) WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These + EC R/W bits are cleared to 0 on VCC1 POR, but not on a WDT. + Note: This field is written by Boot ROM firmware to indicate + the number of times a WDT fired before loading a good EC code + image. */ + + union { + __IO uint32_t AES_HASH_BYTE_SWAP_CONTROL; /*!< (@ 0x4000FC2C) AES HASH Byte Swap Control Register. */ + + struct { + __I uint32_t INPUT_BYTE_SWAP_ENABLE: 1; /*!< [0..0] Used to enable byte swap on a DWORD during AHB read from + AES / HASH block: 1=Enable; 0=Disable. */ + __IO uint32_t OUTPUT_BYTE_SWAP_ENABLE: 1; /*!< [1..1] Used to enable byte swap on a DWORD during AHB write + from AES / HASH block: 1=Enable; 0=Disable. */ + __IO uint32_t INPUT_BLOCK_SWAP_ENABLE: 3; /*!< [2..4] Used to enable word swap on a DWORD during AHB read from + AES / HASH block + 4=Swap 32-bit doublewords in 128-byte blocks + 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus + references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C, + 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,... + 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references + issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,... + 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which + works on 64- */ + __IO uint32_t OUTPUT_BLOCK_SWAP_ENABLE: 3; /*!< [5..7] Used to enable word swap on a DWORD during AHB write + from AES / HASH block + 4=Swap 32-bit doublewords in 128-byte blocks + 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus + references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C, + 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,... + 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references + issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,... + 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which + works on 64 */ + } AES_HASH_BYTE_SWAP_CONTROL_b; /*!< [8] BitSize */ + }; + __I uint32_t RESERVED4[2]; + + union { + __IO uint32_t SYSTEM_SHUTDOWN_RESET; /*!< (@ 0x4000FC38) System Shutdown Reset */ + + struct { + __O uint32_t SYS_SHDN_RST: 1; /*!< [0..0] When this bit is asserted ('1'), the SYS_SHDN# output + is deasserted. */ + } SYSTEM_SHUTDOWN_RESET_b; /*!< [1] BitSize */ + }; + __I uint32_t RESERVED5; + + union { + __IO uint32_t MISC_TRIM; /*!< (@ 0x4000FC40) Misc Trim */ + + struct { + __O uint32_t PECI_DISABLE: 1; /*!< [0..0] When this bit is asserted ('1'), it disables the PECI + pads to reduce leakage. */ + } MISC_TRIM_b; /*!< [1] BitSize */ + }; + __I uint32_t RESERVED6[6]; + + union { + __IO uint32_t CRYPTO_SOFT_RESET; /*!< (@ 0x4000FC5C) System Shutdown Reset */ + + struct { + __O uint32_t RNG_SOFT_RESET: 1; /*!< [0..0] When this bit is asserted ('1'), the Random Number Generator + block is reset. */ + __O uint32_t PUBLIC_KEY_SOFT_RESET: 1; /*!< [1..1] When this bit is asserted ('1'), the Public Key block + is reset. */ + __O uint32_t AES_HASH_SOFT_RESET: 1; /*!< [2..2] When this bit is asserted ('1'), the AES and Hash blocks + are reset. */ + } CRYPTO_SOFT_RESET_b; /*!< [3] BitSize */ + }; + __I uint32_t RESERVED7; + + union { + __IO uint32_t GPIO_BANK_POWER; /*!< (@ 0x4000FC64) GPIO Bank Power Register */ + + struct { + __O uint32_t VTR_LEVEL1 : 1; /*!< [0..0] Voltage value on VTR1. This bit is set by hardware after + a VTR Power On Reset, but may be overridden by software. + It must be set by software if the VTR power rail is not active + when RESET_SYS is de-asserted. + 1=VTR1 is powered by 3.3V + 0=VTR1 is powered by 1.8V. */ + __O uint32_t VTR_LEVEL2 : 1; /*!< [1..1] Voltage value on VTR2. This bit is set by hardware after + a VTR Power On Reset, but may be overridden by software. + It must be set by software if the VTR power rail is not active + when RESET_SYS is de-asserted. + 1=VTR2 is powered by 3.3V + 0=VTR2 is powered by 1.8V. */ + __O uint32_t VTR_LEVEL3 : 1; /*!< [2..2] Voltage value on VTR3. This bit is set by hardware after + a VTR Power On Reset, but may be overridden by software. + It must be set by software if the VTR power rail is not active + when RESET_SYS is de-asserted. + 1=VTR3 is powered by 3.3V + 0=VTR3 is powered by 1.8V. */ + } GPIO_BANK_POWER_b; /*!< [3] BitSize */ + }; + __I uint32_t RESERVED8[2]; + + union { + __IO uint32_t JTAG_MASTER_CFG; /*!< (@ 0x4000FC70) JTAG Master Configuration Register */ + + struct { + __IO uint32_t JTM_CLK : 3; /*!< [0..2] This field determines the JTAG Master clock rate, derived + from the 48MHz master clock. + 7=375KHz; 6=750KHz; 5=1.5Mhz; 4=3Mhz; 3=6Mhz; 2=12Mhz; 1=24MHz; + 0=Reserved. */ + __IO uint32_t MASTER_SLAVE: 1; /*!< [3..3] This bit controls the direction of the JTAG port. 1=The + JTAG Port is configured as a Master + 0=The JTAG Port is configures as a Slave. */ + } JTAG_MASTER_CFG_b; /*!< [4] BitSize */ + }; + + union { + __I uint32_t JTAG_MASTER_STS; /*!< (@ 0x4000FC74) JTAG Master Status Register */ + + struct { + __I uint32_t JTM_DONE : 1; /*!< [0..0] This bit is set to '1b' when the JTAG Master Command + Register is written. It becomes '0b' when shifting has completed. + Software can poll this bit to determine when a command has + completed and it is therefore safe to remove the data in the + JTAG Master TDO + Register and load new data into the JTAG Master TMS Register + and the JTAG Master TDI Register. */ + } JTAG_MASTER_STS_b; /*!< [1] BitSize */ + }; + + union { + __IO uint32_t JTAG_MASTER_TDO; /*!< (@ 0x4000FC78) JTAG Master TDO Register */ + + struct { + __IO uint32_t JTM_TDO : 32; /*!< [0..31] When the JTAG Master Command Register is written, from + 1 to 32 bits are shifted into this register, starting with bit + 0, + from the JTAG_TDO pin. Shifting is at the rate determined by + the JTM_CLK field in the JTAG Master Configuration Register. + */ + } JTAG_MASTER_TDO_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t JTAG_MASTER_TDI; /*!< (@ 0x4000FC7C) JTAG Master TDI Register */ + + struct { + __IO uint32_t JTM_TDI : 32; /*!< [0..31] When the JTAG Master Command Register is written, from + 1 to 32 bits are shifted out of this register, starting with + bit 0, + onto the JTAG_TDI pin. Shifting is at the rate determined by + the JTM_CLK field in the JTAG Master Configuration Register. + */ + } JTAG_MASTER_TDI_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t JTAG_MASTER_TMS; /*!< (@ 0x4000FC80) JTAG Master TMS Register */ + + struct { + __IO uint32_t JTM_TMS : 32; /*!< [0..31] When the JTAG Master Command Register is written, from + 1 to 32 bits are shifted out of this register, starting with + bit 0, + onto the JTAG_TMS pin. Shifting is at the rate determined by + the JTM_CLK field in the JTAG Master Configuration Register. + */ + } JTAG_MASTER_TMS_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t JTAG_MASTER_CMD; /*!< (@ 0x4000FC84) JTAG Master Command Register */ + + struct { + __IO uint32_t JTM_COUNT : 5; /*!< [0..4] If the JTAG Port is configured as a Master, writing this + register starts clocking and shifting on the JTAG port. The + JTAG + Master port will shift JTM_COUNT+1 times, so writing a '0h' + will shift 1 bit, and writing '31h' will shift 32 bits. The + signal JTAG_CLK + will cycle JTM_COUNT+1 times. The contents of the JTAG Master + TMS Register and the JTAG Master TDI Register will be shifted + out on + the falling edge of JTAG_CLK and the.JTAG Master TDO Register + will get shifted in on the rising edge of JTAG_CLK. + If t */ + } JTAG_MASTER_CMD_b; /*!< [5] BitSize */ + }; +} EC_REG_BANK_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ struct 'PCR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */ +#define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bit 0) */ +#define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bitfield-Mask: 0x01) */ +#define PCR_SYS_SLP_CNTRL_TEST_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bit 2) */ +#define PCR_SYS_SLP_CNTRL_TEST_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bitfield-Mask: 0x01) */ +#define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Pos (3UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bit 3) */ +#define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Msk (0x8UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bitfield-Mask: 0x01) */ + +/* ----------------------------- PCR_PROC_CLK_CNTRL ----------------------------- */ +#define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Pos (0UL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bit 0) */ +#define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Msk (0xffUL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bitfield-Mask: 0xff) */ + +/* ----------------------------- PCR_SLOW_CLK_CNTRL ----------------------------- */ +#define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Pos (0UL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bit 0) */ +#define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Msk (0x3ffUL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bitfield-Mask: 0x3ff) */ + +/* --------------------------------- PCR_OSC_ID --------------------------------- */ +#define PCR_OSC_ID_TEST_Pos (0UL) /*!< PCR OSC_ID: TEST (Bit 0) */ +#define PCR_OSC_ID_TEST_Msk (0xffUL) /*!< PCR OSC_ID: TEST (Bitfield-Mask: 0xff) */ +#define PCR_OSC_ID_PLL_LOCK_Pos (8UL) /*!< PCR OSC_ID: PLL_LOCK (Bit 8) */ +#define PCR_OSC_ID_PLL_LOCK_Msk (0x100UL) /*!< PCR OSC_ID: PLL_LOCK (Bitfield-Mask: 0x01) */ + +/* ----------------------------- PCR_PCR_PWR_RST_STS ---------------------------- */ +#define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Pos (2UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bit 2) */ +#define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Msk (0x4UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Pos (3UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bit 3) */ +#define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Msk (0x8UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Pos (5UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bit 5) */ +#define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Msk (0x20UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Pos (6UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bit 6) */ +#define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Msk (0x40UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Pos (7UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bit 7) */ +#define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Msk (0x80UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bit 10) */ +#define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */ +#define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */ +#define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Pos (12UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bit 12) */ +#define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Msk (0x1000UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bitfield-Mask: 0x01) */ + +/* ------------------------------ PCR_PWR_RST_CNTRL ----------------------------- */ +#define PCR_PWR_RST_CNTRL_PWR_INV_Pos (0UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bit 0) */ +#define PCR_PWR_RST_CNTRL_PWR_INV_Msk (0x1UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bitfield-Mask: 0x01) */ +#define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Pos (8UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bit 8) */ +#define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Msk (0x100UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PCR_SYS_RST -------------------------------- */ +#define PCR_SYS_RST_SOFT_SYS_RESET_Pos (8UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bit 8) */ +#define PCR_SYS_RST_SOFT_SYS_RESET_Msk (0x100UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_SLP_EN_0 -------------------------------- */ +#define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bit 0) */ +#define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_0_EFUSE_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bit 1) */ +#define PCR_SLP_EN_0_EFUSE_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_0_ISPI_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bit 2) */ +#define PCR_SLP_EN_0_ISPI_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_SLP_EN_1 -------------------------------- */ +#define PCR_SLP_EN_1_INT_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bit 0) */ +#define PCR_SLP_EN_1_INT_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PECI_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bit 1) */ +#define PCR_SLP_EN_1_PECI_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TACH0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bit 2) */ +#define PCR_SLP_EN_1_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM0_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bit 4) */ +#define PCR_SLP_EN_1_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PMC_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bit 5) */ +#define PCR_SLP_EN_1_PMC_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_DMA_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bit 6) */ +#define PCR_SLP_EN_1_DMA_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TFDP_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bit 7) */ +#define PCR_SLP_EN_1_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bit 8) */ +#define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_WDT_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bit 9) */ +#define PCR_SLP_EN_1_WDT_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_SMB0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bit 10) */ +#define PCR_SLP_EN_1_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TACH1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bit 11) */ +#define PCR_SLP_EN_1_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TACH2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bit 12) */ +#define PCR_SLP_EN_1_TACH2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bit 20) */ +#define PCR_SLP_EN_1_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bit 21) */ +#define PCR_SLP_EN_1_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bit 22) */ +#define PCR_SLP_EN_1_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bit 23) */ +#define PCR_SLP_EN_1_PWM4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM5_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bit 24) */ +#define PCR_SLP_EN_1_PWM5_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM6_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bit 25) */ +#define PCR_SLP_EN_1_PWM6_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM7_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bit 26) */ +#define PCR_SLP_EN_1_PWM7_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_PWM8_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bit 27) */ +#define PCR_SLP_EN_1_PWM8_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bit 29) */ +#define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bit 30) */ +#define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bit 31) */ +#define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_SLP_EN_2 -------------------------------- */ +#define PCR_SLP_EN_2_LPC_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bit 0) */ +#define PCR_SLP_EN_2_LPC_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_UART_0_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bit 1) */ +#define PCR_SLP_EN_2_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_UART_1_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bit 2) */ +#define PCR_SLP_EN_2_UART_1_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bit 12) */ +#define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bit 13) */ +#define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bit 14) */ +#define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bit 15) */ +#define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_KBCEM_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bit 16) */ +#define PCR_SLP_EN_2_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_MBX_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bit 17) */ +#define PCR_SLP_EN_2_MBX_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_RTC_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bit 18) */ +#define PCR_SLP_EN_2_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ESPI_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bit 19) */ +#define PCR_SLP_EN_2_ESPI_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bit 21) */ +#define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bit 22) */ +#define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bit 23) */ +#define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_ASIF_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bit 24) */ +#define PCR_SLP_EN_2_ASIF_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_PORT80_0_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bit 25) */ +#define PCR_SLP_EN_2_PORT80_0_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_2_PORT80_1_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bit 26) */ +#define PCR_SLP_EN_2_PORT80_1_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_SLP_EN_3 -------------------------------- */ +#define PCR_SLP_EN_3_ADC_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bit 3) */ +#define PCR_SLP_EN_3_ADC_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_PS2_0_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bit 5) */ +#define PCR_SLP_EN_3_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_PS2_1_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bit 6) */ +#define PCR_SLP_EN_3_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_PS2_2_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bit 7) */ +#define PCR_SLP_EN_3_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bit 9) */ +#define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bit 10) */ +#define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bit 11) */ +#define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bit 12) */ +#define PCR_SLP_EN_3_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_SMB1_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bit 13) */ +#define PCR_SLP_EN_3_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_SMB2_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bit 14) */ +#define PCR_SLP_EN_3_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_SMB3_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bit 15) */ +#define PCR_SLP_EN_3_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_LED0_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bit 16) */ +#define PCR_SLP_EN_3_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_LED1_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bit 17) */ +#define PCR_SLP_EN_3_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_LED2_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bit 18) */ +#define PCR_SLP_EN_3_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_BCM0_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bit 19) */ +#define PCR_SLP_EN_3_BCM0_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bit 20) */ +#define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bit 21) */ +#define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bit 22) */ +#define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bit 23) */ +#define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bit 24) */ +#define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_LED3_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bit 25) */ +#define PCR_SLP_EN_3_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_PKE_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bit 26) */ +#define PCR_SLP_EN_3_PKE_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_RNG_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bit 27) */ +#define PCR_SLP_EN_3_RNG_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_AES_HASH_SLP_EN_Pos (28UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bit 28) */ +#define PCR_SLP_EN_3_AES_HASH_SLP_EN_Msk (0x10000000UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bit 29) */ +#define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_CCTIMER_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bit 30) */ +#define PCR_SLP_EN_3_CCTIMER_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_3_PWM9_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bit 31) */ +#define PCR_SLP_EN_3_PWM9_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_SLP_EN_4 -------------------------------- */ +#define PCR_SLP_EN_4_PWM10_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bit 0) */ +#define PCR_SLP_EN_4_PWM10_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_PWM11_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bit 1) */ +#define PCR_SLP_EN_4_PWM11_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bit 2) */ +#define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bit 3) */ +#define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bit 4) */ +#define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bit 5) */ +#define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_RTOS_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bit 6) */ +#define PCR_SLP_EN_4_RTOS_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bit 7) */ +#define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_QSPI_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bit 8) */ +#define PCR_SLP_EN_4_QSPI_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_BCM1_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bit 9) */ +#define PCR_SLP_EN_4_BCM1_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_RC_ID0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bit 10) */ +#define PCR_SLP_EN_4_RC_ID0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_RC_ID1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bit 11) */ +#define PCR_SLP_EN_4_RC_ID1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_RC_ID2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bit 12) */ +#define PCR_SLP_EN_4_RC_ID2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_SLP_EN_4_FCL_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bit 15) */ +#define PCR_SLP_EN_4_FCL_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_CLK_REQ_0 ------------------------------- */ +#define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bit 0) */ +#define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bit 1) */ +#define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_0_ISPI_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bit 2) */ +#define PCR_CLK_REQ_0_ISPI_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_CLK_REQ_1 ------------------------------- */ +#define PCR_CLK_REQ_1_INT_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bit 0) */ +#define PCR_CLK_REQ_1_INT_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PECI_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bit 1) */ +#define PCR_CLK_REQ_1_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TACH0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bit 2) */ +#define PCR_CLK_REQ_1_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM0_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bit 4) */ +#define PCR_CLK_REQ_1_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PMC_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bit 5) */ +#define PCR_CLK_REQ_1_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_DMA_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bit 6) */ +#define PCR_CLK_REQ_1_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TFDP_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bit 7) */ +#define PCR_CLK_REQ_1_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bit 8) */ +#define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_WDT_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bit 9) */ +#define PCR_CLK_REQ_1_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_SMB0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bit 10) */ +#define PCR_CLK_REQ_1_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TACH1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bit 11) */ +#define PCR_CLK_REQ_1_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TACH2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bit 12) */ +#define PCR_CLK_REQ_1_TACH2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bit 20) */ +#define PCR_CLK_REQ_1_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bit 21) */ +#define PCR_CLK_REQ_1_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bit 22) */ +#define PCR_CLK_REQ_1_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bit 23) */ +#define PCR_CLK_REQ_1_PWM4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM5_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bit 24) */ +#define PCR_CLK_REQ_1_PWM5_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM6_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bit 25) */ +#define PCR_CLK_REQ_1_PWM6_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM7_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bit 26) */ +#define PCR_CLK_REQ_1_PWM7_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_PWM8_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bit 27) */ +#define PCR_CLK_REQ_1_PWM8_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bit 29) */ +#define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bit 30) */ +#define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bit 31) */ +#define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_CLK_REQ_2 ------------------------------- */ +#define PCR_CLK_REQ_2_LPC_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bit 0) */ +#define PCR_CLK_REQ_2_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_UART_0_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bit 1) */ +#define PCR_CLK_REQ_2_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_UART_1_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bit 2) */ +#define PCR_CLK_REQ_2_UART_1_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bit 12) */ +#define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bit 13) */ +#define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bit 14) */ +#define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bit 15) */ +#define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bit 16) */ +#define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_MBX_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bit 17) */ +#define PCR_CLK_REQ_2_MBX_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_RTC_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bit 18) */ +#define PCR_CLK_REQ_2_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ESPI_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bit 19) */ +#define PCR_CLK_REQ_2_ESPI_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bit 21) */ +#define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bit 22) */ +#define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bit 23) */ +#define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_ASIF_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bit 24) */ +#define PCR_CLK_REQ_2_ASIF_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bit 25) */ +#define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bit 26) */ +#define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_CLK_REQ_3 ------------------------------- */ +#define PCR_CLK_REQ_3_ADC_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bit 3) */ +#define PCR_CLK_REQ_3_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bit 5) */ +#define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bit 6) */ +#define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bit 7) */ +#define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bit 9) */ +#define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bit 10) */ +#define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bit 11) */ +#define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bit 12) */ +#define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_SMB1_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bit 13) */ +#define PCR_CLK_REQ_3_SMB1_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_SMB2_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bit 14) */ +#define PCR_CLK_REQ_3_SMB2_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_SMB3_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bit 15) */ +#define PCR_CLK_REQ_3_SMB3_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_LED0_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bit 16) */ +#define PCR_CLK_REQ_3_LED0_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_LED1_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bit 17) */ +#define PCR_CLK_REQ_3_LED1_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_LED2_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bit 18) */ +#define PCR_CLK_REQ_3_LED2_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_BCM0_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bit 19) */ +#define PCR_CLK_REQ_3_BCM0_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bit 20) */ +#define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bit 21) */ +#define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bit 22) */ +#define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bit 23) */ +#define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bit 24) */ +#define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_LED3_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bit 25) */ +#define PCR_CLK_REQ_3_LED3_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_PKE_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bit 26) */ +#define PCR_CLK_REQ_3_PKE_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_RNG_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bit 27) */ +#define PCR_CLK_REQ_3_RNG_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Pos (28UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bit 28) */ +#define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Msk (0x10000000UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bit 29) */ +#define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bit 30) */ +#define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_3_PWM9_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bit 31) */ +#define PCR_CLK_REQ_3_PWM9_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_CLK_REQ_4 ------------------------------- */ +#define PCR_CLK_REQ_4_PWM10_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bit 0) */ +#define PCR_CLK_REQ_4_PWM10_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_PWM11_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bit 1) */ +#define PCR_CLK_REQ_4_PWM11_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bit 2) */ +#define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bit 3) */ +#define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bit 4) */ +#define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bit 5) */ +#define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_RTOS_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bit 6) */ +#define PCR_CLK_REQ_4_RTOS_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bit 7) */ +#define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_QSPI_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bit 8) */ +#define PCR_CLK_REQ_4_QSPI_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_BCM1_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bit 9) */ +#define PCR_CLK_REQ_4_BCM1_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bit 10) */ +#define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bit 11) */ +#define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bit 12) */ +#define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_CLK_REQ_4_FCL_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bit 15) */ +#define PCR_CLK_REQ_4_FCL_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_RST_EN_0 -------------------------------- */ +#define PCR_RST_EN_0_JTAG_STAP_RST_EN_Pos (0UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bit 0) */ +#define PCR_RST_EN_0_JTAG_STAP_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_0_EFUSE_RST_EN_Pos (1UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bit 1) */ +#define PCR_RST_EN_0_EFUSE_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_0_ISPI_RST_EN_Pos (2UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bit 2) */ +#define PCR_RST_EN_0_ISPI_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_RST_EN_1 -------------------------------- */ +#define PCR_RST_EN_1_INT_RST_EN_Pos (0UL) /*!< PCR RST_EN_1: INT_RST_EN (Bit 0) */ +#define PCR_RST_EN_1_INT_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_1: INT_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PECI_RST_EN_Pos (1UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bit 1) */ +#define PCR_RST_EN_1_PECI_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TACH0_RST_EN_Pos (2UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bit 2) */ +#define PCR_RST_EN_1_TACH0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM0_RST_EN_Pos (4UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bit 4) */ +#define PCR_RST_EN_1_PWM0_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PMC_RST_EN_Pos (5UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bit 5) */ +#define PCR_RST_EN_1_PMC_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_DMA_RST_EN_Pos (6UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bit 6) */ +#define PCR_RST_EN_1_DMA_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TFDP_RST_EN_Pos (7UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bit 7) */ +#define PCR_RST_EN_1_TFDP_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bit 8) */ +#define PCR_RST_EN_1_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_WDT_RST_EN_Pos (9UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bit 9) */ +#define PCR_RST_EN_1_WDT_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_SMB0_RST_EN_Pos (10UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bit 10) */ +#define PCR_RST_EN_1_SMB0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TACH1_RST_EN_Pos (11UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bit 11) */ +#define PCR_RST_EN_1_TACH1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TACH2_RST_EN_Pos (12UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bit 12) */ +#define PCR_RST_EN_1_TACH2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM1_RST_EN_Pos (20UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bit 20) */ +#define PCR_RST_EN_1_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM2_RST_EN_Pos (21UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bit 21) */ +#define PCR_RST_EN_1_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM3_RST_EN_Pos (22UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bit 22) */ +#define PCR_RST_EN_1_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM4_RST_EN_Pos (23UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bit 23) */ +#define PCR_RST_EN_1_PWM4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM5_RST_EN_Pos (24UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bit 24) */ +#define PCR_RST_EN_1_PWM5_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM6_RST_EN_Pos (25UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bit 25) */ +#define PCR_RST_EN_1_PWM6_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM7_RST_EN_Pos (26UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bit 26) */ +#define PCR_RST_EN_1_PWM7_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_PWM8_RST_EN_Pos (27UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bit 27) */ +#define PCR_RST_EN_1_PWM8_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bit 29) */ +#define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bit 30) */ +#define PCR_RST_EN_1_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_1_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bit 31) */ +#define PCR_RST_EN_1_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_RST_EN_2 -------------------------------- */ +#define PCR_RST_EN_2_LPC_RST_EN_Pos (0UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bit 0) */ +#define PCR_RST_EN_2_LPC_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_UART_0_RST_EN_Pos (1UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bit 1) */ +#define PCR_RST_EN_2_UART_0_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_UART_1_RST_EN_Pos (2UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bit 2) */ +#define PCR_RST_EN_2_UART_1_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bit 12) */ +#define PCR_RST_EN_2_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bit 13) */ +#define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bit 14) */ +#define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bit 15) */ +#define PCR_RST_EN_2_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_KBCEM_RST_EN_Pos (16UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bit 16) */ +#define PCR_RST_EN_2_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_MBX_RST_EN_Pos (17UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bit 17) */ +#define PCR_RST_EN_2_MBX_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_RTC_RST_EN_Pos (18UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bit 18) */ +#define PCR_RST_EN_2_RTC_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ESPI_RST_EN_Pos (19UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bit 19) */ +#define PCR_RST_EN_2_ESPI_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bit 21) */ +#define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bit 22) */ +#define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Pos (23UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bit 23) */ +#define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_ASIF_RST_EN_Pos (24UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bit 24) */ +#define PCR_RST_EN_2_ASIF_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_PORT80_0_RST_EN_Pos (25UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bit 25) */ +#define PCR_RST_EN_2_PORT80_0_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_2_PORT80_1_RST_EN_Pos (26UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bit 26) */ +#define PCR_RST_EN_2_PORT80_1_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_RST_EN_3 -------------------------------- */ +#define PCR_RST_EN_3_ADC_RST_EN_Pos (3UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bit 3) */ +#define PCR_RST_EN_3_ADC_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_PS2_0_RST_EN_Pos (5UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bit 5) */ +#define PCR_RST_EN_3_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_PS2_1_RST_EN_Pos (6UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bit 6) */ +#define PCR_RST_EN_3_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_PS2_2_RST_EN_Pos (7UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bit 7) */ +#define PCR_RST_EN_3_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_GP_SPI0_RST_EN_Pos (9UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bit 9) */ +#define PCR_RST_EN_3_GP_SPI0_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_HTIMER_0_RST_EN_Pos (10UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bit 10) */ +#define PCR_RST_EN_3_HTIMER_0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bit 11) */ +#define PCR_RST_EN_3_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_RPMPWM0_RST_EN_Pos (12UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bit 12) */ +#define PCR_RST_EN_3_RPMPWM0_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_SMB1_RST_EN_Pos (13UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bit 13) */ +#define PCR_RST_EN_3_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_SMB2_RST_EN_Pos (14UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bit 14) */ +#define PCR_RST_EN_3_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_SMB3_RST_EN_Pos (15UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bit 15) */ +#define PCR_RST_EN_3_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_LED0_RST_EN_Pos (16UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bit 16) */ +#define PCR_RST_EN_3_LED0_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_LED1_RST_EN_Pos (17UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bit 17) */ +#define PCR_RST_EN_3_LED1_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_LED2_RST_EN_Pos (18UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bit 18) */ +#define PCR_RST_EN_3_LED2_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_BCM0_RST_EN_Pos (19UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bit 19) */ +#define PCR_RST_EN_3_BCM0_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_GP_SPI1_RST_EN_Pos (20UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bit 20) */ +#define PCR_RST_EN_3_GP_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bit 21) */ +#define PCR_RST_EN_3_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bit 22) */ +#define PCR_RST_EN_3_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bit 23) */ +#define PCR_RST_EN_3_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bit 24) */ +#define PCR_RST_EN_3_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_LED3_RST_EN_Pos (25UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bit 25) */ +#define PCR_RST_EN_3_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_PKE_RST_EN_Pos (26UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bit 26) */ +#define PCR_RST_EN_3_PKE_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_RNG_RST_EN_Pos (27UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bit 27) */ +#define PCR_RST_EN_3_RNG_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_AES_HASH_RST_EN_Pos (28UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bit 28) */ +#define PCR_RST_EN_3_AES_HASH_RST_EN_Msk (0x10000000UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_HTIMER_1_RST_EN_Pos (29UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bit 29) */ +#define PCR_RST_EN_3_HTIMER_1_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_CCTIMER_RST_EN_Pos (30UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bit 30) */ +#define PCR_RST_EN_3_CCTIMER_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_3_PWM9_RST_EN_Pos (31UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bit 31) */ +#define PCR_RST_EN_3_PWM9_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_RST_EN_4 -------------------------------- */ +#define PCR_RST_EN_4_PWM10_RST_EN_Pos (0UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bit 0) */ +#define PCR_RST_EN_4_PWM10_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_PWM11_RST_EN_Pos (1UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bit 1) */ +#define PCR_RST_EN_4_PWM11_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_CNT_TMER0_RST_EN_Pos (2UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bit 2) */ +#define PCR_RST_EN_4_CNT_TMER0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_CNT_TMER1_RST_EN_Pos (3UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bit 3) */ +#define PCR_RST_EN_4_CNT_TMER1_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_CNT_TMER2_RST_EN_Pos (4UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bit 4) */ +#define PCR_RST_EN_4_CNT_TMER2_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_CNT_TMER3_RST_EN_Pos (5UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bit 5) */ +#define PCR_RST_EN_4_CNT_TMER3_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_RTOS_RST_EN_Pos (6UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bit 6) */ +#define PCR_RST_EN_4_RTOS_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_RPMPWM1_RST_EN_Pos (7UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bit 7) */ +#define PCR_RST_EN_4_RPMPWM1_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_QSPI_RST_EN_Pos (8UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bit 8) */ +#define PCR_RST_EN_4_QSPI_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_BCM1_RST_EN_Pos (9UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bit 9) */ +#define PCR_RST_EN_4_BCM1_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_RC_ID0_RST_EN_Pos (10UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bit 10) */ +#define PCR_RST_EN_4_RC_ID0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_RC_ID1_RST_EN_Pos (11UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bit 11) */ +#define PCR_RST_EN_4_RC_ID1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_RC_ID2_RST_EN_Pos (12UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bit 12) */ +#define PCR_RST_EN_4_RC_ID2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_RST_EN_4_FCL_RST_EN_Pos (15UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bit 15) */ +#define PCR_RST_EN_4_FCL_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'INTS' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- INTS_BLOCK_ENABLE_SET --------------------------- */ +#define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Pos (0UL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bit 0) */ +#define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bitfield-Mask: 0x7fffffff) */ + +/* --------------------------- INTS_BLOCK_ENABLE_CLEAR -------------------------- */ +#define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Pos (0UL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bit 0) */ +#define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bitfield-Mask: 0x7fffffff) */ + +/* ---------------------------- INTS_BLOCK_IRQ_VECTOR --------------------------- */ +#define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Pos (0UL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bit 0) */ +#define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Msk (0x1ffffffUL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bitfield-Mask: 0x1ffffff) */ + + +/* ================================================================================ */ +/* ================ struct 'WDT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- WDT_WDT_CONTROL ------------------------------ */ +#define WDT_WDT_CONTROL_WDT_ENABLE_Pos (0UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bit 0) */ +#define WDT_WDT_CONTROL_WDT_ENABLE_Msk (0x1UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bitfield-Mask: 0x01) */ +#define WDT_WDT_CONTROL_WDT_STATUS_Pos (1UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bit 1) */ +#define WDT_WDT_CONTROL_WDT_STATUS_Msk (0x2UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bitfield-Mask: 0x01) */ +#define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Pos (2UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bit 2) */ +#define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Msk (0x4UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bitfield-Mask: 0x01) */ +#define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Pos (3UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bit 3) */ +#define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Msk (0x8UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bitfield-Mask: 0x01) */ +#define WDT_WDT_CONTROL_JTAG_STALL_Pos (4UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bit 4) */ +#define WDT_WDT_CONTROL_JTAG_STALL_Msk (0x10UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER0_STATUS ------------------------------- */ +#define TIMER0_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER0_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER0_INT_EN ------------------------------- */ +#define TIMER0_INT_EN_ENABLE_Pos (0UL) /*!< TIMER0 INT_EN: ENABLE (Bit 0) */ +#define TIMER0_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER0 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER0_CONTROL ------------------------------- */ +#define TIMER0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER0 CONTROL: ENABLE (Bit 0) */ +#define TIMER0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER0 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_START_Pos (5UL) /*!< TIMER0 CONTROL: START (Bit 5) */ +#define TIMER0_CONTROL_START_Msk (0x20UL) /*!< TIMER0 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER0 CONTROL: RELOAD (Bit 6) */ +#define TIMER0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_HALT_Pos (7UL) /*!< TIMER0 CONTROL: HALT (Bit 7) */ +#define TIMER0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER0 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER1_STATUS ------------------------------- */ +#define TIMER1_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER1_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER1_INT_EN ------------------------------- */ +#define TIMER1_INT_EN_ENABLE_Pos (0UL) /*!< TIMER1 INT_EN: ENABLE (Bit 0) */ +#define TIMER1_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER1 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER1_CONTROL ------------------------------- */ +#define TIMER1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER1 CONTROL: ENABLE (Bit 0) */ +#define TIMER1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER1 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_START_Pos (5UL) /*!< TIMER1 CONTROL: START (Bit 5) */ +#define TIMER1_CONTROL_START_Msk (0x20UL) /*!< TIMER1 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER1 CONTROL: RELOAD (Bit 6) */ +#define TIMER1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_HALT_Pos (7UL) /*!< TIMER1 CONTROL: HALT (Bit 7) */ +#define TIMER1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER1 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER2_STATUS ------------------------------- */ +#define TIMER2_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER2_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER2_INT_EN ------------------------------- */ +#define TIMER2_INT_EN_ENABLE_Pos (0UL) /*!< TIMER2 INT_EN: ENABLE (Bit 0) */ +#define TIMER2_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER2 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER2_CONTROL ------------------------------- */ +#define TIMER2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER2 CONTROL: ENABLE (Bit 0) */ +#define TIMER2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER2 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_START_Pos (5UL) /*!< TIMER2 CONTROL: START (Bit 5) */ +#define TIMER2_CONTROL_START_Msk (0x20UL) /*!< TIMER2 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER2 CONTROL: RELOAD (Bit 6) */ +#define TIMER2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_HALT_Pos (7UL) /*!< TIMER2 CONTROL: HALT (Bit 7) */ +#define TIMER2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER2 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER3_STATUS ------------------------------- */ +#define TIMER3_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER3_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER3_INT_EN ------------------------------- */ +#define TIMER3_INT_EN_ENABLE_Pos (0UL) /*!< TIMER3 INT_EN: ENABLE (Bit 0) */ +#define TIMER3_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER3 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER3_CONTROL ------------------------------- */ +#define TIMER3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER3 CONTROL: ENABLE (Bit 0) */ +#define TIMER3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER3 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_START_Pos (5UL) /*!< TIMER3 CONTROL: START (Bit 5) */ +#define TIMER3_CONTROL_START_Msk (0x20UL) /*!< TIMER3 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER3 CONTROL: RELOAD (Bit 6) */ +#define TIMER3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_HALT_Pos (7UL) /*!< TIMER3 CONTROL: HALT (Bit 7) */ +#define TIMER3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER3 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER4' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER4_STATUS ------------------------------- */ +#define TIMER4_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER4_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER4_INT_EN ------------------------------- */ +#define TIMER4_INT_EN_ENABLE_Pos (0UL) /*!< TIMER4 INT_EN: ENABLE (Bit 0) */ +#define TIMER4_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER4 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER4_CONTROL ------------------------------- */ +#define TIMER4_CONTROL_ENABLE_Pos (0UL) /*!< TIMER4 CONTROL: ENABLE (Bit 0) */ +#define TIMER4_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER4 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER4 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER4_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER4 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER4_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER4_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_START_Pos (5UL) /*!< TIMER4 CONTROL: START (Bit 5) */ +#define TIMER4_CONTROL_START_Msk (0x20UL) /*!< TIMER4 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_RELOAD_Pos (6UL) /*!< TIMER4 CONTROL: RELOAD (Bit 6) */ +#define TIMER4_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER4 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_HALT_Pos (7UL) /*!< TIMER4 CONTROL: HALT (Bit 7) */ +#define TIMER4_CONTROL_HALT_Msk (0x80UL) /*!< TIMER4 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER4_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER4_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER5' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TIMER5_STATUS ------------------------------- */ +#define TIMER5_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bit 0) */ +#define TIMER5_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- TIMER5_INT_EN ------------------------------- */ +#define TIMER5_INT_EN_ENABLE_Pos (0UL) /*!< TIMER5 INT_EN: ENABLE (Bit 0) */ +#define TIMER5_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER5 INT_EN: ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- TIMER5_CONTROL ------------------------------- */ +#define TIMER5_CONTROL_ENABLE_Pos (0UL) /*!< TIMER5 CONTROL: ENABLE (Bit 0) */ +#define TIMER5_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER5 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER5 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER5_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER5 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER5_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER5_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_START_Pos (5UL) /*!< TIMER5 CONTROL: START (Bit 5) */ +#define TIMER5_CONTROL_START_Msk (0x20UL) /*!< TIMER5 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_RELOAD_Pos (6UL) /*!< TIMER5 CONTROL: RELOAD (Bit 6) */ +#define TIMER5_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER5 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_HALT_Pos (7UL) /*!< TIMER5 CONTROL: HALT (Bit 7) */ +#define TIMER5_CONTROL_HALT_Msk (0x80UL) /*!< TIMER5 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER5_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER5_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'EC_REG_BANK' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------- EC_REG_BANK_DEBUG_Enable -------------------------- */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Pos (0UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bit 0) */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Msk (0x1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Pos (1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bit 1) */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Msk (0x6UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bitfield-Mask: 0x03) */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Pos (3UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bit 3) */ +#define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Msk (0x8UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bitfield-Mask: 0x01) */ + +/* ------------------- EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL ------------------- */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Pos (0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bit 0) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Msk (0x1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Pos (1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bit 1) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Msk (0x2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Pos (2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bit 2) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Msk (0x1cUL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Pos (5UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bit 5) */ +#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Msk (0xe0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */ + +/* ---------------------- EC_REG_BANK_SYSTEM_SHUTDOWN_RESET --------------------- */ +#define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Pos (0UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bit 0) */ +#define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Msk (0x1UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bitfield-Mask: 0x01) */ + +/* ---------------------------- EC_REG_BANK_MISC_TRIM --------------------------- */ +#define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Pos (0UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bit 0) */ +#define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Msk (0x1UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------ EC_REG_BANK_CRYPTO_SOFT_RESET ----------------------- */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Pos (0UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bit 0) */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Msk (0x1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Pos (1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bit 1) */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Msk (0x2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Pos (2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bit 2) */ +#define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Msk (0x4UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bitfield-Mask: 0x01) */ + +/* ------------------------- EC_REG_BANK_GPIO_BANK_POWER ------------------------ */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Pos (0UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bit 0) */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Msk (0x1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Pos (1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bit 1) */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Msk (0x2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bitfield-Mask: 0x01) */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Pos (2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bit 2) */ +#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Msk (0x4UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bitfield-Mask: 0x01) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_CFG ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Msk (0x7UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bitfield-Mask: 0x07) */ +#define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Pos (3UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bit 3) */ +#define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Msk (0x8UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bitfield-Mask: 0x01) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_STS ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Msk (0x1UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bitfield-Mask: 0x01) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_TDO ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_TDI ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_TMS ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------- EC_REG_BANK_JTAG_MASTER_CMD ------------------------ */ +#define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bit 0) */ +#define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Msk (0x1fUL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bitfield-Mask: 0x1f) */ + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define PCR_BASE 0x40080100UL +#define INTS_BASE 0x4000E000UL +#define TIMER0_BASE 0x40000C00UL +#define TIMER1_BASE 0x40000C20UL +#define TIMER2_BASE 0x40000C40UL +#define TIMER3_BASE 0x40000C60UL +#define TIMER4_BASE 0x40000C80UL +#define TIMER5_BASE 0x40000CA0UL +#define EC_REG_BANK_BASE 0x4000FC00UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define MEC2016_PCR ((PCR_Type *) PCR_BASE) +#define MEC2016_INTS ((INTS_Type *) INTS_BASE) +#define MEC2016_TIMER0 ((TIMER0_Type *) TIMER0_BASE) +#define MEC2016_TIMER1 ((TIMER0_Type *) TIMER1_BASE) +#define MEC2016_TIMER2 ((TIMER0_Type *) TIMER2_BASE) +#define MEC2016_TIMER3 ((TIMER0_Type *) TIMER3_BASE) +#define MEC2016_TIMER4 ((TIMER0_Type *) TIMER4_BASE) +#define MEC2016_TIMER5 ((TIMER0_Type *) TIMER5_BASE) +#define MEC2016_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE) + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group MCHP_device_internal */ +/** @} */ /* End of group Microchip Technology Inc. */ + +#ifdef __cplusplus +} +#endif + + +#endif /* MCHP_device_internal_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer.h new file mode 100644 index 000000000..7a946339f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer.h @@ -0,0 +1,409 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated with unit testing feedbacks +******************************************************************************/ +/** @file btimer.h +* \brief Basic Timer Peripheral Header file +* \author jvasanth +* +* This file is the header file for Basic Timer Peripheral +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#ifndef _BTIMER_H +#define _BTIMER_H + +/******************************************************************************/ +/** Logical Timer ID for APIs. + * This is the timer IDs passed to Basic Timer API function calls + *******************************************************************************/ +enum _PID_BTIMER_ +{ + PID_BTIMER_0, + PID_BTIMER_1, + PID_BTIMER_2, + PID_BTIMER_3, + PID_BTIMER_4, + PID_BTIMER_5, + PID_BTIMER_MAX +}; + +/* ---------------------------------------------------------------------- */ +/* Logical flags for Timer Control */ +/* ---------------------------------------------------------------------- */ +//This is for tmr_cntl parameter in btimer_init function +#define BTIMER_AUTO_RESTART (0x08u) +#define BTIMER_ONE_SHOT (0u) +#define BTIMER_COUNT_UP (0x04u) +#define BTIMER_COUNT_DOWN (0u) +#define BTIMER_INT_EN (0x01u) +#define BTIMER_NO_INT (0u) +/* ---------------------------------------------------------------------- */ + + +//Timer Block Hardware Bits and Masks +#define BTIMER_CNTL_HALT (0x80UL) +#define BTIMER_CNTL_RELOAD (0x40UL) +#define BTIMER_CNTL_START (0x20UL) +#define BTIMER_CNTL_SOFT_RESET (0x10UL) +#define BTIMER_CNTL_AUTO_RESTART (0x08UL) +#define BTIMER_CNTL_COUNT_UP (0x04UL) +#define BTIMER_CNTL_ENABLE (0x01UL) + +#define BTIMER_CNTL_HALT_BIT (7U) +#define BTIMER_CNTL_RELOAD_BIT (6U) +#define BTIMER_CNTL_START_BIT (5U) +#define BTIMER_CNTRL_SOFT_RESET_BIT (4U) +#define BTIMER_CNTL_AUTO_RESTART_BIT (3U) +#define BTIMER_CNTL_COUNT_DIR_BIT (2U) +#define BTIMER_CNTL_ENABLE_BIT (0U) + +#define BTIMER_GIRQ MEC_GIRQ23_ID +#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX + + +/* ---------------------------------------------------------------------- */ +/* API - Basic Timer Intitialization function */ +/* ---------------------------------------------------------------------- */ + +/** Initialize specified timer + * @param btimer_id Basic Timer ID + * @param tmr_cntl Logical flags for Timer Control + * @param initial_count Initial Count + * @param preload_count Preload Count + * @note Performs a soft reset of the timer before configuration + */ +void btimer_init(uint8_t btimer_id, + uint16_t tmr_cntl, + uint16_t prescaler, + uint32_t initial_count, + uint32_t preload_count); + +/* ---------------------------------------------------------------------- */ +/* API - Functions to program and read the Basic Timer Counter */ +/* ---------------------------------------------------------------------- */ +/** Program timer's counter register. + * @param btimer_id Basic Timer ID + * @param count new counter value + * @note Timer hardware may implement a 16-bit or 32-bit + * hardware counter. If the timer is 16-bit only the lower + * 16-bits of the count paramter are used. + */ +void btimer_count_set(uint8_t btimer_id, uint32_t count); + +/** Return current value of timer's count register. + * @param btimer_id Basic Timer ID. + * @return uint32_t timer count may be 32 or 16 bits depending + * upon the hardware. Timers 0-3 are 16-bit + * and Timers 4-5 are 32-bit. + */ +uint32_t btimer_count_get(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Function to reload counter from Preload Register */ +/* ---------------------------------------------------------------------- */ +/** Force timer to reload counter from preload + * register. + * @param btimer_id Basic Timer ID. + * @note Hardware will only reload counter if timer is running. + */ +void btimer_reload(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for stopping and starting the basic Timer */ +/* ---------------------------------------------------------------------- */ +/** Start timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_start(uint8_t btimer_id); + +/** Stop timer. + * @param btimer_id Basic Timer ID. + * @note When a stopped timer is started again it will reload + * the count register from preload value. + */ +void btimer_stop(uint8_t btimer_id); + +/** Return state of timer's START bit. + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(timer not started), 1 (timer started) + */ +uint8_t btimer_is_started(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Function to perform basic timer soft reset */ +/* ---------------------------------------------------------------------- */ +/** Peform soft reset of specified timer. + * @param btimer_id Basic Timer ID + * @note Soft reset set all registers to POR values. + * Spins 256 times waiting on hardware to clear reset bit. + */ +void btimer_reset(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions to halt/unhalt the timer counting */ +/* ---------------------------------------------------------------------- */ +/** Halt timer counting with no reload on unhalt. + * @param btimer_id Basic Timer ID. + * @note A halted timer will not reload the count register when + * unhalted, it will continue counting from the current + * count value. + */ +void btimer_halt(uint8_t btimer_id); + +/** Unhalt timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_unhalt(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer interrupt */ +/* ---------------------------------------------------------------------- */ +/** Enable specified timer's interrupt from the block. + * @param btimer_id Basic Timer ID. + * @param ien Non-zero enable interrupt in timer block, 0 + * disable. + */ +void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien); + +/** Read Timer interrupt status and clear if set + * @param btimer_id Basic Timer ID. + * @return uint8_t 1 (Timer interrupt status set) else 0. + * @note If timer interrupt status is set then clear it before + * returning. + */ +uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer GIRQ */ +/* ---------------------------------------------------------------------- */ +/** Enables GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_set(uint8_t btimer_id); + +/** Clears GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_clr(uint8_t btimer_id); + +/** Returns GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(src bit not set), Non-zero (src bit set) + */ +uint8_t btimer_girq_src_get(uint8_t btimer_id); + +/** Clears GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_src_clr(uint8_t btimer_id); + +/** Returns GIRQ result bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(result bit not set), Non-zero (result bit set) + */ +uint8_t btimer_girq_result_get(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer Sleep */ +/* ---------------------------------------------------------------------- */ +/** Enable/Disable clock gating on idle of a timer + * @param btimer_id Basic Timer ID. + * @param sleep_en 1 = Sleep enable, 0 = Sleep disable + */ +void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en); + +/** Returns clk required status for the timer block + * @param btimer_id Basic Timer ID. + * @return Non-zero if clk required, else 0 + */ +uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id); + +/** Enable/Disable reset on sleep for the timer block + * @param btimer_id Basic Timer ID. + * @param reset_en 1 to enable, 0 to disable + */ +void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to set and read Timer Counter Register */ +/* ---------------------------------------------------------------------- */ +/** Sets timer counter + * @param btimer_id Basic Timer ID + * @param count - 32-bit counter + */ +void p_btimer_count_set(uint8_t btimer_id, uint32_t count); + +/** Read the timer counter + * @param btimer_id Basic Timer ID + * @return count - 32-bit counter + */ +uint32_t p_btimer_count_get(uint8_t btimer_id); + + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program the Preload */ +/* ---------------------------------------------------------------------- */ +/** Sets preload for the counter + * @param btimer_id Basic Timer ID + * @param preload_count - 32-bit pre-load value + */ +void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Functions - Functions for basic timer interrupts */ +/* ---------------------------------------------------------------------- */ +/** Reads the interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + * @return status - 1 if interrupt status set, else 0 + */ +uint8_t p_btimer_int_status_get(uint8_t btimer_id); + +/** Clears interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_status_clr(uint8_t btimer_id); + +/** Sets interrupt enable bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_set(uint8_t btimer_id); + +/** Clears interrupt enable bit for the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_clr(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Functions - Functions for Control Register */ +/* ---------------------------------------------------------------------- */ +/** Writes the control register 32-bits + * @param btimer_id Basic Timer ID + * @param value - 32-bit value to program + */ +void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value); + +/** Reads the control register + * @param btimer_id Basic Timer ID + * @return uint32_t - 32-bit value + */ +uint32_t p_btimer_ctrl_read(uint8_t btimer_id); + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_set(uint8_t btimer_id); + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_clr(uint8_t btimer_id); + +/** Sets counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id); + +/** Clears counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id); + +/** Sets auto restart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id); + +/** Clears auto resetart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id); + +/** Sets soft reset bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id); + +/** Read Soft Reset bit + * @param btimer_id Basic Timer ID + * @return 0 if soft reset status bit cleared; else non-zero value + */ +uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id); + +/** Sets start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_set(uint8_t btimer_id); + +/** Read start bit in the control register + * @param btimer_id Basic Timer ID + * @return 0 if start bit not set; else non-zero value + */ +uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id); + +/** Clears start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_clr(uint8_t btimer_id); + +/** Sets reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_set(uint8_t btimer_id); + +/** Clears reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_clr(uint8_t btimer_id); + +/** Sets halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_set(uint8_t btimer_id); + +/** Clears halt bit in the control register + * @param btimer_id Basic Timer ID + */ + +void p_btimer_ctrl_halt_clr(uint8_t btimer_id); + +/** Sets prescale value + * @param btimer_id Basic Timer ID + * @param prescaler - 16-bit pre-scale value + */ +void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler); + + +#endif // #ifndef _BTIMER_H + +/* end btimer_perphl.c */ + +/** @} //Peripherals Basic_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_api.c new file mode 100644 index 000000000..6dbba6c01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_api.c @@ -0,0 +1,474 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file btimer_api.c +* \brief Basic Timer APIs Source file +* \author jvasanth +* +* This file implements the Basic Timer API functions +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#include "common_lib.h" +#include "btimer.h" +#include "..\pcr\pcr.h" +//#include "..\interrupt\ecia.h" + +/** Basic Timer Sleep Registers & Bit Positions */ +static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = { + PCR_BTIMER0, + PCR_BTIMER1, + PCR_BTIMER2, + PCR_BTIMER3, + PCR_BTIMER4, + PCR_BTIMER5 +}; + +#ifdef PLIB_BTIMER_CHECK_ID + +/** Local helper that checks if logical Timer ID is valid. + * @param btimer_id Basic Timer ID + * @return uint8_t Non-zero(VALID), 0(Invalid) + */ +static uint8_t btmr_valid(uint8_t btimer_id) +{ + if ( btimer_id < (PID_BTIMER_MAX ) ) { + return true; + } + return false; +} + +#else + + +/** This version of tmr_valid skips checking always returning 1. + * Compiler may optimize it out. + * @param btimer_id Basic Timer ID + * @return uint8_t 1(VALID) + */ +static uint8_t btmr_valid(uint8_t btimer_id) { return 1; } + +#endif + + +/* ---------------------------------------------------------------------- */ +/* Basic Timer Intitialization function */ +/* ---------------------------------------------------------------------- */ + +/** Initialize specified timer + * @param btimer_id Basic Timer ID + * @param tmr_cntl Logical flags for Timer Control + * @param initial_count Initial Count + * @param preload_count Preload Count + * @note Performs a soft reset of the timer before configuration + */ +void btimer_init(uint8_t btimer_id, + uint16_t tmr_cntl, + uint16_t prescaler, + uint32_t initial_count, + uint32_t preload_count) +{ + uint32_t value; + + if (btmr_valid(btimer_id)) { + + btimer_reset(btimer_id); + + // Ungate timer clocks and program prescale + value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); + p_btimer_ctrl_write(btimer_id, value); + + // Program Preload & initial counter value + p_btimer_preload_set(btimer_id, preload_count); + p_btimer_count_set(btimer_id, initial_count); + + // Program control register, interrupt enable, and clear status + if (tmr_cntl & BTIMER_COUNT_UP) { + p_btimer_ctrl_counter_dir_set(btimer_id); + } + if (tmr_cntl & BTIMER_AUTO_RESTART) { + p_btimer_ctrl_auto_restart_set(btimer_id); + } + if (tmr_cntl & BTIMER_INT_EN) { + p_btimer_int_enable_set(btimer_id); // enable first + p_btimer_int_status_clr(btimer_id); // clear status + } + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to program and read the Basic Timer Counter */ +/* ---------------------------------------------------------------------- */ + +/** Program timer's counter register. + * @param btimer_id Basic Timer ID + * @param count new counter value + * @note Timer hardware may implement a 16-bit or 32-bit + * hardware counter. If the timer is 16-bit only the lower + * 16-bits of the count paramter are used. + */ +void btimer_count_set(uint8_t btimer_id, uint32_t count) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_count_set(btimer_id, count); + } +} + +/** Return current value of timer's count register. + * @param btimer_id Basic Timer ID. + * @return uint32_t timer count may be 32 or 16 bits depending + * upon the hardware. Timers 0-3 are 16-bit + * and Timers 4-5 are 32-bit. + */ +uint32_t btimer_count_get(uint8_t btimer_id) +{ + uint32_t cnt; + + cnt = 0ul; + if ( btmr_valid(btimer_id) ) { + + cnt = p_btimer_count_get(btimer_id); + } + + return cnt; +} + +/* ---------------------------------------------------------------------- */ +/* Function to reload counter from Preload Register */ +/* ---------------------------------------------------------------------- */ + +/** Force timer to reload counter from preload + * register. + * @param btimer_id Basic Timer ID. + * @note Hardware will only reload counter if timer is running. + */ +void btimer_reload(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running + { + p_btimer_ctrl_reload_set(btimer_id); + } + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions for stopping and starting the basic Timer */ +/* ---------------------------------------------------------------------- */ + +/** Start timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_start(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_start_set(btimer_id); + } +} + +/** Stop timer. + * @param btimer_id Basic Timer ID. + * @note When a stopped timer is started again it will reload + * the count register from preload value. + */ +void btimer_stop(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_start_clr(btimer_id); + + } +} + +/** Return state of timer's START bit. + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(timer not started), 1 (timer started) + */ +uint8_t btimer_is_started(uint8_t btimer_id) +{ + uint8_t sts; + + sts = 0; + if ( btmr_valid(btimer_id) ) { + + if (p_btimer_ctrl_start_get(btimer_id)) + { + sts = 1; + } + } + return sts; +} + +/* ---------------------------------------------------------------------- */ +/* Function to perform basic timer soft reset */ +/* ---------------------------------------------------------------------- */ + +/** Peform soft reset of specified timer. + * @param btimer_id Basic Timer ID + * @note Soft reset set all registers to POR values. + * Spins 256 times waiting on hardware to clear reset bit. + */ +void btimer_reset(uint8_t btimer_id) +{ + uint32_t wait_cnt; + uint8_t soft_reset_sts; + + if (btmr_valid(btimer_id)) { + + p_btimer_ctrl_soft_reset_set(btimer_id); + + wait_cnt = 256ul; + do { + soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id); + + if (0 == soft_reset_sts){ + break; + } + } + while ( wait_cnt-- ); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to halt/unhalt the timer counting */ +/* ---------------------------------------------------------------------- */ + +/** Halt timer counting with no reload on unhalt. + * @param btimer_id Basic Timer ID. + * @note A halted timer will not reload the count register when + * unhalted, it will continue counting from the current + * count value. + */ +void btimer_halt(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_halt_set(btimer_id); + } +} + +/** Unhalt timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_unhalt(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_halt_clr(btimer_id); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer interrupt */ +/* ---------------------------------------------------------------------- */ + +/** Enable specified timer's interrupt from the block. + * @param btimer_id Basic Timer ID. + * @param ien Non-zero enable interrupt in timer block, 0 + * disable. + */ +void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien) +{ + if (btmr_valid(btimer_id)) { + + p_btimer_int_enable_set(btimer_id); + + if (ien) { + p_btimer_int_enable_set(btimer_id); + } else { + p_btimer_int_enable_clr(btimer_id); + } + } +} + +/** Read Timer interrupt status and clear if set + * @param btimer_id Basic Timer ID. + * @return uint8_t 1 (Timer interrupt status set) else 0. + * @note If timer interrupt status is set then clear it before + * returning. + */ +uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id) +{ + uint8_t sts; + + sts = 0; + if (btmr_valid(btimer_id)) { + + sts = p_btimer_int_status_get(btimer_id); + if (sts) { + p_btimer_int_status_clr(btimer_id); + } + } + return sts; +} + +#if 0 //Temporary disable until interrupt module + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer GIRQ */ +/* ---------------------------------------------------------------------- */ + +/** Enables GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_set(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id); + } +} + +/** Clears GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_clr(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id); + } + +} + +/** Returns GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(src bit not set), Non-zero (src bit set) + */ +uint8_t btimer_girq_src_get(uint8_t btimer_id) +{ + uint8_t retVal; + + retVal = 0; + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); + } + + return retVal; +} + +/** Clears GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_src_clr(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); + } +} + +/** Returns GIRQ result bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(result bit not set), Non-zero (result bit set) + */ +uint8_t btimer_girq_result_get(uint8_t btimer_id) +{ + uint8_t retVal; + + retVal = 0; + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); + } + + return retVal; +} +#endif + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer Sleep */ +/* ---------------------------------------------------------------------- */ + +/** Enable/Disable clock gating on idle of a timer + * @param btimer_id Basic Timer ID. + * @param sleep_en 1 = Sleep enable, 0 = Sleep disable + */ +void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en) +{ + uint32_t pcr_blk_id; + + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + pcr_sleep_enable(pcr_blk_id, sleep_en); + } +} + +/** Returns clk required status for the timer block + * @param btimer_id Basic Timer ID. + * @return Non-zero if clk required, else 0 + */ +uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id) +{ + uint32_t retVal; + uint32_t pcr_blk_id; + + retVal = 0ul; + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + retVal = pcr_clock_reqd_status_get(pcr_blk_id); + } + + return retVal; +} + +/** Enable/Disable reset on sleep for the timer block + * @param btimer_id Basic Timer ID. + * @param reset_en 1 to enable, 0 to disable + */ +void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en) +{ + uint32_t pcr_blk_id; + + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + pcr_reset_enable(pcr_blk_id, reset_en); + } +} + +/* end btimer_api.c */ + +/** @} //Peripheral Basic_Timer + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c new file mode 100644 index 000000000..39a01c85f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c @@ -0,0 +1,287 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file btimer_perphl.c +* \brief Basic Timer Peripheral Source file +* \author jvasanth +* +* This file implements the Basic Timer Peripheral functions +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#include "common_lib.h" +#include "btimer.h" + +/** Basic Timer Instance base addresses */ +static TIMER0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = { + MEC2016_TIMER0, + MEC2016_TIMER1, + MEC2016_TIMER2, + MEC2016_TIMER3, + MEC2016_TIMER4, + MEC2016_TIMER5 +}; + +/* ---------------------------------------------------------------------- */ +/* Functions to set and read Timer Counter Register */ +/* ---------------------------------------------------------------------- */ + +/** Sets timer counter + * @param btimer_id Basic Timer ID + * @param count - 32-bit counter + */ +void p_btimer_count_set(uint8_t btimer_id, uint32_t count) +{ + btmr_inst[btimer_id]->COUNT = count; +} + +/** Read the timer counter + * @param btimer_id Basic Timer ID + * @return count - 32-bit counter + */ +uint32_t p_btimer_count_get(uint8_t btimer_id) +{ + return btmr_inst[btimer_id]->COUNT; +} + +/* ---------------------------------------------------------------------- */ +/* Function to program the Preload */ +/* ---------------------------------------------------------------------- */ + +/** Sets preload for the counter + * @param btimer_id Basic Timer ID + * @param preload_count - 32-bit pre-load value + */ +void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count) +{ + btmr_inst[btimer_id]->PRE_LOAD = preload_count; +} + +/* ---------------------------------------------------------------------- */ +/* Functions for basic timer interrupts */ +/* ---------------------------------------------------------------------- */ + +/** Reads the interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + * @return status - 1 if interrupt status set, else 0 + */ +uint8_t p_btimer_int_status_get(uint8_t btimer_id) +{ + return (uint8_t)(btmr_inst[btimer_id]->STATUS); +} + +/** Clears interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_status_clr(uint8_t btimer_id) +{ + // Write 1 to clear + btmr_inst[btimer_id]->STATUS = 1; +} + +/** Sets interrupt enable bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->INT_EN = 1; +} + +/** Clears interrupt enable bit for the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->INT_EN = 0; +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Control Register */ +/* ---------------------------------------------------------------------- */ + +/** Writes the control register 32-bits + * @param btimer_id Basic Timer ID + * @param value - 32-bit value to program + */ +void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value) +{ + btmr_inst[btimer_id]->CONTROL.w = value; +} + +/** Reads the control register + * @param btimer_id Basic Timer ID + * @return uint32_t - 32-bit value + */ +uint32_t p_btimer_ctrl_read(uint8_t btimer_id) +{ + uint32_t retVal; + + retVal = btmr_inst[btimer_id]->CONTROL.w; + + return retVal; +} + +/** Sets enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE; +} + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE; +} + +/** Sets counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP; +} + +/** Clears counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP; +} + +/** Sets auto restart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART; +} + +/** Clears auto resetart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART; +} + +/** Sets soft reset bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET; +} + +/** Read Soft Reset bit + * @param btimer_id Basic Timer ID + * @return 0 if soft reset status bit cleared; else non-zero value + */ +uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id) +{ + return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET); +} + +/** Sets start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START; +} + +/** Read start bit in the control register + * @param btimer_id Basic Timer ID + * @return 0 if start bit not set; else non-zero value + */ +uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id) +{ + return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START); +} + +/** Clears start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START; +} + +/** Sets reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD; +} + +/** Clears reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD; +} + +/** Sets halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT; +} + +/** Clears halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT; +} + +/** Sets prescale value + * @param btimer_id Basic Timer ID + * @param prescaler - 16-bit pre-scale value + */ +void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler) +{ + btmr_inst[btimer_id]->CONTROL.h[1] = prescaler; +} + + +/* end btimer_perphl.c */ + +/** @} //Peripheral Basic_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common.h new file mode 100644 index 000000000..ed3e1748c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common.h @@ -0,0 +1,63 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * common.h + * This is the header file including common headers from various modules + ********************************************************************************** + * $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $ + * Description: added ict module + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common.h $ + */ + +/*********************************************************************************/ +/** @defgroup common common + * @{ + */ + +/** @file common.h +* \brief header file including common headers from various modules +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _COMMON_H_ +#define _COMMON_H_ + +// Include common headers from various modules +// !!! The include order is important !!! +#include "platform.h" +#include "MCHP_device_header.h" +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" + +#include "defs.h" +#include "string.h" +#include "interrupt.h" +#include "system_internal.h" + + +#endif /*_COMMON_H_*/ + +/** @} + */ + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common_lib.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common_lib.h new file mode 100644 index 000000000..b49da8fb8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/common_lib.h @@ -0,0 +1,61 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * common.h + * This is the header file including common headers from various modules + ********************************************************************************** + * $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $ + * Description: added ict module + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common_lib.h $ + */ + +/*********************************************************************************/ +/** @defgroup common common + * @{ + */ + +/** @file common.h +* \brief header file including common headers from various modules +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _COMMON_LIB_H_ +#define _COMMON_LIB_H_ + +// Include common headers from various modules +// !!! The include order is important !!! +#include "platform.h" +#include "ARM_REG.h" +#include "MCHP_device_header.h" +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" +#include "defs.h" +#include "string.h" +#include "system_internal.h" +#include +#endif /*_COMMON_LIB_H_*/ + +/** @} + */ + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/defs.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/defs.h new file mode 100644 index 000000000..4c7af072d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/defs.h @@ -0,0 +1,54 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * defs.h + * This is the definition header file for generic usages + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/defs.h $ + */ + + +/*********************************************************************************/ +/** @defgroup defs defs + * @{ + */ + +/** @file defs.h +* \brief definition header file for generic usages +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _DEFS_H_ +#define _DEFS_H_ + +/* bit operation MACRO, xvar could be byte, word or dword */ +#define mSET_BIT(x, xvar) ( xvar |= x ) +#define mCLR_BIT(x, xvar) ( xvar &= ~x ) +#define mGET_BIT(x, xvar) ( xvar & x ) +#define mCLR_SRC_BIT(x, xvar) ( xvar = x ) +#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}} + +#endif /*_DEFS_H_*/ + +/** @} + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt.h new file mode 100644 index 000000000..4ec0d8bde --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt.h @@ -0,0 +1,1371 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Renamed ecia_init to interrupt_init +******************************************************************************/ +/** @file interrupt.h +* \brief Interrupt Header File +* \author jvasanth +* +* This file implements the Interrupt Module Header file +******************************************************************************/ + +/** @defgroup Interrupt + * @{ + */ + +#ifndef _INTERRUPT_H +#define _INTERRUPT_H + +// GIRQ IDs for EC Interrupt Aggregator +enum MEC_GIRQ_IDS +{ + MEC_GIRQ08_ID = 0, + MEC_GIRQ09_ID, + MEC_GIRQ10_ID, + MEC_GIRQ11_ID, + MEC_GIRQ12_ID, + MEC_GIRQ13_ID, + MEC_GIRQ14_ID, + MEC_GIRQ15_ID, + MEC_GIRQ16_ID, + MEC_GIRQ17_ID, + MEC_GIRQ18_ID, + MEC_GIRQ19_ID, + MEC_GIRQ20_ID, + MEC_GIRQ21_ID, + MEC_GIRQ22_ID, + MEC_GIRQ23_ID, + MEC_GIRQ_ID_MAX +}; + +//Bitmask of GIRQ in ECIA Block Registers +#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8)) +#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) +#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) +#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) +#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) +#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) +#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) +#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) +#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) +#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) +#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) +#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) +#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) +#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) +#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) +#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) + +#define INTERRUPT_MODE_ALL_AGGREGATED (0u) +#define INTERRUPT_MODE_DIRECT (1u) + +// Bit map of GIRQs whose sources can be directly connected to the NVIC +// GIRQs 13 - 19, 21, 23, 24-26 +#define ECIA_GIRQ_DIRECT_BITMAP (0x07AFE000ul) + +/* + * n = b[7:0] = zero-based direct mapped NVIC ID + * m = b[15:8] = zero-based aggregated NVIC ID + * a = b[23:16] = block Aggregator register block ID + * b = b[31:24] = block bit position in Aggregator registers +*/ +#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \ + (((uint32_t)(m)&0xFFul)<<8u) + \ + ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \ + (((uint32_t)(b)&0x1Ful)<<24)) + +#define ECIA_NVIC_ID_BITPOS (0u) +#define ECIA_IA_NVIC_ID_BITPOS (8u) +#define ECIA_GIRQ_ID_BITPOS (16u) +#define ECIA_GIRQ_BIT_BITPOS (24u) + +// +// GIRQ08 +// +#define GPIO_0140_IROUTE IROUTE(0,8,0,0) +#define GPIO_0141_IROUTE IROUTE(1,8,0,0) +#define GPIO_0142_IROUTE IROUTE(2,8,0,0) +#define GPIO_0143_IROUTE IROUTE(3,8,0,0) +#define GPIO_0144_IROUTE IROUTE(4,8,0,0) +#define GPIO_0145_IROUTE IROUTE(5,8,0,0) +#define GPIO_0147_IROUTE IROUTE(7,8,0,0) +// +#define GPIO_0150_IROUTE IROUTE(8,8,0,0) +#define GPIO_0151_IROUTE IROUTE(9,8,0,0) +#define GPIO_0152_IROUTE IROUTE(10,8,0,0) +#define GPIO_0153_IROUTE IROUTE(11,8,0,0) +#define GPIO_0154_IROUTE IROUTE(12,8,0,0) +#define GPIO_0155_IROUTE IROUTE(13,8,0,0) +#define GPIO_0156_IROUTE IROUTE(14,8,0,0) +#define GPIO_0157_IROUTE IROUTE(15,8,0,0) +// +#define GPIO_0160_IROUTE IROUTE(16,8,0,0) +#define GPIO_0161_IROUTE IROUTE(17,8,0,0) +#define GPIO_0162_IROUTE IROUTE(18,8,0,0) +#define GPIO_0163_IROUTE IROUTE(19,8,0,0) +#define GPIO_0164_IROUTE IROUTE(20,8,0,0) +#define GPIO_0165_IROUTE IROUTE(21,8,0,0) +#define GPIO_0166_IROUTE IROUTE(22,8,0,0) +#define GPIO_0167_IROUTE IROUTE(23,8,0,0) + +#define GPIO_0170_IROUTE IROUTE(24,8,0,0) +#define GPIO_0171_IROUTE IROUTE(25,8,0,0) +#define GPIO_0172_IROUTE IROUTE(26,8,0,0) +#define GPIO_0173_IROUTE IROUTE(27,8,0,0) +#define GPIO_0174_IROUTE IROUTE(28,8,0,0) +#define GPIO_0175_IROUTE IROUTE(29,8,0,0) +#define GPIO_0176_IROUTE IROUTE(30,8,0,0) + +// +// GIRQ09 +// +#define GPIO_0100_IROUTE IROUTE(0,9,1,1) +#define GPIO_0101_IROUTE IROUTE(1,9,1,1) +#define GPIO_0102_IROUTE IROUTE(2,9,1,1) +#define GPIO_0103_IROUTE IROUTE(3,9,1,1) +#define GPIO_0104_IROUTE IROUTE(4,9,1,1) +#define GPIO_0105_IROUTE IROUTE(5,9,1,1) +#define GPIO_0105_IROUTE IROUTE(5,9,1,1) +#define GPIO_0107_IROUTE IROUTE(7,9,1,1) +// +#define GPIO_0110_IROUTE IROUTE(8,9,1,1) +#define GPIO_0111_IROUTE IROUTE(9,9,1,1) +#define GPIO_0112_IROUTE IROUTE(10,9,1,1) +#define GPIO_0113_IROUTE IROUTE(11,9,1,1) +#define GPIO_0114_IROUTE IROUTE(12,9,1,1) +#define GPIO_0115_IROUTE IROUTE(13,9,1,1) +#define GPIO_0116_IROUTE IROUTE(14,9,1,1) +#define GPIO_0117_IROUTE IROUTE(15,9,1,1) +// +#define GPIO_0120_IROUTE IROUTE(16,9,1,1) +#define GPIO_0121_IROUTE IROUTE(17,9,1,1) +#define GPIO_0122_IROUTE IROUTE(18,9,1,1) +#define GPIO_0124_IROUTE IROUTE(20,9,1,1) +#define GPIO_0125_IROUTE IROUTE(21,9,1,1) +#define GPIO_0126_IROUTE IROUTE(22,9,1,1) +#define GPIO_0127_IROUTE IROUTE(23,9,1,1) +// +#define GPIO_0130_IROUTE IROUTE(24,9,1,1) +#define GPIO_0131_IROUTE IROUTE(25,9,1,1) +#define GPIO_0132_IROUTE IROUTE(26,9,1,1) +#define GPIO_0133_IROUTE IROUTE(27,9,1,1) +#define GPIO_0134_IROUTE IROUTE(28,9,1,1) +#define GPIO_0135_IROUTE IROUTE(29,9,1,1) +#define GPIO_0136_IROUTE IROUTE(30,9,1,1) + +// +// GIRQ10 +// +#define GPIO_0040_IROUTE IROUTE(0,10,2,2) +#define GPIO_0041_IROUTE IROUTE(1,10,2,2) +#define GPIO_0042_IROUTE IROUTE(2,10,2,2) +#define GPIO_0043_IROUTE IROUTE(3,10,2,2) +#define GPIO_0044_IROUTE IROUTE(4,10,2,2) +#define GPIO_0045_IROUTE IROUTE(5,10,2,2) +#define GPIO_0045_IROUTE IROUTE(5,10,2,2) +#define GPIO_0047_IROUTE IROUTE(7,10,2,2) +// +#define GPIO_0050_IROUTE IROUTE(8,10,2,2) +#define GPIO_0051_IROUTE IROUTE(9,10,2,2) +#define GPIO_0052_IROUTE IROUTE(10,10,2,2) +#define GPIO_0053_IROUTE IROUTE(11,10,2,2) +#define GPIO_0054_IROUTE IROUTE(12,10,2,2) +#define GPIO_0055_IROUTE IROUTE(13,10,2,2) +#define GPIO_0056_IROUTE IROUTE(14,10,2,2) +#define GPIO_0057_IROUTE IROUTE(15,10,2,2) +// +#define GPIO_0060_IROUTE IROUTE(16,10,2,2) +#define GPIO_0061_IROUTE IROUTE(17,10,2,2) +#define GPIO_0062_IROUTE IROUTE(18,10,2,2) +#define GPIO_0063_IROUTE IROUTE(19,10,2,2) +#define GPIO_0064_IROUTE IROUTE(20,10,2,2) +#define GPIO_0065_IROUTE IROUTE(21,10,2,2) +#define GPIO_0066_IROUTE IROUTE(22,10,2,2) +#define GPIO_0067_IROUTE IROUTE(23,10,2,2) +// +#define GPIO_0070_IROUTE IROUTE(24,10,2,2) +#define GPIO_0071_IROUTE IROUTE(25,10,2,2) +#define GPIO_0072_IROUTE IROUTE(26,10,2,2) +#define GPIO_0073_IROUTE IROUTE(27,10,2,2) +#define GPIO_0074_IROUTE IROUTE(28,10,2,2) +#define GPIO_0075_IROUTE IROUTE(29,10,2,2) +#define GPIO_0076_IROUTE IROUTE(30,10,2,2) + +// +// GIRQ11 +// +#define GPIO_0000_IROUTE IROUTE(0,11,3,3) +#define GPIO_0001_IROUTE IROUTE(1,11,3,3) +#define GPIO_0002_IROUTE IROUTE(2,11,3,3) +#define GPIO_0003_IROUTE IROUTE(3,11,3,3) +#define GPIO_0004_IROUTE IROUTE(4,11,3,3) +#define GPIO_0005_IROUTE IROUTE(5,11,3,3) +#define GPIO_0006_IROUTE IROUTE(6,11,3,3) +#define GPIO_0007_IROUTE IROUTE(7,11,3,3) +// +#define GPIO_0010_IROUTE IROUTE(8,11,3,3) +#define GPIO_0011_IROUTE IROUTE(9,11,3,3) +#define GPIO_0012_IROUTE IROUTE(10,11,3,3) +#define GPIO_0013_IROUTE IROUTE(11,11,3,3) +#define GPIO_0014_IROUTE IROUTE(12,11,3,3) +#define GPIO_0015_IROUTE IROUTE(13,11,3,3) +#define GPIO_0016_IROUTE IROUTE(14,11,3,3) +#define GPIO_0017_IROUTE IROUTE(15,11,3,3) +// +#define GPIO_0020_IROUTE IROUTE(16,11,3,3) +#define GPIO_0021_IROUTE IROUTE(17,11,3,3) +#define GPIO_0022_IROUTE IROUTE(18,11,3,3) +#define GPIO_0023_IROUTE IROUTE(19,11,3,3) +#define GPIO_0024_IROUTE IROUTE(20,11,3,3) +#define GPIO_0025_IROUTE IROUTE(21,11,3,3) +#define GPIO_0026_IROUTE IROUTE(22,11,3,3) +#define GPIO_0027_IROUTE IROUTE(23,11,3,3) +// +#define GPIO_0030_IROUTE IROUTE(24,11,3,3) +#define GPIO_0031_IROUTE IROUTE(25,11,3,3) +#define GPIO_0032_IROUTE IROUTE(26,11,3,3) +#define GPIO_0033_IROUTE IROUTE(27,11,3,3) +#define GPIO_0034_IROUTE IROUTE(28,11,3,3) +#define GPIO_0035_IROUTE IROUTE(29,11,3,3) +#define GPIO_0036_IROUTE IROUTE(30,11,3,3) + + +// GIRQ12 +// +#define GPIO_0200_IROUTE IROUTE(0,12,4,4) +#define GPIO_0201_IROUTE IROUTE(1,12,4,4) +#define GPIO_0202_IROUTE IROUTE(2,12,4,4) +#define GPIO_0203_IROUTE IROUTE(3,12,4,4) +#define GPIO_0204_IROUTE IROUTE(4,12,4,4) +#define GPIO_0205_IROUTE IROUTE(5,12,4,4) +#define GPIO_0206_IROUTE IROUTE(6,12,4,4) +#define GPIO_0207_IROUTE IROUTE(7,12,4,4) +// +#define GPIO_0210_IROUTE IROUTE(8,12,4,4) +#define GPIO_0211_IROUTE IROUTE(9,12,4,4) +#define GPIO_0212_IROUTE IROUTE(10,12,4,4) +#define GPIO_0213_IROUTE IROUTE(11,12,4,4) +#define GPIO_0214_IROUTE IROUTE(12,12,4,4) +#define GPIO_0215_IROUTE IROUTE(13,12,4,4) +#define GPIO_0216_IROUTE IROUTE(14,12,4,4) +#define GPIO_0217_IROUTE IROUTE(15,12,4,4) +// +#define GPIO_0220_IROUTE IROUTE(16,12,4,4) +#define GPIO_0221_IROUTE IROUTE(17,12,4,4) +#define GPIO_0222_IROUTE IROUTE(18,12,4,4) +#define GPIO_0223_IROUTE IROUTE(19,12,4,4) +#define GPIO_0224_IROUTE IROUTE(20,12,4,4) +#define GPIO_0225_IROUTE IROUTE(21,12,4,4) +#define GPIO_0226_IROUTE IROUTE(22,12,4,4) +#define GPIO_0227_IROUTE IROUTE(23,12,4,4) +// +#define GPIO_0230_IROUTE IROUTE(24,12,4,4) +#define GPIO_0231_IROUTE IROUTE(25,12,4,4) +#define GPIO_0232_IROUTE IROUTE(26,12,4,4) +#define GPIO_0233_IROUTE IROUTE(27,12,4,4) +#define GPIO_0234_IROUTE IROUTE(28,12,4,4) +#define GPIO_0235_IROUTE IROUTE(29,12,4,4) +#define GPIO_0236_IROUTE IROUTE(30,12,4,4) + + + +// +// GIRQ13 +// +#define SMB0_IROUTE IROUTE(0,13,5,20) +#define SMB1_IROUTE IROUTE(1,13,5,21) +#define SMB2_IROUTE IROUTE(2,13,5,22) +#define SMB3_IROUTE IROUTE(3,13,5,23) + +// +// GIRQ14 +// +#define DMA0_IROUTE IROUTE(0,14,6,24) +#define DMA1_IROUTE IROUTE(1,14,6,25) +#define DMA2_IROUTE IROUTE(2,14,6,26) +#define DMA3_IROUTE IROUTE(3,14,6,27) +#define DMA4_IROUTE IROUTE(4,14,6,28) +#define DMA5_IROUTE IROUTE(5,14,6,29) +#define DMA6_IROUTE IROUTE(6,14,6,30) +#define DMA7_IROUTE IROUTE(7,14,6,31) +#define DMA8_IROUTE IROUTE(8,14,6,33) +#define DMA9_IROUTE IROUTE(9,14,6,33) +#define DMA10_IROUTE IROUTE(10,14,6,34) +#define DMA11_IROUTE IROUTE(11,14,6,35) +#define DMA12_IROUTE IROUTE(12,14,6,36) +#define DMA13_IROUTE IROUTE(13,14,6,37) + + +// +// GIRQ15 +// +#define UART0_IROUTE IROUTE(0,15,7,40) +#define UART1_IROUTE IROUTE(1,15,7,41) +#define EMI0_IROUTE IROUTE(2,15,7,42) +#define EMI1_IROUTE IROUTE(3,15,7,43) +#define EMI2_IROUTE IROUTE(4,15,7,44) +#define ACPI_EC0_IBF_IROUTE IROUTE(5,15,7,45) +#define ACPI_EC0_OBF_IROUTE IROUTE(6,15,7,46) +#define ACPI_EC1_IBF_IROUTE IROUTE(7,15,7,47) +#define ACPI_EC1_OBF_IROUTE IROUTE(8,15,7,48) +#define ACPI_EC2_IBF_IROUTE IROUTE(9,15,7,49) +#define ACPI_EC2_OBF_IROUTE IROUTE(10,15,7,50) +#define ACPI_EC3_IBF_IROUTE IROUTE(11,15,7,51) +#define ACPI_EC3_OBF_IROUTE IROUTE(12,15,7,52) +#define ACPI_EC4_IBF_IROUTE IROUTE(13,15,7,53) +#define ACPI_EC4_OBF_IROUTE IROUTE(14,15,7,54) +#define ACPI_PM1_CTL_IROUTE IROUTE(15,15,7,55) +#define ACPI_PM1_EN_IROUTE IROUTE(16,15,7,56) +#define ACPI_PM1_STS_IROUTE IROUTE(17,15,7,57) +#define EM8042_OBF_IROUTE IROUTE(18,15,7,58) +#define EM8042_IBF_IROUTE IROUTE(19,15,7,59) +#define MBOX_IROUTE IROUTE(20,15,7,60) +#define PORT80_DBG0_BDPINT_IROUTE IROUTE(22,15,7,62) +#define PORT80_DBG1_BDPINT_IROUTE IROUTE(23,15,7,63) +#define TEST_IROUTE IROUTE(24,15,7,64) + +// +// GIRQ16 +// +#define PKE_ERROR_IROUTE IROUTE(0,16,8,65) +#define PKE_END_IROUTE IROUTE(1,16,8,66) +#define RNG_IROUTE IROUTE(2,16,8,67) +#define AES_IROUTE IROUTE(3,16,8,68) +#define HASH_IROUTE IROUTE(4,16,8,69) + +// +// GIRQ17 +// +#define PECI_IROUTE IROUTE(0,17,9,70) +#define TACH0_IROUTE IROUTE(1,17,9,71) +#define TACH1_IROUTE IROUTE(2,17,9,72) +#define TACH2_IROUTE IROUTE(3,17,9,73) +#define RPM2PWM0_FAIL_IROUTE IROUTE(4,17,9,74) +#define RPM2PWM0_STALL_IROUTE IROUTE(5,17,9,75) +#define RPM2PWM1_FAIL_IROUTE IROUTE(6,17,9,76) +#define RPM2PWM1_STALL_IROUTE IROUTE(7,17,9,77) +#define ADC_SNGL_IROUTE IROUTE(8,17,9,78) +#define ADC_RPT_IROUTE IROUTE(9,17,9,79) +#define RC_ID0_IROUTE IROUTE(10,17,9,80) +#define RC_ID1_IROUTE IROUTE(11,17,9,81) +#define RC_ID2_IROUTE IROUTE(12,17,9,82) +#define LED0_IROUTE IROUTE(13,17,9,83) +#define LED1_IROUTE IROUTE(14,17,9,84) +#define LED2_IROUTE IROUTE(15,17,9,85) +#define LED3_IROUTE IROUTE(16,17,9,86) +#define PHOT_IROUTE IROUTE(17,17,9,87) +#define POWER_GUARD0_IROUTE IROUTE(18,17,9,88) +#define POWER_GUARD1_IROUTE IROUTE(19,17,9,89) +#define RTOS_SWI0_IROUTE IROUTE(25,17,9,9) +#define RTOS_SWI1_IROUTE IROUTE(26,17,9,9) +#define RTOS_SWI2_IROUTE IROUTE(27,17,9,9) +#define RTOS_SWI3_IROUTE IROUTE(28,17,9,9) + +// +// GIRQ18 +// +#define LPC_INT_ERR_IROUTE IROUTE(0,18,10,90) +#define QMSPI_INT_IROUTE IROUTE(1,18,10,91) +#define GP_SPI0_TXBE_STS_IROUTE IROUTE(2,18,10,92) +#define GP_SPI0_RXBF_STS_IROUTE IROUTE(3,18,10,93) +#define GP_SPI1_TXBE_STS_IROUTE IROUTE(4,18,10,94) +#define GP_SPI1_RXBF_STS_IROUTE IROUTE(5,18,10,95) +#define BCLINK0_BCM_ERR_IROUTE IROUTE(6,18,10,96) +#define BCLINK0_BUSY_CLR_IROUTE IROUTE(7,18,10,97) +#define BCLINK1_BCM_ERR_IROUTE IROUTE(8,18,10,98) +#define BCLINK1_BUSY_CLR_IROUTE IROUTE(9,18,10,99) +#define PS2_IFACE0_ACT_IROUTE IROUTE(10,18,10,100) +#define PS2_IFACE1_ACT_IROUTE IROUTE(11,18,10,101) +#define PS2_IFACE2_ACT_IROUTE IROUTE(12,18,10,102) +#define EEPROM_IROUTE IROUTE(13,18,10,155) + + +// +// GIRQ19 +// +#define ESPI_SLAVE_INTR_PC_IROUTE IROUTE(0,19,11,103) +#define ESPI_SLAVE_INTR_BM1_IROUTE IROUTE(1,19,11,104) +#define ESPI_SLAVE_INTR_BM2_IROUTE IROUTE(2,19,11,105) +#define ESPI_SLAVE_INTR_LTR_IROUTE IROUTE(3,19,11,106) +#define ESPI_SLAVE_INTR_OOB_UP_IROUTE IROUTE(4,19,11,107) +#define ESPI_SLAVE_INTR_OOB_DN_IROUTE IROUTE(5,19,11,108) +#define ESPI_SLAVE_INTR_FLASH_IROUTE IROUTE(6,19,11,109) +#define ESPI_SLAVE_ESPI_RESET_IROUTE IROUTE(7,19,11,110) +#define ESPI_SLAVE_VW_ENABLE_IROUTE IROUTE(8,19,11,156) + +// +// GIRQ20 +// + + +// +// GIRQ21 +// +#define RTOS_TIMER_IROUTE IROUTE(0,21,13,111) +#define HTIMER0_IROUTE IROUTE(1,21,13,112) +#define HTIMER1_IROUTE IROUTE(2,21,13,113) +#define WEEK_ALARM_INT_IROUTE IROUTE(3,21,13,114) +#define SUB_WEEK_ALARM_IN_IROUTE IROUTE(4,21,13,115) +#define WEEK_ALARM_ONE_SECOND_IROUTE IROUTE(5,21,13,116) +#define WEEK_ALARM_SUB_SECOND_IROUTE IROUTE(6,21,13,117) +#define WEEK_ALARM_SYSPWR_PRES_IROUTE IROUTE(7,21,13,118) +#define RTC_IROUTE IROUTE(8,21,13,119) +#define RTC_ALARM_IROUTE IROUTE(9,21,13,120) +#define VBAT_VCI_OVRD_IN_IROUTE IROUTE(10,21,13,121) +#define VBAT_VCI_IN0_IROUTE IROUTE(11,21,13,122) +#define VBAT_VCI_IN1_IROUTE IROUTE(12,21,13,123) +#define VBAT_VCI_IN2_IROUTE IROUTE(13,21,13,124) +#define VBAT_VCI_IN3_IROUTE IROUTE(14,21,13,125) +#define VBAT_VCI_IN4_IROUTE IROUTE(15,21,13,126) +#define VBAT_VCI_IN5_IROUTE IROUTE(16,21,13,127) +#define VBAT_VCI_IN6_IROUTE IROUTE(17,21,13,128) +#define PS2_0A_WK_IROUTE IROUTE(18,21,13,129) +#define PS2_0B_WK_IROUTE IROUTE(19,21,13,130) +#define PS2_1A_WK_IROUTE IROUTE(20,21,13,131) +#define PS2_1B_WK_IROUTE IROUTE(21,21,13,132) +#define PS2_2_WK_IROUTE IROUTE(22,21,13,133) +#define ENVMON_IROUTE IROUTE(24,21,13,134) +#define KSC_INT_IROUTE IROUTE(25,21,13,135) + + +// +// GIRQ22 (No Aggregated & No direct source, WAKE ONLY EVENTS) +// +#define LPC_WAKE_ONLY_IROUTE IROUTE(0,22,22,22) +#define SMB0_WAKE_ONLY_IROUTE IROUTE(1,22,22,22) +#define SMB1_WAKE_ONLY_IROUTE IROUTE(2,22,22,22) +#define SMB2_WAKE_ONLY_IROUTE IROUTE(3,22,22,22) +#define SMB3_WAKE_ONLY_IROUTE IROUTE(4,22,22,22) +#define ESPI_WAKE_ONLY_IROUTE IROUTE(9,22,22,22) + +// +// GIRQ23 +// +#define BTMR0_IROUTE IROUTE(0,23,14,136) +#define BTMR1_IROUTE IROUTE(1,23,14,137) +#define BTMR2_IROUTE IROUTE(2,23,14,138) +#define BTMR3_IROUTE IROUTE(3,23,14,139) +#define BTMR4_IROUTE IROUTE(4,23,14,140) +#define BTMR5_IROUTE IROUTE(5,23,14,141) +#define CTIMER0_IROUTE IROUTE(6,23,14,142) +#define CTIMER1_IROUTE IROUTE(7,23,14,143) +#define CTIMER2_IROUTE IROUTE(8,23,14,144) +#define CTIMER3_IROUTE IROUTE(9,23,14,145) +#define CAP_TIMER_IROUTE IROUTE(10,23,14,146) +#define CC_TIMER0_IROUTE IROUTE(11,23,14,147) +#define CC_TIMER1_IROUTE IROUTE(12,23,14,148) +#define CC_TIMER2_IROUTE IROUTE(13,23,14,149) +#define CC_TIMER3_IROUTE IROUTE(14,23,14,150) +#define CC_TIMER4_IROUTE IROUTE(15,23,14,151) +#define CC_TIMER5_IROUTE IROUTE(16,23,14,152) +#define CC_TIMER_CMP0_IROUTE IROUTE(17,23,14,153) +#define CC_TIMER_CMP1_IROUTE IROUTE(18,23,14,154) + +// +// GIRQ23 +// +#define ESPI_SLAVE_VW00_SRC0_IROUTE IROUTE(0,24,15,15) +#define ESPI_SLAVE_VW00_SRC1_IROUTE IROUTE(1,24,15,15) +#define ESPI_SLAVE_VW00_SRC2_IROUTE IROUTE(2,24,15,15) +#define ESPI_SLAVE_VW00_SRC3_IROUTE IROUTE(3,24,15,15) +#define ESPI_SLAVE_VW01_SRC0_IROUTE IROUTE(4,24,15,15) +#define ESPI_SLAVE_VW01_SRC1_IROUTE IROUTE(5,24,15,15) +#define ESPI_SLAVE_VW01_SRC2_IROUTE IROUTE(6,24,15,15) +#define ESPI_SLAVE_VW01_SRC3_IROUTE IROUTE(7,24,15,15) +#define ESPI_SLAVE_VW02_SRC0_IROUTE IROUTE(8,24,15,15) +#define ESPI_SLAVE_VW02_SRC1_IROUTE IROUTE(9,24,15,15) +#define ESPI_SLAVE_VW02_SRC2_IROUTE IROUTE(10,24,15,15) +#define ESPI_SLAVE_VW02_SRC3_IROUTE IROUTE(11,24,15,15) +#define ESPI_SLAVE_VW03_SRC0_IROUTE IROUTE(12,24,15,15) +#define ESPI_SLAVE_VW03_SRC1_IROUTE IROUTE(13,24,15,15) +#define ESPI_SLAVE_VW03_SRC2_IROUTE IROUTE(14,24,15,15) +#define ESPI_SLAVE_VW03_SRC3_IROUTE IROUTE(15,24,15,15) +#define ESPI_SLAVE_VW04_SRC0_IROUTE IROUTE(16,24,15,15) +#define ESPI_SLAVE_VW04_SRC1_IROUTE IROUTE(17,24,15,15) +#define ESPI_SLAVE_VW04_SRC2_IROUTE IROUTE(18,24,15,15) +#define ESPI_SLAVE_VW04_SRC3_IROUTE IROUTE(19,24,15,15) +#define ESPI_SLAVE_VW05_SRC0_IROUTE IROUTE(20,24,15,15) +#define ESPI_SLAVE_VW05_SRC1_IROUTE IROUTE(21,24,15,15) +#define ESPI_SLAVE_VW05_SRC2_IROUTE IROUTE(22,24,15,15) +#define ESPI_SLAVE_VW05_SRC3_IROUTE IROUTE(23,24,15,15) +#define ESPI_SLAVE_VW06_SRC0_IROUTE IROUTE(24,24,15,15) +#define ESPI_SLAVE_VW06_SRC1_IROUTE IROUTE(25,24,15,15) +#define ESPI_SLAVE_VW06_SRC2_IROUTE IROUTE(26,24,15,15) +#define ESPI_SLAVE_VW06_SRC3_IROUTE IROUTE(27,24,15,15) + + +// +// GIRQ25 +// +#define ESPI_SLAVE_VW07_SRC0_IROUTE IROUTE(0,25,15,15) +#define ESPI_SLAVE_VW07_SRC1_IROUTE IROUTE(1,25,15,15) +#define ESPI_SLAVE_VW07_SRC2_IROUTE IROUTE(2,25,15,15) +#define ESPI_SLAVE_VW07_SRC3_IROUTE IROUTE(3,25,15,15) +#define ESPI_SLAVE_VW08_SRC0_IROUTE IROUTE(4,25,15,15) +#define ESPI_SLAVE_VW08_SRC1_IROUTE IROUTE(5,25,15,15) +#define ESPI_SLAVE_VW08_SRC2_IROUTE IROUTE(6,25,15,15) +#define ESPI_SLAVE_VW08_SRC3_IROUTE IROUTE(7,25,15,15) +#define ESPI_SLAVE_VW09_SRC0_IROUTE IROUTE(8,25,15,15) +#define ESPI_SLAVE_VW09_SRC1_IROUTE IROUTE(9,25,15,15) +#define ESPI_SLAVE_VW09_SRC2_IROUTE IROUTE(10,25,15,15) +#define ESPI_SLAVE_VW09_SRC3_IROUTE IROUTE(11,25,15,15) +#define ESPI_SLAVE_VW10_SRC0_IROUTE IROUTE(12,25,15,15) +#define ESPI_SLAVE_VW10_SRC1_IROUTE IROUTE(13,25,15,15) +#define ESPI_SLAVE_VW10_SRC2_IROUTE IROUTE(14,25,15,15) +#define ESPI_SLAVE_VW10_SRC3_IROUTE IROUTE(15,25,15,15) + +// +// GIRQ26 +// +#define GPIO_0240_IROUTE IROUTE(0,26,17,17) +#define GPIO_0241_IROUTE IROUTE(1,26,17,17) +#define GPIO_0242_IROUTE IROUTE(2,26,17,17) +#define GPIO_0243_IROUTE IROUTE(3,26,17,17) +#define GPIO_0244_IROUTE IROUTE(4,26,17,17) +#define GPIO_0245_IROUTE IROUTE(5,26,17,17) +#define GPIO_0246_IROUTE IROUTE(6,26,17,17) +#define GPIO_0247_IROUTE IROUTE(7,26,17,17) +// +#define GPIO_0250_IROUTE IROUTE(8,26,17,17) +#define GPIO_0251_IROUTE IROUTE(9,26,17,17) +#define GPIO_0252_IROUTE IROUTE(10,26,17,17) +#define GPIO_0253_IROUTE IROUTE(11,26,17,17) +#define GPIO_0254_IROUTE IROUTE(12,26,17,17) +#define GPIO_0255_IROUTE IROUTE(13,26,17,17) +#define GPIO_0256_IROUTE IROUTE(14,26,17,17) +#define GPIO_0257_IROUTE IROUTE(15,26,17,17) +// +#define GPIO_0260_IROUTE IROUTE(16,26,17,17) +#define GPIO_0261_IROUTE IROUTE(17,26,17,17) +#define GPIO_0262_IROUTE IROUTE(18,26,17,17) +#define GPIO_0263_IROUTE IROUTE(19,26,17,17) +#define GPIO_0264_IROUTE IROUTE(20,26,17,17) +#define GPIO_0265_IROUTE IROUTE(21,26,17,17) +#define GPIO_0266_IROUTE IROUTE(22,26,17,17) +#define GPIO_0267_IROUTE IROUTE(23,26,17,17) +// +#define GPIO_0270_IROUTE IROUTE(24,26,17,17) +#define GPIO_0271_IROUTE IROUTE(25,26,17,17) +#define GPIO_0272_IROUTE IROUTE(26,26,17,17) +#define GPIO_0273_IROUTE IROUTE(27,26,17,17) +#define GPIO_0274_IROUTE IROUTE(28,26,17,17) +#define GPIO_0275_IROUTE IROUTE(29,26,17,17) +#define GPIO_0276_IROUTE IROUTE(30,26,17,17) + + +// GIRQ08 Bit Positions +#define GIRQ08_GPIO_0140_BITPOS (0) +#define GIRQ08_GPIO_0141_BITPOS (1) +#define GIRQ08_GPIO_0142_BITPOS (2) +#define GIRQ08_GPIO_0143_BITPOS (3) +#define GIRQ08_GPIO_0144_BITPOS (4) +#define GIRQ08_GPIO_0145_BITPOS (5) +#define GIRQ08_GPIO_0146_BITPOS (6) +#define GIRQ08_GPIO_0147_BITPOS (7) +// +#define GIRQ08_GPIO_0150_BITPOS (8) +#define GIRQ08_GPIO_0151_BITPOS (9) +#define GIRQ08_GPIO_0152_BITPOS (10) +#define GIRQ08_GPIO_0153_BITPOS (11) +#define GIRQ08_GPIO_0154_BITPOS (12) +#define GIRQ08_GPIO_0155_BITPOS (13) +#define GIRQ08_GPIO_0156_BITPOS (14) +#define GIRQ08_GPIO_0157_BITPOS (15) +// +#define GIRQ08_GPIO_0160_BITPOS (16) +#define GIRQ08_GPIO_0161_BITPOS (17) +#define GIRQ08_GPIO_0162_BITPOS (18) +#define GIRQ08_GPIO_0163_BITPOS (19) +#define GIRQ08_GPIO_0164_BITPOS (20) +#define GIRQ08_GPIO_0165_BITPOS (21) +#define GIRQ08_GPIO_0166_BITPOS (22) +#define GIRQ08_GPIO_0167_BITPOS (23) + +#define GIRQ08_GPIO_0170_BITPOS (24) +#define GIRQ08_GPIO_0171_BITPOS (25) +#define GIRQ08_GPIO_0172_BITPOS (26) +#define GIRQ08_GPIO_0173_BITPOS (27) +#define GIRQ08_GPIO_0174_BITPOS (28) +#define GIRQ08_GPIO_0175_BITPOS (29) +#define GIRQ08_GPIO_0176_BITPOS (30) + +// +#define GIRQ08_MASK (0x7FFFFFFFul) +#define GIRQ08_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ09 Bit Positions +#define GIRQ09_GPIO_0100_BITPOS (0) +#define GIRQ09_GPIO_0101_BITPOS (1) +#define GIRQ09_GPIO_0102_BITPOS (2) +#define GIRQ09_GPIO_0103_BITPOS (3) +#define GIRQ09_GPIO_0104_BITPOS (4) +#define GIRQ09_GPIO_0105_BITPOS (5) +#define GIRQ09_GPIO_0106_BITPOS (6) +#define GIRQ09_GPIO_0107_BITPOS (7) +// +#define GIRQ09_GPIO_0110_BITPOS (8) +#define GIRQ09_GPIO_0111_BITPOS (9) +#define GIRQ09_GPIO_0112_BITPOS (10) +#define GIRQ09_GPIO_0113_BITPOS (11) +#define GIRQ09_GPIO_0114_BITPOS (12) +#define GIRQ09_GPIO_0115_BITPOS (13) +#define GIRQ09_GPIO_0116_BITPOS (14) +#define GIRQ09_GPIO_0117_BITPOS (15) +// +#define GIRQ09_GPIO_0120_BITPOS (16) +#define GIRQ09_GPIO_0121_BITPOS (17) +#define GIRQ09_GPIO_0122_BITPOS (18) +#define GIRQ09_GPIO_0123_BITPOS (19) +#define GIRQ09_GPIO_0124_BITPOS (20) +#define GIRQ09_GPIO_0125_BITPOS (21) +#define GIRQ09_GPIO_0126_BITPOS (22) +#define GIRQ09_GPIO_0127_BITPOS (23) +// +#define GIRQ09_GPIO_0130_BITPOS (24) +#define GIRQ09_GPIO_0131_BITPOS (25) +#define GIRQ09_GPIO_0132_BITPOS (26) +#define GIRQ09_GPIO_0133_BITPOS (27) +#define GIRQ09_GPIO_0134_BITPOS (28) +#define GIRQ09_GPIO_0135_BITPOS (29) +#define GIRQ09_GPIO_0136_BITPOS (30) + +// +#define GIRQ09_MASK (0x7FFFFFFFul) +#define GIRQ09_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ10 Bit Positions +#define GIRQ10_GPIO_0040_BITPOS (0) +#define GIRQ10_GPIO_0041_BITPOS (1) +#define GIRQ10_GPIO_0042_BITPOS (2) +#define GIRQ10_GPIO_0043_BITPOS (3) +#define GIRQ10_GPIO_0044_BITPOS (4) +#define GIRQ10_GPIO_0045_BITPOS (5) +#define GIRQ10_GPIO_0046_BITPOS (6) +#define GIRQ10_GPIO_0047_BITPOS (7) +// +#define GIRQ10_GPIO_0050_BITPOS (8) +#define GIRQ10_GPIO_0051_BITPOS (9) +#define GIRQ10_GPIO_0052_BITPOS (10) +#define GIRQ10_GPIO_0053_BITPOS (11) +#define GIRQ10_GPIO_0054_BITPOS (12) +#define GIRQ10_GPIO_0055_BITPOS (13) +#define GIRQ10_GPIO_0056_BITPOS (14) +#define GIRQ10_GPIO_0057_BITPOS (15) +// +#define GIRQ10_GPIO_0060_BITPOS (16) +#define GIRQ10_GPIO_0061_BITPOS (17) +#define GIRQ10_GPIO_0062_BITPOS (18) +#define GIRQ10_GPIO_0063_BITPOS (19) +#define GIRQ10_GPIO_0064_BITPOS (20) +#define GIRQ10_GPIO_0065_BITPOS (21) +#define GIRQ10_GPIO_0066_BITPOS (22) +#define GIRQ10_GPIO_0067_BITPOS (23) +// +#define GIRQ10_GPIO_0070_BITPOS (24) +#define GIRQ10_GPIO_0071_BITPOS (25) +#define GIRQ10_GPIO_0072_BITPOS (26) +#define GIRQ10_GPIO_0073_BITPOS (27) +#define GIRQ10_GPIO_0074_BITPOS (28) +#define GIRQ10_GPIO_0075_BITPOS (29) +#define GIRQ10_GPIO_0076_BITPOS (30) + +// +#define GIRQ10_MASK (0x7FFFFFFFul) +#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ11 Bit Positions +#define GIRQ11_GPIO_0000_BITPOS (0) +#define GIRQ11_GPIO_0001_BITPOS (1) +#define GIRQ11_GPIO_0002_BITPOS (2) +#define GIRQ11_GPIO_0003_BITPOS (3) +#define GIRQ11_GPIO_0004_BITPOS (4) +#define GIRQ11_GPIO_0005_BITPOS (5) +#define GIRQ11_GPIO_0006_BITPOS (6) +#define GIRQ11_GPIO_0007_BITPOS (7) +// +#define GIRQ11_GPIO_0010_BITPOS (8) +#define GIRQ11_GPIO_0011_BITPOS (9) +#define GIRQ11_GPIO_0012_BITPOS (10) +#define GIRQ11_GPIO_0013_BITPOS (11) +#define GIRQ11_GPIO_0014_BITPOS (12) +#define GIRQ11_GPIO_0015_BITPOS (13) +#define GIRQ11_GPIO_0016_BITPOS (14) +#define GIRQ11_GPIO_0017_BITPOS (15) +// +#define GIRQ11_GPIO_0020_BITPOS (16) +#define GIRQ11_GPIO_0021_BITPOS (17) +#define GIRQ11_GPIO_0022_BITPOS (18) +#define GIRQ11_GPIO_0023_BITPOS (19) +#define GIRQ11_GPIO_0024_BITPOS (20) +#define GIRQ11_GPIO_0025_BITPOS (21) +#define GIRQ11_GPIO_0026_BITPOS (22) +#define GIRQ11_GPIO_0027_BITPOS (23) +// +#define GIRQ11_GPIO_0030_BITPOS (24) +#define GIRQ11_GPIO_0031_BITPOS (25) +#define GIRQ11_GPIO_0032_BITPOS (26) +#define GIRQ11_GPIO_0033_BITPOS (27) +#define GIRQ11_GPIO_0034_BITPOS (28) +#define GIRQ11_GPIO_0035_BITPOS (29) +#define GIRQ11_GPIO_0036_BITPOS (30) + +// +#define GIRQ11_MASK (0x7FFFFFFFul) +#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ12 Bit Positions +#define GIRQ12_GPIO_0200_BITPOS (0) +#define GIRQ12_GPIO_0201_BITPOS (1) +#define GIRQ12_GPIO_0202_BITPOS (2) +#define GIRQ12_GPIO_0203_BITPOS (3) +#define GIRQ12_GPIO_0204_BITPOS (4) +#define GIRQ12_GPIO_0205_BITPOS (5) +#define GIRQ12_GPIO_0206_BITPOS (6) +#define GIRQ12_GPIO_0207_BITPOS (7) +// +#define GIRQ12_GPIO_0210_BITPOS (8) +#define GIRQ12_GPIO_0211_BITPOS (9) +#define GIRQ12_GPIO_0212_BITPOS (10) +#define GIRQ12_GPIO_0213_BITPOS (11) +#define GIRQ12_GPIO_0214_BITPOS (12) +#define GIRQ12_GPIO_0215_BITPOS (13) +#define GIRQ12_GPIO_0216_BITPOS (14) +#define GIRQ12_GPIO_0217_BITPOS (15) +// +#define GIRQ12_GPIO_0220_BITPOS (16) +#define GIRQ12_GPIO_0221_BITPOS (17) +#define GIRQ12_GPIO_0222_BITPOS (18) +#define GIRQ12_GPIO_0223_BITPOS (19) +#define GIRQ12_GPIO_0224_BITPOS (20) +#define GIRQ12_GPIO_0225_BITPOS (21) +#define GIRQ12_GPIO_0226_BITPOS (22) +#define GIRQ12_GPIO_0227_BITPOS (23) +// +#define GIRQ12_GPIO_0230_BITPOS (24) +#define GIRQ12_GPIO_0231_BITPOS (25) +#define GIRQ12_GPIO_0232_BITPOS (26) +#define GIRQ12_GPIO_0233_BITPOS (27) +#define GIRQ12_GPIO_0234_BITPOS (28) +#define GIRQ12_GPIO_0235_BITPOS (29) +#define GIRQ12_GPIO_0236_BITPOS (30) + +// +#define GIRQ12_MASK (0x7FFFFFFFul) +#define GIRQ12_WAKE_CAPABLE_MASK (0x7FFFFFFFul) + +// GIRQ13 Bit Positions +#define GIRQ13_SMBUS0_BITPOS (0) +#define GIRQ13_SMBUS1_BITPOS (1) +#define GIRQ13_SMBUS2_BITPOS (2) +#define GIRQ13_SMBUS3_BITPOS (3) + +#define GIRQ13_MASK (0xFul) +#define GIRQ13_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ14 Bit Positions +#define GIRQ14_DMA0_BITPOS (0) +#define GIRQ14_DMA1_BITPOS (1) +#define GIRQ14_DMA2_BITPOS (2) +#define GIRQ14_DMA3_BITPOS (3) +#define GIRQ14_DMA4_BITPOS (4) +#define GIRQ14_DMA5_BITPOS (5) +#define GIRQ14_DMA6_BITPOS (6) +#define GIRQ14_DMA7_BITPOS (7) +#define GIRQ14_DMA8_BITPOS (8) +#define GIRQ14_DMA9_BITPOS (9) +#define GIRQ14_DMA10_BITPOS (10) +#define GIRQ14_DMA11_BITPOS (11) +#define GIRQ14_DMA12_BITPOS (12) +#define GIRQ14_DMA13_BITPOS (13) +// +#define GIRQ14_MASK (0x3FFFul) +#define GIRQ14_WAKE_CAPABLE_MASK (0x00000000ul) +// + + +// GIRQ15 Bit Positions +#define GIRQ15_UART0_BITPOS (0) +#define GIRQ15_UART1_BITPOS (1) +#define GIRQ15_EMI0_BITPOS (2) +#define GIRQ15_EMI1_BITPOS (3) +#define GIRQ15_EMI2_BITPOS (4) +#define GIRQ15_ACPI0_IBF_BITPOS (5) +#define GIRQ15_ACPI0_OBF_BITPOS (6) +#define GIRQ15_ACPI1_IBF_BITPOS (7) +#define GIRQ15_ACPI1_OBF_BITPOS (8) +#define GIRQ15_ACPI2_IBF_BITPOS (9) +#define GIRQ15_ACPI2_OBF_BITPOS (10) +#define GIRQ15_ACPI3_IBF_BITPOS (11) +#define GIRQ15_ACPI3_OBF_BITPOS (12) +#define GIRQ15_ACPI4_IBF_BITPOS (13) +#define GIRQ15_ACPI4_OBF_BITPOS (14) +#define GIRQ15_ACPI_PM1CTL_BITPOS (15) +#define GIRQ15_ACPI_PM1EN_BITPOS (16) +#define GIRQ15_ACPI_PM1STS_BITPOS (17) +#define GIRQ15_MF8042_OBF_BITPOS (18) +#define GIRQ15_MF8042_IBF_BITPOS (19) +#define GIRQ15_MAILBOX_BITPOS (20) +#define GIRQ15_PORT80_DBG0_BITPOS (22) +#define GIRQ15_PORT80_DBG1_BITPOS (23) +#define GIRQ15_TEST_BITPOS (24) + +// +#define GIRQ15_MASK (0x1FFFFFFul) +#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul) +// + +// GIRQ16 Bit Positions +#define PKE_ERROR_BITPOS (0) +#define PKE_END_BITPOS (1) +#define RNG_BITPOS (2) +#define AES_BITPOS (3) +#define HASH_BITPOS (4) + +// +#define GIRQ16_MASK (0x1Ful) +#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul) +// + +// GIRQ17 Bit Positions +#define GIRQ17_PECI_BITPOS (0) +#define GIRQ17_TACH0_BITPOS (1) +#define GIRQ17_TACH1_BITPOS (2) +#define GIRQ17_TACH2_BITPOS (3) +#define GIRQ17_RPM2PWM0_FAIL_BITPOS (4) +#define GIRQ17_RPM2PWM0_STALL_BITPOS (5) +#define GIRQ17_RPM2PWM1_FAIL_BITPOS (6) +#define GIRQ17_RPM2PWM1_STALL_BITPOS (7) +#define GIRQ17_ADC_INT0_BITPOS (8) +#define GIRQ17_ADC_INT1_BITPOS (9) +#define GIRQ17_RC_ID0_BITPOS (10) +#define GIRQ17_RC_ID1_BITPOS (11) +#define GIRQ17_RC_ID2_BITPOS (12) +#define GIRQ17_LED0_BITPOS (13) +#define GIRQ17_LED1_BITPOS (14) +#define GIRQ17_LED2_BITPOS (15) +#define GIRQ17_LED3_BITPOS (16) +#define GIRQ17_PHOT_BITPOS (17) +#define GIRQ17_PWRGUARD0_BITPOS (18) +#define GIRQ17_PWRGUARD1_BITPOS (19) +#define GIRQ17_RTOS_SWI0_BITPOS (25) +#define GIRQ17_RTOS_SWI1_BITPOS (26) +#define GIRQ17_RTOS_SWI2_BITPOS (27) +#define GIRQ17_RTOS_SWI3_BITPOS (28) + +// +#define GIRQ17_MASK (0x1E0FFFFFul) +#define GIRQ17_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ18 Bit Positions +#define GIRQ18_LPC_ERROR_BITPOS (0) +#define GIRQ18_QMSPI_INT_BITPOS (1) +#define GIRQ18_SPI0_TX_BITPOS (2) +#define GIRQ18_SPI0_RX_BITPOS (3) +#define GIRQ18_SPI1_TX_BITPOS (4) +#define GIRQ18_SPI1_RX_BITPOS (5) +#define GIRQ18_BCM0_BUSY_CLR_BITPOS (6) +#define GIRQ18_BCM0_ERROR_BITPOS (7) +#define GIRQ18_BCM1_BUSY_CLR_BITPOS (8) +#define GIRQ18_BCM1_ERROR_BITPOS (9) +#define GIRQ18_PS2_ACT0_BITPOS (10) +#define GIRQ18_PS2_ACT1_BITPOS (11) +#define GIRQ18_PS2_ACT2_BITPOS (12) +#define GIRQ18_EEPROM_BITPOS (13) + +// +#define GIRQ18_MASK (0x3FFFul) +#define GIRQ18_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ19 Bit Positions +#define GIRQ19_ESPI_INTR_PC_BITPOS (0) +#define GIRQ19_ESPI_INTR_BM1_BITPOS (1) +#define GIRQ19_ESPI_INTR_BM2_BITPOS (2) +#define GIRQ19_ESPI_INTR_LTR_BITPOS (3) +#define GIRQ19_ESPI_INTR_OOB_UP_BITPOS (4) +#define GIRQ19_ESPI_INTR_OOB_DN_BITPOS (5) +#define GIRQ19_ESPI_INTR_FLASH_BITPOS (6) +#define GIRQ19_ESPI_RESET_BITPOS (7) +#define GIRQ19_ESPI_VW_ENABLE_BITPOS (8) + +// +#define GIRQ19_MASK (0x01FFul) +#define GIRQ19_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ20 Bit Positions + +// +#define GIRQ20_MASK (0x0ul) +#define GIRQ20_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ21 Bit Positions +#define GIRQ21_RTOS_TIMER_BITPOS (0) +#define GIRQ21_HTIMER0_BITPOS (1) +#define GIRQ21_HTIMER1_BITPOS (2) +#define GIRQ21_WEEK_ALRM_INT_BITPOS (3) +#define GIRQ21_SUB_WEEK_ALRM_INT_BITPOS (4) +#define GIRQ21_ONE_SECOND_BITPOS (5) +#define GIRQ21_SUB_SECOND_BITPOS (6) +#define GIRQ21_SYSPWR_PRES_BITPOS (7) +#define GIRQ21_RTC_BITPOS (8) +#define GIRQ21_RTC_ALARM_BITPOS (9) +#define GIRQ21_VBAT_VCI_OVRD_IN_BITPOS (10) +#define GIRQ21_VBAT_VCI_IN0_BITPOS (11) +#define GIRQ21_VBAT_VCI_IN1_BITPOS (12) +#define GIRQ21_VBAT_VCI_IN2_BITPOS (13) +#define GIRQ21_VBAT_VCI_IN3_BITPOS (14) +#define GIRQ21_VBAT_VCI_IN4_BITPOS (15) +#define GIRQ21_VBAT_VCI_IN5_BITPOS (16) +#define GIRQ21_VBAT_VCI_IN6_BITPOS (17) +#define GIRQ21_PS2_0A_WK_BITPOS (18) +#define GIRQ21_PS2_0B_WK_BITPOS (19) +#define GIRQ21_PS2_1A_WK_BITPOS (20) +#define GIRQ21_PS2_1B_WK_BITPOS (21) +#define GIRQ21_PS2_2_WK_BITPOS (22) +#define GIRQ21_ENVMON_BITPOS (24) +#define GIRQ21_KSC_INT_BITPOS (25) + +// +#define GIRQ21_MASK (0x37FFFFFul) +#define GIRQ21_WAKE_CAPABLE_MASK (0x37FFFFFul) +// + +// GIRQ22 Bit Positions +#define GIRQ22_LPC_WAKE_ONLY_BITPOS (0) +#define GIRQ22_SMB0_WAKE_ONLY_BITPOS (1) +#define GIRQ22_SMB1_WAKE_ONLY_BITPOS (2) +#define GIRQ22_SMB2_WAKE_ONLY_BITPOS (3) +#define GIRQ22_SMB3_WAKE_ONLY_BITPOS (4) +#define GIRQ22_ESPI_WAKE_ONLY_BITPOS (9) + +#define GIRQ22_MASK (0x021Ful) +#define GIRQ22_WAKE_CAPABLE_MASK (0x021Ful) + +// GIRQ23 Bit Positions +#define GIRQ23_TMR0_BITPOS (0) +#define GIRQ23_TMR1_BITPOS (1) +#define GIRQ23_TMR2_BITPOS (2) +#define GIRQ23_TMR3_BITPOS (3) +#define GIRQ23_TMR4_BITPOS (4) +#define GIRQ23_TMR5_BITPOS (5) +#define GIRQ23_CTIMER0_BITPOS (6) +#define GIRQ23_CTIMER1_BITPOS (7) +#define GIRQ23_CTIMER2_BITPOS (8) +#define GIRQ23_CTIMER3_BITPOS (9) +#define GIRQ23_CAP_TIMER_BITPOS (10) +#define GIRQ23_CCTIMER0_BITPOS (11) +#define GIRQ23_CCTIMER1_BITPOS (12) +#define GIRQ23_CCTIMER2_BITPOS (13) +#define GIRQ23_CCTIMER3_BITPOS (14) +#define GIRQ23_CCTIMER4_BITPOS (15) +#define GIRQ23_CCTIMER5_BITPOS (16) +#define GIRQ23_CCTIMER6_BITPOS (17) +#define GIRQ23_CCTIMER7_BITPOS (18) + +// +#define GIRQ23_MASK (0x07FFFFul) +#define GIRQ23_WAKE_CAPABLE_MASK (0x0ul) +// + +// GIRQ24 Bit Positions +#define GIRQ24_ESPI_VW00_SRC0_BITPOS (0) +#define GIRQ24_ESPI_VW00_SRC1_BITPOS (1) +#define GIRQ24_ESPI_VW00_SRC2_BITPOS (2) +#define GIRQ24_ESPI_VW00_SRC3_BITPOS (3) +#define GIRQ24_ESPI_VW01_SRC0_BITPOS (4) +#define GIRQ24_ESPI_VW01_SRC1_BITPOS (5) +#define GIRQ24_ESPI_VW01_SRC2_BITPOS (6) +#define GIRQ24_ESPI_VW01_SRC3_BITPOS (7) +#define GIRQ24_ESPI_VW02_SRC0_BITPOS (8) +#define GIRQ24_ESPI_VW02_SRC1_BITPOS (9) +#define GIRQ24_ESPI_VW02_SRC2_BITPOS (10) +#define GIRQ24_ESPI_VW02_SRC3_BITPOS (11) +#define GIRQ24_ESPI_VW03_SRC0_BITPOS (12) +#define GIRQ24_ESPI_VW03_SRC1_BITPOS (13) +#define GIRQ24_ESPI_VW03_SRC2_BITPOS (14) +#define GIRQ24_ESPI_VW03_SRC3_BITPOS (15) +#define GIRQ24_ESPI_VW04_SRC0_BITPOS (16) +#define GIRQ24_ESPI_VW04_SRC1_BITPOS (17) +#define GIRQ24_ESPI_VW04_SRC2_BITPOS (18) +#define GIRQ24_ESPI_VW04_SRC3_BITPOS (19) +#define GIRQ24_ESPI_VW05_SRC0_BITPOS (20) +#define GIRQ24_ESPI_VW05_SRC1_BITPOS (21) +#define GIRQ24_ESPI_VW05_SRC2_BITPOS (22) +#define GIRQ24_ESPI_VW05_SRC3_BITPOS (23) +#define GIRQ24_ESPI_VW06_SRC0_BITPOS (24) +#define GIRQ24_ESPI_VW06_SRC1_BITPOS (25) +#define GIRQ24_ESPI_VW06_SRC2_BITPOS (26) +#define GIRQ24_ESPI_VW06_SRC3_BITPOS (27) + +// +#define GIRQ24_MASK (0x0FFFFFFFul) +#define GIRQ24_WAKE_CAPABLE_MASK (0x0FFFFFFFul) +// + +// GIRQ25 Bit Positions +#define GIRQ25_ESPI_VW07_SRC0_BITPOS (0) +#define GIRQ25_ESPI_VW07_SRC1_BITPOS (1) +#define GIRQ25_ESPI_VW07_SRC2_BITPOS (2) +#define GIRQ25_ESPI_VW07_SRC3_BITPOS (3) +#define GIRQ25_ESPI_VW08_SRC0_BITPOS (4) +#define GIRQ25_ESPI_VW08_SRC1_BITPOS (5) +#define GIRQ25_ESPI_VW08_SRC2_BITPOS (6) +#define GIRQ25_ESPI_VW08_SRC3_BITPOS (7) +#define GIRQ25_ESPI_VW09_SRC0_BITPOS (8) +#define GIRQ25_ESPI_VW09_SRC1_BITPOS (9) +#define GIRQ25_ESPI_VW09_SRC2_BITPOS (10) +#define GIRQ25_ESPI_VW09_SRC3_BITPOS (11) +#define GIRQ25_ESPI_VW10_SRC0_BITPOS (12) +#define GIRQ25_ESPI_VW10_SRC1_BITPOS (13) +#define GIRQ25_ESPI_VW10_SRC2_BITPOS (14) +#define GIRQ25_ESPI_VW10_SRC3_BITPOS (15) + +// +#define GIRQ25_MASK (0x0FFFFul) +#define GIRQ25_WAKE_CAPABLE_MASK (0x0FFFFul) +// + +// GIRQ26 bit positions +#define GIRQ26_GPIO240_BITPOS (0) +#define GIRQ26_GPIO241_BITPOS (1) +#define GIRQ26_GPIO242_BITPOS (2) +#define GIRQ26_GPIO243_BITPOS (3) +#define GIRQ26_GPIO244_BITPOS (4) +#define GIRQ26_GPIO245_BITPOS (5) +#define GIRQ26_GPIO246_BITPOS (6) +#define GIRQ26_GPIO247_BITPOS (7) + +#define GIRQ26_GPIO250_BITPOS (8) +#define GIRQ26_GPIO251_BITPOS (9) +#define GIRQ26_GPIO252_BITPOS (10) +#define GIRQ26_GPIO253_BITPOS (11) +#define GIRQ26_GPIO254_BITPOS (12) +#define GIRQ26_GPIO255_BITPOS (13) +#define GIRQ26_GPIO256_BITPOS (14) +#define GIRQ26_GPIO257_BITPOS (15) + +#define GIRQ26_GPIO260_BITPOS (16) +#define GIRQ26_GPIO261_BITPOS (17) +#define GIRQ26_GPIO262_BITPOS (18) +#define GIRQ26_GPIO263_BITPOS (19) +#define GIRQ26_GPIO264_BITPOS (20) +#define GIRQ26_GPIO265_BITPOS (21) +#define GIRQ26_GPIO266_BITPOS (22) +#define GIRQ26_GPIO267_BITPOS (23) + +#define GIRQ26_GPIO270_BITPOS (24) +#define GIRQ26_GPIO271_BITPOS (25) +#define GIRQ26_GPIO272_BITPOS (26) +#define GIRQ26_GPIO273_BITPOS (27) +#define GIRQ26_GPIO274_BITPOS (28) +#define GIRQ26_GPIO275_BITPOS (29) +#define GIRQ26_GPIO276_BITPOS (30) + +#define GIRQ26_MASK (0x7FFFFFFFul) +#define GIRQ26_WAKE_CAPABLE_MASK (0x7FFFFFFFul) + +/* ------------------------------------------------------------------------------- */ +/* NVIC,ECIA Routing Policy for Direct Mode */ +/* ------------------------------------------------------------------------------- */ +/* In Direct Mode, some interrupts could be configured to be used as aggregated. + * Configuration: + * 1. Always set ECS Interrupt Direct enable bit. + * 2. If GIRQn aggregated set Block Enable bit. + * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs. + * Switching issues: + * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers. + * Also requires set/clear of individual NVIC Enables. + * + * Note: interrupt_is_girq_direct() internal function uses this policy to detect + * if any interrupt is configured as direct or aggregated +*/ + +/** Initialize EC Interrupt Aggregator + * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode + * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated + * This parameter is only applicable in direct mode. + * @note All GPIO's and wake capable sources are always + * aggregated! GPIO's interrupts will still work in direct mode. + * Block wakes are not be routed to the processor in direct + * mode. + * Note2: This function disables and enables global interrupt + */ +void interrupt_init(uint8_t mode, uint32_t girq_bitmask); + +/** Set interrupt routing mode to aggregated or direct. + * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated + * @note In direct mode, one could enable certain GIRQs as aggregated using + * p_interrupt_ecia_block_enable_set function + */ +void interrupt_mode_set(uint8_t mode); + +/** Clears all individual interrupts Enables and Source in ECIA, + * and Clears all NVIC external enables and pending bits + */ +void interrupt_reset(void); + +/** Enables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_enable(uint32_t dev_iroute); + +/** Disables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_disable(uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* ECIA APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ + +/** Clear Source in the ECIA for the device + * @param devi - device IROUTING value + */ +void interrupt_device_ecia_source_clear(const uint32_t dev_iroute); + +/** Get the Source bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if source bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute); + +/** Get the Result bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if result bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* NVIC APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ +/* Note that if the device interrupt is aggregated, then these APIs would affect the + * NVIC corresponding to the aggregated GIRQ + */ + +/** Enable/Disable the NVIC (in the NVIC controller) for the device + * @param dev_iroute : source IROUTING information (encoded in a uint32_t) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + * @note Recommended to use interrupt_device_enable, interrupt_device_disable + * to enable/disable interrupts for the device, since those APIs configure ECIA as well + */ +void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag); + +/** Set NVIC priority for specified peripheral interrupt source + * @param dev_iroute - source IROUTING information (encoded in a uint32_t) + * @param nvic_pri - NVIC Priority + * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt + * sources in the GIRQ. + * 2. This function disables and enables global interrupt + */ +void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri); + +/** Return NVIC priority for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint32_t NVIC priority + */ +uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute); + +/** Return NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) + * + */ +uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute); + +/** Set NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + */ +void interrupt_device_nvic_pending_set(const uint32_t dev_iroute); + +/** Clears NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear + * @note This function disables and enables global interrupt + */ +uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear * + * and Status Register */ +/* ------------------------------------------------------------------------------- */ + +/** Enable specified GIRQ in ECIA block + * @param girq_id - enum MEC_GIRQ_IDS + */ + void p_interrupt_ecia_block_enable_set(uint8_t girq_id); + + /** Enable GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask); + +/** Check if specified GIRQ block enabled or not + * @param girq_id - enum MEC_GIRQ_IDS + * @return retVal - 1 if the particular GIRQ block enabled, else 0 + */ +uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id); + +/** Set all GIRQ block enables */ +void p_interrupt_ecia_block_enable_all_set(void); + +/** Clear specified GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + */ +void p_interrupt_ecia_block_enable_clr(uint8_t girq_id); + +/** Clear GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask); + +/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */ +void p_interrupt_ecia_block_enable_all_clr(void); + + /** Get status of GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + * @return 0 if status bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id); + +/** Reads the Block IRQ Vector Register + * @return 32-bit value + */ +uint32_t p_interrupt_ecia_block_irq_all_status_get(void); + +/* ---------------------------------------------------------------------------- */ +/* Peripheral Functions - Operations on GIRQx Source, Enable, Result * + * and Enable Registers */ +/* ---------------------------------------------------------------------------- */ + +/** Clear specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + */ +void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum); + +/** Read the specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if source bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum); + +/** Enable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum); + +/** Disable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum); + +/** Read the status of the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum); + +/** Read the result bit of the interrupt in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Function - Operations on all GIRQs */ +/* ------------------------------------------------------------------------------- */ + +/** Clear all aggregator GIRQn status registers */ +void p_interrupt_ecia_girqs_source_reset(void); + +/** Clear all aggregator GIRQn enables */ + void p_interrupt_ecia_girqs_enable_reset(void); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Function - Function to set interrupt control */ +/* ------------------------------------------------------------------------------- */ + +/** Set interrupt control + * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ + void p_interrupt_control_set(uint8_t nvic_en_flag); + + /** Read interrupt control + * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ +uint8_t p_interrupt_control_get(void); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Functions - NVIC */ +/* ------------------------------------------------------------------------------- */ + +/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller + * @param nvic_num : NVIC number (see enum IRQn_Type) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + * @note Application should perform this operation + */ + void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag); + + /** ecia_nvic_clr_en - Clear all NVIC external enables */ +void p_interrupt_nvic_extEnables_clr(void); + +/** Clear all NVIC external enables and pending bits */ +void p_interrupt_nvic_enpend_clr(void); + +/** Set NVIC external priorities to POR value */ +void p_interrupt_nvic_priorities_default_set(void); + +/** Set NVIC external priorities to specified priority (0 - 7) + * @param zero-based 3-bit priority value: 0=highest, 7=lowest. + * @note NVIC highest priority is the value 0, lowest is all 1's. + * Each external interrupt has an 8-bit register and the priority + * is left justified in the registers. MECxxx implements 8 priority + * levels or bits [7:5] in the register. Lowest priority = 0xE0 + */ +void p_interrupt_nvic_priorities_set(uint8_t new_pri); + +#endif // #ifndef _INTERRUPT_H +/* end interrupt.h */ +/** @} + */ + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_api.c new file mode 100644 index 000000000..aadaddeb2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_api.c @@ -0,0 +1,449 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Renamed ecia_init to interrupt_init +******************************************************************************/ +/** @file interrupt_api.c +* \brief Interrupt APIs Source File +* \author jvasanth +* +* This file implements the Interrupt Source file +******************************************************************************/ + +/** @defgroup Interrupt + * @{ + */ + +#include "common_lib.h" +#include "interrupt.h" +#include "..\pcr\pcr.h" + +static uint8_t interrupt_is_girq_direct(uint8_t girq_num); + +/* ------------------------------------------------------------------------------- */ +/* NVIC,ECIA Routing Policy for Direct Mode */ +/* ------------------------------------------------------------------------------- */ +/* In Direct Mode, some interrupts could be configured to be used as aggregated. + * Configuration: + * 1. Always set ECS Interrupt Direct enable bit. + * 2. If GIRQn aggregated set Block Enable bit. + * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs. + * Switching issues: + * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers. + * Also requires set/clear of individual NVIC Enables. + * + * Note: interrupt_is_girq_direct() internal function uses this policy to detect + * if any interrupt is configured as direct or aggregated +*/ + +/** Initialize EC Interrupt Aggregator + * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode + * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated + * This parameter is only applicable in direct mode. + * @note All GPIO's and wake capable sources are always + * aggregated! GPIO's interrupts will still work in direct mode. + * Block wakes are not be routed to the processor in direct + * mode. + * Note2: This function disables and enables global interrupt + */ +void interrupt_init(uint8_t mode, uint32_t girq_bitmask) +{ + uint32_t isave; + + isave = __get_PRIMASK(); + __disable_irq(); + + //Clear Sleep for Interrupt block + pcr_sleep_enable(PCR_INT, 0); + + interrupt_mode_set(mode); + + p_interrupt_ecia_girqs_enable_reset(); + + p_interrupt_nvic_enpend_clr(); + + p_interrupt_nvic_priorities_default_set(); + + if (mode) + {//If direct mode, enable specific GIRQs to be aggregated + p_interrupt_ecia_block_enable_bitmask_set(girq_bitmask); + } + + if (!isave) { + __enable_irq(); + } +} + +/** Set interrupt routing mode to aggregated or direct. + * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated + * @note In direct mode, one could enable certain GIRQs as aggregated using + * p_interrupt_ecia_block_enable_set function + */ +void interrupt_mode_set(uint8_t mode) +{ + if (mode) + { + p_interrupt_ecia_block_enable_all_clr(); + } + else + { + p_interrupt_ecia_block_enable_all_set(); + } + + p_interrupt_control_set(mode); +} + +/** Clears all individual interrupts Enables and Source in ECIA, + * and Clears all NVIC external enables and pending bits + */ +void interrupt_reset(void) +{ + p_interrupt_ecia_girqs_enable_reset(); + p_interrupt_ecia_girqs_source_reset(); + + p_interrupt_nvic_enpend_clr(); +} + +/** Enables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_enable(uint32_t dev_iroute) +{ + uint32_t isave; + IRQn_Type nvic_num; + uint8_t girq_num; + uint8_t ia_bitpos; + + girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu; + ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; + + if (interrupt_is_girq_direct(girq_num)) + { // GIRQ is hooked direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else + { // GIRQ is aggregated + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + isave = __get_PRIMASK(); + __disable_irq(); + + NVIC_EnableIRQ(nvic_num); + p_interrupt_ecia_girq_enable_set(girq_num, ia_bitpos); + __DSB(); + + if (!isave) { + __enable_irq(); + } +} + + +/** Disables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_disable(uint32_t dev_iroute) +{ + uint32_t isave; + IRQn_Type nvic_num; + uint8_t girq_num; + uint8_t ia_bitpos; + + girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu; + ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; + + isave = __get_PRIMASK(); + __disable_irq(); + + if (interrupt_is_girq_direct(girq_num)) + { // GIRQ is hooked direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + NVIC_DisableIRQ(nvic_num); + } + + p_interrupt_ecia_girq_enable_clr(girq_num, ia_bitpos); + __DSB(); + + if (!isave) { + __enable_irq(); + } +} + +/** ecia_is_girq_direct - Return true if GIRQn sources can be directly + * connected to the NVIC - based on ECS->INTERRUPT_CONTROL and GIRQ block enable + * @param girq_num - enum MEC_GIRQ_IDS + * @return 1 if GIRQn sources can be directly routed to the NVIC, else 0 + */ +static uint8_t interrupt_is_girq_direct(uint8_t girq_num) +{ + uint32_t bpos; + uint8_t retVal; + uint8_t girq_block_enabled; + + retVal = 0; + + bpos = (girq_num & 0x1Fu) + 8u; + + if ((ECIA_GIRQ_DIRECT_BITMAP) & (1ul << bpos)) + { + if (p_interrupt_control_get()) + {// direct NVIC enabled + + girq_block_enabled = p_interrupt_ecia_block_enable_get(girq_num); + + if (!girq_block_enabled) + { + retVal = 1; + } + } + } + return retVal; +} + + +/* ------------------------------------------------------------------------------- */ +/* ECIA APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ + +/** Clear Source in the ECIA for the device + * @param devi - device IROUTING value + */ +void interrupt_device_ecia_source_clear(const uint32_t dev_iroute) +{ + uint8_t girq_num; + uint8_t ia_bit_pos; + + girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu; + ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; + + p_interrupt_ecia_girq_source_clr(girq_num, ia_bit_pos); + __DSB(); +} + +/** Get the Source bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if source bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute) +{ + uint8_t girq_num; + uint8_t ia_bit_pos; + uint8_t retVal; + + girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu; + ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; + + retVal = p_interrupt_ecia_girq_source_get(girq_num, ia_bit_pos); + return retVal; +} + +/** Get the Result bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if result bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute) +{ + uint8_t girq_num; + uint8_t ia_bit_pos; + uint8_t retVal; + + girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu; + ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; + + retVal = p_interrupt_ecia_girq_result_get(girq_num, ia_bit_pos); + return retVal; +} + +/* ------------------------------------------------------------------------------- */ +/* NVIC APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ +/* Note that if the device interrupt is aggregated, then these APIs would affect the + * NVIC corresponding to the aggregated GIRQ + */ + +/** Enable/Disable the NVIC (in the NVIC controller) for the device + * @param dev_iroute : source IROUTING information (encoded in a uint32_t) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + * @note 1. Recommended to use interrupt_device_enable, interrupt_device_disable + * to enable/disable interrupts for the device, since those APIs configure ECIA as well + * 2. This function disables and enables global interrupt + */ +void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag) +{ + uint32_t isave; + IRQn_Type nvic_num; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + isave = __get_PRIMASK(); + __disable_irq(); + + p_interrupt_nvic_enable(nvic_num, en_flag); + + if (!isave) { + __enable_irq(); + } +} + + +/** Set NVIC priority for specified peripheral interrupt + * @param dev_iroute - source IROUTING information (encoded in a uint32_t) + * @param nvic_pri - NVIC Priority + * @note If ECIA is in aggregated mode, the priority affects all interrupt + * sources in the GIRQ. + */ +void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri) +{ + IRQn_Type nvic_num; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + NVIC_SetPriority(nvic_num, (uint32_t)nvic_pri); +} + +/** Return NVIC priority for the device's interrupt + * @param dev_iroute - source IROUTING information + * @return uint32_t NVIC priority + */ +uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute) +{ + IRQn_Type nvic_num; + uint32_t nvic_priority; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + nvic_priority = NVIC_GetPriority(nvic_num); + + return nvic_priority; +} + + +/** Return NVIC pending for the device + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) + * + */ +uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute) +{ + IRQn_Type nvic_num; + uint8_t nvic_pending; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + nvic_pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num)); + + return nvic_pending; +} + + +/** Set NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + */ +void interrupt_device_nvic_pending_set(const uint32_t dev_iroute) +{ + IRQn_Type nvic_num; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + NVIC_SetPendingIRQ(nvic_num); +} + +/** Clears NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear + * @note This function disables and enables global interrupt + */ +uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute) +{ + uint32_t was_masked; + IRQn_Type nvic_num; + uint8_t pending; + + if (p_interrupt_control_get()) + { // direct + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); + } + else // fully aggregated + { + nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul); + } + + was_masked = __get_PRIMASK(); + __disable_irq(); + + pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num)); + + NVIC_ClearPendingIRQ(nvic_num); + __DSB(); + + if (!was_masked) { + __enable_irq(); + } + + return pending; +} + +/* ------------------------------------------------------------------------------- */ + +/* end interrupt_api.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_ecia_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_ecia_perphl.c new file mode 100644 index 000000000..bdb77f584 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_ecia_perphl.c @@ -0,0 +1,349 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Initial Draft +******************************************************************************/ +/** @file interrupt_ecia_perphl.c +* \brief Interrupt ECIA Peripheral Source File +* \author jvasanth +* +* This file implements the ECIA peripheral functions +******************************************************************************/ + +/** @defgroup Interrupt + * @{ + */ + +#include "common_lib.h" +#include "interrupt.h" + +#define ECIA ((INTS_Type *) INTS_BASE) +#define ECS ((EC_REG_BANK_Type *) EC_REG_BANK_BASE) + +/* ------------------------------------------------------------------------------- */ +/* Operations on GIRQ Block Enable Set, Enable Clear and Status Register */ +/* ------------------------------------------------------------------------------- */ + +/** Enable specified GIRQ in ECIA block + * @param girq_id - enum MEC_GIRQ_IDS + */ +void p_interrupt_ecia_block_enable_set(uint8_t girq_id) +{ + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + ECIA->BLOCK_ENABLE_SET = (1ul << ((girq_id + 8) & 0x1Fu)); + } +} + +/** Enable GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask) +{ + ECIA->BLOCK_ENABLE_SET = girq_bitmask; +} + +/** Check if specified GIRQ block enabled or not + * @param girq_id - enum MEC_GIRQ_IDS + * @return retVal - 1 if the particular GIRQ block enabled, else 0 + */ +uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id) +{ + uint8_t retVal; + + retVal = 0; + if ( girq_id < (MEC_GIRQ_ID_MAX) ) + { + if ((ECIA->BLOCK_ENABLE_SET) & (1ul << ((girq_id + 8) & 0x1Fu))) + { + retVal = 1; + } + } + return retVal; +} + +/** Set all GIRQ block enables */ +void p_interrupt_ecia_block_enable_all_set(void) +{ + ECIA->BLOCK_ENABLE_SET = 0xfffffffful; +} + +/** Clear specified GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + */ +void p_interrupt_ecia_block_enable_clr(uint8_t girq_id) +{ + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + ECIA->BLOCK_ENABLE_CLEAR = (1ul << ((girq_id + 8) & 0x1Fu)); + } +} + +/** Clear GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask) +{ + ECIA->BLOCK_ENABLE_CLEAR = girq_bitmask; +} + +/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */ + void p_interrupt_ecia_block_enable_all_clr(void) +{ + ECIA->BLOCK_ENABLE_CLEAR = 0xfffffffful; +} + +/** Get status of GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + * @return 0 if status bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id) +{ + uint32_t retVal; + + retVal = ECIA->BLOCK_IRQ_VECTOR & (1ul << ((girq_id + 8) & 0x1Fu)); + + return retVal; +} + +/** Reads the Block IRQ Vector Register + * @return 32-bit value + */ +uint32_t p_interrupt_ecia_block_irq_all_status_get(void) +{ + uint32_t retVal; + + retVal = ECIA->BLOCK_IRQ_VECTOR; + + return retVal; +} + + +/* ------------------------------------------------------------------------------- */ +/* Operations on GIRQx Source, Enable, Result and Enable Registers */ +/* ------------------------------------------------------------------------------- */ + +/** Clear specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + */ +void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum) +{ + __IO uint32_t *girq_source = (uint32_t*)ECIA; + + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_source += (5 * girq_id); + *girq_source |= (1ul << (bitnum & 0x1Fu)); + } +} + +/** Read the specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if source bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum) +{ + uint32_t retVal; + __IO uint32_t *girq_source = (uint32_t*)ECIA; + + retVal = 0; + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_source += (5 * girq_id); + retVal = (*girq_source & (1ul << (bitnum & 0x1Fu))); + } + return retVal; +} + +/** Enable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum) +{ + __IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET)); + + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_enable_set += (5 * girq_id); + *girq_enable_set |= (1ul << (bitnum & 0x1Fu)); + } +} + +/** Disable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum) +{ + __IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR)); + + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_enable_clr += (5 * girq_id); + *girq_enable_clr |= (1ul << (bitnum & 0x1Fu)); + } +} + +/** Read the status of the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum) +{ + uint32_t retVal; + __IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET)); + + retVal = 0; + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_enable_set += (5 * girq_id); + retVal = (*girq_enable_set & (1ul << (bitnum & 0x1Fu))); + } + return retVal; +} + +/** Read the result bit of the interrupt in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum) +{ + uint32_t retVal; + __IO uint32_t *girq_result = (uint32_t*)(&(ECIA->GIRQ08_RESULT)); + + retVal = 0; + if ( girq_id < (MEC_GIRQ_ID_MAX) ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_result += (5 * girq_id); + retVal = (*girq_result & (1ul << (bitnum & 0x1Fu))); + } + + return retVal; +} + +/* ------------------------------------------------------------------------------- */ +/* Operations on all GIRQs */ +/* ------------------------------------------------------------------------------- */ + +/** Clear all aggregator GIRQn status registers */ +void p_interrupt_ecia_girqs_source_reset(void) +{ + uint16_t i; + __IO uint32_t *girq_source = (uint32_t*)ECIA; + + for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_source += 5; + *girq_source = 0xfffffffful; + } +} + +/** Clear all aggregator GIRQn enables */ + void p_interrupt_ecia_girqs_enable_reset(void) +{ + uint16_t i; + __IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR)); + + for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) { + /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED + * please refer INTS_Type in MCHP_device_internal.h + * Based on the girq id calculate the offset in the structure INTS_Type + * + * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON + * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES + */ + girq_enable_clr += 5; + *girq_enable_clr = 0xfffffffful; + } +} + +/* ------------------------------------------------------------------------------- */ +/* Function to set interrupt control */ +/* ------------------------------------------------------------------------------- */ + +/** Set interrupt control + * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ +void p_interrupt_control_set(uint8_t nvic_en_flag) +{ + ECS->INTERRUPT_CONTROL = nvic_en_flag; +} + +/** Read interrupt control + * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ +uint8_t p_interrupt_control_get(void) +{ + return (ECS->INTERRUPT_CONTROL & 0x1); +} + +/* end interrupt_ecia_perphl.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_nvic_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_nvic_perphl.c new file mode 100644 index 000000000..21109b4c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/interrupt/interrupt_nvic_perphl.c @@ -0,0 +1,119 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Initial Draft +******************************************************************************/ +/** @file interrupt_nvic_perphl.c +* \brief Interrupt NVIC Peripheral Source File +* \author jvasanth +* +* This file implements the NVIC peripheral functions +******************************************************************************/ + +/** @defgroup Interrupt + * @{ + */ + +#include "common_lib.h" +#include "interrupt.h" + +/* ------------------------------------------------------------------------------- */ +/* NVIC Functions */ +/* ------------------------------------------------------------------------------- */ + +/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller + * @param nvic_num : NVIC number (see enum IRQn_Type) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + */ +void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag) +{ + if (en_flag) { + NVIC_EnableIRQ(nvic_num); + } else { + NVIC_DisableIRQ(nvic_num); + } + __DSB(); +} + +/** ecia_nvic_clr_en - Clear all NVIC external enables */ +void p_interrupt_nvic_extEnables_clr(void) +{ + uint32_t i, m; + + m = (uint32_t)(MAX_IRQn) >> 5; + if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; } + + for ( i = 0ul; i < m ; i++ ) + { + NVIC->ICER[i] = 0xfffffffful; + } +} + +/** Clear all NVIC external enables and pending bits */ +void p_interrupt_nvic_enpend_clr(void) +{ + uint32_t i, m; + + // Clear NVIC enables & pending status + m = (uint32_t)(MAX_IRQn) >> 5; + if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; } + + for ( i = 0ul; i < m ; i++ ) + { + NVIC->ICER[i] = 0xfffffffful; + NVIC->ICPR[i] = 0xfffffffful; + } +} + +/** Set NVIC external priorities to POR value */ +void p_interrupt_nvic_priorities_default_set(void) +{ + uint32_t i; + // Set POR default NVIC priority (highest) + for ( i = 0ul; i < (uint32_t)MAX_IRQn; i++ ) { + NVIC->IP[i] = 0u; + } +} + +/** Set NVIC external priorities to specified priority (0 - 7) + * @param zero-based 3-bit priority value: 0=highest, 7=lowest. + * @note NVIC highest priority is the value 0, lowest is all 1's. + * Each external interrupt has an 8-bit register and the priority + * is left justified in the registers. MECxxx implements 8 priority + * levels or bits [7:5] in the register. Lowest priority = 0xE0 + */ +void p_interrupt_nvic_priorities_set(uint8_t new_pri) +{ + uint16_t i; + + for ( i = 0ul; i < MAX_IRQn; i++ ) { + NVIC_SetPriority((IRQn_Type)i, new_pri); + } +} + + +/* end interrupt_nvic_perphl.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr.h new file mode 100644 index 000000000..68dcce40f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr.h @@ -0,0 +1,671 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr.h +* \brief Power, Clocks, and Resets Header file +* \author jvasanth +* +* This file is the PCR header file +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#ifndef _PCR_H +#define _PCR_H + + +/******************************************************************************/ +/** PCR Register IDS + *******************************************************************************/ +enum _PCR_REGSET_ID_ +{ + PCR_REG_SYSTEM_SLEEP_CTRL = 0, + PCR_REG_PROCESSOR_CLK_CTRL, + PCR_REG_SLOW_CLK_CTRL, + PCR_REG_OSCILLATOR_ID, + PCR_REG_PWR_RESET_STS, + PCR_REG_PWR_RESET_CTRL, + PCR_REG_SYSTEM_RESET, + PCR_TEST0, + PCR_TEST1, + PCR_REG_EC_SLEEP_ENABLE_0 = 12, + PCR_REG_EC_SLEEP_ENABLE_1, + PCR_REG_EC_SLEEP_ENABLE_2, + PCR_REG_EC_SLEEP_ENABLE_3, + PCR_REG_EC_SLEEP_ENABLE_4, + PCR_REG_EC_CLK_REQD_STS_0 = 20, + PCR_REG_EC_CLK_REQD_STS_1, + PCR_REG_EC_CLK_REQD_STS_2, + PCR_REG_EC_CLK_REQD_STS_3, + PCR_REG_EC_CLK_REQD_STS_4, + PCR_REG_EC_RESET_ENABLE_0 = 28, + PCR_REG_EC_RESET_ENABLE_1, + PCR_REG_EC_RESET_ENABLE_2, + PCR_REG_EC_RESET_ENABLE_3, + PCR_REG_EC_RESET_ENABLE_4, + +}; +/* ---------------------------------------------------------------------- */ + +// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable +//PCR register group 0 - EC 0 +#define PCR0_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_0) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_0) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_0) & 0xFF)<<16u)) + +//PCR register group 1 - EC 1 +#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_1) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_1) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_1) & 0xFF)<<16u)) + +//PCR register group 2 - EC 2 +#define PCR2_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u)) + +//PCR register group 3 - EC 3 +#define PCR3_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_3) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_3) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_3) & 0xFF)<<16u)) + +//PCR register group 4 - EC 4 +#define PCR4_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_4) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_4) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_4) & 0xFF)<<16u)) + +//PCR0_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR0_EC_JTAG_STAP_BITPOS (0u) +#define PCR0_EC_EFUSE_BITPOS (1u) +#define PCR0_EC_ISPI_BITPOS (2u) + +//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR1_EC_INT_BITPOS (0u) +#define PCR1_EC_PECI_BITPOS (1u) +#define PCR1_EC_TACH0_BITPOS (2u) +#define PCR1_EC_PWM0_BITPOS (4u) +#define PCR1_EC_PMC_BITPOS (5u) +#define PCR1_EC_DMA_BITPOS (6u) +#define PCR1_EC_TFDP_BITPOS (7u) +#define PCR1_EC_CPU_BITPOS (8u) +#define PCR1_EC_WDT_BITPOS (9u) +#define PCR1_EC_SMB0_BITPOS (10u) +#define PCR1_EC_TACH1_BITPOS (11u) +#define PCR1_EC_TACH2_BITPOS (12u) +#define PCR1_EC_PWM1_BITPOS (20u) +#define PCR1_EC_PWM2_BITPOS (21u) +#define PCR1_EC_PWM3_BITPOS (22u) +#define PCR1_EC_PWM4_BITPOS (23u) +#define PCR1_EC_PWM5_BITPOS (24u) +#define PCR1_EC_PWM6_BITPOS (25u) +#define PCR1_EC_PWM7_BITPOS (26u) +#define PCR1_EC_PWM8_BITPOS (27u) +#define PCR1_EC_REG_BITPOS (29u) +#define PCR1_EC_BTIMER0_BITPOS (30u) +#define PCR1_EC_BTIMER1_BITPOS (31u) + +//PCR2_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR2_EC_LPC_BITPOS (0u) +#define PCR2_EC_UART0_BITPOS (1u) +#define PCR2_EC_UART1_BITPOS (2u) +#define PCR2_EC_GLBL_CFG_BITPOS (12u) +#define PCR2_EC_ACPI_EC0_BITPOS (13u) +#define PCR2_EC_ACPI_EC1_BITPOS (14u) +#define PCR2_EC_ACPI_PM1_BITPOS (15u) +#define PCR2_EC_8042EM_BITPOS (16u) +#define PCR2_EC_MBOX_BITPOS (17u) +#define PCR2_EC_RTC_BITPOS (18u) +#define PCR2_EC_ESPI_BITPOS (19u) +#define PCR2_EC_ACPI_EC_2_BITPOS (21u) +#define PCR2_EC_ACPI_EC_3_BITPOS (22u) +#define PCR2_EC_ACPI_EC_BITPOS (23u) +#define PCR2_EC_PORT80_0_BITPOS (25u) +#define PCR2_EC_PORT80_1_BITPOS (26u) + +//PCR3_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR3_EC_ADC_BITPOS (3u) +#define PCR3_EC_PS2_0_BITPOS (5u) +#define PCR3_EC_PS2_1_BITPOS (6u) +#define PCR3_EC_PS2_2_BITPOS (7u) +#define PCR3_EC_SPI0_BITPOS (9u) +#define PCR3_EC_HTIMER_BITPOS (10u) +#define PCR3_EC_KEYSCAN_BITPOS (11u) +#define PCR3_EC_RPM_PWM_BITPOS (12u) +#define PCR3_EC_SMB1_BITPOS (13u) +#define PCR3_EC_SMB2_BITPOS (14u) +#define PCR3_EC_SMB3_BITPOS (15u) +#define PCR3_EC_LED0_BITPOS (16u) +#define PCR3_EC_LED1_BITPOS (17u) +#define PCR3_EC_LED2_BITPOS (18u) +#define PCR3_EC_BCM_BITPOS (19u) +#define PCR3_EC_SPI1_BITPOS (20u) +#define PCR3_EC_BTIMER2_BITPOS (21u) +#define PCR3_EC_BTIMER3_BITPOS (22u) +#define PCR3_EC_BTIMER4_BITPOS (23u) +#define PCR3_EC_BTIMER5_BITPOS (24u) +#define PCR3_EC_LED3_BITPOS (25u) +#define PCR3_EC_PKE_BITPOS (26u) +#define PCR3_EC_RNG_BITPOS (27u) +#define PCR3_EC_AES_BITPOS (28u) +#define PCR3_EC_HTIMER_1_BITPOS (29u) +#define PCR3_EC_C_C_TIMER_BITPOS (30u) +#define PCR3_EC_PWM9_BITPOS (31u) + + +//PCR4_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR4_EC_PWM10_BITPOS (0u) +#define PCR4_EC_PWM11_BITPOS (1u) +#define PCR4_EC_CTIMER0_BITPOS (2u) +#define PCR4_EC_CTIMER1_BITPOS (3u) +#define PCR4_EC_CTIMER2_BITPOS (4u) +#define PCR4_EC_CTIMER3_BITPOS (5u) +#define PCR4_EC_RTOS_TIMER_BITPOS (6u) +#define PCR4_EC_RPM2_PWM_BITPOS (7u) +#define PCR4_EC_QMSPI_BITPOS (8u) +#define PCR4_EC_BCM_1_BITPOS (9u) +#define PCR4_EC_RC_ID0_BITPOS (10u) +#define PCR4_EC_RC_ID1_BITPOS (11u) +#define PCR4_EC_RC_ID2_BITPOS (12u) +#define PCR4_EC_PROCHOT_BITPOS (13u) +#define PCR4_EC_EEPROM_BITPOS (14u) +#define PCR4_EC_CUST_LOG_BITPOS (15u) + + +/* + * n = b[7:0] = PCR Reg Bit Position + * m = b[31:8] = PCRx Regs IDs + */ +//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) + +//PCRx_REGS_BIT positions +#define PCRx_REGS_POS_SLEEP_ENABLE (8u) +#define PCRx_REGS_POS_CLK_REQD_STS (16u) +#define PCRx_REGS_POS_RESET_ENABLE (24u) + + +/******************************************************************************/ +/** PCR Block IDS. + * These IDs are used to directly refer to a block + *******************************************************************************/ +typedef enum { + PCR_JTAG = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_JTAG_STAP_BITPOS & 0xFFu)), + PCR_EFUSE = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_EFUSE_BITPOS & 0xFFu)), + PCR_ISPI = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_ISPI_BITPOS & 0xFFu)), + + PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), + PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), + PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), + PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), + PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), + PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), + PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), + PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), + PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), + PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), + PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), + PCR_TACH2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH2_BITPOS & 0xFFu)), + PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), + PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), + PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), + PCR_PWM4 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM4_BITPOS & 0xFFu)), + PCR_PWM5 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM5_BITPOS & 0xFFu)), + PCR_PWM6 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM6_BITPOS & 0xFFu)), + PCR_PWM7 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM7_BITPOS & 0xFFu)), + PCR_PWM8 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM8_BITPOS & 0xFFu)), + PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), + PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), + PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), + + PCR_LPC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_LPC_BITPOS & 0xFFu)), + PCR_UART0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART0_BITPOS & 0xFFu)), + PCR_UART1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART1_BITPOS & 0xFFu)), + PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_GLBL_CFG_BITPOS & 0xFFu)), + PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC0_BITPOS & 0xFFu)), + PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC1_BITPOS & 0xFFu)), + PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_PM1_BITPOS & 0xFFu)), + PCR_8042EM = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_8042EM_BITPOS & 0xFFu)), + PCR_MBOX = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_MBOX_BITPOS & 0xFFu)), + PCR_RTC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_RTC_BITPOS & 0xFFu)), + PCR_ESPI = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ESPI_BITPOS & 0xFFu)), + PCR_ACPI_EC2 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_2_BITPOS & 0xFFu)), + PCR_ACPI_EC3 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_3_BITPOS & 0xFFu)), + PCR_ACPI_EC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_BITPOS & 0xFFu)), + PCR_PORT80_0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_0_BITPOS & 0xFFu)), + PCR_PORT80_1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_1_BITPOS & 0xFFu)), + + PCR_ADC = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_ADC_BITPOS & 0xFFu)), + PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_0_BITPOS & 0xFFu)), + PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_1_BITPOS & 0xFFu)), + PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_2_BITPOS & 0xFFu)), + PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI0_BITPOS & 0xFFu)), + PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_BITPOS & 0xFFu)), + PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_KEYSCAN_BITPOS & 0xFFu)), + PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RPM_PWM_BITPOS & 0xFFu)), + PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB1_BITPOS & 0xFFu)), + PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB2_BITPOS & 0xFFu)), + PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB3_BITPOS & 0xFFu)), + PCR_LED0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED0_BITPOS & 0xFFu)), + PCR_LED1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED1_BITPOS & 0xFFu)), + PCR_LED2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED2_BITPOS & 0xFFu)), + PCR_BCM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BCM_BITPOS & 0xFFu)), + PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI1_BITPOS & 0xFFu)), + PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER2_BITPOS & 0xFFu)), + PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER3_BITPOS & 0xFFu)), + PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER4_BITPOS & 0xFFu)), + PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER5_BITPOS & 0xFFu)), + PCR_LED3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED3_BITPOS & 0xFFu)), + PCR_PKE = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PKE_BITPOS & 0xFFu)), + PCR_RNG = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RNG_BITPOS & 0xFFu)), + PCR_AES = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_AES_BITPOS & 0xFFu)), + PCR_HTIMER_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_1_BITPOS & 0xFFu)), + PCR_C_C_TIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_C_C_TIMER_BITPOS & 0xFFu)), + PCR_PWM9 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PWM9_BITPOS & 0xFFu)), + + PCR_PWM10 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM10_BITPOS & 0xFFu)), + PCR_PWM11 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM11_BITPOS & 0xFFu)), + PCR_CTIMER0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER0_BITPOS & 0xFFu)), + PCR_CTIMER1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER1_BITPOS & 0xFFu)), + PCR_CTIMER2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER2_BITPOS & 0xFFu)), + PCR_CTIMER3 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER3_BITPOS & 0xFFu)), + PCR_RTOS_TIMER = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RTOS_TIMER_BITPOS & 0xFFu)), + PCR_RPM2_PWM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RPM2_PWM_BITPOS & 0xFFu)), + PCR_QMSPI = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_QMSPI_BITPOS & 0xFFu)), + PCR_BCM1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_BCM_1_BITPOS & 0xFFu)), + PCR_RCID0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID0_BITPOS & 0xFFu)), + PCR_RCID1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID1_BITPOS & 0xFFu)), + PCR_RCID2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID2_BITPOS & 0xFFu)), + PCR_PROCHOT = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PROCHOT_BITPOS & 0xFFu)), + PCR_EEPROM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_EEPROM_BITPOS & 0xFFu)), + PCR_CUST_LOG = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CUST_LOG_BITPOS & 0xFFu)), +} PCR_BLK_ID; + + +/******************************************************************************/ +/** PCR Processor ClK Divide Values + *******************************************************************************/ +enum PROCESSOR_CLK_DIVIDE_VALUE +{ + PCR_CPU_CLK_DIVIDE_1 = 1, + PCR_CPU_CLK_DIVIDE_2 = 2, + PCR_CPU_CLK_DIVIDE_3 = 3, + PCR_CPU_CLK_DIVIDE_4 = 4, + PCR_CPU_CLK_DIVIDE_16 = 16, + PCR_CPU_CLK_DIVIDE_48 = 48 +}; + +/******************************************************************************/ +/** System Sleep Modes + *******************************************************************************/ +enum SYSTEM_SLEEP_MODES +{ + SYSTEM_LIGHT_SLEEP = 0, + SYSTEM_HEAVY_SLEEP = 1, + SYSTEM_SLEEP_ALL = 4 +}; + +/* Bitmask for Power Reset Status Register */ +#define PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK (1UL<<2) +#define PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK (1UL<<3) +#define PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK (1UL<<5) +#define PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK (1UL<<6) +#define PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK (1UL<<7) +#define PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK (1UL<<10) +#define PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK (1UL<<11) +#define PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK (1UL<<12) + +/* Bitmask for Processor Clock Control Register */ +#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8) + +/* Bitmask for Power Reset Control Register */ +#define PCR_PWR_RESET_CTRL_PWR_INV_BITMASK (1UL<<0) +#define PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK (1UL<<8) + +/* Bitmask for OScillator ID register */ +#define PCR_OSCILLATOR_ID_FOUNDARY_BITMASK (3UL<<5) +#define PCR_OSCILLATOR_ID_REVISION_BITMASK (0xFUL) + +#define PCR_OSCILLATOR_ID_FOUNDARY_CHART_TSMC (0UL) +#define PCR_OSCILLATOR_ID_FOUNDARY_TSMC (0x10u) +#define PCR_OSCILLATOR_ID_FOUNDARY_CHART (0x20u) +#define PCR_OSCILLATOR_ID_FOUNDARY_GRACE (0x30u) + +/* Bitmask for PKE Clock register */ +#define PCR_PKE_CLOCK_REG_PKE_CLK_BITMASK (1UL<<1) +#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_BITMASK (1UL<<0) + +#define PCR_PKE_CLOCK_REG_PKE_CLK_48MHZ (1UL<<1) +#define PCR_PKE_CLOCK_REG_PKE_CLK_96MHZ (0UL<<0) +#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_EN (1UL<<0) +#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_DIS (0UL<<0) + +/* ---------------------------------------------------------------------- */ +/* API - Functions to program Sleep Enable, CLK Reqd Status, * + * Reset Enable for a block * + * ---------------------------------------------------------------------- */ + /** Sets or Clears block specific bit in PCR Sleep Enable Register + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register + */ +void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); + +/** Get Clock Required Status for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @return uint8_t - 1 if Clock Required Status set, else 0 + */ +uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id); + +/** Sets or Clears Reset Enable register bit for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register + */ +void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for entering low power modes */ +/* ---------------------------------------------------------------------- */ +/** Instructs all blocks to sleep by setting the Sleep Enable bits */ +void pcr_all_blocks_sleep(void); + +/** Clears the Sleep Enable bits for all blocks */ +void pcr_all_blocks_wake(void); + +/** Programs required sleep mode in System Sleep Control Register + * @param sleep_mode - see enum SYSTEM_SLEEP_MODES + */ +void pcr_system_sleep(uint8_t sleep_mode); + +/** Reads the value of Power Reset status register + * @param none + * @return Power Status Reg value + */ +uint16_t pcr_power_reset_status_read(void); + +/** Reads the value of Power Reset control register + * @param none + * @return Power reset control Reg value + */ +uint16_t pcr_power_reset_ctrl_read(void); + +/** Sets the value of PWR_INV bit to 1 or 0 +* @param set_clr: 1 or 0 + * @return none + */ +void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr); + +/** Sets the value of HOST_RESET bit to 1 or 0 +* @param set_clr: 1 or 0 + * @return none + */ +void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr); + +/** Sets the SOFT SYS RESET bit to 1 +* @param none + * @return none + */ +void pcr_system_reset_set(void); + +/** Writes to the PKE Clock register +* @param clock value + * @return none + */ +void pcr_pke_clock_write(uint8_t pke_clk_val); + +/** Reads the PKE clock register +* @param none + * @return clock value + */ +uint8_t pcr_pke_clock_read(void); + +/** Writes to the OSC cal register +* @param calibration value: 1 or 0 + * @return none + */ +void pcr_osc_cal_write(uint8_t pke_clk_val); + +/** Reads the osc cal register +* @param none + * @return cal value + */ +uint8_t pcr_osc_cal_read(void); + + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to program and read 32-bit values * + * from PCR Registers * + * ---------------------------------------------------------------------- */ + /** Write 32-bit value in the PCR Register + * @param pcr_reg_id - pcr register id + * @param value - 32-bit value + */ +void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value); + +/** Reads 32-bit value from the PCR Register + * @param pcr_reg_id - pcr register id + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_read(uint8_t pcr_reg_id); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to set, clr and get bits in * + * PCR Registers * + * ---------------------------------------------------------------------- */ + /** Sets bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set + */ +void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Clears bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to clear + */ +void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Read bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to read + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Sets or Clears bits in a PCR Register - Helper Function + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set or clear + * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register + */ +void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag); + +//Functions to operate on System Sleep Control Register + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to operate on System Sleep Control * + * Register * + * ---------------------------------------------------------------------- */ +/** Writes required sleep mode in System Sleep Control Register + * @param sleep_value - System Sleep control value - [D2, D1, D0] + */ +void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value); + +/** Reads the System Sleep Control PCR Register + * @return value - byte 0 of the system sleep control PCR register + */ +uint8_t p_pcr_system_sleep_ctrl_read(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program to CLK Divide Value * + * ---------------------------------------------------------------------- */ + /** Writes the clock divide value in the Processor Clock Control Register + * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE + */ +void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program the Slow Clock Control * + * Register * + * ---------------------------------------------------------------------- */ + /** Write the slow clock divide value in the Slow Clock Control Register + * @param slow_clk_divide_value - slow clk divide value + */ +void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to read the Oscillator Lock Status */ +/* ---------------------------------------------------------------------- */ +/** Reads the Oscillator Lock status bit in the Oscillator ID Register + * @return 1 if Oscillator Lock Status bit is set, else 0 + */ +uint8_t p_pcr_oscillator_lock_sts_get(void); + +/** Reads the Oscillator ID Register + * @return oscillator ID value + */ +uint16_t p_pcr_oscillator_id_reg_read(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to read various power status in * + * Power Reset register * + * ---------------------------------------------------------------------- */ + /** Reads the VCC Reset Status bit + * in the Power Reset Status Register + * @return 1 if VCC Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vcc_reset_sts_get(void); + +/** Reads the Host Reset Status bit + * in the Power Reset Status Register + * @return 1 if Host Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_host_reset_sts_get(void); + +/** Reads the VBAT Reset Status bit + * in the Power Reset Status Register + * @return 1 if VBAT Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void); + +/** Clears the VBAT Reset Status bit + * in the Power Reset Status Register + */ +void p_pcr_pwr_reset_vbat_reset_sts_clr(void); + +/** Reads the VTR Reset Status bit + * in the Power Reset Status Register + * @return 1 if VCC1 Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void); + +/** Clears the VTR Reset Status bit + * in the Power Reset Status Register + */ +void p_pcr_chip_subsystem_vtr_reset_sts_clr(void); + +/** Reads the 32K_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if 32_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_32K_active_sts_get(void); + +/** Reads the PCICLK_ACTIVE status bit + * in the Power Reset Status Register + * @return 1 if CICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void); + +/** Reads the ESPICLK_ACTIVE status bit + * in the Power Reset Status Register + * @return 1 if ESPICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void); + +/** Reads the Power status reg + * @return Power Status Reg value + */ +uint16_t p_pcr_pwr_reset_sts_get(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions for Power Reset Control Register */ +/* ---------------------------------------------------------------------- */ + +/** Reads the Power Reset Control Register + * @return Power Reset Control Register value + */ +uint16_t p_pcr_pwr_reset_ctrl_read(void); + +/** Set the PWR_INV bit in the Power Reset Control Register + * @param set_clr value 1 or 0 + * @return none + */ +void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr); + +/** Set the HOST RESET SELECT bit in the Power Reset Control Register + * @param set_clr value 1 or 0 + * @return none + */ +void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions for System Reset Register */ +/* ---------------------------------------------------------------------- */ +/** Set the SOFT_SYS_RESET bit in the System Reset Register + * @param none + * @return none + */ +void p_pcr_system_reset_set(void); + + +/** Set the value in PKE CLOCK Register + * @param PKE Clock value + * @return none + */ +void p_pcr_pke_clock_write(uint8_t pke_clk_val); + +/** Read the value in PKE CLOCK Register + * @none + * @return PKE Clock value + */ +uint8_t p_pcr_pke_clock_read(void); + +/** Set the value in Oscillator calibration Register + * @param Oscillator calibration value + * @return none + */ +void p_pcr_osc_cal_write(uint8_t osc_cal_val); + +/** Read the value in Osc cal Register + * @none + * @return Osc cal value + */ +uint8_t p_pcr_osc_cal_read(void); + +#endif // #ifndef _PCR_H +/* end pcr.h */ +/** @} + */ + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_api.c new file mode 100644 index 000000000..1cb209241 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_api.c @@ -0,0 +1,216 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr_api.c +* \brief Power, Clocks, and Resets API Source file +* \author jvasanth +* +* This file implements the PCR APIs +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#include "common_lib.h" +#include "pcr.h" + + +/* ------------------------------------------------------------------------------- */ +/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */ +/* ------------------------------------------------------------------------------- */ + +/** Sets or Clears block specific bit in PCR Sleep Enable Register + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register + */ +void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu); + + p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); +} + + +/** Get Clock Required Status for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @return uint8_t - 1 if Clock Required Status set, else 0 + */ +uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id, retVal; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu); + + retVal = 0; + if (p_pcr_reg_get(pcr_reg_id, bit_mask)) + { + retVal = 1; + } + + return retVal; +} + +/** Sets or Clears Reset Enable register bit for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register + */ +void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu); + + p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); +} + + +/* ------------------------------------------------------------------------------- */ +/* Functions for entering low power modes */ +/* ------------------------------------------------------------------------------- */ + +/** Instructs all blocks to sleep by setting the Sleep Enable bits */ +void pcr_all_blocks_sleep(void) +{ + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0xFFFFFFFF); +} + +/** Clears the Sleep Enable bits for all blocks */ + void pcr_all_blocks_wake(void) +{ + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0); +} + +/** Programs required sleep mode in System Sleep Control Register + * @param sleep_mode - see enum SYSTEM_SLEEP_MODES + */ +void pcr_system_sleep(uint8_t sleep_mode) +{ + p_pcr_system_sleep_ctrl_write(sleep_mode); +} + +/** Reads the value of Power Reset status register + * @param none + * @return Power Reset Status Reg value + */ +uint16_t pcr_power_reset_status_read(void) +{ + return (p_pcr_pwr_reset_sts_get()); +} + +/** Reads the value of Power Reset control register + * @param none + * @return Power reset control Reg value + */ +uint16_t pcr_power_reset_ctrl_read(void) +{ + return (p_pcr_pwr_reset_ctrl_read()); +} + +/** Sets the value of PWR_INV bit to 1 or 0 +* @param set_clr: 1 or 0 + * @return none + */ +void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr) +{ + p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(set_clr); +} + +/** Sets the value of HOST_RESET bit to 1 or 0 +* @param set_clr: 1 or 0 + * @return none + */ +void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr) +{ + p_pcr_pwr_reset_ctrl_host_rst_set_clr(set_clr); +} + +/** Sets the SOFT SYS RESET bit to 1 +* @param none + * @return none + */ +void pcr_system_reset_set() +{ + p_pcr_system_reset_set(); +} + +/** Writes to the PKE Clock register +* @param clock value + * @return none + */ +void pcr_pke_clock_write(uint8_t pke_clk_val) +{ + p_pcr_pke_clock_write(pke_clk_val); +} + +/** Reads the PKE clock register +* @param none + * @return clock value + */ +uint8_t pcr_pke_clock_read() +{ + return (p_pcr_pke_clock_read()); +} + +/** Writes to the OSC cal register +* @param calibration value: 1 or 0 + * @return none + */ +void pcr_osc_cal_write(uint8_t pke_clk_val) +{ + p_pcr_osc_cal_write(pke_clk_val); +} + +/** Reads the osc cal register +* @param none + * @return cal value + */ +uint8_t pcr_osc_cal_read() +{ + return (p_pcr_osc_cal_read()); +} + + +/* end pcr_api.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_perphl.c new file mode 100644 index 000000000..be1a636d0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/pcr/pcr_perphl.c @@ -0,0 +1,642 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2016/09/22 08:03:49 $ +$Author: pramans $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr_perphl.c +* \brief Power, Clocks, and Resets Peripheral Source file +* \author jvasanth +* +* This file implements the PCR Peripheral functions +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#include "common_lib.h" +#include "pcr.h" + +/* ---------------------------------------------------------------------- */ +/* Generic functions to program and read 32-bit values from PCR Registers */ +/* ---------------------------------------------------------------------- */ +/** Writes 32-bit value in the PCR Register + * @param pcr_reg_id - pcr register id + * @param value - 32-bit value + */ +void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg = value; +} + +/** Reads 32-bit value from the PCR Register + * @param pcr_reg_id - pcr register id + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_read(uint8_t pcr_reg_id) +{ + __IO uint32_t *pPCR_Reg; + uint32_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + retVal = *pPCR_Reg; + + return retVal; +} + +/* ---------------------------------------------------------------------- */ +/* Functions to set, clr and get bits in PCR Registers */ +/* ---------------------------------------------------------------------- */ + +/** Sets bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set + */ +void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg |= bit_mask; +} + +/** Clears bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to clear + */ +void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg &= ~bit_mask; +} + +/** Read bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to read + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + uint32_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + retVal = (*pPCR_Reg) & bit_mask; + + return retVal; +} + +/** Sets or Clears bits in a PCR Register - Helper Function + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set or clear + * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register + */ +void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag) +{ + if (set_clr_flag) + { + p_pcr_reg_set(pcr_reg_id, bit_mask); + } + else + { + p_pcr_reg_clr(pcr_reg_id, bit_mask); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to operate on System Sleep Control Register */ +/* ---------------------------------------------------------------------- */ + + +/** Writes required sleep mode in System Sleep Control Register + * @param sleep_value - System Sleep control value (Heavy/Light/Sleep All) + */ +void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value) +{ + __IO uint32_t *pPCR_Reg; + + /* Check for valid value */ + if ((sleep_value == SYSTEM_LIGHT_SLEEP) || + (sleep_value == SYSTEM_LIGHT_SLEEP) || + (sleep_value == SYSTEM_LIGHT_SLEEP)) + { + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + *pPCR_Reg = (sleep_value & 0x7); + } +} + +/** Reads the System Sleep Control PCR Register + * @return value - byte 0 of the system sleep control PCR register + */ +uint8_t p_pcr_system_sleep_ctrl_read(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + retVal = (uint8_t)((*pPCR_Reg) & 0xFF); + + return retVal; +} + + + +/* ---------------------------------------------------------------------- */ +/* Function to program to CLK Divide Value */ +/* ---------------------------------------------------------------------- */ + +/** Writes the clock divide value in the Processor Clock Control Register + * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE + */ +void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value) +{ + __IO uint32_t *pPCR_Reg; + + /* Check for valid value */ + if (((clk_divide_value >= PCR_CPU_CLK_DIVIDE_1) && + (clk_divide_value <= PCR_CPU_CLK_DIVIDE_4)) || + (clk_divide_value == PCR_CPU_CLK_DIVIDE_16) || + (clk_divide_value == PCR_CPU_CLK_DIVIDE_48)) + { + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; + + *pPCR_Reg = (clk_divide_value & 0xFF); + } + +} + +/** Writes the clock divide value in the Processor Clock Control Register + * @param none + * @ return value - clk divide value, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE + */ +uint8_t p_pcr_processor_clk_ctrl_read(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; + + retVal = ((uint8_t)((*pPCR_Reg) & 0xFF)); + + return retVal; + +} + +/* ---------------------------------------------------------------------- */ +/* Function to program the slow clock divide value */ +/* ---------------------------------------------------------------------- */ + +/** Write the slow clock divide value in the Slow Clock Control Register + * @param slow_clk_divide_value - slow clk divide value + */ +void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; + + *pPCR_Reg = (slow_clk_divide_value & 0x3FF); + +} + +/* ---------------------------------------------------------------------- */ +/* Function to read the Oscillator Lock Status */ +/* ---------------------------------------------------------------------- */ + +/** Reads the Oscillator Lock status bit in the Oscillator ID Register + * @return 1 if Oscillator Lock Status bit is set, else 0 + */ +uint8_t p_pcr_oscillator_lock_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; + + retVal = 0; + if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK) + { + retVal = 1; + } + + return retVal; + +} + + +/** Reads the Oscillator ID Register + * @return oscillator ID value + */ +uint16_t p_pcr_oscillator_id_reg_read(void) +{ + __IO uint32_t *pPCR_Reg; + uint16_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; + + retVal = ((uint16_t)((*pPCR_Reg) & 0x1FFu)); + + return retVal; + +} + +/* ---------------------------------------------------------------------- */ +/* Functions to read various power status in Power Reset register */ +/* ---------------------------------------------------------------------- */ + +/** Reads the VCC PWRGD Status bit + * in the Power Reset Status Register + * @return 1 if VCC PWRGD Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vcc_pwrdg_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the Host Reset Status bit + * in the Power Reset Status Register + * @return 1 if Host Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_host_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the VBAT Reset Status bit + * in the Power Reset Status Register + * @return 1 if VBAT Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Clears the VBAT Reset Status bit + * in the Power Reset Status Register + */ +void p_pcr_pwr_reset_vbat_reset_sts_clr(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + // Write to clear + *pPCR_Reg |= PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK; + +} + +/** Reads the VTR Reset Status bit + * in the Power Reset Status Register + * @return 1 if VTR Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Clears the VTR Reset Status bit + * in the Power Reset Status Register + */ +void p_pcr_pwr_reset_vtr_reset_sts_clr(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + // Write to clear + *pPCR_Reg |= PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK; + +} + +/** Reads the JTAG Reset Status bit + * in the Power Reset Status Register + * @return 1 if JTAG Reset Status bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_jtag_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Clears the JTAG Reset Status bit + * in the Power Reset Status Register + */ +void p_pcr_pwr_reset_jtag_reset_sts_clr(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + // Write to clear + *pPCR_Reg |= PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK; + +} + +/** Reads the 32K_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if 32_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_32K_active_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the PCICLK_ACTIVE status bit + * in the Power Reset Status Register + * @return 1 if PCICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK) + { + retVal = 1; + } + return retVal; +} + +/** Reads the ESPI status bit + * in the Power Reset Status Register + * @return 1 if ESPICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK) + { + retVal = 1; + } + return retVal; +} + +/** Reads the Power status reg + * @return Power Status Reg value + */ +uint16_t p_pcr_pwr_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint16_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; + + retVal = (uint16_t)((*pPCR_Reg) & 0xFFF); + + return (retVal); +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Power Reset Control Register */ +/* ---------------------------------------------------------------------- */ + +/** Reads the Power Reset Control Register + * @return Power Reset Control Register value + */ +uint16_t p_pcr_pwr_reset_ctrl_read(void) +{ + __IO uint32_t *pPCR_Reg; + uint16_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; + + retVal = (uint16_t)((*pPCR_Reg) & 0x1FFUL); + + return retVal; +} + +/** Set the PWR_INV bit in the Power Reset Control Register + * @param set_clr value 1 or 0 + * @return none + */ +void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; + + if (set_clr) + { + *pPCR_Reg |= (PCR_PWR_RESET_CTRL_PWR_INV_BITMASK); + } + else + { + *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_PWR_INV_BITMASK); + } +} + +/** Set the HOST RESET SELECT bit in the Power Reset Control Register + * @param set_clr value 1 or 0 + * @return none + */ +void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; + + if (set_clr) + { + *pPCR_Reg |= (PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); + } + else + { + *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); + } +} + + +/* ---------------------------------------------------------------------- */ +/* Functions for System Reset Register */ +/* ---------------------------------------------------------------------- */ +/** Set the SOFT_SYS_RESET bit in the System Reset Register + * @param none + * @return none + */ +void p_pcr_system_reset_set() +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_RESET; + + *pPCR_Reg |= (1<<8); +} + +/* ---------------------------------------------------------------------- */ +/* Functions for PKE Clock Register */ +/* ---------------------------------------------------------------------- */ +/** Set the value in PKE CLOCK Register + * @param PKE Clock value + * @return none + */ +void p_pcr_pke_clock_write(uint8_t pke_clk_val) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; + + *pPCR_Reg = pke_clk_val; +} + +/** Read the value in PKE CLOCK Register + * @none + * @return PKE Clock value + */ +uint8_t p_pcr_pke_clock_read(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; + + return ((uint8_t)(*pPCR_Reg & 0xFF)); +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Oscillator calibration Register */ +/* ---------------------------------------------------------------------- */ +/** Set the value in Oscillator calibration Register + * @param Oscillator calibration value + * @return none + */ +void p_pcr_osc_cal_write(uint8_t osc_cal_val) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; + + *pPCR_Reg = osc_cal_val; +} + +/** Read the value in Osc cal Register + * @none + * @return Osc cal value + */ +uint8_t p_pcr_osc_cal_read(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; + + return ((uint8_t)(*pPCR_Reg & 0xFF)); +} + +/* end pcr_perphl.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h new file mode 100644 index 000000000..b069d5c27 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h @@ -0,0 +1,398 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup pwm pwm_c_wrapper + * @{ + */ +/** @file pwm_c_wrapper.cpp + \brief the pwm component C wrapper + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/platform.h $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2016/09/22 08:03:49 $ + * AUTHOR: $Author: pramans $ + * + * Revision history (latest first): + * #xx + *********************************************************************************** + */ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ +#include + +/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */ +#define DISAGGREGATED_INPT_DEFINED 1 +//#define AGGREGATED_INPT_DEFINED 1 + +/* Platform Configuration PreProcessor Conditions */ +#define TOOLKEIL 1 +#define TOOLPC 2 +#define TOOLMW 3 +#define TOOLMDK 4 + +#define PCLINT 9 //added to satisfy PC Lint's need for a value here + +#ifdef __CC_ARM // Keil ARM MDK +#define TOOLSET TOOLMDK +#endif + +#if 0 +#ifdef _WIN32 //always defined by visual c++ +#define TOOLSET TOOLPC +#endif + +#ifdef __WIN32__ //always defined by borland +#define TOOLSET TOOLPC +#endif +#endif + + +#ifdef _ARC +#define TOOLSET TOOLMW // ARC Metaware +#endif + +#ifndef TOOLSET +//#error "ERROR: cfg.h TOOLSET not defined!" +#endif + +#if TOOLSET == TOOLMDK +#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */ +#define _KEIL_ 0 /* Make 1 for Keil Compiler */ +#define _PC_ 0 +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLKEIL +#define _KEIL_ARM_ 0 +#define _KEIL_ 1 /* Make 1 for Keil Compiler */ +#define _PC_ 0 +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLPC +#define _KEIL_ARM_ 0 +#define _KEIL_ 0 +#define _PC_ 1 /* Make 1 for PC Environment */ +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLMW +#define _KEIL_ARM_ 0 +#define _KEIL_ 0 +#define _PC_ 0 +#define _ARC_CORE_ 1 +#endif + +/* Short form for Standard Data Types */ +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned long UINT32; + +typedef volatile unsigned char REG8; + +typedef unsigned char BYTE; +typedef unsigned short WORD; +typedef unsigned long DWORD; + +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned long ULONG; + +typedef unsigned char BOOL; +typedef unsigned int UINT; + +/* signed types */ +typedef signed char INT8; +typedef signed short INT16; +typedef signed long INT32; + +typedef void VOID; + +typedef volatile unsigned char VUINT8; +typedef volatile unsigned short int VUINT16; +typedef volatile unsigned long int VUINT32; +/* union types */ +typedef union _BITS_8 +{ + UINT8 byte; + struct + { + UINT8 bit0: 1; + UINT8 bit1: 1; + UINT8 bit2: 1; + UINT8 bit3: 1; + UINT8 bit4: 1; + UINT8 bit5: 1; + UINT8 bit6: 1; + UINT8 bit7: 1; + }bit; +}BITS_8; + + +/* MACROS FOR Platform Portability */ + +/* macro for defining MMCR register */ +/* add MMCRARRAY() & EXTERNMMCRARRAY() */ +#if _KEIL_ +#define MMCR(name,address) volatile unsigned char xdata name _at_ address +#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address +#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address +#define EXTERNMMCR(name) extern volatile unsigned char xdata name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name +#define SFR(name,address) sfr name = address +#define SFRBIT(name,address) sbit name = address +#define EXTERNSFR(name) +#define BITADDRESSTYPE(name) bit name +#define XDATA xdata +#define CODE code +#define DATA data +#define IDATA idata +#define INTERRUPT(x) interrupt x +#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) +#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) +#define NULLPTR (char *)(0) +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() +#define DISABLE_INTERRUPTS() sfrIE_EAbit=0 +#define ENABLE_INTERRUPTS() sfrIE_EAbit=1 +#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; } +#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; } +#define ATOMIC_CPU_SLEEP() +#define NUM_IRQ_VECTORS 12 // DW-8051 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start +#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start +#define FUNC_NEVER_RETURNS +#define BEGIN_SMALL_DATA_BLOCK(x) +#define END_SMALL_DATA_BLOCK() +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _PC_ +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) volatile unsigned char name +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) +#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) +#define NULLPTR (char *)(0) +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() +#define DISABLE_INTERRUPTS() +#define ENABLE_INTERRUPTS() +#define SAVE_DIS_INTERRUPTS(x) +#define RESTORE_INTERRUPTS(x) +#define ATOMIC_CPU_SLEEP() +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define FUNC_NEVER_RETURNS +#define BEGIN_SMALL_DATA_BLOCK(x) +#define END_SMALL_DATA_BLOCK() +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _ARC_CORE_ +// ARC C has no equivalent operator to specify address of a variable +// ARC MMCR's are 32-bit registers +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (_enable()) +#define CLR_GLOBAL_INTR_ENABLE() (_disable()) +#define NULLPTR (char *)(0) +#define NULLVOIDPTR (void *)(0) +#define NULLFPTR (void (*)(void))0 +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() _nop() +#define DISABLE_INTERRUPTS() _disable() +#define ENABLE_INTERRUPTS() _enable() +#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } +#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } +#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop(); +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 0 +#define DCCM_CODE_ALIAS_ADDR 0x00060000 +#define PLAT_ROM_IRQ_VECTOR_BASE 0 +#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) +/// y #define IRQ_VECTABLE_IN_RAM 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) +#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) +#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() +#define NORM(x) _norm(x) + +#define INLINE_FUNCTION(x) #pragma On_inline(x) + +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _KEIL_ARM_ +// For ARM MDK compiler +// ARM MMCR's are 32-bit registers +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (__enable_irq()) +#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq()) +#define NULLPTR (char *)(0) +#define NULLVOIDPTR (void *)(0) +#define NULLFPTR (void (*)(void))0 +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() __NOP() +#define DISABLE_INTERRUPTS() __disable_irq() +#define ENABLE_INTERRUPTS() __enable_irq() +#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop(); + +#if 0 /* need further efforts if needed */ +#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } +#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 0 +#define DCCM_CODE_ALIAS_ADDR 0x00060000 +#define PLAT_ROM_IRQ_VECTOR_BASE 0 +#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) +/// y #define IRQ_VECTABLE_IN_RAM 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) +#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() +#define INLINE_FUNCTION(x) #pragma On_inline(x) +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if 0 +#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) +#define NORM(x) _norm(x) +#else +/* for ARM MDK */ +#define FUNC_NEVER_RETURNS +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +#endif +#endif + +/* General Constants */ +#define FALSE 0x00 +#define TRUE !FALSE + +#define BIT_n_MASK(n) (1U << (n)) +#define BIT_0_MASK (1<<0) +#define BIT_1_MASK (1<<1) +#define BIT_2_MASK (1<<2) +#define BIT_3_MASK (1<<3) +#define BIT_4_MASK (1<<4) +#define BIT_5_MASK (1<<5) +#define BIT_6_MASK (1<<6) +#define BIT_7_MASK (1<<7) +#define BIT_8_MASK ((UINT16)1<<8) +#define BIT_9_MASK ((UINT16)1<<9) +#define BIT_10_MASK ((UINT16)1<<10) +#define BIT_11_MASK ((UINT16)1<<11) +#define BIT_12_MASK ((UINT16)1<<12) +#define BIT_13_MASK ((UINT16)1<<13) +#define BIT_14_MASK ((UINT16)1<<14) +#define BIT_15_MASK ((UINT16)1<<15) +#define BIT_16_MASK ((UINT32)1<<16) +#define BIT_17_MASK ((UINT32)1<<17) +#define BIT_18_MASK ((UINT32)1<<18) +#define BIT_19_MASK ((UINT32)1<<19) +#define BIT_20_MASK ((UINT32)1<<20) +#define BIT_21_MASK ((UINT32)1<<21) +#define BIT_22_MASK ((UINT32)1<<22) +#define BIT_23_MASK ((UINT32)1<<23) +#define BIT_24_MASK ((UINT32)1<<24) +#define BIT_25_MASK ((UINT32)1<<25) +#define BIT_26_MASK ((UINT32)1<<26) +#define BIT_27_MASK ((UINT32)1<<27) +#define BIT_28_MASK ((UINT32)1<<28) +#define BIT_29_MASK ((UINT32)1<<29) +#define BIT_30_MASK ((UINT32)1<<30) +#define BIT_31_MASK ((UINT32)1<<31) + + +/* For CEC application */ +#define ON 1 +#define OFF 0 + +#endif /*_PLATFORM_H_*/ + +/** @} + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h.ini new file mode 100644 index 000000000..0aca50b74 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/platform.h.ini @@ -0,0 +1,5 @@ +[Position] +Line=79 +Column=1 +[FoldedLines] +Count=0 diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.c new file mode 100644 index 000000000..f8c8da4fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.c @@ -0,0 +1,122 @@ +/**************************************************************************//** + * @file system_internal.c + * @brief CMSIS Device System Source File for + * Microchip ARMCM4F Device Series + * @version V1.09 + * @date 27. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +/* + * Device CMSIS header file + */ +#include "common_lib.h" +#include "MCHP_device_header.h" + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 48000000UL) +#define __XTAL ( 48000000UL) /* Oscillator frequency */ + +/* + * Core system clock is 48MHz derived from an internal oscillator + * It may be divided down using the PCR Processor Clock Control register. + * Supported dividers are: 1, 2, 3, 4, 16, and 48. + * Power on default is 4. + */ +#define __SYSTEM_CLOCK (__XTAL) + +/* !!!! Define EC_INIT_CLK_DIV for the clock divider you + * want the ARM CM4F core to run at !!!! + */ +#ifndef EC_INIT_CLK_DIV +#define EC_INIT_CLK_DIV (1u) +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */ + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + * @note Read the EC core clock divider from the PCR block's processor + * clock control register. Actual EC core frequency is 48MHz / proc_clock_control[7:0]. + */ +void SystemCoreClockUpdate (void) +{ + uint32_t cpu_clk_div; + + SystemCoreClock = __SYSTEM_CLOCK; + cpu_clk_div = PCR->PROC_CLK_CNTRL; + if (cpu_clk_div) { + SystemCoreClock = __SYSTEM_CLOCK / cpu_clk_div; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + * @note SystemInit is usually called from early startup code before + * C/C++ library initialization. It is used for early hardware initialization + * such as clocks, FPU, debug hardware, etc. + */ +void SystemInit (void) +{ + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Program device PCR Processor Clock Control divider to set the EC core clock */ + PCR->PROC_CLK_CNTRL = (EC_INIT_CLK_DIV); + SystemCoreClock = ( __SYSTEM_CLOCK / (EC_INIT_CLK_DIV) ); + +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.h new file mode 100644 index 000000000..bb02122b8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_Keil_GCC/peripheral_library/system_internal.h @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_internal.h + * @brief CMSIS Device System Header File for + * Microchip ARMCM4F Device Series + * @version V1.08 + * @date 23. November 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_INTERNAL_H +#define SYSTEM_INTERNAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#define PCR MEC2016_PCR +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_INTERNAL_H */