From: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Date: Tue, 8 Apr 2008 07:20:35 +0000 (+0900)
Subject: cpu/mips/cpu.c: Fix flush_cache bug
X-Git-Tag: v1.3.3-rc1~69
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=188e94c370621708d13547d58dbc6ed3c5602aa8;p=u-boot

cpu/mips/cpu.c: Fix flush_cache bug

Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
---

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 8b43d8eb36..e267bba469 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
 	while (1) {
-		cache_op(Hit_Writeback_Inv_D, start_addr);
-		cache_op(Hit_Invalidate_I, start_addr);
+		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(Hit_Invalidate_I, addr);
 		if (addr == aend)
 			break;
 		addr += lsize;